vmwgfx_kms.c 50 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853
  1. /**************************************************************************
  2. *
  3. * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. **************************************************************************/
  27. #include "vmwgfx_kms.h"
  28. /* Might need a hrtimer here? */
  29. #define VMWGFX_PRESENT_RATE ((HZ / 60 > 0) ? HZ / 60 : 1)
  30. void vmw_display_unit_cleanup(struct vmw_display_unit *du)
  31. {
  32. if (du->cursor_surface)
  33. vmw_surface_unreference(&du->cursor_surface);
  34. if (du->cursor_dmabuf)
  35. vmw_dmabuf_unreference(&du->cursor_dmabuf);
  36. drm_crtc_cleanup(&du->crtc);
  37. drm_encoder_cleanup(&du->encoder);
  38. drm_connector_cleanup(&du->connector);
  39. }
  40. /*
  41. * Display Unit Cursor functions
  42. */
  43. int vmw_cursor_update_image(struct vmw_private *dev_priv,
  44. u32 *image, u32 width, u32 height,
  45. u32 hotspotX, u32 hotspotY)
  46. {
  47. struct {
  48. u32 cmd;
  49. SVGAFifoCmdDefineAlphaCursor cursor;
  50. } *cmd;
  51. u32 image_size = width * height * 4;
  52. u32 cmd_size = sizeof(*cmd) + image_size;
  53. if (!image)
  54. return -EINVAL;
  55. cmd = vmw_fifo_reserve(dev_priv, cmd_size);
  56. if (unlikely(cmd == NULL)) {
  57. DRM_ERROR("Fifo reserve failed.\n");
  58. return -ENOMEM;
  59. }
  60. memset(cmd, 0, sizeof(*cmd));
  61. memcpy(&cmd[1], image, image_size);
  62. cmd->cmd = cpu_to_le32(SVGA_CMD_DEFINE_ALPHA_CURSOR);
  63. cmd->cursor.id = cpu_to_le32(0);
  64. cmd->cursor.width = cpu_to_le32(width);
  65. cmd->cursor.height = cpu_to_le32(height);
  66. cmd->cursor.hotspotX = cpu_to_le32(hotspotX);
  67. cmd->cursor.hotspotY = cpu_to_le32(hotspotY);
  68. vmw_fifo_commit(dev_priv, cmd_size);
  69. return 0;
  70. }
  71. void vmw_cursor_update_position(struct vmw_private *dev_priv,
  72. bool show, int x, int y)
  73. {
  74. __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  75. uint32_t count;
  76. iowrite32(show ? 1 : 0, fifo_mem + SVGA_FIFO_CURSOR_ON);
  77. iowrite32(x, fifo_mem + SVGA_FIFO_CURSOR_X);
  78. iowrite32(y, fifo_mem + SVGA_FIFO_CURSOR_Y);
  79. count = ioread32(fifo_mem + SVGA_FIFO_CURSOR_COUNT);
  80. iowrite32(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT);
  81. }
  82. int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
  83. uint32_t handle, uint32_t width, uint32_t height)
  84. {
  85. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  86. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  87. struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
  88. struct vmw_surface *surface = NULL;
  89. struct vmw_dma_buffer *dmabuf = NULL;
  90. int ret;
  91. /* A lot of the code assumes this */
  92. if (handle && (width != 64 || height != 64))
  93. return -EINVAL;
  94. if (handle) {
  95. ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
  96. handle, &surface);
  97. if (!ret) {
  98. if (!surface->snooper.image) {
  99. DRM_ERROR("surface not suitable for cursor\n");
  100. vmw_surface_unreference(&surface);
  101. return -EINVAL;
  102. }
  103. } else {
  104. ret = vmw_user_dmabuf_lookup(tfile,
  105. handle, &dmabuf);
  106. if (ret) {
  107. DRM_ERROR("failed to find surface or dmabuf: %i\n", ret);
  108. return -EINVAL;
  109. }
  110. }
  111. }
  112. /* takedown old cursor */
  113. if (du->cursor_surface) {
  114. du->cursor_surface->snooper.crtc = NULL;
  115. vmw_surface_unreference(&du->cursor_surface);
  116. }
  117. if (du->cursor_dmabuf)
  118. vmw_dmabuf_unreference(&du->cursor_dmabuf);
  119. /* setup new image */
  120. if (surface) {
  121. /* vmw_user_surface_lookup takes one reference */
  122. du->cursor_surface = surface;
  123. du->cursor_surface->snooper.crtc = crtc;
  124. du->cursor_age = du->cursor_surface->snooper.age;
  125. vmw_cursor_update_image(dev_priv, surface->snooper.image,
  126. 64, 64, du->hotspot_x, du->hotspot_y);
  127. } else if (dmabuf) {
  128. struct ttm_bo_kmap_obj map;
  129. unsigned long kmap_offset;
  130. unsigned long kmap_num;
  131. void *virtual;
  132. bool dummy;
  133. /* vmw_user_surface_lookup takes one reference */
  134. du->cursor_dmabuf = dmabuf;
  135. kmap_offset = 0;
  136. kmap_num = (64*64*4) >> PAGE_SHIFT;
  137. ret = ttm_bo_reserve(&dmabuf->base, true, false, false, 0);
  138. if (unlikely(ret != 0)) {
  139. DRM_ERROR("reserve failed\n");
  140. return -EINVAL;
  141. }
  142. ret = ttm_bo_kmap(&dmabuf->base, kmap_offset, kmap_num, &map);
  143. if (unlikely(ret != 0))
  144. goto err_unreserve;
  145. virtual = ttm_kmap_obj_virtual(&map, &dummy);
  146. vmw_cursor_update_image(dev_priv, virtual, 64, 64,
  147. du->hotspot_x, du->hotspot_y);
  148. ttm_bo_kunmap(&map);
  149. err_unreserve:
  150. ttm_bo_unreserve(&dmabuf->base);
  151. } else {
  152. vmw_cursor_update_position(dev_priv, false, 0, 0);
  153. return 0;
  154. }
  155. vmw_cursor_update_position(dev_priv, true,
  156. du->cursor_x + du->hotspot_x,
  157. du->cursor_y + du->hotspot_y);
  158. return 0;
  159. }
  160. int vmw_du_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  161. {
  162. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  163. struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
  164. bool shown = du->cursor_surface || du->cursor_dmabuf ? true : false;
  165. du->cursor_x = x + crtc->x;
  166. du->cursor_y = y + crtc->y;
  167. vmw_cursor_update_position(dev_priv, shown,
  168. du->cursor_x + du->hotspot_x,
  169. du->cursor_y + du->hotspot_y);
  170. return 0;
  171. }
  172. void vmw_kms_cursor_snoop(struct vmw_surface *srf,
  173. struct ttm_object_file *tfile,
  174. struct ttm_buffer_object *bo,
  175. SVGA3dCmdHeader *header)
  176. {
  177. struct ttm_bo_kmap_obj map;
  178. unsigned long kmap_offset;
  179. unsigned long kmap_num;
  180. SVGA3dCopyBox *box;
  181. unsigned box_count;
  182. void *virtual;
  183. bool dummy;
  184. struct vmw_dma_cmd {
  185. SVGA3dCmdHeader header;
  186. SVGA3dCmdSurfaceDMA dma;
  187. } *cmd;
  188. int i, ret;
  189. cmd = container_of(header, struct vmw_dma_cmd, header);
  190. /* No snooper installed */
  191. if (!srf->snooper.image)
  192. return;
  193. if (cmd->dma.host.face != 0 || cmd->dma.host.mipmap != 0) {
  194. DRM_ERROR("face and mipmap for cursors should never != 0\n");
  195. return;
  196. }
  197. if (cmd->header.size < 64) {
  198. DRM_ERROR("at least one full copy box must be given\n");
  199. return;
  200. }
  201. box = (SVGA3dCopyBox *)&cmd[1];
  202. box_count = (cmd->header.size - sizeof(SVGA3dCmdSurfaceDMA)) /
  203. sizeof(SVGA3dCopyBox);
  204. if (cmd->dma.guest.ptr.offset % PAGE_SIZE ||
  205. box->x != 0 || box->y != 0 || box->z != 0 ||
  206. box->srcx != 0 || box->srcy != 0 || box->srcz != 0 ||
  207. box->d != 1 || box_count != 1) {
  208. /* TODO handle none page aligned offsets */
  209. /* TODO handle more dst & src != 0 */
  210. /* TODO handle more then one copy */
  211. DRM_ERROR("Cant snoop dma request for cursor!\n");
  212. DRM_ERROR("(%u, %u, %u) (%u, %u, %u) (%ux%ux%u) %u %u\n",
  213. box->srcx, box->srcy, box->srcz,
  214. box->x, box->y, box->z,
  215. box->w, box->h, box->d, box_count,
  216. cmd->dma.guest.ptr.offset);
  217. return;
  218. }
  219. kmap_offset = cmd->dma.guest.ptr.offset >> PAGE_SHIFT;
  220. kmap_num = (64*64*4) >> PAGE_SHIFT;
  221. ret = ttm_bo_reserve(bo, true, false, false, 0);
  222. if (unlikely(ret != 0)) {
  223. DRM_ERROR("reserve failed\n");
  224. return;
  225. }
  226. ret = ttm_bo_kmap(bo, kmap_offset, kmap_num, &map);
  227. if (unlikely(ret != 0))
  228. goto err_unreserve;
  229. virtual = ttm_kmap_obj_virtual(&map, &dummy);
  230. if (box->w == 64 && cmd->dma.guest.pitch == 64*4) {
  231. memcpy(srf->snooper.image, virtual, 64*64*4);
  232. } else {
  233. /* Image is unsigned pointer. */
  234. for (i = 0; i < box->h; i++)
  235. memcpy(srf->snooper.image + i * 64,
  236. virtual + i * cmd->dma.guest.pitch,
  237. box->w * 4);
  238. }
  239. srf->snooper.age++;
  240. /* we can't call this function from this function since execbuf has
  241. * reserved fifo space.
  242. *
  243. * if (srf->snooper.crtc)
  244. * vmw_ldu_crtc_cursor_update_image(dev_priv,
  245. * srf->snooper.image, 64, 64,
  246. * du->hotspot_x, du->hotspot_y);
  247. */
  248. ttm_bo_kunmap(&map);
  249. err_unreserve:
  250. ttm_bo_unreserve(bo);
  251. }
  252. void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
  253. {
  254. struct drm_device *dev = dev_priv->dev;
  255. struct vmw_display_unit *du;
  256. struct drm_crtc *crtc;
  257. mutex_lock(&dev->mode_config.mutex);
  258. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  259. du = vmw_crtc_to_du(crtc);
  260. if (!du->cursor_surface ||
  261. du->cursor_age == du->cursor_surface->snooper.age)
  262. continue;
  263. du->cursor_age = du->cursor_surface->snooper.age;
  264. vmw_cursor_update_image(dev_priv,
  265. du->cursor_surface->snooper.image,
  266. 64, 64, du->hotspot_x, du->hotspot_y);
  267. }
  268. mutex_unlock(&dev->mode_config.mutex);
  269. }
  270. /*
  271. * Generic framebuffer code
  272. */
  273. int vmw_framebuffer_create_handle(struct drm_framebuffer *fb,
  274. struct drm_file *file_priv,
  275. unsigned int *handle)
  276. {
  277. if (handle)
  278. handle = 0;
  279. return 0;
  280. }
  281. /*
  282. * Surface framebuffer code
  283. */
  284. #define vmw_framebuffer_to_vfbs(x) \
  285. container_of(x, struct vmw_framebuffer_surface, base.base)
  286. struct vmw_framebuffer_surface {
  287. struct vmw_framebuffer base;
  288. struct vmw_surface *surface;
  289. struct vmw_dma_buffer *buffer;
  290. struct list_head head;
  291. struct drm_master *master;
  292. };
  293. void vmw_framebuffer_surface_destroy(struct drm_framebuffer *framebuffer)
  294. {
  295. struct vmw_framebuffer_surface *vfbs =
  296. vmw_framebuffer_to_vfbs(framebuffer);
  297. struct vmw_master *vmaster = vmw_master(vfbs->master);
  298. mutex_lock(&vmaster->fb_surf_mutex);
  299. list_del(&vfbs->head);
  300. mutex_unlock(&vmaster->fb_surf_mutex);
  301. drm_master_put(&vfbs->master);
  302. drm_framebuffer_cleanup(framebuffer);
  303. vmw_surface_unreference(&vfbs->surface);
  304. ttm_base_object_unref(&vfbs->base.user_obj);
  305. kfree(vfbs);
  306. }
  307. static int do_surface_dirty_sou(struct vmw_private *dev_priv,
  308. struct drm_file *file_priv,
  309. struct vmw_framebuffer *framebuffer,
  310. unsigned flags, unsigned color,
  311. struct drm_clip_rect *clips,
  312. unsigned num_clips, int inc)
  313. {
  314. struct drm_clip_rect *clips_ptr;
  315. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  316. struct drm_crtc *crtc;
  317. size_t fifo_size;
  318. int i, num_units;
  319. int ret = 0; /* silence warning */
  320. int left, right, top, bottom;
  321. struct {
  322. SVGA3dCmdHeader header;
  323. SVGA3dCmdBlitSurfaceToScreen body;
  324. } *cmd;
  325. SVGASignedRect *blits;
  326. num_units = 0;
  327. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list,
  328. head) {
  329. if (crtc->fb != &framebuffer->base)
  330. continue;
  331. units[num_units++] = vmw_crtc_to_du(crtc);
  332. }
  333. BUG_ON(!clips || !num_clips);
  334. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
  335. cmd = kzalloc(fifo_size, GFP_KERNEL);
  336. if (unlikely(cmd == NULL)) {
  337. DRM_ERROR("Temporary fifo memory alloc failed.\n");
  338. return -ENOMEM;
  339. }
  340. left = clips->x1;
  341. right = clips->x2;
  342. top = clips->y1;
  343. bottom = clips->y2;
  344. /* skip the first clip rect */
  345. for (i = 1, clips_ptr = clips + inc;
  346. i < num_clips; i++, clips_ptr += inc) {
  347. left = min_t(int, left, (int)clips_ptr->x1);
  348. right = max_t(int, right, (int)clips_ptr->x2);
  349. top = min_t(int, top, (int)clips_ptr->y1);
  350. bottom = max_t(int, bottom, (int)clips_ptr->y2);
  351. }
  352. /* only need to do this once */
  353. memset(cmd, 0, fifo_size);
  354. cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
  355. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  356. cmd->body.srcRect.left = left;
  357. cmd->body.srcRect.right = right;
  358. cmd->body.srcRect.top = top;
  359. cmd->body.srcRect.bottom = bottom;
  360. clips_ptr = clips;
  361. blits = (SVGASignedRect *)&cmd[1];
  362. for (i = 0; i < num_clips; i++, clips_ptr += inc) {
  363. blits[i].left = clips_ptr->x1 - left;
  364. blits[i].right = clips_ptr->x2 - left;
  365. blits[i].top = clips_ptr->y1 - top;
  366. blits[i].bottom = clips_ptr->y2 - top;
  367. }
  368. /* do per unit writing, reuse fifo for each */
  369. for (i = 0; i < num_units; i++) {
  370. struct vmw_display_unit *unit = units[i];
  371. int clip_x1 = left - unit->crtc.x;
  372. int clip_y1 = top - unit->crtc.y;
  373. int clip_x2 = right - unit->crtc.x;
  374. int clip_y2 = bottom - unit->crtc.y;
  375. /* skip any crtcs that misses the clip region */
  376. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  377. clip_y1 >= unit->crtc.mode.vdisplay ||
  378. clip_x2 <= 0 || clip_y2 <= 0)
  379. continue;
  380. /* need to reset sid as it is changed by execbuf */
  381. cmd->body.srcImage.sid = cpu_to_le32(framebuffer->user_handle);
  382. cmd->body.destScreenId = unit->unit;
  383. /*
  384. * The blit command is a lot more resilient then the
  385. * readback command when it comes to clip rects. So its
  386. * okay to go out of bounds.
  387. */
  388. cmd->body.destRect.left = clip_x1;
  389. cmd->body.destRect.right = clip_x2;
  390. cmd->body.destRect.top = clip_y1;
  391. cmd->body.destRect.bottom = clip_y2;
  392. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  393. fifo_size, 0, NULL);
  394. if (unlikely(ret != 0))
  395. break;
  396. }
  397. kfree(cmd);
  398. return ret;
  399. }
  400. int vmw_framebuffer_surface_dirty(struct drm_framebuffer *framebuffer,
  401. struct drm_file *file_priv,
  402. unsigned flags, unsigned color,
  403. struct drm_clip_rect *clips,
  404. unsigned num_clips)
  405. {
  406. struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
  407. struct vmw_master *vmaster = vmw_master(file_priv->master);
  408. struct vmw_framebuffer_surface *vfbs =
  409. vmw_framebuffer_to_vfbs(framebuffer);
  410. struct drm_clip_rect norect;
  411. int ret, inc = 1;
  412. if (unlikely(vfbs->master != file_priv->master))
  413. return -EINVAL;
  414. /* Require ScreenObject support for 3D */
  415. if (!dev_priv->sou_priv)
  416. return -EINVAL;
  417. ret = ttm_read_lock(&vmaster->lock, true);
  418. if (unlikely(ret != 0))
  419. return ret;
  420. if (!num_clips) {
  421. num_clips = 1;
  422. clips = &norect;
  423. norect.x1 = norect.y1 = 0;
  424. norect.x2 = framebuffer->width;
  425. norect.y2 = framebuffer->height;
  426. } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
  427. num_clips /= 2;
  428. inc = 2; /* skip source rects */
  429. }
  430. ret = do_surface_dirty_sou(dev_priv, file_priv, &vfbs->base,
  431. flags, color,
  432. clips, num_clips, inc);
  433. ttm_read_unlock(&vmaster->lock);
  434. return 0;
  435. }
  436. static struct drm_framebuffer_funcs vmw_framebuffer_surface_funcs = {
  437. .destroy = vmw_framebuffer_surface_destroy,
  438. .dirty = vmw_framebuffer_surface_dirty,
  439. .create_handle = vmw_framebuffer_create_handle,
  440. };
  441. static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv,
  442. struct drm_file *file_priv,
  443. struct vmw_surface *surface,
  444. struct vmw_framebuffer **out,
  445. const struct drm_mode_fb_cmd
  446. *mode_cmd)
  447. {
  448. struct drm_device *dev = dev_priv->dev;
  449. struct vmw_framebuffer_surface *vfbs;
  450. enum SVGA3dSurfaceFormat format;
  451. struct vmw_master *vmaster = vmw_master(file_priv->master);
  452. int ret;
  453. /* 3D is only supported on HWv8 hosts which supports screen objects */
  454. if (!dev_priv->sou_priv)
  455. return -ENOSYS;
  456. /*
  457. * Sanity checks.
  458. */
  459. if (unlikely(surface->mip_levels[0] != 1 ||
  460. surface->num_sizes != 1 ||
  461. surface->sizes[0].width < mode_cmd->width ||
  462. surface->sizes[0].height < mode_cmd->height ||
  463. surface->sizes[0].depth != 1)) {
  464. DRM_ERROR("Incompatible surface dimensions "
  465. "for requested mode.\n");
  466. return -EINVAL;
  467. }
  468. switch (mode_cmd->depth) {
  469. case 32:
  470. format = SVGA3D_A8R8G8B8;
  471. break;
  472. case 24:
  473. format = SVGA3D_X8R8G8B8;
  474. break;
  475. case 16:
  476. format = SVGA3D_R5G6B5;
  477. break;
  478. case 15:
  479. format = SVGA3D_A1R5G5B5;
  480. break;
  481. case 8:
  482. format = SVGA3D_LUMINANCE8;
  483. break;
  484. default:
  485. DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
  486. return -EINVAL;
  487. }
  488. if (unlikely(format != surface->format)) {
  489. DRM_ERROR("Invalid surface format for requested mode.\n");
  490. return -EINVAL;
  491. }
  492. vfbs = kzalloc(sizeof(*vfbs), GFP_KERNEL);
  493. if (!vfbs) {
  494. ret = -ENOMEM;
  495. goto out_err1;
  496. }
  497. ret = drm_framebuffer_init(dev, &vfbs->base.base,
  498. &vmw_framebuffer_surface_funcs);
  499. if (ret)
  500. goto out_err2;
  501. if (!vmw_surface_reference(surface)) {
  502. DRM_ERROR("failed to reference surface %p\n", surface);
  503. goto out_err3;
  504. }
  505. /* XXX get the first 3 from the surface info */
  506. vfbs->base.base.bits_per_pixel = mode_cmd->bpp;
  507. vfbs->base.base.pitches[0] = mode_cmd->pitch;
  508. vfbs->base.base.depth = mode_cmd->depth;
  509. vfbs->base.base.width = mode_cmd->width;
  510. vfbs->base.base.height = mode_cmd->height;
  511. vfbs->surface = surface;
  512. vfbs->base.user_handle = mode_cmd->handle;
  513. vfbs->master = drm_master_get(file_priv->master);
  514. mutex_lock(&vmaster->fb_surf_mutex);
  515. list_add_tail(&vfbs->head, &vmaster->fb_surf);
  516. mutex_unlock(&vmaster->fb_surf_mutex);
  517. *out = &vfbs->base;
  518. return 0;
  519. out_err3:
  520. drm_framebuffer_cleanup(&vfbs->base.base);
  521. out_err2:
  522. kfree(vfbs);
  523. out_err1:
  524. return ret;
  525. }
  526. /*
  527. * Dmabuf framebuffer code
  528. */
  529. #define vmw_framebuffer_to_vfbd(x) \
  530. container_of(x, struct vmw_framebuffer_dmabuf, base.base)
  531. struct vmw_framebuffer_dmabuf {
  532. struct vmw_framebuffer base;
  533. struct vmw_dma_buffer *buffer;
  534. };
  535. void vmw_framebuffer_dmabuf_destroy(struct drm_framebuffer *framebuffer)
  536. {
  537. struct vmw_framebuffer_dmabuf *vfbd =
  538. vmw_framebuffer_to_vfbd(framebuffer);
  539. drm_framebuffer_cleanup(framebuffer);
  540. vmw_dmabuf_unreference(&vfbd->buffer);
  541. ttm_base_object_unref(&vfbd->base.user_obj);
  542. kfree(vfbd);
  543. }
  544. static int do_dmabuf_dirty_ldu(struct vmw_private *dev_priv,
  545. struct vmw_framebuffer *framebuffer,
  546. unsigned flags, unsigned color,
  547. struct drm_clip_rect *clips,
  548. unsigned num_clips, int increment)
  549. {
  550. size_t fifo_size;
  551. int i;
  552. struct {
  553. uint32_t header;
  554. SVGAFifoCmdUpdate body;
  555. } *cmd;
  556. fifo_size = sizeof(*cmd) * num_clips;
  557. cmd = vmw_fifo_reserve(dev_priv, fifo_size);
  558. if (unlikely(cmd == NULL)) {
  559. DRM_ERROR("Fifo reserve failed.\n");
  560. return -ENOMEM;
  561. }
  562. memset(cmd, 0, fifo_size);
  563. for (i = 0; i < num_clips; i++, clips += increment) {
  564. cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE);
  565. cmd[i].body.x = cpu_to_le32(clips->x1);
  566. cmd[i].body.y = cpu_to_le32(clips->y1);
  567. cmd[i].body.width = cpu_to_le32(clips->x2 - clips->x1);
  568. cmd[i].body.height = cpu_to_le32(clips->y2 - clips->y1);
  569. }
  570. vmw_fifo_commit(dev_priv, fifo_size);
  571. return 0;
  572. }
  573. static int do_dmabuf_define_gmrfb(struct drm_file *file_priv,
  574. struct vmw_private *dev_priv,
  575. struct vmw_framebuffer *framebuffer)
  576. {
  577. int depth = framebuffer->base.depth;
  578. size_t fifo_size;
  579. int ret;
  580. struct {
  581. uint32_t header;
  582. SVGAFifoCmdDefineGMRFB body;
  583. } *cmd;
  584. /* Emulate RGBA support, contrary to svga_reg.h this is not
  585. * supported by hosts. This is only a problem if we are reading
  586. * this value later and expecting what we uploaded back.
  587. */
  588. if (depth == 32)
  589. depth = 24;
  590. fifo_size = sizeof(*cmd);
  591. cmd = kmalloc(fifo_size, GFP_KERNEL);
  592. if (unlikely(cmd == NULL)) {
  593. DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
  594. return -ENOMEM;
  595. }
  596. memset(cmd, 0, fifo_size);
  597. cmd->header = SVGA_CMD_DEFINE_GMRFB;
  598. cmd->body.format.bitsPerPixel = framebuffer->base.bits_per_pixel;
  599. cmd->body.format.colorDepth = depth;
  600. cmd->body.format.reserved = 0;
  601. cmd->body.bytesPerLine = framebuffer->base.pitches[0];
  602. cmd->body.ptr.gmrId = framebuffer->user_handle;
  603. cmd->body.ptr.offset = 0;
  604. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  605. fifo_size, 0, NULL);
  606. kfree(cmd);
  607. return ret;
  608. }
  609. static int do_dmabuf_dirty_sou(struct drm_file *file_priv,
  610. struct vmw_private *dev_priv,
  611. struct vmw_framebuffer *framebuffer,
  612. unsigned flags, unsigned color,
  613. struct drm_clip_rect *clips,
  614. unsigned num_clips, int increment)
  615. {
  616. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  617. struct drm_clip_rect *clips_ptr;
  618. int i, k, num_units, ret;
  619. struct drm_crtc *crtc;
  620. size_t fifo_size;
  621. struct {
  622. uint32_t header;
  623. SVGAFifoCmdBlitGMRFBToScreen body;
  624. } *blits;
  625. ret = do_dmabuf_define_gmrfb(file_priv, dev_priv, framebuffer);
  626. if (unlikely(ret != 0))
  627. return ret; /* define_gmrfb prints warnings */
  628. fifo_size = sizeof(*blits) * num_clips;
  629. blits = kmalloc(fifo_size, GFP_KERNEL);
  630. if (unlikely(blits == NULL)) {
  631. DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
  632. return -ENOMEM;
  633. }
  634. num_units = 0;
  635. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  636. if (crtc->fb != &framebuffer->base)
  637. continue;
  638. units[num_units++] = vmw_crtc_to_du(crtc);
  639. }
  640. for (k = 0; k < num_units; k++) {
  641. struct vmw_display_unit *unit = units[k];
  642. int hit_num = 0;
  643. clips_ptr = clips;
  644. for (i = 0; i < num_clips; i++, clips_ptr += increment) {
  645. int clip_x1 = clips_ptr->x1 - unit->crtc.x;
  646. int clip_y1 = clips_ptr->y1 - unit->crtc.y;
  647. int clip_x2 = clips_ptr->x2 - unit->crtc.x;
  648. int clip_y2 = clips_ptr->y2 - unit->crtc.y;
  649. /* skip any crtcs that misses the clip region */
  650. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  651. clip_y1 >= unit->crtc.mode.vdisplay ||
  652. clip_x2 <= 0 || clip_y2 <= 0)
  653. continue;
  654. blits[hit_num].header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
  655. blits[hit_num].body.destScreenId = unit->unit;
  656. blits[hit_num].body.srcOrigin.x = clips_ptr->x1;
  657. blits[hit_num].body.srcOrigin.y = clips_ptr->y1;
  658. blits[hit_num].body.destRect.left = clip_x1;
  659. blits[hit_num].body.destRect.top = clip_y1;
  660. blits[hit_num].body.destRect.right = clip_x2;
  661. blits[hit_num].body.destRect.bottom = clip_y2;
  662. hit_num++;
  663. }
  664. /* no clips hit the crtc */
  665. if (hit_num == 0)
  666. continue;
  667. fifo_size = sizeof(*blits) * hit_num;
  668. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, blits,
  669. fifo_size, 0, NULL);
  670. if (unlikely(ret != 0))
  671. break;
  672. }
  673. kfree(blits);
  674. return ret;
  675. }
  676. int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer,
  677. struct drm_file *file_priv,
  678. unsigned flags, unsigned color,
  679. struct drm_clip_rect *clips,
  680. unsigned num_clips)
  681. {
  682. struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
  683. struct vmw_master *vmaster = vmw_master(file_priv->master);
  684. struct vmw_framebuffer_dmabuf *vfbd =
  685. vmw_framebuffer_to_vfbd(framebuffer);
  686. struct drm_clip_rect norect;
  687. int ret, increment = 1;
  688. ret = ttm_read_lock(&vmaster->lock, true);
  689. if (unlikely(ret != 0))
  690. return ret;
  691. if (!num_clips) {
  692. num_clips = 1;
  693. clips = &norect;
  694. norect.x1 = norect.y1 = 0;
  695. norect.x2 = framebuffer->width;
  696. norect.y2 = framebuffer->height;
  697. } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
  698. num_clips /= 2;
  699. increment = 2;
  700. }
  701. if (dev_priv->ldu_priv) {
  702. ret = do_dmabuf_dirty_ldu(dev_priv, &vfbd->base,
  703. flags, color,
  704. clips, num_clips, increment);
  705. } else {
  706. ret = do_dmabuf_dirty_sou(file_priv, dev_priv, &vfbd->base,
  707. flags, color,
  708. clips, num_clips, increment);
  709. }
  710. ttm_read_unlock(&vmaster->lock);
  711. return ret;
  712. }
  713. static struct drm_framebuffer_funcs vmw_framebuffer_dmabuf_funcs = {
  714. .destroy = vmw_framebuffer_dmabuf_destroy,
  715. .dirty = vmw_framebuffer_dmabuf_dirty,
  716. .create_handle = vmw_framebuffer_create_handle,
  717. };
  718. /**
  719. * Pin the dmabuffer to the start of vram.
  720. */
  721. static int vmw_framebuffer_dmabuf_pin(struct vmw_framebuffer *vfb)
  722. {
  723. struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
  724. struct vmw_framebuffer_dmabuf *vfbd =
  725. vmw_framebuffer_to_vfbd(&vfb->base);
  726. int ret;
  727. /* This code should not be used with screen objects */
  728. BUG_ON(dev_priv->sou_priv);
  729. vmw_overlay_pause_all(dev_priv);
  730. ret = vmw_dmabuf_to_start_of_vram(dev_priv, vfbd->buffer, true, false);
  731. vmw_overlay_resume_all(dev_priv);
  732. WARN_ON(ret != 0);
  733. return 0;
  734. }
  735. static int vmw_framebuffer_dmabuf_unpin(struct vmw_framebuffer *vfb)
  736. {
  737. struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
  738. struct vmw_framebuffer_dmabuf *vfbd =
  739. vmw_framebuffer_to_vfbd(&vfb->base);
  740. if (!vfbd->buffer) {
  741. WARN_ON(!vfbd->buffer);
  742. return 0;
  743. }
  744. return vmw_dmabuf_unpin(dev_priv, vfbd->buffer, false);
  745. }
  746. static int vmw_kms_new_framebuffer_dmabuf(struct vmw_private *dev_priv,
  747. struct vmw_dma_buffer *dmabuf,
  748. struct vmw_framebuffer **out,
  749. const struct drm_mode_fb_cmd
  750. *mode_cmd)
  751. {
  752. struct drm_device *dev = dev_priv->dev;
  753. struct vmw_framebuffer_dmabuf *vfbd;
  754. unsigned int requested_size;
  755. int ret;
  756. requested_size = mode_cmd->height * mode_cmd->pitch;
  757. if (unlikely(requested_size > dmabuf->base.num_pages * PAGE_SIZE)) {
  758. DRM_ERROR("Screen buffer object size is too small "
  759. "for requested mode.\n");
  760. return -EINVAL;
  761. }
  762. /* Limited framebuffer color depth support for screen objects */
  763. if (dev_priv->sou_priv) {
  764. switch (mode_cmd->depth) {
  765. case 32:
  766. case 24:
  767. /* Only support 32 bpp for 32 and 24 depth fbs */
  768. if (mode_cmd->bpp == 32)
  769. break;
  770. DRM_ERROR("Invalid color depth/bbp: %d %d\n",
  771. mode_cmd->depth, mode_cmd->bpp);
  772. return -EINVAL;
  773. case 16:
  774. case 15:
  775. /* Only support 16 bpp for 16 and 15 depth fbs */
  776. if (mode_cmd->bpp == 16)
  777. break;
  778. DRM_ERROR("Invalid color depth/bbp: %d %d\n",
  779. mode_cmd->depth, mode_cmd->bpp);
  780. return -EINVAL;
  781. default:
  782. DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
  783. return -EINVAL;
  784. }
  785. }
  786. vfbd = kzalloc(sizeof(*vfbd), GFP_KERNEL);
  787. if (!vfbd) {
  788. ret = -ENOMEM;
  789. goto out_err1;
  790. }
  791. ret = drm_framebuffer_init(dev, &vfbd->base.base,
  792. &vmw_framebuffer_dmabuf_funcs);
  793. if (ret)
  794. goto out_err2;
  795. if (!vmw_dmabuf_reference(dmabuf)) {
  796. DRM_ERROR("failed to reference dmabuf %p\n", dmabuf);
  797. goto out_err3;
  798. }
  799. vfbd->base.base.bits_per_pixel = mode_cmd->bpp;
  800. vfbd->base.base.pitches[0] = mode_cmd->pitch;
  801. vfbd->base.base.depth = mode_cmd->depth;
  802. vfbd->base.base.width = mode_cmd->width;
  803. vfbd->base.base.height = mode_cmd->height;
  804. if (!dev_priv->sou_priv) {
  805. vfbd->base.pin = vmw_framebuffer_dmabuf_pin;
  806. vfbd->base.unpin = vmw_framebuffer_dmabuf_unpin;
  807. }
  808. vfbd->base.dmabuf = true;
  809. vfbd->buffer = dmabuf;
  810. vfbd->base.user_handle = mode_cmd->handle;
  811. *out = &vfbd->base;
  812. return 0;
  813. out_err3:
  814. drm_framebuffer_cleanup(&vfbd->base.base);
  815. out_err2:
  816. kfree(vfbd);
  817. out_err1:
  818. return ret;
  819. }
  820. /*
  821. * Generic Kernel modesetting functions
  822. */
  823. static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
  824. struct drm_file *file_priv,
  825. struct drm_mode_fb_cmd2 *mode_cmd2)
  826. {
  827. struct vmw_private *dev_priv = vmw_priv(dev);
  828. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  829. struct vmw_framebuffer *vfb = NULL;
  830. struct vmw_surface *surface = NULL;
  831. struct vmw_dma_buffer *bo = NULL;
  832. struct ttm_base_object *user_obj;
  833. struct drm_mode_fb_cmd mode_cmd;
  834. u64 required_size;
  835. int ret;
  836. mode_cmd.width = mode_cmd2->width;
  837. mode_cmd.height = mode_cmd2->height;
  838. mode_cmd.pitch = mode_cmd2->pitches[0];
  839. mode_cmd.handle = mode_cmd2->handles[0];
  840. drm_fb_get_bpp_depth(mode_cmd2->pixel_format, &mode_cmd.depth,
  841. &mode_cmd.bpp);
  842. /**
  843. * This code should be conditioned on Screen Objects not being used.
  844. * If screen objects are used, we can allocate a GMR to hold the
  845. * requested framebuffer.
  846. */
  847. required_size = mode_cmd.pitch * mode_cmd.height;
  848. if (unlikely(required_size > (u64) dev_priv->vram_size)) {
  849. DRM_ERROR("VRAM size is too small for requested mode.\n");
  850. return ERR_PTR(-ENOMEM);
  851. }
  852. /*
  853. * Take a reference on the user object of the resource
  854. * backing the kms fb. This ensures that user-space handle
  855. * lookups on that resource will always work as long as
  856. * it's registered with a kms framebuffer. This is important,
  857. * since vmw_execbuf_process identifies resources in the
  858. * command stream using user-space handles.
  859. */
  860. user_obj = ttm_base_object_lookup(tfile, mode_cmd.handle);
  861. if (unlikely(user_obj == NULL)) {
  862. DRM_ERROR("Could not locate requested kms frame buffer.\n");
  863. return ERR_PTR(-ENOENT);
  864. }
  865. /**
  866. * End conditioned code.
  867. */
  868. ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
  869. mode_cmd.handle, &surface);
  870. if (ret)
  871. goto try_dmabuf;
  872. if (!surface->scanout)
  873. goto err_not_scanout;
  874. ret = vmw_kms_new_framebuffer_surface(dev_priv, file_priv, surface,
  875. &vfb, &mode_cmd);
  876. /* vmw_user_surface_lookup takes one ref so does new_fb */
  877. vmw_surface_unreference(&surface);
  878. if (ret) {
  879. DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
  880. ttm_base_object_unref(&user_obj);
  881. return ERR_PTR(ret);
  882. } else
  883. vfb->user_obj = user_obj;
  884. return &vfb->base;
  885. try_dmabuf:
  886. DRM_INFO("%s: trying buffer\n", __func__);
  887. ret = vmw_user_dmabuf_lookup(tfile, mode_cmd.handle, &bo);
  888. if (ret) {
  889. DRM_ERROR("failed to find buffer: %i\n", ret);
  890. return ERR_PTR(-ENOENT);
  891. }
  892. ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb,
  893. &mode_cmd);
  894. /* vmw_user_dmabuf_lookup takes one ref so does new_fb */
  895. vmw_dmabuf_unreference(&bo);
  896. if (ret) {
  897. DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
  898. ttm_base_object_unref(&user_obj);
  899. return ERR_PTR(ret);
  900. } else
  901. vfb->user_obj = user_obj;
  902. return &vfb->base;
  903. err_not_scanout:
  904. DRM_ERROR("surface not marked as scanout\n");
  905. /* vmw_user_surface_lookup takes one ref */
  906. vmw_surface_unreference(&surface);
  907. ttm_base_object_unref(&user_obj);
  908. return ERR_PTR(-EINVAL);
  909. }
  910. static struct drm_mode_config_funcs vmw_kms_funcs = {
  911. .fb_create = vmw_kms_fb_create,
  912. };
  913. int vmw_kms_present(struct vmw_private *dev_priv,
  914. struct drm_file *file_priv,
  915. struct vmw_framebuffer *vfb,
  916. struct vmw_surface *surface,
  917. uint32_t sid,
  918. int32_t destX, int32_t destY,
  919. struct drm_vmw_rect *clips,
  920. uint32_t num_clips)
  921. {
  922. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  923. struct drm_crtc *crtc;
  924. size_t fifo_size;
  925. int i, k, num_units;
  926. int ret = 0; /* silence warning */
  927. struct {
  928. SVGA3dCmdHeader header;
  929. SVGA3dCmdBlitSurfaceToScreen body;
  930. } *cmd;
  931. SVGASignedRect *blits;
  932. num_units = 0;
  933. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  934. if (crtc->fb != &vfb->base)
  935. continue;
  936. units[num_units++] = vmw_crtc_to_du(crtc);
  937. }
  938. BUG_ON(surface == NULL);
  939. BUG_ON(!clips || !num_clips);
  940. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
  941. cmd = kmalloc(fifo_size, GFP_KERNEL);
  942. if (unlikely(cmd == NULL)) {
  943. DRM_ERROR("Failed to allocate temporary fifo memory.\n");
  944. return -ENOMEM;
  945. }
  946. /* only need to do this once */
  947. memset(cmd, 0, fifo_size);
  948. cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
  949. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  950. cmd->body.srcRect.left = 0;
  951. cmd->body.srcRect.right = surface->sizes[0].width;
  952. cmd->body.srcRect.top = 0;
  953. cmd->body.srcRect.bottom = surface->sizes[0].height;
  954. blits = (SVGASignedRect *)&cmd[1];
  955. for (i = 0; i < num_clips; i++) {
  956. blits[i].left = clips[i].x;
  957. blits[i].right = clips[i].x + clips[i].w;
  958. blits[i].top = clips[i].y;
  959. blits[i].bottom = clips[i].y + clips[i].h;
  960. }
  961. for (k = 0; k < num_units; k++) {
  962. struct vmw_display_unit *unit = units[k];
  963. int clip_x1 = destX - unit->crtc.x;
  964. int clip_y1 = destY - unit->crtc.y;
  965. int clip_x2 = clip_x1 + surface->sizes[0].width;
  966. int clip_y2 = clip_y1 + surface->sizes[0].height;
  967. /* skip any crtcs that misses the clip region */
  968. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  969. clip_y1 >= unit->crtc.mode.vdisplay ||
  970. clip_x2 <= 0 || clip_y2 <= 0)
  971. continue;
  972. /* need to reset sid as it is changed by execbuf */
  973. cmd->body.srcImage.sid = sid;
  974. cmd->body.destScreenId = unit->unit;
  975. /*
  976. * The blit command is a lot more resilient then the
  977. * readback command when it comes to clip rects. So its
  978. * okay to go out of bounds.
  979. */
  980. cmd->body.destRect.left = clip_x1;
  981. cmd->body.destRect.right = clip_x2;
  982. cmd->body.destRect.top = clip_y1;
  983. cmd->body.destRect.bottom = clip_y2;
  984. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  985. fifo_size, 0, NULL);
  986. if (unlikely(ret != 0))
  987. break;
  988. }
  989. kfree(cmd);
  990. return ret;
  991. }
  992. int vmw_kms_readback(struct vmw_private *dev_priv,
  993. struct drm_file *file_priv,
  994. struct vmw_framebuffer *vfb,
  995. struct drm_vmw_fence_rep __user *user_fence_rep,
  996. struct drm_vmw_rect *clips,
  997. uint32_t num_clips)
  998. {
  999. struct vmw_framebuffer_dmabuf *vfbd =
  1000. vmw_framebuffer_to_vfbd(&vfb->base);
  1001. struct vmw_dma_buffer *dmabuf = vfbd->buffer;
  1002. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  1003. struct drm_crtc *crtc;
  1004. size_t fifo_size;
  1005. int i, k, ret, num_units, blits_pos;
  1006. struct {
  1007. uint32_t header;
  1008. SVGAFifoCmdDefineGMRFB body;
  1009. } *cmd;
  1010. struct {
  1011. uint32_t header;
  1012. SVGAFifoCmdBlitScreenToGMRFB body;
  1013. } *blits;
  1014. num_units = 0;
  1015. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  1016. if (crtc->fb != &vfb->base)
  1017. continue;
  1018. units[num_units++] = vmw_crtc_to_du(crtc);
  1019. }
  1020. BUG_ON(dmabuf == NULL);
  1021. BUG_ON(!clips || !num_clips);
  1022. /* take a safe guess at fifo size */
  1023. fifo_size = sizeof(*cmd) + sizeof(*blits) * num_clips * num_units;
  1024. cmd = kmalloc(fifo_size, GFP_KERNEL);
  1025. if (unlikely(cmd == NULL)) {
  1026. DRM_ERROR("Failed to allocate temporary fifo memory.\n");
  1027. return -ENOMEM;
  1028. }
  1029. memset(cmd, 0, fifo_size);
  1030. cmd->header = SVGA_CMD_DEFINE_GMRFB;
  1031. cmd->body.format.bitsPerPixel = vfb->base.bits_per_pixel;
  1032. cmd->body.format.colorDepth = vfb->base.depth;
  1033. cmd->body.format.reserved = 0;
  1034. cmd->body.bytesPerLine = vfb->base.pitches[0];
  1035. cmd->body.ptr.gmrId = vfb->user_handle;
  1036. cmd->body.ptr.offset = 0;
  1037. blits = (void *)&cmd[1];
  1038. blits_pos = 0;
  1039. for (i = 0; i < num_units; i++) {
  1040. struct drm_vmw_rect *c = clips;
  1041. for (k = 0; k < num_clips; k++, c++) {
  1042. /* transform clip coords to crtc origin based coords */
  1043. int clip_x1 = c->x - units[i]->crtc.x;
  1044. int clip_x2 = c->x - units[i]->crtc.x + c->w;
  1045. int clip_y1 = c->y - units[i]->crtc.y;
  1046. int clip_y2 = c->y - units[i]->crtc.y + c->h;
  1047. int dest_x = c->x;
  1048. int dest_y = c->y;
  1049. /* compensate for clipping, we negate
  1050. * a negative number and add that.
  1051. */
  1052. if (clip_x1 < 0)
  1053. dest_x += -clip_x1;
  1054. if (clip_y1 < 0)
  1055. dest_y += -clip_y1;
  1056. /* clip */
  1057. clip_x1 = max(clip_x1, 0);
  1058. clip_y1 = max(clip_y1, 0);
  1059. clip_x2 = min(clip_x2, units[i]->crtc.mode.hdisplay);
  1060. clip_y2 = min(clip_y2, units[i]->crtc.mode.vdisplay);
  1061. /* and cull any rects that misses the crtc */
  1062. if (clip_x1 >= units[i]->crtc.mode.hdisplay ||
  1063. clip_y1 >= units[i]->crtc.mode.vdisplay ||
  1064. clip_x2 <= 0 || clip_y2 <= 0)
  1065. continue;
  1066. blits[blits_pos].header = SVGA_CMD_BLIT_SCREEN_TO_GMRFB;
  1067. blits[blits_pos].body.srcScreenId = units[i]->unit;
  1068. blits[blits_pos].body.destOrigin.x = dest_x;
  1069. blits[blits_pos].body.destOrigin.y = dest_y;
  1070. blits[blits_pos].body.srcRect.left = clip_x1;
  1071. blits[blits_pos].body.srcRect.top = clip_y1;
  1072. blits[blits_pos].body.srcRect.right = clip_x2;
  1073. blits[blits_pos].body.srcRect.bottom = clip_y2;
  1074. blits_pos++;
  1075. }
  1076. }
  1077. /* reset size here and use calculated exact size from loops */
  1078. fifo_size = sizeof(*cmd) + sizeof(*blits) * blits_pos;
  1079. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd, fifo_size,
  1080. 0, user_fence_rep);
  1081. kfree(cmd);
  1082. return ret;
  1083. }
  1084. int vmw_kms_init(struct vmw_private *dev_priv)
  1085. {
  1086. struct drm_device *dev = dev_priv->dev;
  1087. int ret;
  1088. drm_mode_config_init(dev);
  1089. dev->mode_config.funcs = &vmw_kms_funcs;
  1090. dev->mode_config.min_width = 1;
  1091. dev->mode_config.min_height = 1;
  1092. /* assumed largest fb size */
  1093. dev->mode_config.max_width = 8192;
  1094. dev->mode_config.max_height = 8192;
  1095. ret = vmw_kms_init_screen_object_display(dev_priv);
  1096. if (ret) /* Fallback */
  1097. (void)vmw_kms_init_legacy_display_system(dev_priv);
  1098. return 0;
  1099. }
  1100. int vmw_kms_close(struct vmw_private *dev_priv)
  1101. {
  1102. /*
  1103. * Docs says we should take the lock before calling this function
  1104. * but since it destroys encoders and our destructor calls
  1105. * drm_encoder_cleanup which takes the lock we deadlock.
  1106. */
  1107. drm_mode_config_cleanup(dev_priv->dev);
  1108. if (dev_priv->sou_priv)
  1109. vmw_kms_close_screen_object_display(dev_priv);
  1110. else
  1111. vmw_kms_close_legacy_display_system(dev_priv);
  1112. return 0;
  1113. }
  1114. int vmw_kms_cursor_bypass_ioctl(struct drm_device *dev, void *data,
  1115. struct drm_file *file_priv)
  1116. {
  1117. struct drm_vmw_cursor_bypass_arg *arg = data;
  1118. struct vmw_display_unit *du;
  1119. struct drm_mode_object *obj;
  1120. struct drm_crtc *crtc;
  1121. int ret = 0;
  1122. mutex_lock(&dev->mode_config.mutex);
  1123. if (arg->flags & DRM_VMW_CURSOR_BYPASS_ALL) {
  1124. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1125. du = vmw_crtc_to_du(crtc);
  1126. du->hotspot_x = arg->xhot;
  1127. du->hotspot_y = arg->yhot;
  1128. }
  1129. mutex_unlock(&dev->mode_config.mutex);
  1130. return 0;
  1131. }
  1132. obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
  1133. if (!obj) {
  1134. ret = -EINVAL;
  1135. goto out;
  1136. }
  1137. crtc = obj_to_crtc(obj);
  1138. du = vmw_crtc_to_du(crtc);
  1139. du->hotspot_x = arg->xhot;
  1140. du->hotspot_y = arg->yhot;
  1141. out:
  1142. mutex_unlock(&dev->mode_config.mutex);
  1143. return ret;
  1144. }
  1145. int vmw_kms_write_svga(struct vmw_private *vmw_priv,
  1146. unsigned width, unsigned height, unsigned pitch,
  1147. unsigned bpp, unsigned depth)
  1148. {
  1149. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1150. vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);
  1151. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1152. iowrite32(pitch, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
  1153. vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
  1154. vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
  1155. vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
  1156. if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {
  1157. DRM_ERROR("Invalid depth %u for %u bpp, host expects %u\n",
  1158. depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH));
  1159. return -EINVAL;
  1160. }
  1161. return 0;
  1162. }
  1163. int vmw_kms_save_vga(struct vmw_private *vmw_priv)
  1164. {
  1165. struct vmw_vga_topology_state *save;
  1166. uint32_t i;
  1167. vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);
  1168. vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT);
  1169. vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL);
  1170. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1171. vmw_priv->vga_pitchlock =
  1172. vmw_read(vmw_priv, SVGA_REG_PITCHLOCK);
  1173. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1174. vmw_priv->vga_pitchlock = ioread32(vmw_priv->mmio_virt +
  1175. SVGA_FIFO_PITCHLOCK);
  1176. if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
  1177. return 0;
  1178. vmw_priv->num_displays = vmw_read(vmw_priv,
  1179. SVGA_REG_NUM_GUEST_DISPLAYS);
  1180. if (vmw_priv->num_displays == 0)
  1181. vmw_priv->num_displays = 1;
  1182. for (i = 0; i < vmw_priv->num_displays; ++i) {
  1183. save = &vmw_priv->vga_save[i];
  1184. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
  1185. save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY);
  1186. save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X);
  1187. save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y);
  1188. save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH);
  1189. save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT);
  1190. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
  1191. if (i == 0 && vmw_priv->num_displays == 1 &&
  1192. save->width == 0 && save->height == 0) {
  1193. /*
  1194. * It should be fairly safe to assume that these
  1195. * values are uninitialized.
  1196. */
  1197. save->width = vmw_priv->vga_width - save->pos_x;
  1198. save->height = vmw_priv->vga_height - save->pos_y;
  1199. }
  1200. }
  1201. return 0;
  1202. }
  1203. int vmw_kms_restore_vga(struct vmw_private *vmw_priv)
  1204. {
  1205. struct vmw_vga_topology_state *save;
  1206. uint32_t i;
  1207. vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);
  1208. vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);
  1209. vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);
  1210. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1211. vmw_write(vmw_priv, SVGA_REG_PITCHLOCK,
  1212. vmw_priv->vga_pitchlock);
  1213. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1214. iowrite32(vmw_priv->vga_pitchlock,
  1215. vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
  1216. if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
  1217. return 0;
  1218. for (i = 0; i < vmw_priv->num_displays; ++i) {
  1219. save = &vmw_priv->vga_save[i];
  1220. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
  1221. vmw_write(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY, save->primary);
  1222. vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_X, save->pos_x);
  1223. vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y, save->pos_y);
  1224. vmw_write(vmw_priv, SVGA_REG_DISPLAY_WIDTH, save->width);
  1225. vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, save->height);
  1226. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
  1227. }
  1228. return 0;
  1229. }
  1230. bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
  1231. uint32_t pitch,
  1232. uint32_t height)
  1233. {
  1234. return ((u64) pitch * (u64) height) < (u64) dev_priv->vram_size;
  1235. }
  1236. /**
  1237. * Function called by DRM code called with vbl_lock held.
  1238. */
  1239. u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc)
  1240. {
  1241. return 0;
  1242. }
  1243. /**
  1244. * Function called by DRM code called with vbl_lock held.
  1245. */
  1246. int vmw_enable_vblank(struct drm_device *dev, int crtc)
  1247. {
  1248. return -ENOSYS;
  1249. }
  1250. /**
  1251. * Function called by DRM code called with vbl_lock held.
  1252. */
  1253. void vmw_disable_vblank(struct drm_device *dev, int crtc)
  1254. {
  1255. }
  1256. /*
  1257. * Small shared kms functions.
  1258. */
  1259. int vmw_du_update_layout(struct vmw_private *dev_priv, unsigned num,
  1260. struct drm_vmw_rect *rects)
  1261. {
  1262. struct drm_device *dev = dev_priv->dev;
  1263. struct vmw_display_unit *du;
  1264. struct drm_connector *con;
  1265. mutex_lock(&dev->mode_config.mutex);
  1266. #if 0
  1267. {
  1268. unsigned int i;
  1269. DRM_INFO("%s: new layout ", __func__);
  1270. for (i = 0; i < num; i++)
  1271. DRM_INFO("(%i, %i %ux%u) ", rects[i].x, rects[i].y,
  1272. rects[i].w, rects[i].h);
  1273. DRM_INFO("\n");
  1274. }
  1275. #endif
  1276. list_for_each_entry(con, &dev->mode_config.connector_list, head) {
  1277. du = vmw_connector_to_du(con);
  1278. if (num > du->unit) {
  1279. du->pref_width = rects[du->unit].w;
  1280. du->pref_height = rects[du->unit].h;
  1281. du->pref_active = true;
  1282. du->gui_x = rects[du->unit].x;
  1283. du->gui_y = rects[du->unit].y;
  1284. } else {
  1285. du->pref_width = 800;
  1286. du->pref_height = 600;
  1287. du->pref_active = false;
  1288. }
  1289. con->status = vmw_du_connector_detect(con, true);
  1290. }
  1291. mutex_unlock(&dev->mode_config.mutex);
  1292. return 0;
  1293. }
  1294. void vmw_du_crtc_save(struct drm_crtc *crtc)
  1295. {
  1296. }
  1297. void vmw_du_crtc_restore(struct drm_crtc *crtc)
  1298. {
  1299. }
  1300. void vmw_du_crtc_gamma_set(struct drm_crtc *crtc,
  1301. u16 *r, u16 *g, u16 *b,
  1302. uint32_t start, uint32_t size)
  1303. {
  1304. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  1305. int i;
  1306. for (i = 0; i < size; i++) {
  1307. DRM_DEBUG("%d r/g/b = 0x%04x / 0x%04x / 0x%04x\n", i,
  1308. r[i], g[i], b[i]);
  1309. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8);
  1310. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8);
  1311. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8);
  1312. }
  1313. }
  1314. void vmw_du_connector_dpms(struct drm_connector *connector, int mode)
  1315. {
  1316. }
  1317. void vmw_du_connector_save(struct drm_connector *connector)
  1318. {
  1319. }
  1320. void vmw_du_connector_restore(struct drm_connector *connector)
  1321. {
  1322. }
  1323. enum drm_connector_status
  1324. vmw_du_connector_detect(struct drm_connector *connector, bool force)
  1325. {
  1326. uint32_t num_displays;
  1327. struct drm_device *dev = connector->dev;
  1328. struct vmw_private *dev_priv = vmw_priv(dev);
  1329. struct vmw_display_unit *du = vmw_connector_to_du(connector);
  1330. mutex_lock(&dev_priv->hw_mutex);
  1331. num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);
  1332. mutex_unlock(&dev_priv->hw_mutex);
  1333. return ((vmw_connector_to_du(connector)->unit < num_displays &&
  1334. du->pref_active) ?
  1335. connector_status_connected : connector_status_disconnected);
  1336. }
  1337. static struct drm_display_mode vmw_kms_connector_builtin[] = {
  1338. /* 640x480@60Hz */
  1339. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
  1340. 752, 800, 0, 480, 489, 492, 525, 0,
  1341. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1342. /* 800x600@60Hz */
  1343. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
  1344. 968, 1056, 0, 600, 601, 605, 628, 0,
  1345. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1346. /* 1024x768@60Hz */
  1347. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
  1348. 1184, 1344, 0, 768, 771, 777, 806, 0,
  1349. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1350. /* 1152x864@75Hz */
  1351. { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
  1352. 1344, 1600, 0, 864, 865, 868, 900, 0,
  1353. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1354. /* 1280x768@60Hz */
  1355. { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
  1356. 1472, 1664, 0, 768, 771, 778, 798, 0,
  1357. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1358. /* 1280x800@60Hz */
  1359. { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
  1360. 1480, 1680, 0, 800, 803, 809, 831, 0,
  1361. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1362. /* 1280x960@60Hz */
  1363. { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
  1364. 1488, 1800, 0, 960, 961, 964, 1000, 0,
  1365. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1366. /* 1280x1024@60Hz */
  1367. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
  1368. 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
  1369. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1370. /* 1360x768@60Hz */
  1371. { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
  1372. 1536, 1792, 0, 768, 771, 777, 795, 0,
  1373. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1374. /* 1440x1050@60Hz */
  1375. { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
  1376. 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
  1377. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1378. /* 1440x900@60Hz */
  1379. { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
  1380. 1672, 1904, 0, 900, 903, 909, 934, 0,
  1381. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1382. /* 1600x1200@60Hz */
  1383. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
  1384. 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
  1385. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1386. /* 1680x1050@60Hz */
  1387. { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
  1388. 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
  1389. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1390. /* 1792x1344@60Hz */
  1391. { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
  1392. 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
  1393. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1394. /* 1853x1392@60Hz */
  1395. { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
  1396. 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
  1397. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1398. /* 1920x1200@60Hz */
  1399. { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
  1400. 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
  1401. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1402. /* 1920x1440@60Hz */
  1403. { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
  1404. 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
  1405. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1406. /* 2560x1600@60Hz */
  1407. { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
  1408. 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
  1409. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1410. /* Terminate */
  1411. { DRM_MODE("", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) },
  1412. };
  1413. /**
  1414. * vmw_guess_mode_timing - Provide fake timings for a
  1415. * 60Hz vrefresh mode.
  1416. *
  1417. * @mode - Pointer to a struct drm_display_mode with hdisplay and vdisplay
  1418. * members filled in.
  1419. */
  1420. static void vmw_guess_mode_timing(struct drm_display_mode *mode)
  1421. {
  1422. mode->hsync_start = mode->hdisplay + 50;
  1423. mode->hsync_end = mode->hsync_start + 50;
  1424. mode->htotal = mode->hsync_end + 50;
  1425. mode->vsync_start = mode->vdisplay + 50;
  1426. mode->vsync_end = mode->vsync_start + 50;
  1427. mode->vtotal = mode->vsync_end + 50;
  1428. mode->clock = (u32)mode->htotal * (u32)mode->vtotal / 100 * 6;
  1429. mode->vrefresh = drm_mode_vrefresh(mode);
  1430. }
  1431. int vmw_du_connector_fill_modes(struct drm_connector *connector,
  1432. uint32_t max_width, uint32_t max_height)
  1433. {
  1434. struct vmw_display_unit *du = vmw_connector_to_du(connector);
  1435. struct drm_device *dev = connector->dev;
  1436. struct vmw_private *dev_priv = vmw_priv(dev);
  1437. struct drm_display_mode *mode = NULL;
  1438. struct drm_display_mode *bmode;
  1439. struct drm_display_mode prefmode = { DRM_MODE("preferred",
  1440. DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
  1441. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  1442. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)
  1443. };
  1444. int i;
  1445. /* Add preferred mode */
  1446. {
  1447. mode = drm_mode_duplicate(dev, &prefmode);
  1448. if (!mode)
  1449. return 0;
  1450. mode->hdisplay = du->pref_width;
  1451. mode->vdisplay = du->pref_height;
  1452. vmw_guess_mode_timing(mode);
  1453. if (vmw_kms_validate_mode_vram(dev_priv, mode->hdisplay * 2,
  1454. mode->vdisplay)) {
  1455. drm_mode_probed_add(connector, mode);
  1456. } else {
  1457. drm_mode_destroy(dev, mode);
  1458. mode = NULL;
  1459. }
  1460. if (du->pref_mode) {
  1461. list_del_init(&du->pref_mode->head);
  1462. drm_mode_destroy(dev, du->pref_mode);
  1463. }
  1464. /* mode might be null here, this is intended */
  1465. du->pref_mode = mode;
  1466. }
  1467. for (i = 0; vmw_kms_connector_builtin[i].type != 0; i++) {
  1468. bmode = &vmw_kms_connector_builtin[i];
  1469. if (bmode->hdisplay > max_width ||
  1470. bmode->vdisplay > max_height)
  1471. continue;
  1472. if (!vmw_kms_validate_mode_vram(dev_priv, bmode->hdisplay * 2,
  1473. bmode->vdisplay))
  1474. continue;
  1475. mode = drm_mode_duplicate(dev, bmode);
  1476. if (!mode)
  1477. return 0;
  1478. mode->vrefresh = drm_mode_vrefresh(mode);
  1479. drm_mode_probed_add(connector, mode);
  1480. }
  1481. /* Move the prefered mode first, help apps pick the right mode. */
  1482. if (du->pref_mode)
  1483. list_move(&du->pref_mode->head, &connector->probed_modes);
  1484. drm_mode_connector_list_update(connector);
  1485. return 1;
  1486. }
  1487. int vmw_du_connector_set_property(struct drm_connector *connector,
  1488. struct drm_property *property,
  1489. uint64_t val)
  1490. {
  1491. return 0;
  1492. }
  1493. int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
  1494. struct drm_file *file_priv)
  1495. {
  1496. struct vmw_private *dev_priv = vmw_priv(dev);
  1497. struct drm_vmw_update_layout_arg *arg =
  1498. (struct drm_vmw_update_layout_arg *)data;
  1499. struct vmw_master *vmaster = vmw_master(file_priv->master);
  1500. void __user *user_rects;
  1501. struct drm_vmw_rect *rects;
  1502. unsigned rects_size;
  1503. int ret;
  1504. int i;
  1505. struct drm_mode_config *mode_config = &dev->mode_config;
  1506. ret = ttm_read_lock(&vmaster->lock, true);
  1507. if (unlikely(ret != 0))
  1508. return ret;
  1509. if (!arg->num_outputs) {
  1510. struct drm_vmw_rect def_rect = {0, 0, 800, 600};
  1511. vmw_du_update_layout(dev_priv, 1, &def_rect);
  1512. goto out_unlock;
  1513. }
  1514. rects_size = arg->num_outputs * sizeof(struct drm_vmw_rect);
  1515. rects = kcalloc(arg->num_outputs, sizeof(struct drm_vmw_rect),
  1516. GFP_KERNEL);
  1517. if (unlikely(!rects)) {
  1518. ret = -ENOMEM;
  1519. goto out_unlock;
  1520. }
  1521. user_rects = (void __user *)(unsigned long)arg->rects;
  1522. ret = copy_from_user(rects, user_rects, rects_size);
  1523. if (unlikely(ret != 0)) {
  1524. DRM_ERROR("Failed to get rects.\n");
  1525. ret = -EFAULT;
  1526. goto out_free;
  1527. }
  1528. for (i = 0; i < arg->num_outputs; ++i) {
  1529. if (rects[i].x < 0 ||
  1530. rects[i].y < 0 ||
  1531. rects[i].x + rects[i].w > mode_config->max_width ||
  1532. rects[i].y + rects[i].h > mode_config->max_height) {
  1533. DRM_ERROR("Invalid GUI layout.\n");
  1534. ret = -EINVAL;
  1535. goto out_free;
  1536. }
  1537. }
  1538. vmw_du_update_layout(dev_priv, arg->num_outputs, rects);
  1539. out_free:
  1540. kfree(rects);
  1541. out_unlock:
  1542. ttm_read_unlock(&vmaster->lock);
  1543. return ret;
  1544. }