radeon_fence.c 14 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Dave Airlie
  30. */
  31. #include <linux/seq_file.h>
  32. #include <linux/atomic.h>
  33. #include <linux/wait.h>
  34. #include <linux/list.h>
  35. #include <linux/kref.h>
  36. #include <linux/slab.h>
  37. #include "drmP.h"
  38. #include "drm.h"
  39. #include "radeon_reg.h"
  40. #include "radeon.h"
  41. #include "radeon_trace.h"
  42. static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
  43. {
  44. if (rdev->wb.enabled) {
  45. *rdev->fence_drv[ring].cpu_addr = cpu_to_le32(seq);
  46. } else {
  47. WREG32(rdev->fence_drv[ring].scratch_reg, seq);
  48. }
  49. }
  50. static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
  51. {
  52. u32 seq = 0;
  53. if (rdev->wb.enabled) {
  54. seq = le32_to_cpu(*rdev->fence_drv[ring].cpu_addr);
  55. } else {
  56. seq = RREG32(rdev->fence_drv[ring].scratch_reg);
  57. }
  58. return seq;
  59. }
  60. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
  61. {
  62. unsigned long irq_flags;
  63. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  64. if (fence->emitted) {
  65. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  66. return 0;
  67. }
  68. fence->seq = atomic_add_return(1, &rdev->fence_drv[fence->ring].seq);
  69. if (!rdev->ring[fence->ring].ready)
  70. /* FIXME: cp is not running assume everythings is done right
  71. * away
  72. */
  73. radeon_fence_write(rdev, fence->seq, fence->ring);
  74. else
  75. radeon_fence_ring_emit(rdev, fence->ring, fence);
  76. trace_radeon_fence_emit(rdev->ddev, fence->seq);
  77. fence->emitted = true;
  78. list_move_tail(&fence->list, &rdev->fence_drv[fence->ring].emitted);
  79. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  80. return 0;
  81. }
  82. static bool radeon_fence_poll_locked(struct radeon_device *rdev, int ring)
  83. {
  84. struct radeon_fence *fence;
  85. struct list_head *i, *n;
  86. uint32_t seq;
  87. bool wake = false;
  88. unsigned long cjiffies;
  89. seq = radeon_fence_read(rdev, ring);
  90. if (seq != rdev->fence_drv[ring].last_seq) {
  91. rdev->fence_drv[ring].last_seq = seq;
  92. rdev->fence_drv[ring].last_jiffies = jiffies;
  93. rdev->fence_drv[ring].last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  94. } else {
  95. cjiffies = jiffies;
  96. if (time_after(cjiffies, rdev->fence_drv[ring].last_jiffies)) {
  97. cjiffies -= rdev->fence_drv[ring].last_jiffies;
  98. if (time_after(rdev->fence_drv[ring].last_timeout, cjiffies)) {
  99. /* update the timeout */
  100. rdev->fence_drv[ring].last_timeout -= cjiffies;
  101. } else {
  102. /* the 500ms timeout is elapsed we should test
  103. * for GPU lockup
  104. */
  105. rdev->fence_drv[ring].last_timeout = 1;
  106. }
  107. } else {
  108. /* wrap around update last jiffies, we will just wait
  109. * a little longer
  110. */
  111. rdev->fence_drv[ring].last_jiffies = cjiffies;
  112. }
  113. return false;
  114. }
  115. n = NULL;
  116. list_for_each(i, &rdev->fence_drv[ring].emitted) {
  117. fence = list_entry(i, struct radeon_fence, list);
  118. if (fence->seq == seq) {
  119. n = i;
  120. break;
  121. }
  122. }
  123. /* all fence previous to this one are considered as signaled */
  124. if (n) {
  125. i = n;
  126. do {
  127. n = i->prev;
  128. list_move_tail(i, &rdev->fence_drv[ring].signaled);
  129. fence = list_entry(i, struct radeon_fence, list);
  130. fence->signaled = true;
  131. i = n;
  132. } while (i != &rdev->fence_drv[ring].emitted);
  133. wake = true;
  134. }
  135. return wake;
  136. }
  137. static void radeon_fence_destroy(struct kref *kref)
  138. {
  139. unsigned long irq_flags;
  140. struct radeon_fence *fence;
  141. fence = container_of(kref, struct radeon_fence, kref);
  142. write_lock_irqsave(&fence->rdev->fence_lock, irq_flags);
  143. list_del(&fence->list);
  144. fence->emitted = false;
  145. write_unlock_irqrestore(&fence->rdev->fence_lock, irq_flags);
  146. kfree(fence);
  147. }
  148. int radeon_fence_create(struct radeon_device *rdev,
  149. struct radeon_fence **fence,
  150. int ring)
  151. {
  152. unsigned long irq_flags;
  153. *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
  154. if ((*fence) == NULL) {
  155. return -ENOMEM;
  156. }
  157. kref_init(&((*fence)->kref));
  158. (*fence)->rdev = rdev;
  159. (*fence)->emitted = false;
  160. (*fence)->signaled = false;
  161. (*fence)->seq = 0;
  162. (*fence)->ring = ring;
  163. INIT_LIST_HEAD(&(*fence)->list);
  164. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  165. list_add_tail(&(*fence)->list, &rdev->fence_drv[ring].created);
  166. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  167. return 0;
  168. }
  169. bool radeon_fence_signaled(struct radeon_fence *fence)
  170. {
  171. unsigned long irq_flags;
  172. bool signaled = false;
  173. if (!fence)
  174. return true;
  175. if (fence->rdev->gpu_lockup)
  176. return true;
  177. write_lock_irqsave(&fence->rdev->fence_lock, irq_flags);
  178. signaled = fence->signaled;
  179. /* if we are shuting down report all fence as signaled */
  180. if (fence->rdev->shutdown) {
  181. signaled = true;
  182. }
  183. if (!fence->emitted) {
  184. WARN(1, "Querying an unemitted fence : %p !\n", fence);
  185. signaled = true;
  186. }
  187. if (!signaled) {
  188. radeon_fence_poll_locked(fence->rdev, fence->ring);
  189. signaled = fence->signaled;
  190. }
  191. write_unlock_irqrestore(&fence->rdev->fence_lock, irq_flags);
  192. return signaled;
  193. }
  194. int radeon_fence_wait(struct radeon_fence *fence, bool intr)
  195. {
  196. struct radeon_device *rdev;
  197. unsigned long irq_flags, timeout;
  198. u32 seq;
  199. int r;
  200. if (fence == NULL) {
  201. WARN(1, "Querying an invalid fence : %p !\n", fence);
  202. return 0;
  203. }
  204. rdev = fence->rdev;
  205. if (radeon_fence_signaled(fence)) {
  206. return 0;
  207. }
  208. timeout = rdev->fence_drv[fence->ring].last_timeout;
  209. retry:
  210. /* save current sequence used to check for GPU lockup */
  211. seq = rdev->fence_drv[fence->ring].last_seq;
  212. trace_radeon_fence_wait_begin(rdev->ddev, seq);
  213. if (intr) {
  214. radeon_irq_kms_sw_irq_get(rdev, fence->ring);
  215. r = wait_event_interruptible_timeout(rdev->fence_drv[fence->ring].queue,
  216. radeon_fence_signaled(fence), timeout);
  217. radeon_irq_kms_sw_irq_put(rdev, fence->ring);
  218. if (unlikely(r < 0)) {
  219. return r;
  220. }
  221. } else {
  222. radeon_irq_kms_sw_irq_get(rdev, fence->ring);
  223. r = wait_event_timeout(rdev->fence_drv[fence->ring].queue,
  224. radeon_fence_signaled(fence), timeout);
  225. radeon_irq_kms_sw_irq_put(rdev, fence->ring);
  226. }
  227. trace_radeon_fence_wait_end(rdev->ddev, seq);
  228. if (unlikely(!radeon_fence_signaled(fence))) {
  229. /* we were interrupted for some reason and fence isn't
  230. * isn't signaled yet, resume wait
  231. */
  232. if (r) {
  233. timeout = r;
  234. goto retry;
  235. }
  236. /* don't protect read access to rdev->fence_drv[t].last_seq
  237. * if we experiencing a lockup the value doesn't change
  238. */
  239. if (seq == rdev->fence_drv[fence->ring].last_seq &&
  240. radeon_gpu_is_lockup(rdev, &rdev->ring[fence->ring])) {
  241. /* good news we believe it's a lockup */
  242. printk(KERN_WARNING "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n",
  243. fence->seq, seq);
  244. /* FIXME: what should we do ? marking everyone
  245. * as signaled for now
  246. */
  247. rdev->gpu_lockup = true;
  248. r = radeon_gpu_reset(rdev);
  249. if (r)
  250. return r;
  251. radeon_fence_write(rdev, fence->seq, fence->ring);
  252. rdev->gpu_lockup = false;
  253. }
  254. timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  255. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  256. rdev->fence_drv[fence->ring].last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  257. rdev->fence_drv[fence->ring].last_jiffies = jiffies;
  258. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  259. goto retry;
  260. }
  261. return 0;
  262. }
  263. int radeon_fence_wait_next(struct radeon_device *rdev, int ring)
  264. {
  265. unsigned long irq_flags;
  266. struct radeon_fence *fence;
  267. int r;
  268. if (rdev->gpu_lockup) {
  269. return 0;
  270. }
  271. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  272. if (list_empty(&rdev->fence_drv[ring].emitted)) {
  273. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  274. return 0;
  275. }
  276. fence = list_entry(rdev->fence_drv[ring].emitted.next,
  277. struct radeon_fence, list);
  278. radeon_fence_ref(fence);
  279. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  280. r = radeon_fence_wait(fence, false);
  281. radeon_fence_unref(&fence);
  282. return r;
  283. }
  284. int radeon_fence_wait_last(struct radeon_device *rdev, int ring)
  285. {
  286. unsigned long irq_flags;
  287. struct radeon_fence *fence;
  288. int r;
  289. if (rdev->gpu_lockup) {
  290. return 0;
  291. }
  292. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  293. if (list_empty(&rdev->fence_drv[ring].emitted)) {
  294. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  295. return 0;
  296. }
  297. fence = list_entry(rdev->fence_drv[ring].emitted.prev,
  298. struct radeon_fence, list);
  299. radeon_fence_ref(fence);
  300. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  301. r = radeon_fence_wait(fence, false);
  302. radeon_fence_unref(&fence);
  303. return r;
  304. }
  305. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
  306. {
  307. kref_get(&fence->kref);
  308. return fence;
  309. }
  310. void radeon_fence_unref(struct radeon_fence **fence)
  311. {
  312. struct radeon_fence *tmp = *fence;
  313. *fence = NULL;
  314. if (tmp) {
  315. kref_put(&tmp->kref, radeon_fence_destroy);
  316. }
  317. }
  318. void radeon_fence_process(struct radeon_device *rdev, int ring)
  319. {
  320. unsigned long irq_flags;
  321. bool wake;
  322. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  323. wake = radeon_fence_poll_locked(rdev, ring);
  324. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  325. if (wake) {
  326. wake_up_all(&rdev->fence_drv[ring].queue);
  327. }
  328. }
  329. int radeon_fence_count_emitted(struct radeon_device *rdev, int ring)
  330. {
  331. unsigned long irq_flags;
  332. int not_processed = 0;
  333. read_lock_irqsave(&rdev->fence_lock, irq_flags);
  334. if (!rdev->fence_drv[ring].initialized)
  335. return 0;
  336. if (!list_empty(&rdev->fence_drv[ring].emitted)) {
  337. struct list_head *ptr;
  338. list_for_each(ptr, &rdev->fence_drv[ring].emitted) {
  339. /* count up to 3, that's enought info */
  340. if (++not_processed >= 3)
  341. break;
  342. }
  343. }
  344. read_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  345. return not_processed;
  346. }
  347. int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
  348. {
  349. unsigned long irq_flags;
  350. uint64_t index;
  351. int r;
  352. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  353. radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
  354. if (rdev->wb.use_event) {
  355. rdev->fence_drv[ring].scratch_reg = 0;
  356. index = R600_WB_EVENT_OFFSET + ring * 4;
  357. } else {
  358. r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
  359. if (r) {
  360. dev_err(rdev->dev, "fence failed to get scratch register\n");
  361. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  362. return r;
  363. }
  364. index = RADEON_WB_SCRATCH_OFFSET +
  365. rdev->fence_drv[ring].scratch_reg -
  366. rdev->scratch.reg_base;
  367. }
  368. rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
  369. rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
  370. radeon_fence_write(rdev, atomic_read(&rdev->fence_drv[ring].seq), ring);
  371. rdev->fence_drv[ring].initialized = true;
  372. DRM_INFO("fence driver on ring %d use gpu addr 0x%08Lx and cpu addr 0x%p\n",
  373. ring, rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr);
  374. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  375. return 0;
  376. }
  377. static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)
  378. {
  379. rdev->fence_drv[ring].scratch_reg = -1;
  380. rdev->fence_drv[ring].cpu_addr = NULL;
  381. rdev->fence_drv[ring].gpu_addr = 0;
  382. atomic_set(&rdev->fence_drv[ring].seq, 0);
  383. INIT_LIST_HEAD(&rdev->fence_drv[ring].created);
  384. INIT_LIST_HEAD(&rdev->fence_drv[ring].emitted);
  385. INIT_LIST_HEAD(&rdev->fence_drv[ring].signaled);
  386. init_waitqueue_head(&rdev->fence_drv[ring].queue);
  387. rdev->fence_drv[ring].initialized = false;
  388. }
  389. int radeon_fence_driver_init(struct radeon_device *rdev)
  390. {
  391. unsigned long irq_flags;
  392. int ring;
  393. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  394. for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
  395. radeon_fence_driver_init_ring(rdev, ring);
  396. }
  397. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  398. if (radeon_debugfs_fence_init(rdev)) {
  399. dev_err(rdev->dev, "fence debugfs file creation failed\n");
  400. }
  401. return 0;
  402. }
  403. void radeon_fence_driver_fini(struct radeon_device *rdev)
  404. {
  405. unsigned long irq_flags;
  406. int ring;
  407. for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
  408. if (!rdev->fence_drv[ring].initialized)
  409. continue;
  410. radeon_fence_wait_last(rdev, ring);
  411. wake_up_all(&rdev->fence_drv[ring].queue);
  412. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  413. radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
  414. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  415. rdev->fence_drv[ring].initialized = false;
  416. }
  417. }
  418. /*
  419. * Fence debugfs
  420. */
  421. #if defined(CONFIG_DEBUG_FS)
  422. static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
  423. {
  424. struct drm_info_node *node = (struct drm_info_node *)m->private;
  425. struct drm_device *dev = node->minor->dev;
  426. struct radeon_device *rdev = dev->dev_private;
  427. struct radeon_fence *fence;
  428. int i;
  429. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  430. if (!rdev->fence_drv[i].initialized)
  431. continue;
  432. seq_printf(m, "--- ring %d ---\n", i);
  433. seq_printf(m, "Last signaled fence 0x%08X\n",
  434. radeon_fence_read(rdev, i));
  435. if (!list_empty(&rdev->fence_drv[i].emitted)) {
  436. fence = list_entry(rdev->fence_drv[i].emitted.prev,
  437. struct radeon_fence, list);
  438. seq_printf(m, "Last emitted fence %p with 0x%08X\n",
  439. fence, fence->seq);
  440. }
  441. }
  442. return 0;
  443. }
  444. static struct drm_info_list radeon_debugfs_fence_list[] = {
  445. {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
  446. };
  447. #endif
  448. int radeon_debugfs_fence_init(struct radeon_device *rdev)
  449. {
  450. #if defined(CONFIG_DEBUG_FS)
  451. return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
  452. #else
  453. return 0;
  454. #endif
  455. }