i915_debugfs.c 47 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Keith Packard <keithp@keithp.com>
  26. *
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/debugfs.h>
  30. #include <linux/slab.h>
  31. #include <linux/export.h>
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "intel_drv.h"
  35. #include "intel_ringbuffer.h"
  36. #include "i915_drm.h"
  37. #include "i915_drv.h"
  38. #define DRM_I915_RING_DEBUG 1
  39. #if defined(CONFIG_DEBUG_FS)
  40. enum {
  41. ACTIVE_LIST,
  42. FLUSHING_LIST,
  43. INACTIVE_LIST,
  44. PINNED_LIST,
  45. DEFERRED_FREE_LIST,
  46. };
  47. static const char *yesno(int v)
  48. {
  49. return v ? "yes" : "no";
  50. }
  51. static int i915_capabilities(struct seq_file *m, void *data)
  52. {
  53. struct drm_info_node *node = (struct drm_info_node *) m->private;
  54. struct drm_device *dev = node->minor->dev;
  55. const struct intel_device_info *info = INTEL_INFO(dev);
  56. seq_printf(m, "gen: %d\n", info->gen);
  57. seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  58. #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x))
  59. B(is_mobile);
  60. B(is_i85x);
  61. B(is_i915g);
  62. B(is_i945gm);
  63. B(is_g33);
  64. B(need_gfx_hws);
  65. B(is_g4x);
  66. B(is_pineview);
  67. B(is_broadwater);
  68. B(is_crestline);
  69. B(has_fbc);
  70. B(has_pipe_cxsr);
  71. B(has_hotplug);
  72. B(cursor_needs_physical);
  73. B(has_overlay);
  74. B(overlay_needs_physical);
  75. B(supports_tv);
  76. B(has_bsd_ring);
  77. B(has_blt_ring);
  78. #undef B
  79. return 0;
  80. }
  81. static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  82. {
  83. if (obj->user_pin_count > 0)
  84. return "P";
  85. else if (obj->pin_count > 0)
  86. return "p";
  87. else
  88. return " ";
  89. }
  90. static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
  91. {
  92. switch (obj->tiling_mode) {
  93. default:
  94. case I915_TILING_NONE: return " ";
  95. case I915_TILING_X: return "X";
  96. case I915_TILING_Y: return "Y";
  97. }
  98. }
  99. static const char *cache_level_str(int type)
  100. {
  101. switch (type) {
  102. case I915_CACHE_NONE: return " uncached";
  103. case I915_CACHE_LLC: return " snooped (LLC)";
  104. case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
  105. default: return "";
  106. }
  107. }
  108. static void
  109. describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
  110. {
  111. seq_printf(m, "%p: %s%s %8zd %04x %04x %d %d%s%s%s",
  112. &obj->base,
  113. get_pin_flag(obj),
  114. get_tiling_flag(obj),
  115. obj->base.size,
  116. obj->base.read_domains,
  117. obj->base.write_domain,
  118. obj->last_rendering_seqno,
  119. obj->last_fenced_seqno,
  120. cache_level_str(obj->cache_level),
  121. obj->dirty ? " dirty" : "",
  122. obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
  123. if (obj->base.name)
  124. seq_printf(m, " (name: %d)", obj->base.name);
  125. if (obj->fence_reg != I915_FENCE_REG_NONE)
  126. seq_printf(m, " (fence: %d)", obj->fence_reg);
  127. if (obj->gtt_space != NULL)
  128. seq_printf(m, " (gtt offset: %08x, size: %08x)",
  129. obj->gtt_offset, (unsigned int)obj->gtt_space->size);
  130. if (obj->pin_mappable || obj->fault_mappable) {
  131. char s[3], *t = s;
  132. if (obj->pin_mappable)
  133. *t++ = 'p';
  134. if (obj->fault_mappable)
  135. *t++ = 'f';
  136. *t = '\0';
  137. seq_printf(m, " (%s mappable)", s);
  138. }
  139. if (obj->ring != NULL)
  140. seq_printf(m, " (%s)", obj->ring->name);
  141. }
  142. static int i915_gem_object_list_info(struct seq_file *m, void *data)
  143. {
  144. struct drm_info_node *node = (struct drm_info_node *) m->private;
  145. uintptr_t list = (uintptr_t) node->info_ent->data;
  146. struct list_head *head;
  147. struct drm_device *dev = node->minor->dev;
  148. drm_i915_private_t *dev_priv = dev->dev_private;
  149. struct drm_i915_gem_object *obj;
  150. size_t total_obj_size, total_gtt_size;
  151. int count, ret;
  152. ret = mutex_lock_interruptible(&dev->struct_mutex);
  153. if (ret)
  154. return ret;
  155. switch (list) {
  156. case ACTIVE_LIST:
  157. seq_printf(m, "Active:\n");
  158. head = &dev_priv->mm.active_list;
  159. break;
  160. case INACTIVE_LIST:
  161. seq_printf(m, "Inactive:\n");
  162. head = &dev_priv->mm.inactive_list;
  163. break;
  164. case PINNED_LIST:
  165. seq_printf(m, "Pinned:\n");
  166. head = &dev_priv->mm.pinned_list;
  167. break;
  168. case FLUSHING_LIST:
  169. seq_printf(m, "Flushing:\n");
  170. head = &dev_priv->mm.flushing_list;
  171. break;
  172. case DEFERRED_FREE_LIST:
  173. seq_printf(m, "Deferred free:\n");
  174. head = &dev_priv->mm.deferred_free_list;
  175. break;
  176. default:
  177. mutex_unlock(&dev->struct_mutex);
  178. return -EINVAL;
  179. }
  180. total_obj_size = total_gtt_size = count = 0;
  181. list_for_each_entry(obj, head, mm_list) {
  182. seq_printf(m, " ");
  183. describe_obj(m, obj);
  184. seq_printf(m, "\n");
  185. total_obj_size += obj->base.size;
  186. total_gtt_size += obj->gtt_space->size;
  187. count++;
  188. }
  189. mutex_unlock(&dev->struct_mutex);
  190. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  191. count, total_obj_size, total_gtt_size);
  192. return 0;
  193. }
  194. #define count_objects(list, member) do { \
  195. list_for_each_entry(obj, list, member) { \
  196. size += obj->gtt_space->size; \
  197. ++count; \
  198. if (obj->map_and_fenceable) { \
  199. mappable_size += obj->gtt_space->size; \
  200. ++mappable_count; \
  201. } \
  202. } \
  203. } while (0)
  204. static int i915_gem_object_info(struct seq_file *m, void* data)
  205. {
  206. struct drm_info_node *node = (struct drm_info_node *) m->private;
  207. struct drm_device *dev = node->minor->dev;
  208. struct drm_i915_private *dev_priv = dev->dev_private;
  209. u32 count, mappable_count;
  210. size_t size, mappable_size;
  211. struct drm_i915_gem_object *obj;
  212. int ret;
  213. ret = mutex_lock_interruptible(&dev->struct_mutex);
  214. if (ret)
  215. return ret;
  216. seq_printf(m, "%u objects, %zu bytes\n",
  217. dev_priv->mm.object_count,
  218. dev_priv->mm.object_memory);
  219. size = count = mappable_size = mappable_count = 0;
  220. count_objects(&dev_priv->mm.gtt_list, gtt_list);
  221. seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
  222. count, mappable_count, size, mappable_size);
  223. size = count = mappable_size = mappable_count = 0;
  224. count_objects(&dev_priv->mm.active_list, mm_list);
  225. count_objects(&dev_priv->mm.flushing_list, mm_list);
  226. seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
  227. count, mappable_count, size, mappable_size);
  228. size = count = mappable_size = mappable_count = 0;
  229. count_objects(&dev_priv->mm.pinned_list, mm_list);
  230. seq_printf(m, " %u [%u] pinned objects, %zu [%zu] bytes\n",
  231. count, mappable_count, size, mappable_size);
  232. size = count = mappable_size = mappable_count = 0;
  233. count_objects(&dev_priv->mm.inactive_list, mm_list);
  234. seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
  235. count, mappable_count, size, mappable_size);
  236. size = count = mappable_size = mappable_count = 0;
  237. count_objects(&dev_priv->mm.deferred_free_list, mm_list);
  238. seq_printf(m, " %u [%u] freed objects, %zu [%zu] bytes\n",
  239. count, mappable_count, size, mappable_size);
  240. size = count = mappable_size = mappable_count = 0;
  241. list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
  242. if (obj->fault_mappable) {
  243. size += obj->gtt_space->size;
  244. ++count;
  245. }
  246. if (obj->pin_mappable) {
  247. mappable_size += obj->gtt_space->size;
  248. ++mappable_count;
  249. }
  250. }
  251. seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
  252. mappable_count, mappable_size);
  253. seq_printf(m, "%u fault mappable objects, %zu bytes\n",
  254. count, size);
  255. seq_printf(m, "%zu [%zu] gtt total\n",
  256. dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
  257. mutex_unlock(&dev->struct_mutex);
  258. return 0;
  259. }
  260. static int i915_gem_gtt_info(struct seq_file *m, void* data)
  261. {
  262. struct drm_info_node *node = (struct drm_info_node *) m->private;
  263. struct drm_device *dev = node->minor->dev;
  264. struct drm_i915_private *dev_priv = dev->dev_private;
  265. struct drm_i915_gem_object *obj;
  266. size_t total_obj_size, total_gtt_size;
  267. int count, ret;
  268. ret = mutex_lock_interruptible(&dev->struct_mutex);
  269. if (ret)
  270. return ret;
  271. total_obj_size = total_gtt_size = count = 0;
  272. list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
  273. seq_printf(m, " ");
  274. describe_obj(m, obj);
  275. seq_printf(m, "\n");
  276. total_obj_size += obj->base.size;
  277. total_gtt_size += obj->gtt_space->size;
  278. count++;
  279. }
  280. mutex_unlock(&dev->struct_mutex);
  281. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  282. count, total_obj_size, total_gtt_size);
  283. return 0;
  284. }
  285. static int i915_gem_pageflip_info(struct seq_file *m, void *data)
  286. {
  287. struct drm_info_node *node = (struct drm_info_node *) m->private;
  288. struct drm_device *dev = node->minor->dev;
  289. unsigned long flags;
  290. struct intel_crtc *crtc;
  291. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  292. const char pipe = pipe_name(crtc->pipe);
  293. const char plane = plane_name(crtc->plane);
  294. struct intel_unpin_work *work;
  295. spin_lock_irqsave(&dev->event_lock, flags);
  296. work = crtc->unpin_work;
  297. if (work == NULL) {
  298. seq_printf(m, "No flip due on pipe %c (plane %c)\n",
  299. pipe, plane);
  300. } else {
  301. if (!work->pending) {
  302. seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
  303. pipe, plane);
  304. } else {
  305. seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
  306. pipe, plane);
  307. }
  308. if (work->enable_stall_check)
  309. seq_printf(m, "Stall check enabled, ");
  310. else
  311. seq_printf(m, "Stall check waiting for page flip ioctl, ");
  312. seq_printf(m, "%d prepares\n", work->pending);
  313. if (work->old_fb_obj) {
  314. struct drm_i915_gem_object *obj = work->old_fb_obj;
  315. if (obj)
  316. seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  317. }
  318. if (work->pending_flip_obj) {
  319. struct drm_i915_gem_object *obj = work->pending_flip_obj;
  320. if (obj)
  321. seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  322. }
  323. }
  324. spin_unlock_irqrestore(&dev->event_lock, flags);
  325. }
  326. return 0;
  327. }
  328. static int i915_gem_request_info(struct seq_file *m, void *data)
  329. {
  330. struct drm_info_node *node = (struct drm_info_node *) m->private;
  331. struct drm_device *dev = node->minor->dev;
  332. drm_i915_private_t *dev_priv = dev->dev_private;
  333. struct drm_i915_gem_request *gem_request;
  334. int ret, count;
  335. ret = mutex_lock_interruptible(&dev->struct_mutex);
  336. if (ret)
  337. return ret;
  338. count = 0;
  339. if (!list_empty(&dev_priv->ring[RCS].request_list)) {
  340. seq_printf(m, "Render requests:\n");
  341. list_for_each_entry(gem_request,
  342. &dev_priv->ring[RCS].request_list,
  343. list) {
  344. seq_printf(m, " %d @ %d\n",
  345. gem_request->seqno,
  346. (int) (jiffies - gem_request->emitted_jiffies));
  347. }
  348. count++;
  349. }
  350. if (!list_empty(&dev_priv->ring[VCS].request_list)) {
  351. seq_printf(m, "BSD requests:\n");
  352. list_for_each_entry(gem_request,
  353. &dev_priv->ring[VCS].request_list,
  354. list) {
  355. seq_printf(m, " %d @ %d\n",
  356. gem_request->seqno,
  357. (int) (jiffies - gem_request->emitted_jiffies));
  358. }
  359. count++;
  360. }
  361. if (!list_empty(&dev_priv->ring[BCS].request_list)) {
  362. seq_printf(m, "BLT requests:\n");
  363. list_for_each_entry(gem_request,
  364. &dev_priv->ring[BCS].request_list,
  365. list) {
  366. seq_printf(m, " %d @ %d\n",
  367. gem_request->seqno,
  368. (int) (jiffies - gem_request->emitted_jiffies));
  369. }
  370. count++;
  371. }
  372. mutex_unlock(&dev->struct_mutex);
  373. if (count == 0)
  374. seq_printf(m, "No requests\n");
  375. return 0;
  376. }
  377. static void i915_ring_seqno_info(struct seq_file *m,
  378. struct intel_ring_buffer *ring)
  379. {
  380. if (ring->get_seqno) {
  381. seq_printf(m, "Current sequence (%s): %d\n",
  382. ring->name, ring->get_seqno(ring));
  383. seq_printf(m, "Waiter sequence (%s): %d\n",
  384. ring->name, ring->waiting_seqno);
  385. seq_printf(m, "IRQ sequence (%s): %d\n",
  386. ring->name, ring->irq_seqno);
  387. }
  388. }
  389. static int i915_gem_seqno_info(struct seq_file *m, void *data)
  390. {
  391. struct drm_info_node *node = (struct drm_info_node *) m->private;
  392. struct drm_device *dev = node->minor->dev;
  393. drm_i915_private_t *dev_priv = dev->dev_private;
  394. int ret, i;
  395. ret = mutex_lock_interruptible(&dev->struct_mutex);
  396. if (ret)
  397. return ret;
  398. for (i = 0; i < I915_NUM_RINGS; i++)
  399. i915_ring_seqno_info(m, &dev_priv->ring[i]);
  400. mutex_unlock(&dev->struct_mutex);
  401. return 0;
  402. }
  403. static int i915_interrupt_info(struct seq_file *m, void *data)
  404. {
  405. struct drm_info_node *node = (struct drm_info_node *) m->private;
  406. struct drm_device *dev = node->minor->dev;
  407. drm_i915_private_t *dev_priv = dev->dev_private;
  408. int ret, i, pipe;
  409. ret = mutex_lock_interruptible(&dev->struct_mutex);
  410. if (ret)
  411. return ret;
  412. if (!HAS_PCH_SPLIT(dev)) {
  413. seq_printf(m, "Interrupt enable: %08x\n",
  414. I915_READ(IER));
  415. seq_printf(m, "Interrupt identity: %08x\n",
  416. I915_READ(IIR));
  417. seq_printf(m, "Interrupt mask: %08x\n",
  418. I915_READ(IMR));
  419. for_each_pipe(pipe)
  420. seq_printf(m, "Pipe %c stat: %08x\n",
  421. pipe_name(pipe),
  422. I915_READ(PIPESTAT(pipe)));
  423. } else {
  424. seq_printf(m, "North Display Interrupt enable: %08x\n",
  425. I915_READ(DEIER));
  426. seq_printf(m, "North Display Interrupt identity: %08x\n",
  427. I915_READ(DEIIR));
  428. seq_printf(m, "North Display Interrupt mask: %08x\n",
  429. I915_READ(DEIMR));
  430. seq_printf(m, "South Display Interrupt enable: %08x\n",
  431. I915_READ(SDEIER));
  432. seq_printf(m, "South Display Interrupt identity: %08x\n",
  433. I915_READ(SDEIIR));
  434. seq_printf(m, "South Display Interrupt mask: %08x\n",
  435. I915_READ(SDEIMR));
  436. seq_printf(m, "Graphics Interrupt enable: %08x\n",
  437. I915_READ(GTIER));
  438. seq_printf(m, "Graphics Interrupt identity: %08x\n",
  439. I915_READ(GTIIR));
  440. seq_printf(m, "Graphics Interrupt mask: %08x\n",
  441. I915_READ(GTIMR));
  442. }
  443. seq_printf(m, "Interrupts received: %d\n",
  444. atomic_read(&dev_priv->irq_received));
  445. for (i = 0; i < I915_NUM_RINGS; i++) {
  446. if (IS_GEN6(dev) || IS_GEN7(dev)) {
  447. seq_printf(m, "Graphics Interrupt mask (%s): %08x\n",
  448. dev_priv->ring[i].name,
  449. I915_READ_IMR(&dev_priv->ring[i]));
  450. }
  451. i915_ring_seqno_info(m, &dev_priv->ring[i]);
  452. }
  453. mutex_unlock(&dev->struct_mutex);
  454. return 0;
  455. }
  456. static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
  457. {
  458. struct drm_info_node *node = (struct drm_info_node *) m->private;
  459. struct drm_device *dev = node->minor->dev;
  460. drm_i915_private_t *dev_priv = dev->dev_private;
  461. int i, ret;
  462. ret = mutex_lock_interruptible(&dev->struct_mutex);
  463. if (ret)
  464. return ret;
  465. seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
  466. seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
  467. for (i = 0; i < dev_priv->num_fence_regs; i++) {
  468. struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
  469. seq_printf(m, "Fenced object[%2d] = ", i);
  470. if (obj == NULL)
  471. seq_printf(m, "unused");
  472. else
  473. describe_obj(m, obj);
  474. seq_printf(m, "\n");
  475. }
  476. mutex_unlock(&dev->struct_mutex);
  477. return 0;
  478. }
  479. static int i915_hws_info(struct seq_file *m, void *data)
  480. {
  481. struct drm_info_node *node = (struct drm_info_node *) m->private;
  482. struct drm_device *dev = node->minor->dev;
  483. drm_i915_private_t *dev_priv = dev->dev_private;
  484. struct intel_ring_buffer *ring;
  485. const volatile u32 __iomem *hws;
  486. int i;
  487. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  488. hws = (volatile u32 __iomem *)ring->status_page.page_addr;
  489. if (hws == NULL)
  490. return 0;
  491. for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
  492. seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
  493. i * 4,
  494. hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
  495. }
  496. return 0;
  497. }
  498. static void i915_dump_object(struct seq_file *m,
  499. struct io_mapping *mapping,
  500. struct drm_i915_gem_object *obj)
  501. {
  502. int page, page_count, i;
  503. page_count = obj->base.size / PAGE_SIZE;
  504. for (page = 0; page < page_count; page++) {
  505. u32 *mem = io_mapping_map_wc(mapping,
  506. obj->gtt_offset + page * PAGE_SIZE);
  507. for (i = 0; i < PAGE_SIZE; i += 4)
  508. seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
  509. io_mapping_unmap(mem);
  510. }
  511. }
  512. static int i915_batchbuffer_info(struct seq_file *m, void *data)
  513. {
  514. struct drm_info_node *node = (struct drm_info_node *) m->private;
  515. struct drm_device *dev = node->minor->dev;
  516. drm_i915_private_t *dev_priv = dev->dev_private;
  517. struct drm_i915_gem_object *obj;
  518. int ret;
  519. ret = mutex_lock_interruptible(&dev->struct_mutex);
  520. if (ret)
  521. return ret;
  522. list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
  523. if (obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) {
  524. seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset);
  525. i915_dump_object(m, dev_priv->mm.gtt_mapping, obj);
  526. }
  527. }
  528. mutex_unlock(&dev->struct_mutex);
  529. return 0;
  530. }
  531. static int i915_ringbuffer_data(struct seq_file *m, void *data)
  532. {
  533. struct drm_info_node *node = (struct drm_info_node *) m->private;
  534. struct drm_device *dev = node->minor->dev;
  535. drm_i915_private_t *dev_priv = dev->dev_private;
  536. struct intel_ring_buffer *ring;
  537. int ret;
  538. ret = mutex_lock_interruptible(&dev->struct_mutex);
  539. if (ret)
  540. return ret;
  541. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  542. if (!ring->obj) {
  543. seq_printf(m, "No ringbuffer setup\n");
  544. } else {
  545. const u8 __iomem *virt = ring->virtual_start;
  546. uint32_t off;
  547. for (off = 0; off < ring->size; off += 4) {
  548. uint32_t *ptr = (uint32_t *)(virt + off);
  549. seq_printf(m, "%08x : %08x\n", off, *ptr);
  550. }
  551. }
  552. mutex_unlock(&dev->struct_mutex);
  553. return 0;
  554. }
  555. static int i915_ringbuffer_info(struct seq_file *m, void *data)
  556. {
  557. struct drm_info_node *node = (struct drm_info_node *) m->private;
  558. struct drm_device *dev = node->minor->dev;
  559. drm_i915_private_t *dev_priv = dev->dev_private;
  560. struct intel_ring_buffer *ring;
  561. int ret;
  562. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  563. if (ring->size == 0)
  564. return 0;
  565. ret = mutex_lock_interruptible(&dev->struct_mutex);
  566. if (ret)
  567. return ret;
  568. seq_printf(m, "Ring %s:\n", ring->name);
  569. seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);
  570. seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
  571. seq_printf(m, " Size : %08x\n", ring->size);
  572. seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring));
  573. seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring));
  574. if (IS_GEN6(dev)) {
  575. seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring));
  576. seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring));
  577. }
  578. seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring));
  579. seq_printf(m, " Start : %08x\n", I915_READ_START(ring));
  580. mutex_unlock(&dev->struct_mutex);
  581. return 0;
  582. }
  583. static const char *ring_str(int ring)
  584. {
  585. switch (ring) {
  586. case RING_RENDER: return " render";
  587. case RING_BSD: return " bsd";
  588. case RING_BLT: return " blt";
  589. default: return "";
  590. }
  591. }
  592. static const char *pin_flag(int pinned)
  593. {
  594. if (pinned > 0)
  595. return " P";
  596. else if (pinned < 0)
  597. return " p";
  598. else
  599. return "";
  600. }
  601. static const char *tiling_flag(int tiling)
  602. {
  603. switch (tiling) {
  604. default:
  605. case I915_TILING_NONE: return "";
  606. case I915_TILING_X: return " X";
  607. case I915_TILING_Y: return " Y";
  608. }
  609. }
  610. static const char *dirty_flag(int dirty)
  611. {
  612. return dirty ? " dirty" : "";
  613. }
  614. static const char *purgeable_flag(int purgeable)
  615. {
  616. return purgeable ? " purgeable" : "";
  617. }
  618. static void print_error_buffers(struct seq_file *m,
  619. const char *name,
  620. struct drm_i915_error_buffer *err,
  621. int count)
  622. {
  623. seq_printf(m, "%s [%d]:\n", name, count);
  624. while (count--) {
  625. seq_printf(m, " %08x %8u %04x %04x %08x%s%s%s%s%s%s",
  626. err->gtt_offset,
  627. err->size,
  628. err->read_domains,
  629. err->write_domain,
  630. err->seqno,
  631. pin_flag(err->pinned),
  632. tiling_flag(err->tiling),
  633. dirty_flag(err->dirty),
  634. purgeable_flag(err->purgeable),
  635. ring_str(err->ring),
  636. cache_level_str(err->cache_level));
  637. if (err->name)
  638. seq_printf(m, " (name: %d)", err->name);
  639. if (err->fence_reg != I915_FENCE_REG_NONE)
  640. seq_printf(m, " (fence: %d)", err->fence_reg);
  641. seq_printf(m, "\n");
  642. err++;
  643. }
  644. }
  645. static int i915_error_state(struct seq_file *m, void *unused)
  646. {
  647. struct drm_info_node *node = (struct drm_info_node *) m->private;
  648. struct drm_device *dev = node->minor->dev;
  649. drm_i915_private_t *dev_priv = dev->dev_private;
  650. struct drm_i915_error_state *error;
  651. unsigned long flags;
  652. int i, page, offset, elt;
  653. spin_lock_irqsave(&dev_priv->error_lock, flags);
  654. if (!dev_priv->first_error) {
  655. seq_printf(m, "no error state collected\n");
  656. goto out;
  657. }
  658. error = dev_priv->first_error;
  659. seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
  660. error->time.tv_usec);
  661. seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
  662. seq_printf(m, "EIR: 0x%08x\n", error->eir);
  663. seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
  664. if (INTEL_INFO(dev)->gen >= 6) {
  665. seq_printf(m, "ERROR: 0x%08x\n", error->error);
  666. seq_printf(m, "Blitter command stream:\n");
  667. seq_printf(m, " ACTHD: 0x%08x\n", error->bcs_acthd);
  668. seq_printf(m, " IPEIR: 0x%08x\n", error->bcs_ipeir);
  669. seq_printf(m, " IPEHR: 0x%08x\n", error->bcs_ipehr);
  670. seq_printf(m, " INSTDONE: 0x%08x\n", error->bcs_instdone);
  671. seq_printf(m, " seqno: 0x%08x\n", error->bcs_seqno);
  672. seq_printf(m, "Video (BSD) command stream:\n");
  673. seq_printf(m, " ACTHD: 0x%08x\n", error->vcs_acthd);
  674. seq_printf(m, " IPEIR: 0x%08x\n", error->vcs_ipeir);
  675. seq_printf(m, " IPEHR: 0x%08x\n", error->vcs_ipehr);
  676. seq_printf(m, " INSTDONE: 0x%08x\n", error->vcs_instdone);
  677. seq_printf(m, " seqno: 0x%08x\n", error->vcs_seqno);
  678. }
  679. seq_printf(m, "Render command stream:\n");
  680. seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);
  681. seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);
  682. seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
  683. seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
  684. if (INTEL_INFO(dev)->gen >= 4) {
  685. seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
  686. seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
  687. }
  688. seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
  689. seq_printf(m, " seqno: 0x%08x\n", error->seqno);
  690. for (i = 0; i < dev_priv->num_fence_regs; i++)
  691. seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
  692. if (error->active_bo)
  693. print_error_buffers(m, "Active",
  694. error->active_bo,
  695. error->active_bo_count);
  696. if (error->pinned_bo)
  697. print_error_buffers(m, "Pinned",
  698. error->pinned_bo,
  699. error->pinned_bo_count);
  700. for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) {
  701. if (error->batchbuffer[i]) {
  702. struct drm_i915_error_object *obj = error->batchbuffer[i];
  703. seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
  704. dev_priv->ring[i].name,
  705. obj->gtt_offset);
  706. offset = 0;
  707. for (page = 0; page < obj->page_count; page++) {
  708. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  709. seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
  710. offset += 4;
  711. }
  712. }
  713. }
  714. }
  715. for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++) {
  716. if (error->ringbuffer[i]) {
  717. struct drm_i915_error_object *obj = error->ringbuffer[i];
  718. seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
  719. dev_priv->ring[i].name,
  720. obj->gtt_offset);
  721. offset = 0;
  722. for (page = 0; page < obj->page_count; page++) {
  723. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  724. seq_printf(m, "%08x : %08x\n",
  725. offset,
  726. obj->pages[page][elt]);
  727. offset += 4;
  728. }
  729. }
  730. }
  731. }
  732. if (error->overlay)
  733. intel_overlay_print_error_state(m, error->overlay);
  734. if (error->display)
  735. intel_display_print_error_state(m, dev, error->display);
  736. out:
  737. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  738. return 0;
  739. }
  740. static int i915_rstdby_delays(struct seq_file *m, void *unused)
  741. {
  742. struct drm_info_node *node = (struct drm_info_node *) m->private;
  743. struct drm_device *dev = node->minor->dev;
  744. drm_i915_private_t *dev_priv = dev->dev_private;
  745. u16 crstanddelay;
  746. int ret;
  747. ret = mutex_lock_interruptible(&dev->struct_mutex);
  748. if (ret)
  749. return ret;
  750. crstanddelay = I915_READ16(CRSTANDVID);
  751. mutex_unlock(&dev->struct_mutex);
  752. seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
  753. return 0;
  754. }
  755. static int i915_cur_delayinfo(struct seq_file *m, void *unused)
  756. {
  757. struct drm_info_node *node = (struct drm_info_node *) m->private;
  758. struct drm_device *dev = node->minor->dev;
  759. drm_i915_private_t *dev_priv = dev->dev_private;
  760. int ret;
  761. if (IS_GEN5(dev)) {
  762. u16 rgvswctl = I915_READ16(MEMSWCTL);
  763. u16 rgvstat = I915_READ16(MEMSTAT_ILK);
  764. seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
  765. seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
  766. seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
  767. MEMSTAT_VID_SHIFT);
  768. seq_printf(m, "Current P-state: %d\n",
  769. (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
  770. } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
  771. u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  772. u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
  773. u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  774. u32 rpstat;
  775. u32 rpupei, rpcurup, rpprevup;
  776. u32 rpdownei, rpcurdown, rpprevdown;
  777. int max_freq;
  778. /* RPSTAT1 is in the GT power well */
  779. ret = mutex_lock_interruptible(&dev->struct_mutex);
  780. if (ret)
  781. return ret;
  782. gen6_gt_force_wake_get(dev_priv);
  783. rpstat = I915_READ(GEN6_RPSTAT1);
  784. rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
  785. rpcurup = I915_READ(GEN6_RP_CUR_UP);
  786. rpprevup = I915_READ(GEN6_RP_PREV_UP);
  787. rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
  788. rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
  789. rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
  790. gen6_gt_force_wake_put(dev_priv);
  791. mutex_unlock(&dev->struct_mutex);
  792. seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
  793. seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
  794. seq_printf(m, "Render p-state ratio: %d\n",
  795. (gt_perf_status & 0xff00) >> 8);
  796. seq_printf(m, "Render p-state VID: %d\n",
  797. gt_perf_status & 0xff);
  798. seq_printf(m, "Render p-state limit: %d\n",
  799. rp_state_limits & 0xff);
  800. seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
  801. GEN6_CAGF_SHIFT) * 50);
  802. seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
  803. GEN6_CURICONT_MASK);
  804. seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
  805. GEN6_CURBSYTAVG_MASK);
  806. seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
  807. GEN6_CURBSYTAVG_MASK);
  808. seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
  809. GEN6_CURIAVG_MASK);
  810. seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
  811. GEN6_CURBSYTAVG_MASK);
  812. seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
  813. GEN6_CURBSYTAVG_MASK);
  814. max_freq = (rp_state_cap & 0xff0000) >> 16;
  815. seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
  816. max_freq * 50);
  817. max_freq = (rp_state_cap & 0xff00) >> 8;
  818. seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
  819. max_freq * 50);
  820. max_freq = rp_state_cap & 0xff;
  821. seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
  822. max_freq * 50);
  823. } else {
  824. seq_printf(m, "no P-state info available\n");
  825. }
  826. return 0;
  827. }
  828. static int i915_delayfreq_table(struct seq_file *m, void *unused)
  829. {
  830. struct drm_info_node *node = (struct drm_info_node *) m->private;
  831. struct drm_device *dev = node->minor->dev;
  832. drm_i915_private_t *dev_priv = dev->dev_private;
  833. u32 delayfreq;
  834. int ret, i;
  835. ret = mutex_lock_interruptible(&dev->struct_mutex);
  836. if (ret)
  837. return ret;
  838. for (i = 0; i < 16; i++) {
  839. delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
  840. seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
  841. (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
  842. }
  843. mutex_unlock(&dev->struct_mutex);
  844. return 0;
  845. }
  846. static inline int MAP_TO_MV(int map)
  847. {
  848. return 1250 - (map * 25);
  849. }
  850. static int i915_inttoext_table(struct seq_file *m, void *unused)
  851. {
  852. struct drm_info_node *node = (struct drm_info_node *) m->private;
  853. struct drm_device *dev = node->minor->dev;
  854. drm_i915_private_t *dev_priv = dev->dev_private;
  855. u32 inttoext;
  856. int ret, i;
  857. ret = mutex_lock_interruptible(&dev->struct_mutex);
  858. if (ret)
  859. return ret;
  860. for (i = 1; i <= 32; i++) {
  861. inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
  862. seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
  863. }
  864. mutex_unlock(&dev->struct_mutex);
  865. return 0;
  866. }
  867. static int i915_drpc_info(struct seq_file *m, void *unused)
  868. {
  869. struct drm_info_node *node = (struct drm_info_node *) m->private;
  870. struct drm_device *dev = node->minor->dev;
  871. drm_i915_private_t *dev_priv = dev->dev_private;
  872. u32 rgvmodectl, rstdbyctl;
  873. u16 crstandvid;
  874. int ret;
  875. ret = mutex_lock_interruptible(&dev->struct_mutex);
  876. if (ret)
  877. return ret;
  878. rgvmodectl = I915_READ(MEMMODECTL);
  879. rstdbyctl = I915_READ(RSTDBYCTL);
  880. crstandvid = I915_READ16(CRSTANDVID);
  881. mutex_unlock(&dev->struct_mutex);
  882. seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
  883. "yes" : "no");
  884. seq_printf(m, "Boost freq: %d\n",
  885. (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
  886. MEMMODE_BOOST_FREQ_SHIFT);
  887. seq_printf(m, "HW control enabled: %s\n",
  888. rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
  889. seq_printf(m, "SW control enabled: %s\n",
  890. rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
  891. seq_printf(m, "Gated voltage change: %s\n",
  892. rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
  893. seq_printf(m, "Starting frequency: P%d\n",
  894. (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
  895. seq_printf(m, "Max P-state: P%d\n",
  896. (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
  897. seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
  898. seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
  899. seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
  900. seq_printf(m, "Render standby enabled: %s\n",
  901. (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
  902. seq_printf(m, "Current RS state: ");
  903. switch (rstdbyctl & RSX_STATUS_MASK) {
  904. case RSX_STATUS_ON:
  905. seq_printf(m, "on\n");
  906. break;
  907. case RSX_STATUS_RC1:
  908. seq_printf(m, "RC1\n");
  909. break;
  910. case RSX_STATUS_RC1E:
  911. seq_printf(m, "RC1E\n");
  912. break;
  913. case RSX_STATUS_RS1:
  914. seq_printf(m, "RS1\n");
  915. break;
  916. case RSX_STATUS_RS2:
  917. seq_printf(m, "RS2 (RC6)\n");
  918. break;
  919. case RSX_STATUS_RS3:
  920. seq_printf(m, "RC3 (RC6+)\n");
  921. break;
  922. default:
  923. seq_printf(m, "unknown\n");
  924. break;
  925. }
  926. return 0;
  927. }
  928. static int i915_fbc_status(struct seq_file *m, void *unused)
  929. {
  930. struct drm_info_node *node = (struct drm_info_node *) m->private;
  931. struct drm_device *dev = node->minor->dev;
  932. drm_i915_private_t *dev_priv = dev->dev_private;
  933. if (!I915_HAS_FBC(dev)) {
  934. seq_printf(m, "FBC unsupported on this chipset\n");
  935. return 0;
  936. }
  937. if (intel_fbc_enabled(dev)) {
  938. seq_printf(m, "FBC enabled\n");
  939. } else {
  940. seq_printf(m, "FBC disabled: ");
  941. switch (dev_priv->no_fbc_reason) {
  942. case FBC_NO_OUTPUT:
  943. seq_printf(m, "no outputs");
  944. break;
  945. case FBC_STOLEN_TOO_SMALL:
  946. seq_printf(m, "not enough stolen memory");
  947. break;
  948. case FBC_UNSUPPORTED_MODE:
  949. seq_printf(m, "mode not supported");
  950. break;
  951. case FBC_MODE_TOO_LARGE:
  952. seq_printf(m, "mode too large");
  953. break;
  954. case FBC_BAD_PLANE:
  955. seq_printf(m, "FBC unsupported on plane");
  956. break;
  957. case FBC_NOT_TILED:
  958. seq_printf(m, "scanout buffer not tiled");
  959. break;
  960. case FBC_MULTIPLE_PIPES:
  961. seq_printf(m, "multiple pipes are enabled");
  962. break;
  963. case FBC_MODULE_PARAM:
  964. seq_printf(m, "disabled per module param (default off)");
  965. break;
  966. default:
  967. seq_printf(m, "unknown reason");
  968. }
  969. seq_printf(m, "\n");
  970. }
  971. return 0;
  972. }
  973. static int i915_sr_status(struct seq_file *m, void *unused)
  974. {
  975. struct drm_info_node *node = (struct drm_info_node *) m->private;
  976. struct drm_device *dev = node->minor->dev;
  977. drm_i915_private_t *dev_priv = dev->dev_private;
  978. bool sr_enabled = false;
  979. if (HAS_PCH_SPLIT(dev))
  980. sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
  981. else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
  982. sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
  983. else if (IS_I915GM(dev))
  984. sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
  985. else if (IS_PINEVIEW(dev))
  986. sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
  987. seq_printf(m, "self-refresh: %s\n",
  988. sr_enabled ? "enabled" : "disabled");
  989. return 0;
  990. }
  991. static int i915_emon_status(struct seq_file *m, void *unused)
  992. {
  993. struct drm_info_node *node = (struct drm_info_node *) m->private;
  994. struct drm_device *dev = node->minor->dev;
  995. drm_i915_private_t *dev_priv = dev->dev_private;
  996. unsigned long temp, chipset, gfx;
  997. int ret;
  998. ret = mutex_lock_interruptible(&dev->struct_mutex);
  999. if (ret)
  1000. return ret;
  1001. temp = i915_mch_val(dev_priv);
  1002. chipset = i915_chipset_val(dev_priv);
  1003. gfx = i915_gfx_val(dev_priv);
  1004. mutex_unlock(&dev->struct_mutex);
  1005. seq_printf(m, "GMCH temp: %ld\n", temp);
  1006. seq_printf(m, "Chipset power: %ld\n", chipset);
  1007. seq_printf(m, "GFX power: %ld\n", gfx);
  1008. seq_printf(m, "Total power: %ld\n", chipset + gfx);
  1009. return 0;
  1010. }
  1011. static int i915_ring_freq_table(struct seq_file *m, void *unused)
  1012. {
  1013. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1014. struct drm_device *dev = node->minor->dev;
  1015. drm_i915_private_t *dev_priv = dev->dev_private;
  1016. int ret;
  1017. int gpu_freq, ia_freq;
  1018. if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
  1019. seq_printf(m, "unsupported on this chipset\n");
  1020. return 0;
  1021. }
  1022. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1023. if (ret)
  1024. return ret;
  1025. seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
  1026. for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay;
  1027. gpu_freq++) {
  1028. I915_WRITE(GEN6_PCODE_DATA, gpu_freq);
  1029. I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
  1030. GEN6_PCODE_READ_MIN_FREQ_TABLE);
  1031. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
  1032. GEN6_PCODE_READY) == 0, 10)) {
  1033. DRM_ERROR("pcode read of freq table timed out\n");
  1034. continue;
  1035. }
  1036. ia_freq = I915_READ(GEN6_PCODE_DATA);
  1037. seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100);
  1038. }
  1039. mutex_unlock(&dev->struct_mutex);
  1040. return 0;
  1041. }
  1042. static int i915_gfxec(struct seq_file *m, void *unused)
  1043. {
  1044. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1045. struct drm_device *dev = node->minor->dev;
  1046. drm_i915_private_t *dev_priv = dev->dev_private;
  1047. int ret;
  1048. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1049. if (ret)
  1050. return ret;
  1051. seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
  1052. mutex_unlock(&dev->struct_mutex);
  1053. return 0;
  1054. }
  1055. static int i915_opregion(struct seq_file *m, void *unused)
  1056. {
  1057. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1058. struct drm_device *dev = node->minor->dev;
  1059. drm_i915_private_t *dev_priv = dev->dev_private;
  1060. struct intel_opregion *opregion = &dev_priv->opregion;
  1061. int ret;
  1062. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1063. if (ret)
  1064. return ret;
  1065. if (opregion->header)
  1066. seq_write(m, opregion->header, OPREGION_SIZE);
  1067. mutex_unlock(&dev->struct_mutex);
  1068. return 0;
  1069. }
  1070. static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
  1071. {
  1072. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1073. struct drm_device *dev = node->minor->dev;
  1074. drm_i915_private_t *dev_priv = dev->dev_private;
  1075. struct intel_fbdev *ifbdev;
  1076. struct intel_framebuffer *fb;
  1077. int ret;
  1078. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1079. if (ret)
  1080. return ret;
  1081. ifbdev = dev_priv->fbdev;
  1082. fb = to_intel_framebuffer(ifbdev->helper.fb);
  1083. seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
  1084. fb->base.width,
  1085. fb->base.height,
  1086. fb->base.depth,
  1087. fb->base.bits_per_pixel);
  1088. describe_obj(m, fb->obj);
  1089. seq_printf(m, "\n");
  1090. list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
  1091. if (&fb->base == ifbdev->helper.fb)
  1092. continue;
  1093. seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
  1094. fb->base.width,
  1095. fb->base.height,
  1096. fb->base.depth,
  1097. fb->base.bits_per_pixel);
  1098. describe_obj(m, fb->obj);
  1099. seq_printf(m, "\n");
  1100. }
  1101. mutex_unlock(&dev->mode_config.mutex);
  1102. return 0;
  1103. }
  1104. static int i915_context_status(struct seq_file *m, void *unused)
  1105. {
  1106. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1107. struct drm_device *dev = node->minor->dev;
  1108. drm_i915_private_t *dev_priv = dev->dev_private;
  1109. int ret;
  1110. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1111. if (ret)
  1112. return ret;
  1113. if (dev_priv->pwrctx) {
  1114. seq_printf(m, "power context ");
  1115. describe_obj(m, dev_priv->pwrctx);
  1116. seq_printf(m, "\n");
  1117. }
  1118. if (dev_priv->renderctx) {
  1119. seq_printf(m, "render context ");
  1120. describe_obj(m, dev_priv->renderctx);
  1121. seq_printf(m, "\n");
  1122. }
  1123. mutex_unlock(&dev->mode_config.mutex);
  1124. return 0;
  1125. }
  1126. static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
  1127. {
  1128. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1129. struct drm_device *dev = node->minor->dev;
  1130. struct drm_i915_private *dev_priv = dev->dev_private;
  1131. seq_printf(m, "forcewake count = %d\n",
  1132. atomic_read(&dev_priv->forcewake_count));
  1133. return 0;
  1134. }
  1135. static int
  1136. i915_wedged_open(struct inode *inode,
  1137. struct file *filp)
  1138. {
  1139. filp->private_data = inode->i_private;
  1140. return 0;
  1141. }
  1142. static ssize_t
  1143. i915_wedged_read(struct file *filp,
  1144. char __user *ubuf,
  1145. size_t max,
  1146. loff_t *ppos)
  1147. {
  1148. struct drm_device *dev = filp->private_data;
  1149. drm_i915_private_t *dev_priv = dev->dev_private;
  1150. char buf[80];
  1151. int len;
  1152. len = snprintf(buf, sizeof(buf),
  1153. "wedged : %d\n",
  1154. atomic_read(&dev_priv->mm.wedged));
  1155. if (len > sizeof(buf))
  1156. len = sizeof(buf);
  1157. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1158. }
  1159. static ssize_t
  1160. i915_wedged_write(struct file *filp,
  1161. const char __user *ubuf,
  1162. size_t cnt,
  1163. loff_t *ppos)
  1164. {
  1165. struct drm_device *dev = filp->private_data;
  1166. char buf[20];
  1167. int val = 1;
  1168. if (cnt > 0) {
  1169. if (cnt > sizeof(buf) - 1)
  1170. return -EINVAL;
  1171. if (copy_from_user(buf, ubuf, cnt))
  1172. return -EFAULT;
  1173. buf[cnt] = 0;
  1174. val = simple_strtoul(buf, NULL, 0);
  1175. }
  1176. DRM_INFO("Manually setting wedged to %d\n", val);
  1177. i915_handle_error(dev, val);
  1178. return cnt;
  1179. }
  1180. static const struct file_operations i915_wedged_fops = {
  1181. .owner = THIS_MODULE,
  1182. .open = i915_wedged_open,
  1183. .read = i915_wedged_read,
  1184. .write = i915_wedged_write,
  1185. .llseek = default_llseek,
  1186. };
  1187. static int
  1188. i915_max_freq_open(struct inode *inode,
  1189. struct file *filp)
  1190. {
  1191. filp->private_data = inode->i_private;
  1192. return 0;
  1193. }
  1194. static ssize_t
  1195. i915_max_freq_read(struct file *filp,
  1196. char __user *ubuf,
  1197. size_t max,
  1198. loff_t *ppos)
  1199. {
  1200. struct drm_device *dev = filp->private_data;
  1201. drm_i915_private_t *dev_priv = dev->dev_private;
  1202. char buf[80];
  1203. int len;
  1204. len = snprintf(buf, sizeof(buf),
  1205. "max freq: %d\n", dev_priv->max_delay * 50);
  1206. if (len > sizeof(buf))
  1207. len = sizeof(buf);
  1208. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1209. }
  1210. static ssize_t
  1211. i915_max_freq_write(struct file *filp,
  1212. const char __user *ubuf,
  1213. size_t cnt,
  1214. loff_t *ppos)
  1215. {
  1216. struct drm_device *dev = filp->private_data;
  1217. struct drm_i915_private *dev_priv = dev->dev_private;
  1218. char buf[20];
  1219. int val = 1;
  1220. if (cnt > 0) {
  1221. if (cnt > sizeof(buf) - 1)
  1222. return -EINVAL;
  1223. if (copy_from_user(buf, ubuf, cnt))
  1224. return -EFAULT;
  1225. buf[cnt] = 0;
  1226. val = simple_strtoul(buf, NULL, 0);
  1227. }
  1228. DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
  1229. /*
  1230. * Turbo will still be enabled, but won't go above the set value.
  1231. */
  1232. dev_priv->max_delay = val / 50;
  1233. gen6_set_rps(dev, val / 50);
  1234. return cnt;
  1235. }
  1236. static const struct file_operations i915_max_freq_fops = {
  1237. .owner = THIS_MODULE,
  1238. .open = i915_max_freq_open,
  1239. .read = i915_max_freq_read,
  1240. .write = i915_max_freq_write,
  1241. .llseek = default_llseek,
  1242. };
  1243. static int
  1244. i915_cache_sharing_open(struct inode *inode,
  1245. struct file *filp)
  1246. {
  1247. filp->private_data = inode->i_private;
  1248. return 0;
  1249. }
  1250. static ssize_t
  1251. i915_cache_sharing_read(struct file *filp,
  1252. char __user *ubuf,
  1253. size_t max,
  1254. loff_t *ppos)
  1255. {
  1256. struct drm_device *dev = filp->private_data;
  1257. drm_i915_private_t *dev_priv = dev->dev_private;
  1258. char buf[80];
  1259. u32 snpcr;
  1260. int len;
  1261. mutex_lock(&dev_priv->dev->struct_mutex);
  1262. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  1263. mutex_unlock(&dev_priv->dev->struct_mutex);
  1264. len = snprintf(buf, sizeof(buf),
  1265. "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
  1266. GEN6_MBC_SNPCR_SHIFT);
  1267. if (len > sizeof(buf))
  1268. len = sizeof(buf);
  1269. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1270. }
  1271. static ssize_t
  1272. i915_cache_sharing_write(struct file *filp,
  1273. const char __user *ubuf,
  1274. size_t cnt,
  1275. loff_t *ppos)
  1276. {
  1277. struct drm_device *dev = filp->private_data;
  1278. struct drm_i915_private *dev_priv = dev->dev_private;
  1279. char buf[20];
  1280. u32 snpcr;
  1281. int val = 1;
  1282. if (cnt > 0) {
  1283. if (cnt > sizeof(buf) - 1)
  1284. return -EINVAL;
  1285. if (copy_from_user(buf, ubuf, cnt))
  1286. return -EFAULT;
  1287. buf[cnt] = 0;
  1288. val = simple_strtoul(buf, NULL, 0);
  1289. }
  1290. if (val < 0 || val > 3)
  1291. return -EINVAL;
  1292. DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val);
  1293. /* Update the cache sharing policy here as well */
  1294. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  1295. snpcr &= ~GEN6_MBC_SNPCR_MASK;
  1296. snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
  1297. I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
  1298. return cnt;
  1299. }
  1300. static const struct file_operations i915_cache_sharing_fops = {
  1301. .owner = THIS_MODULE,
  1302. .open = i915_cache_sharing_open,
  1303. .read = i915_cache_sharing_read,
  1304. .write = i915_cache_sharing_write,
  1305. .llseek = default_llseek,
  1306. };
  1307. /* As the drm_debugfs_init() routines are called before dev->dev_private is
  1308. * allocated we need to hook into the minor for release. */
  1309. static int
  1310. drm_add_fake_info_node(struct drm_minor *minor,
  1311. struct dentry *ent,
  1312. const void *key)
  1313. {
  1314. struct drm_info_node *node;
  1315. node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
  1316. if (node == NULL) {
  1317. debugfs_remove(ent);
  1318. return -ENOMEM;
  1319. }
  1320. node->minor = minor;
  1321. node->dent = ent;
  1322. node->info_ent = (void *) key;
  1323. mutex_lock(&minor->debugfs_lock);
  1324. list_add(&node->list, &minor->debugfs_list);
  1325. mutex_unlock(&minor->debugfs_lock);
  1326. return 0;
  1327. }
  1328. static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
  1329. {
  1330. struct drm_device *dev = minor->dev;
  1331. struct dentry *ent;
  1332. ent = debugfs_create_file("i915_wedged",
  1333. S_IRUGO | S_IWUSR,
  1334. root, dev,
  1335. &i915_wedged_fops);
  1336. if (IS_ERR(ent))
  1337. return PTR_ERR(ent);
  1338. return drm_add_fake_info_node(minor, ent, &i915_wedged_fops);
  1339. }
  1340. static int i915_forcewake_open(struct inode *inode, struct file *file)
  1341. {
  1342. struct drm_device *dev = inode->i_private;
  1343. struct drm_i915_private *dev_priv = dev->dev_private;
  1344. int ret;
  1345. if (!IS_GEN6(dev))
  1346. return 0;
  1347. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1348. if (ret)
  1349. return ret;
  1350. gen6_gt_force_wake_get(dev_priv);
  1351. mutex_unlock(&dev->struct_mutex);
  1352. return 0;
  1353. }
  1354. int i915_forcewake_release(struct inode *inode, struct file *file)
  1355. {
  1356. struct drm_device *dev = inode->i_private;
  1357. struct drm_i915_private *dev_priv = dev->dev_private;
  1358. if (!IS_GEN6(dev))
  1359. return 0;
  1360. /*
  1361. * It's bad that we can potentially hang userspace if struct_mutex gets
  1362. * forever stuck. However, if we cannot acquire this lock it means that
  1363. * almost certainly the driver has hung, is not unload-able. Therefore
  1364. * hanging here is probably a minor inconvenience not to be seen my
  1365. * almost every user.
  1366. */
  1367. mutex_lock(&dev->struct_mutex);
  1368. gen6_gt_force_wake_put(dev_priv);
  1369. mutex_unlock(&dev->struct_mutex);
  1370. return 0;
  1371. }
  1372. static const struct file_operations i915_forcewake_fops = {
  1373. .owner = THIS_MODULE,
  1374. .open = i915_forcewake_open,
  1375. .release = i915_forcewake_release,
  1376. };
  1377. static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
  1378. {
  1379. struct drm_device *dev = minor->dev;
  1380. struct dentry *ent;
  1381. ent = debugfs_create_file("i915_forcewake_user",
  1382. S_IRUSR,
  1383. root, dev,
  1384. &i915_forcewake_fops);
  1385. if (IS_ERR(ent))
  1386. return PTR_ERR(ent);
  1387. return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
  1388. }
  1389. static int i915_max_freq_create(struct dentry *root, struct drm_minor *minor)
  1390. {
  1391. struct drm_device *dev = minor->dev;
  1392. struct dentry *ent;
  1393. ent = debugfs_create_file("i915_max_freq",
  1394. S_IRUGO | S_IWUSR,
  1395. root, dev,
  1396. &i915_max_freq_fops);
  1397. if (IS_ERR(ent))
  1398. return PTR_ERR(ent);
  1399. return drm_add_fake_info_node(minor, ent, &i915_max_freq_fops);
  1400. }
  1401. static int i915_cache_sharing_create(struct dentry *root, struct drm_minor *minor)
  1402. {
  1403. struct drm_device *dev = minor->dev;
  1404. struct dentry *ent;
  1405. ent = debugfs_create_file("i915_cache_sharing",
  1406. S_IRUGO | S_IWUSR,
  1407. root, dev,
  1408. &i915_cache_sharing_fops);
  1409. if (IS_ERR(ent))
  1410. return PTR_ERR(ent);
  1411. return drm_add_fake_info_node(minor, ent, &i915_cache_sharing_fops);
  1412. }
  1413. static struct drm_info_list i915_debugfs_list[] = {
  1414. {"i915_capabilities", i915_capabilities, 0},
  1415. {"i915_gem_objects", i915_gem_object_info, 0},
  1416. {"i915_gem_gtt", i915_gem_gtt_info, 0},
  1417. {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
  1418. {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
  1419. {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
  1420. {"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST},
  1421. {"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST},
  1422. {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
  1423. {"i915_gem_request", i915_gem_request_info, 0},
  1424. {"i915_gem_seqno", i915_gem_seqno_info, 0},
  1425. {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
  1426. {"i915_gem_interrupt", i915_interrupt_info, 0},
  1427. {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
  1428. {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
  1429. {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
  1430. {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RCS},
  1431. {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RCS},
  1432. {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)VCS},
  1433. {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS},
  1434. {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS},
  1435. {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS},
  1436. {"i915_batchbuffers", i915_batchbuffer_info, 0},
  1437. {"i915_error_state", i915_error_state, 0},
  1438. {"i915_rstdby_delays", i915_rstdby_delays, 0},
  1439. {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
  1440. {"i915_delayfreq_table", i915_delayfreq_table, 0},
  1441. {"i915_inttoext_table", i915_inttoext_table, 0},
  1442. {"i915_drpc_info", i915_drpc_info, 0},
  1443. {"i915_emon_status", i915_emon_status, 0},
  1444. {"i915_ring_freq_table", i915_ring_freq_table, 0},
  1445. {"i915_gfxec", i915_gfxec, 0},
  1446. {"i915_fbc_status", i915_fbc_status, 0},
  1447. {"i915_sr_status", i915_sr_status, 0},
  1448. {"i915_opregion", i915_opregion, 0},
  1449. {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
  1450. {"i915_context_status", i915_context_status, 0},
  1451. {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
  1452. };
  1453. #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
  1454. int i915_debugfs_init(struct drm_minor *minor)
  1455. {
  1456. int ret;
  1457. ret = i915_wedged_create(minor->debugfs_root, minor);
  1458. if (ret)
  1459. return ret;
  1460. ret = i915_forcewake_create(minor->debugfs_root, minor);
  1461. if (ret)
  1462. return ret;
  1463. ret = i915_max_freq_create(minor->debugfs_root, minor);
  1464. if (ret)
  1465. return ret;
  1466. ret = i915_cache_sharing_create(minor->debugfs_root, minor);
  1467. if (ret)
  1468. return ret;
  1469. return drm_debugfs_create_files(i915_debugfs_list,
  1470. I915_DEBUGFS_ENTRIES,
  1471. minor->debugfs_root, minor);
  1472. }
  1473. void i915_debugfs_cleanup(struct drm_minor *minor)
  1474. {
  1475. drm_debugfs_remove_files(i915_debugfs_list,
  1476. I915_DEBUGFS_ENTRIES, minor);
  1477. drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
  1478. 1, minor);
  1479. drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
  1480. 1, minor);
  1481. drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
  1482. 1, minor);
  1483. drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
  1484. 1, minor);
  1485. }
  1486. #endif /* CONFIG_DEBUG_FS */