iwl-agn.c 134 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/pci-aspm.h>
  35. #include <linux/slab.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/delay.h>
  38. #include <linux/sched.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/wireless.h>
  42. #include <linux/firmware.h>
  43. #include <linux/etherdevice.h>
  44. #include <linux/if_arp.h>
  45. #include <net/mac80211.h>
  46. #include <asm/div64.h>
  47. #define DRV_NAME "iwlagn"
  48. #include "iwl-eeprom.h"
  49. #include "iwl-dev.h"
  50. #include "iwl-core.h"
  51. #include "iwl-io.h"
  52. #include "iwl-helpers.h"
  53. #include "iwl-sta.h"
  54. #include "iwl-calib.h"
  55. #include "iwl-agn.h"
  56. /******************************************************************************
  57. *
  58. * module boiler plate
  59. *
  60. ******************************************************************************/
  61. /*
  62. * module name, copyright, version, etc.
  63. */
  64. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  65. #ifdef CONFIG_IWLWIFI_DEBUG
  66. #define VD "d"
  67. #else
  68. #define VD
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. MODULE_ALIAS("iwl4965");
  76. static int iwlagn_ant_coupling;
  77. /**
  78. * iwl_commit_rxon - commit staging_rxon to hardware
  79. *
  80. * The RXON command in staging_rxon is committed to the hardware and
  81. * the active_rxon structure is updated with the new data. This
  82. * function correctly transitions out of the RXON_ASSOC_MSK state if
  83. * a HW tune is required based on the RXON structure changes.
  84. */
  85. int iwl_commit_rxon(struct iwl_priv *priv)
  86. {
  87. /* cast away the const for active_rxon in this function */
  88. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  89. int ret;
  90. bool new_assoc =
  91. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  92. if (!iwl_is_alive(priv))
  93. return -EBUSY;
  94. /* always get timestamp with Rx frame */
  95. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  96. ret = iwl_check_rxon_cmd(priv);
  97. if (ret) {
  98. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  99. return -EINVAL;
  100. }
  101. /*
  102. * receive commit_rxon request
  103. * abort any previous channel switch if still in process
  104. */
  105. if (priv->switch_rxon.switch_in_progress &&
  106. (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
  107. IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
  108. le16_to_cpu(priv->switch_rxon.channel));
  109. iwl_chswitch_done(priv, false);
  110. }
  111. /* If we don't need to send a full RXON, we can use
  112. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  113. * and other flags for the current radio configuration. */
  114. if (!iwl_full_rxon_required(priv)) {
  115. ret = iwl_send_rxon_assoc(priv);
  116. if (ret) {
  117. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  118. return ret;
  119. }
  120. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  121. iwl_print_rx_config_cmd(priv);
  122. return 0;
  123. }
  124. /* If we are currently associated and the new config requires
  125. * an RXON_ASSOC and the new config wants the associated mask enabled,
  126. * we must clear the associated from the active configuration
  127. * before we apply the new config */
  128. if (iwl_is_associated(priv) && new_assoc) {
  129. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  130. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  131. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  132. sizeof(struct iwl_rxon_cmd),
  133. &priv->active_rxon);
  134. /* If the mask clearing failed then we set
  135. * active_rxon back to what it was previously */
  136. if (ret) {
  137. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  138. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  139. return ret;
  140. }
  141. iwl_clear_ucode_stations(priv);
  142. iwl_restore_stations(priv);
  143. ret = iwl_restore_default_wep_keys(priv);
  144. if (ret) {
  145. IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
  146. return ret;
  147. }
  148. }
  149. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  150. "* with%s RXON_FILTER_ASSOC_MSK\n"
  151. "* channel = %d\n"
  152. "* bssid = %pM\n",
  153. (new_assoc ? "" : "out"),
  154. le16_to_cpu(priv->staging_rxon.channel),
  155. priv->staging_rxon.bssid_addr);
  156. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  157. /* Apply the new configuration
  158. * RXON unassoc clears the station table in uCode so restoration of
  159. * stations is needed after it (the RXON command) completes
  160. */
  161. if (!new_assoc) {
  162. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  163. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  164. if (ret) {
  165. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  166. return ret;
  167. }
  168. IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
  169. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  170. iwl_clear_ucode_stations(priv);
  171. iwl_restore_stations(priv);
  172. ret = iwl_restore_default_wep_keys(priv);
  173. if (ret) {
  174. IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
  175. return ret;
  176. }
  177. }
  178. priv->start_calib = 0;
  179. if (new_assoc) {
  180. /* Apply the new configuration
  181. * RXON assoc doesn't clear the station table in uCode,
  182. */
  183. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  184. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  185. if (ret) {
  186. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  187. return ret;
  188. }
  189. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  190. }
  191. iwl_print_rx_config_cmd(priv);
  192. iwl_init_sensitivity(priv);
  193. /* If we issue a new RXON command which required a tune then we must
  194. * send a new TXPOWER command or we won't be able to Tx any frames */
  195. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  196. if (ret) {
  197. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  198. return ret;
  199. }
  200. return 0;
  201. }
  202. void iwl_update_chain_flags(struct iwl_priv *priv)
  203. {
  204. if (priv->cfg->ops->hcmd->set_rxon_chain)
  205. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  206. iwlcore_commit_rxon(priv);
  207. }
  208. static void iwl_clear_free_frames(struct iwl_priv *priv)
  209. {
  210. struct list_head *element;
  211. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  212. priv->frames_count);
  213. while (!list_empty(&priv->free_frames)) {
  214. element = priv->free_frames.next;
  215. list_del(element);
  216. kfree(list_entry(element, struct iwl_frame, list));
  217. priv->frames_count--;
  218. }
  219. if (priv->frames_count) {
  220. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  221. priv->frames_count);
  222. priv->frames_count = 0;
  223. }
  224. }
  225. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  226. {
  227. struct iwl_frame *frame;
  228. struct list_head *element;
  229. if (list_empty(&priv->free_frames)) {
  230. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  231. if (!frame) {
  232. IWL_ERR(priv, "Could not allocate frame!\n");
  233. return NULL;
  234. }
  235. priv->frames_count++;
  236. return frame;
  237. }
  238. element = priv->free_frames.next;
  239. list_del(element);
  240. return list_entry(element, struct iwl_frame, list);
  241. }
  242. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  243. {
  244. memset(frame, 0, sizeof(*frame));
  245. list_add(&frame->list, &priv->free_frames);
  246. }
  247. static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
  248. struct ieee80211_hdr *hdr,
  249. int left)
  250. {
  251. if (!priv->ibss_beacon)
  252. return 0;
  253. if (priv->ibss_beacon->len > left)
  254. return 0;
  255. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  256. return priv->ibss_beacon->len;
  257. }
  258. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  259. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  260. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  261. u8 *beacon, u32 frame_size)
  262. {
  263. u16 tim_idx;
  264. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  265. /*
  266. * The index is relative to frame start but we start looking at the
  267. * variable-length part of the beacon.
  268. */
  269. tim_idx = mgmt->u.beacon.variable - beacon;
  270. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  271. while ((tim_idx < (frame_size - 2)) &&
  272. (beacon[tim_idx] != WLAN_EID_TIM))
  273. tim_idx += beacon[tim_idx+1] + 2;
  274. /* If TIM field was found, set variables */
  275. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  276. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  277. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  278. } else
  279. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  280. }
  281. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  282. struct iwl_frame *frame)
  283. {
  284. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  285. u32 frame_size;
  286. u32 rate_flags;
  287. u32 rate;
  288. /*
  289. * We have to set up the TX command, the TX Beacon command, and the
  290. * beacon contents.
  291. */
  292. /* Initialize memory */
  293. tx_beacon_cmd = &frame->u.beacon;
  294. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  295. /* Set up TX beacon contents */
  296. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  297. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  298. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  299. return 0;
  300. /* Set up TX command fields */
  301. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  302. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  303. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  304. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  305. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  306. /* Set up TX beacon command fields */
  307. iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  308. frame_size);
  309. /* Set up packet rate and flags */
  310. rate = iwl_rate_get_lowest_plcp(priv);
  311. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
  312. priv->hw_params.valid_tx_ant);
  313. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  314. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  315. rate_flags |= RATE_MCS_CCK_MSK;
  316. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  317. rate_flags);
  318. return sizeof(*tx_beacon_cmd) + frame_size;
  319. }
  320. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  321. {
  322. struct iwl_frame *frame;
  323. unsigned int frame_size;
  324. int rc;
  325. frame = iwl_get_free_frame(priv);
  326. if (!frame) {
  327. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  328. "command.\n");
  329. return -ENOMEM;
  330. }
  331. frame_size = iwl_hw_get_beacon_cmd(priv, frame);
  332. if (!frame_size) {
  333. IWL_ERR(priv, "Error configuring the beacon command\n");
  334. iwl_free_frame(priv, frame);
  335. return -EINVAL;
  336. }
  337. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  338. &frame->u.cmd[0]);
  339. iwl_free_frame(priv, frame);
  340. return rc;
  341. }
  342. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  343. {
  344. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  345. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  346. if (sizeof(dma_addr_t) > sizeof(u32))
  347. addr |=
  348. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  349. return addr;
  350. }
  351. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  352. {
  353. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  354. return le16_to_cpu(tb->hi_n_len) >> 4;
  355. }
  356. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  357. dma_addr_t addr, u16 len)
  358. {
  359. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  360. u16 hi_n_len = len << 4;
  361. put_unaligned_le32(addr, &tb->lo);
  362. if (sizeof(dma_addr_t) > sizeof(u32))
  363. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  364. tb->hi_n_len = cpu_to_le16(hi_n_len);
  365. tfd->num_tbs = idx + 1;
  366. }
  367. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  368. {
  369. return tfd->num_tbs & 0x1f;
  370. }
  371. /**
  372. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  373. * @priv - driver private data
  374. * @txq - tx queue
  375. *
  376. * Does NOT advance any TFD circular buffer read/write indexes
  377. * Does NOT free the TFD itself (which is within circular buffer)
  378. */
  379. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  380. {
  381. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  382. struct iwl_tfd *tfd;
  383. struct pci_dev *dev = priv->pci_dev;
  384. int index = txq->q.read_ptr;
  385. int i;
  386. int num_tbs;
  387. tfd = &tfd_tmp[index];
  388. /* Sanity check on number of chunks */
  389. num_tbs = iwl_tfd_get_num_tbs(tfd);
  390. if (num_tbs >= IWL_NUM_OF_TBS) {
  391. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  392. /* @todo issue fatal error, it is quite serious situation */
  393. return;
  394. }
  395. /* Unmap tx_cmd */
  396. if (num_tbs)
  397. pci_unmap_single(dev,
  398. dma_unmap_addr(&txq->meta[index], mapping),
  399. dma_unmap_len(&txq->meta[index], len),
  400. PCI_DMA_BIDIRECTIONAL);
  401. /* Unmap chunks, if any. */
  402. for (i = 1; i < num_tbs; i++)
  403. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  404. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  405. /* free SKB */
  406. if (txq->txb) {
  407. struct sk_buff *skb;
  408. skb = txq->txb[txq->q.read_ptr].skb;
  409. /* can be called from irqs-disabled context */
  410. if (skb) {
  411. dev_kfree_skb_any(skb);
  412. txq->txb[txq->q.read_ptr].skb = NULL;
  413. }
  414. }
  415. }
  416. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  417. struct iwl_tx_queue *txq,
  418. dma_addr_t addr, u16 len,
  419. u8 reset, u8 pad)
  420. {
  421. struct iwl_queue *q;
  422. struct iwl_tfd *tfd, *tfd_tmp;
  423. u32 num_tbs;
  424. q = &txq->q;
  425. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  426. tfd = &tfd_tmp[q->write_ptr];
  427. if (reset)
  428. memset(tfd, 0, sizeof(*tfd));
  429. num_tbs = iwl_tfd_get_num_tbs(tfd);
  430. /* Each TFD can point to a maximum 20 Tx buffers */
  431. if (num_tbs >= IWL_NUM_OF_TBS) {
  432. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  433. IWL_NUM_OF_TBS);
  434. return -EINVAL;
  435. }
  436. BUG_ON(addr & ~DMA_BIT_MASK(36));
  437. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  438. IWL_ERR(priv, "Unaligned address = %llx\n",
  439. (unsigned long long)addr);
  440. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  441. return 0;
  442. }
  443. /*
  444. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  445. * given Tx queue, and enable the DMA channel used for that queue.
  446. *
  447. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  448. * channels supported in hardware.
  449. */
  450. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  451. struct iwl_tx_queue *txq)
  452. {
  453. int txq_id = txq->q.id;
  454. /* Circular buffer (TFD queue in DRAM) physical base address */
  455. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  456. txq->q.dma_addr >> 8);
  457. return 0;
  458. }
  459. /******************************************************************************
  460. *
  461. * Generic RX handler implementations
  462. *
  463. ******************************************************************************/
  464. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  465. struct iwl_rx_mem_buffer *rxb)
  466. {
  467. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  468. struct iwl_alive_resp *palive;
  469. struct delayed_work *pwork;
  470. palive = &pkt->u.alive_frame;
  471. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  472. "0x%01X 0x%01X\n",
  473. palive->is_valid, palive->ver_type,
  474. palive->ver_subtype);
  475. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  476. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  477. memcpy(&priv->card_alive_init,
  478. &pkt->u.alive_frame,
  479. sizeof(struct iwl_init_alive_resp));
  480. pwork = &priv->init_alive_start;
  481. } else {
  482. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  483. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  484. sizeof(struct iwl_alive_resp));
  485. pwork = &priv->alive_start;
  486. }
  487. /* We delay the ALIVE response by 5ms to
  488. * give the HW RF Kill time to activate... */
  489. if (palive->is_valid == UCODE_VALID_OK)
  490. queue_delayed_work(priv->workqueue, pwork,
  491. msecs_to_jiffies(5));
  492. else
  493. IWL_WARN(priv, "uCode did not respond OK.\n");
  494. }
  495. static void iwl_bg_beacon_update(struct work_struct *work)
  496. {
  497. struct iwl_priv *priv =
  498. container_of(work, struct iwl_priv, beacon_update);
  499. struct sk_buff *beacon;
  500. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  501. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  502. if (!beacon) {
  503. IWL_ERR(priv, "update beacon failed\n");
  504. return;
  505. }
  506. mutex_lock(&priv->mutex);
  507. /* new beacon skb is allocated every time; dispose previous.*/
  508. if (priv->ibss_beacon)
  509. dev_kfree_skb(priv->ibss_beacon);
  510. priv->ibss_beacon = beacon;
  511. mutex_unlock(&priv->mutex);
  512. iwl_send_beacon_cmd(priv);
  513. }
  514. static void iwl_bg_bt_full_concurrency(struct work_struct *work)
  515. {
  516. struct iwl_priv *priv =
  517. container_of(work, struct iwl_priv, bt_full_concurrency);
  518. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  519. return;
  520. /* dont send host command if rf-kill is on */
  521. if (!iwl_is_ready_rf(priv))
  522. return;
  523. IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
  524. priv->bt_full_concurrent ?
  525. "full concurrency" : "3-wire");
  526. /*
  527. * LQ & RXON updated cmds must be sent before BT Config cmd
  528. * to avoid 3-wire collisions
  529. */
  530. if (priv->cfg->ops->hcmd->set_rxon_chain)
  531. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  532. iwlcore_commit_rxon(priv);
  533. priv->cfg->ops->hcmd->send_bt_config(priv);
  534. }
  535. /**
  536. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  537. *
  538. * This callback is provided in order to send a statistics request.
  539. *
  540. * This timer function is continually reset to execute within
  541. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  542. * was received. We need to ensure we receive the statistics in order
  543. * to update the temperature used for calibrating the TXPOWER.
  544. */
  545. static void iwl_bg_statistics_periodic(unsigned long data)
  546. {
  547. struct iwl_priv *priv = (struct iwl_priv *)data;
  548. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  549. return;
  550. /* dont send host command if rf-kill is on */
  551. if (!iwl_is_ready_rf(priv))
  552. return;
  553. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  554. }
  555. static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
  556. u32 start_idx, u32 num_events,
  557. u32 mode)
  558. {
  559. u32 i;
  560. u32 ptr; /* SRAM byte address of log data */
  561. u32 ev, time, data; /* event log data */
  562. unsigned long reg_flags;
  563. if (mode == 0)
  564. ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
  565. else
  566. ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
  567. /* Make sure device is powered up for SRAM reads */
  568. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  569. if (iwl_grab_nic_access(priv)) {
  570. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  571. return;
  572. }
  573. /* Set starting address; reads will auto-increment */
  574. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  575. rmb();
  576. /*
  577. * "time" is actually "data" for mode 0 (no timestamp).
  578. * place event id # at far right for easier visual parsing.
  579. */
  580. for (i = 0; i < num_events; i++) {
  581. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  582. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  583. if (mode == 0) {
  584. trace_iwlwifi_dev_ucode_cont_event(priv,
  585. 0, time, ev);
  586. } else {
  587. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  588. trace_iwlwifi_dev_ucode_cont_event(priv,
  589. time, data, ev);
  590. }
  591. }
  592. /* Allow device to power down */
  593. iwl_release_nic_access(priv);
  594. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  595. }
  596. static void iwl_continuous_event_trace(struct iwl_priv *priv)
  597. {
  598. u32 capacity; /* event log capacity in # entries */
  599. u32 base; /* SRAM byte address of event log header */
  600. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  601. u32 num_wraps; /* # times uCode wrapped to top of log */
  602. u32 next_entry; /* index of next entry to be written by uCode */
  603. if (priv->ucode_type == UCODE_INIT)
  604. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  605. else
  606. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  607. if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  608. capacity = iwl_read_targ_mem(priv, base);
  609. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  610. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  611. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  612. } else
  613. return;
  614. if (num_wraps == priv->event_log.num_wraps) {
  615. iwl_print_cont_event_trace(priv,
  616. base, priv->event_log.next_entry,
  617. next_entry - priv->event_log.next_entry,
  618. mode);
  619. priv->event_log.non_wraps_count++;
  620. } else {
  621. if ((num_wraps - priv->event_log.num_wraps) > 1)
  622. priv->event_log.wraps_more_count++;
  623. else
  624. priv->event_log.wraps_once_count++;
  625. trace_iwlwifi_dev_ucode_wrap_event(priv,
  626. num_wraps - priv->event_log.num_wraps,
  627. next_entry, priv->event_log.next_entry);
  628. if (next_entry < priv->event_log.next_entry) {
  629. iwl_print_cont_event_trace(priv, base,
  630. priv->event_log.next_entry,
  631. capacity - priv->event_log.next_entry,
  632. mode);
  633. iwl_print_cont_event_trace(priv, base, 0,
  634. next_entry, mode);
  635. } else {
  636. iwl_print_cont_event_trace(priv, base,
  637. next_entry, capacity - next_entry,
  638. mode);
  639. iwl_print_cont_event_trace(priv, base, 0,
  640. next_entry, mode);
  641. }
  642. }
  643. priv->event_log.num_wraps = num_wraps;
  644. priv->event_log.next_entry = next_entry;
  645. }
  646. /**
  647. * iwl_bg_ucode_trace - Timer callback to log ucode event
  648. *
  649. * The timer is continually set to execute every
  650. * UCODE_TRACE_PERIOD milliseconds after the last timer expired
  651. * this function is to perform continuous uCode event logging operation
  652. * if enabled
  653. */
  654. static void iwl_bg_ucode_trace(unsigned long data)
  655. {
  656. struct iwl_priv *priv = (struct iwl_priv *)data;
  657. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  658. return;
  659. if (priv->event_log.ucode_trace) {
  660. iwl_continuous_event_trace(priv);
  661. /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
  662. mod_timer(&priv->ucode_trace,
  663. jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
  664. }
  665. }
  666. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  667. struct iwl_rx_mem_buffer *rxb)
  668. {
  669. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  670. struct iwl4965_beacon_notif *beacon =
  671. (struct iwl4965_beacon_notif *)pkt->u.raw;
  672. #ifdef CONFIG_IWLWIFI_DEBUG
  673. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  674. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  675. "tsf %d %d rate %d\n",
  676. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  677. beacon->beacon_notify_hdr.failure_frame,
  678. le32_to_cpu(beacon->ibss_mgr_status),
  679. le32_to_cpu(beacon->high_tsf),
  680. le32_to_cpu(beacon->low_tsf), rate);
  681. #endif
  682. priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
  683. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  684. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  685. queue_work(priv->workqueue, &priv->beacon_update);
  686. }
  687. /* Handle notification from uCode that card's power state is changing
  688. * due to software, hardware, or critical temperature RFKILL */
  689. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  690. struct iwl_rx_mem_buffer *rxb)
  691. {
  692. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  693. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  694. unsigned long status = priv->status;
  695. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
  696. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  697. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  698. (flags & CT_CARD_DISABLED) ?
  699. "Reached" : "Not reached");
  700. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  701. CT_CARD_DISABLED)) {
  702. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  703. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  704. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  705. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  706. if (!(flags & RXON_CARD_DISABLED)) {
  707. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  708. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  709. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  710. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  711. }
  712. if (flags & CT_CARD_DISABLED)
  713. iwl_tt_enter_ct_kill(priv);
  714. }
  715. if (!(flags & CT_CARD_DISABLED))
  716. iwl_tt_exit_ct_kill(priv);
  717. if (flags & HW_CARD_DISABLED)
  718. set_bit(STATUS_RF_KILL_HW, &priv->status);
  719. else
  720. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  721. if (!(flags & RXON_CARD_DISABLED))
  722. iwl_scan_cancel(priv);
  723. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  724. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  725. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  726. test_bit(STATUS_RF_KILL_HW, &priv->status));
  727. else
  728. wake_up_interruptible(&priv->wait_command_queue);
  729. }
  730. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  731. {
  732. if (src == IWL_PWR_SRC_VAUX) {
  733. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  734. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  735. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  736. ~APMG_PS_CTRL_MSK_PWR_SRC);
  737. } else {
  738. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  739. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  740. ~APMG_PS_CTRL_MSK_PWR_SRC);
  741. }
  742. return 0;
  743. }
  744. static void iwl_bg_tx_flush(struct work_struct *work)
  745. {
  746. struct iwl_priv *priv =
  747. container_of(work, struct iwl_priv, tx_flush);
  748. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  749. return;
  750. /* do nothing if rf-kill is on */
  751. if (!iwl_is_ready_rf(priv))
  752. return;
  753. if (priv->cfg->ops->lib->txfifo_flush) {
  754. IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
  755. iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
  756. }
  757. }
  758. /**
  759. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  760. *
  761. * Setup the RX handlers for each of the reply types sent from the uCode
  762. * to the host.
  763. *
  764. * This function chains into the hardware specific files for them to setup
  765. * any hardware specific handlers as well.
  766. */
  767. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  768. {
  769. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  770. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  771. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  772. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  773. iwl_rx_spectrum_measure_notif;
  774. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  775. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  776. iwl_rx_pm_debug_statistics_notif;
  777. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  778. /*
  779. * The same handler is used for both the REPLY to a discrete
  780. * statistics request from the host as well as for the periodic
  781. * statistics notifications (after received beacons) from the uCode.
  782. */
  783. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
  784. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  785. iwl_setup_rx_scan_handlers(priv);
  786. /* status change handler */
  787. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  788. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  789. iwl_rx_missed_beacon_notif;
  790. /* Rx handlers */
  791. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
  792. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
  793. /* block ack */
  794. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
  795. /* Set up hardware specific Rx handlers */
  796. priv->cfg->ops->lib->rx_handler_setup(priv);
  797. }
  798. /**
  799. * iwl_rx_handle - Main entry function for receiving responses from uCode
  800. *
  801. * Uses the priv->rx_handlers callback function array to invoke
  802. * the appropriate handlers, including command responses,
  803. * frame-received notifications, and other notifications.
  804. */
  805. void iwl_rx_handle(struct iwl_priv *priv)
  806. {
  807. struct iwl_rx_mem_buffer *rxb;
  808. struct iwl_rx_packet *pkt;
  809. struct iwl_rx_queue *rxq = &priv->rxq;
  810. u32 r, i;
  811. int reclaim;
  812. unsigned long flags;
  813. u8 fill_rx = 0;
  814. u32 count = 8;
  815. int total_empty;
  816. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  817. * buffer that the driver may process (last buffer filled by ucode). */
  818. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  819. i = rxq->read;
  820. /* Rx interrupt, but nothing sent from uCode */
  821. if (i == r)
  822. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  823. /* calculate total frames need to be restock after handling RX */
  824. total_empty = r - rxq->write_actual;
  825. if (total_empty < 0)
  826. total_empty += RX_QUEUE_SIZE;
  827. if (total_empty > (RX_QUEUE_SIZE / 2))
  828. fill_rx = 1;
  829. while (i != r) {
  830. int len;
  831. rxb = rxq->queue[i];
  832. /* If an RXB doesn't have a Rx queue slot associated with it,
  833. * then a bug has been introduced in the queue refilling
  834. * routines -- catch it here */
  835. BUG_ON(rxb == NULL);
  836. rxq->queue[i] = NULL;
  837. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  838. PAGE_SIZE << priv->hw_params.rx_page_order,
  839. PCI_DMA_FROMDEVICE);
  840. pkt = rxb_addr(rxb);
  841. len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  842. len += sizeof(u32); /* account for status word */
  843. trace_iwlwifi_dev_rx(priv, pkt, len);
  844. /* Reclaim a command buffer only if this packet is a response
  845. * to a (driver-originated) command.
  846. * If the packet (e.g. Rx frame) originated from uCode,
  847. * there is no command buffer to reclaim.
  848. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  849. * but apparently a few don't get set; catch them here. */
  850. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  851. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  852. (pkt->hdr.cmd != REPLY_RX) &&
  853. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  854. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  855. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  856. (pkt->hdr.cmd != REPLY_TX);
  857. /* Based on type of command response or notification,
  858. * handle those that need handling via function in
  859. * rx_handlers table. See iwl_setup_rx_handlers() */
  860. if (priv->rx_handlers[pkt->hdr.cmd]) {
  861. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  862. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  863. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  864. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  865. } else {
  866. /* No handling needed */
  867. IWL_DEBUG_RX(priv,
  868. "r %d i %d No handler needed for %s, 0x%02x\n",
  869. r, i, get_cmd_string(pkt->hdr.cmd),
  870. pkt->hdr.cmd);
  871. }
  872. /*
  873. * XXX: After here, we should always check rxb->page
  874. * against NULL before touching it or its virtual
  875. * memory (pkt). Because some rx_handler might have
  876. * already taken or freed the pages.
  877. */
  878. if (reclaim) {
  879. /* Invoke any callbacks, transfer the buffer to caller,
  880. * and fire off the (possibly) blocking iwl_send_cmd()
  881. * as we reclaim the driver command queue */
  882. if (rxb->page)
  883. iwl_tx_cmd_complete(priv, rxb);
  884. else
  885. IWL_WARN(priv, "Claim null rxb?\n");
  886. }
  887. /* Reuse the page if possible. For notification packets and
  888. * SKBs that fail to Rx correctly, add them back into the
  889. * rx_free list for reuse later. */
  890. spin_lock_irqsave(&rxq->lock, flags);
  891. if (rxb->page != NULL) {
  892. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  893. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  894. PCI_DMA_FROMDEVICE);
  895. list_add_tail(&rxb->list, &rxq->rx_free);
  896. rxq->free_count++;
  897. } else
  898. list_add_tail(&rxb->list, &rxq->rx_used);
  899. spin_unlock_irqrestore(&rxq->lock, flags);
  900. i = (i + 1) & RX_QUEUE_MASK;
  901. /* If there are a lot of unused frames,
  902. * restock the Rx queue so ucode wont assert. */
  903. if (fill_rx) {
  904. count++;
  905. if (count >= 8) {
  906. rxq->read = i;
  907. iwlagn_rx_replenish_now(priv);
  908. count = 0;
  909. }
  910. }
  911. }
  912. /* Backtrack one entry */
  913. rxq->read = i;
  914. if (fill_rx)
  915. iwlagn_rx_replenish_now(priv);
  916. else
  917. iwlagn_rx_queue_restock(priv);
  918. }
  919. /* call this function to flush any scheduled tasklet */
  920. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  921. {
  922. /* wait to make sure we flush pending tasklet*/
  923. synchronize_irq(priv->pci_dev->irq);
  924. tasklet_kill(&priv->irq_tasklet);
  925. }
  926. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  927. {
  928. u32 inta, handled = 0;
  929. u32 inta_fh;
  930. unsigned long flags;
  931. u32 i;
  932. #ifdef CONFIG_IWLWIFI_DEBUG
  933. u32 inta_mask;
  934. #endif
  935. spin_lock_irqsave(&priv->lock, flags);
  936. /* Ack/clear/reset pending uCode interrupts.
  937. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  938. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  939. inta = iwl_read32(priv, CSR_INT);
  940. iwl_write32(priv, CSR_INT, inta);
  941. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  942. * Any new interrupts that happen after this, either while we're
  943. * in this tasklet, or later, will show up in next ISR/tasklet. */
  944. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  945. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  946. #ifdef CONFIG_IWLWIFI_DEBUG
  947. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  948. /* just for debug */
  949. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  950. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  951. inta, inta_mask, inta_fh);
  952. }
  953. #endif
  954. spin_unlock_irqrestore(&priv->lock, flags);
  955. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  956. * atomic, make sure that inta covers all the interrupts that
  957. * we've discovered, even if FH interrupt came in just after
  958. * reading CSR_INT. */
  959. if (inta_fh & CSR49_FH_INT_RX_MASK)
  960. inta |= CSR_INT_BIT_FH_RX;
  961. if (inta_fh & CSR49_FH_INT_TX_MASK)
  962. inta |= CSR_INT_BIT_FH_TX;
  963. /* Now service all interrupt bits discovered above. */
  964. if (inta & CSR_INT_BIT_HW_ERR) {
  965. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  966. /* Tell the device to stop sending interrupts */
  967. iwl_disable_interrupts(priv);
  968. priv->isr_stats.hw++;
  969. iwl_irq_handle_error(priv);
  970. handled |= CSR_INT_BIT_HW_ERR;
  971. return;
  972. }
  973. #ifdef CONFIG_IWLWIFI_DEBUG
  974. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  975. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  976. if (inta & CSR_INT_BIT_SCD) {
  977. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  978. "the frame/frames.\n");
  979. priv->isr_stats.sch++;
  980. }
  981. /* Alive notification via Rx interrupt will do the real work */
  982. if (inta & CSR_INT_BIT_ALIVE) {
  983. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  984. priv->isr_stats.alive++;
  985. }
  986. }
  987. #endif
  988. /* Safely ignore these bits for debug checks below */
  989. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  990. /* HW RF KILL switch toggled */
  991. if (inta & CSR_INT_BIT_RF_KILL) {
  992. int hw_rf_kill = 0;
  993. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  994. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  995. hw_rf_kill = 1;
  996. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  997. hw_rf_kill ? "disable radio" : "enable radio");
  998. priv->isr_stats.rfkill++;
  999. /* driver only loads ucode once setting the interface up.
  1000. * the driver allows loading the ucode even if the radio
  1001. * is killed. Hence update the killswitch state here. The
  1002. * rfkill handler will care about restarting if needed.
  1003. */
  1004. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1005. if (hw_rf_kill)
  1006. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1007. else
  1008. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1009. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  1010. }
  1011. handled |= CSR_INT_BIT_RF_KILL;
  1012. }
  1013. /* Chip got too hot and stopped itself */
  1014. if (inta & CSR_INT_BIT_CT_KILL) {
  1015. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1016. priv->isr_stats.ctkill++;
  1017. handled |= CSR_INT_BIT_CT_KILL;
  1018. }
  1019. /* Error detected by uCode */
  1020. if (inta & CSR_INT_BIT_SW_ERR) {
  1021. IWL_ERR(priv, "Microcode SW error detected. "
  1022. " Restarting 0x%X.\n", inta);
  1023. priv->isr_stats.sw++;
  1024. priv->isr_stats.sw_err = inta;
  1025. iwl_irq_handle_error(priv);
  1026. handled |= CSR_INT_BIT_SW_ERR;
  1027. }
  1028. /*
  1029. * uCode wakes up after power-down sleep.
  1030. * Tell device about any new tx or host commands enqueued,
  1031. * and about any Rx buffers made available while asleep.
  1032. */
  1033. if (inta & CSR_INT_BIT_WAKEUP) {
  1034. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1035. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1036. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1037. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1038. priv->isr_stats.wakeup++;
  1039. handled |= CSR_INT_BIT_WAKEUP;
  1040. }
  1041. /* All uCode command responses, including Tx command responses,
  1042. * Rx "responses" (frame-received notification), and other
  1043. * notifications from uCode come through here*/
  1044. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1045. iwl_rx_handle(priv);
  1046. priv->isr_stats.rx++;
  1047. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1048. }
  1049. /* This "Tx" DMA channel is used only for loading uCode */
  1050. if (inta & CSR_INT_BIT_FH_TX) {
  1051. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1052. priv->isr_stats.tx++;
  1053. handled |= CSR_INT_BIT_FH_TX;
  1054. /* Wake up uCode load routine, now that load is complete */
  1055. priv->ucode_write_complete = 1;
  1056. wake_up_interruptible(&priv->wait_command_queue);
  1057. }
  1058. if (inta & ~handled) {
  1059. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1060. priv->isr_stats.unhandled++;
  1061. }
  1062. if (inta & ~(priv->inta_mask)) {
  1063. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1064. inta & ~priv->inta_mask);
  1065. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  1066. }
  1067. /* Re-enable all interrupts */
  1068. /* only Re-enable if diabled by irq */
  1069. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1070. iwl_enable_interrupts(priv);
  1071. #ifdef CONFIG_IWLWIFI_DEBUG
  1072. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1073. inta = iwl_read32(priv, CSR_INT);
  1074. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1075. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1076. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1077. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1078. }
  1079. #endif
  1080. }
  1081. /* tasklet for iwlagn interrupt */
  1082. static void iwl_irq_tasklet(struct iwl_priv *priv)
  1083. {
  1084. u32 inta = 0;
  1085. u32 handled = 0;
  1086. unsigned long flags;
  1087. u32 i;
  1088. #ifdef CONFIG_IWLWIFI_DEBUG
  1089. u32 inta_mask;
  1090. #endif
  1091. spin_lock_irqsave(&priv->lock, flags);
  1092. /* Ack/clear/reset pending uCode interrupts.
  1093. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1094. */
  1095. /* There is a hardware bug in the interrupt mask function that some
  1096. * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
  1097. * they are disabled in the CSR_INT_MASK register. Furthermore the
  1098. * ICT interrupt handling mechanism has another bug that might cause
  1099. * these unmasked interrupts fail to be detected. We workaround the
  1100. * hardware bugs here by ACKing all the possible interrupts so that
  1101. * interrupt coalescing can still be achieved.
  1102. */
  1103. iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
  1104. inta = priv->_agn.inta;
  1105. #ifdef CONFIG_IWLWIFI_DEBUG
  1106. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  1107. /* just for debug */
  1108. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1109. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  1110. inta, inta_mask);
  1111. }
  1112. #endif
  1113. spin_unlock_irqrestore(&priv->lock, flags);
  1114. /* saved interrupt in inta variable now we can reset priv->_agn.inta */
  1115. priv->_agn.inta = 0;
  1116. /* Now service all interrupt bits discovered above. */
  1117. if (inta & CSR_INT_BIT_HW_ERR) {
  1118. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  1119. /* Tell the device to stop sending interrupts */
  1120. iwl_disable_interrupts(priv);
  1121. priv->isr_stats.hw++;
  1122. iwl_irq_handle_error(priv);
  1123. handled |= CSR_INT_BIT_HW_ERR;
  1124. return;
  1125. }
  1126. #ifdef CONFIG_IWLWIFI_DEBUG
  1127. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1128. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1129. if (inta & CSR_INT_BIT_SCD) {
  1130. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  1131. "the frame/frames.\n");
  1132. priv->isr_stats.sch++;
  1133. }
  1134. /* Alive notification via Rx interrupt will do the real work */
  1135. if (inta & CSR_INT_BIT_ALIVE) {
  1136. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  1137. priv->isr_stats.alive++;
  1138. }
  1139. }
  1140. #endif
  1141. /* Safely ignore these bits for debug checks below */
  1142. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1143. /* HW RF KILL switch toggled */
  1144. if (inta & CSR_INT_BIT_RF_KILL) {
  1145. int hw_rf_kill = 0;
  1146. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  1147. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  1148. hw_rf_kill = 1;
  1149. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  1150. hw_rf_kill ? "disable radio" : "enable radio");
  1151. priv->isr_stats.rfkill++;
  1152. /* driver only loads ucode once setting the interface up.
  1153. * the driver allows loading the ucode even if the radio
  1154. * is killed. Hence update the killswitch state here. The
  1155. * rfkill handler will care about restarting if needed.
  1156. */
  1157. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1158. if (hw_rf_kill)
  1159. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1160. else
  1161. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1162. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  1163. }
  1164. handled |= CSR_INT_BIT_RF_KILL;
  1165. }
  1166. /* Chip got too hot and stopped itself */
  1167. if (inta & CSR_INT_BIT_CT_KILL) {
  1168. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1169. priv->isr_stats.ctkill++;
  1170. handled |= CSR_INT_BIT_CT_KILL;
  1171. }
  1172. /* Error detected by uCode */
  1173. if (inta & CSR_INT_BIT_SW_ERR) {
  1174. IWL_ERR(priv, "Microcode SW error detected. "
  1175. " Restarting 0x%X.\n", inta);
  1176. priv->isr_stats.sw++;
  1177. priv->isr_stats.sw_err = inta;
  1178. iwl_irq_handle_error(priv);
  1179. handled |= CSR_INT_BIT_SW_ERR;
  1180. }
  1181. /* uCode wakes up after power-down sleep */
  1182. if (inta & CSR_INT_BIT_WAKEUP) {
  1183. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1184. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1185. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1186. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1187. priv->isr_stats.wakeup++;
  1188. handled |= CSR_INT_BIT_WAKEUP;
  1189. }
  1190. /* All uCode command responses, including Tx command responses,
  1191. * Rx "responses" (frame-received notification), and other
  1192. * notifications from uCode come through here*/
  1193. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1194. CSR_INT_BIT_RX_PERIODIC)) {
  1195. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1196. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1197. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1198. iwl_write32(priv, CSR_FH_INT_STATUS,
  1199. CSR49_FH_INT_RX_MASK);
  1200. }
  1201. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1202. handled |= CSR_INT_BIT_RX_PERIODIC;
  1203. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1204. }
  1205. /* Sending RX interrupt require many steps to be done in the
  1206. * the device:
  1207. * 1- write interrupt to current index in ICT table.
  1208. * 2- dma RX frame.
  1209. * 3- update RX shared data to indicate last write index.
  1210. * 4- send interrupt.
  1211. * This could lead to RX race, driver could receive RX interrupt
  1212. * but the shared data changes does not reflect this;
  1213. * periodic interrupt will detect any dangling Rx activity.
  1214. */
  1215. /* Disable periodic interrupt; we use it as just a one-shot. */
  1216. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1217. CSR_INT_PERIODIC_DIS);
  1218. iwl_rx_handle(priv);
  1219. /*
  1220. * Enable periodic interrupt in 8 msec only if we received
  1221. * real RX interrupt (instead of just periodic int), to catch
  1222. * any dangling Rx interrupt. If it was just the periodic
  1223. * interrupt, there was no dangling Rx activity, and no need
  1224. * to extend the periodic interrupt; one-shot is enough.
  1225. */
  1226. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1227. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1228. CSR_INT_PERIODIC_ENA);
  1229. priv->isr_stats.rx++;
  1230. }
  1231. /* This "Tx" DMA channel is used only for loading uCode */
  1232. if (inta & CSR_INT_BIT_FH_TX) {
  1233. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1234. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1235. priv->isr_stats.tx++;
  1236. handled |= CSR_INT_BIT_FH_TX;
  1237. /* Wake up uCode load routine, now that load is complete */
  1238. priv->ucode_write_complete = 1;
  1239. wake_up_interruptible(&priv->wait_command_queue);
  1240. }
  1241. if (inta & ~handled) {
  1242. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1243. priv->isr_stats.unhandled++;
  1244. }
  1245. if (inta & ~(priv->inta_mask)) {
  1246. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1247. inta & ~priv->inta_mask);
  1248. }
  1249. /* Re-enable all interrupts */
  1250. /* only Re-enable if diabled by irq */
  1251. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1252. iwl_enable_interrupts(priv);
  1253. }
  1254. /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
  1255. #define ACK_CNT_RATIO (50)
  1256. #define BA_TIMEOUT_CNT (5)
  1257. #define BA_TIMEOUT_MAX (16)
  1258. /**
  1259. * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
  1260. *
  1261. * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
  1262. * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
  1263. * operation state.
  1264. */
  1265. bool iwl_good_ack_health(struct iwl_priv *priv,
  1266. struct iwl_rx_packet *pkt)
  1267. {
  1268. bool rc = true;
  1269. int actual_ack_cnt_delta, expected_ack_cnt_delta;
  1270. int ba_timeout_delta;
  1271. actual_ack_cnt_delta =
  1272. le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
  1273. le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
  1274. expected_ack_cnt_delta =
  1275. le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
  1276. le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
  1277. ba_timeout_delta =
  1278. le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
  1279. le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
  1280. if ((priv->_agn.agg_tids_count > 0) &&
  1281. (expected_ack_cnt_delta > 0) &&
  1282. (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
  1283. < ACK_CNT_RATIO) &&
  1284. (ba_timeout_delta > BA_TIMEOUT_CNT)) {
  1285. IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
  1286. " expected_ack_cnt = %d\n",
  1287. actual_ack_cnt_delta, expected_ack_cnt_delta);
  1288. #ifdef CONFIG_IWLWIFI_DEBUGFS
  1289. /*
  1290. * This is ifdef'ed on DEBUGFS because otherwise the
  1291. * statistics aren't available. If DEBUGFS is set but
  1292. * DEBUG is not, these will just compile out.
  1293. */
  1294. IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
  1295. priv->_agn.delta_statistics.tx.rx_detected_cnt);
  1296. IWL_DEBUG_RADIO(priv,
  1297. "ack_or_ba_timeout_collision delta = %d\n",
  1298. priv->_agn.delta_statistics.tx.
  1299. ack_or_ba_timeout_collision);
  1300. #endif
  1301. IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
  1302. ba_timeout_delta);
  1303. if (!actual_ack_cnt_delta &&
  1304. (ba_timeout_delta >= BA_TIMEOUT_MAX))
  1305. rc = false;
  1306. }
  1307. return rc;
  1308. }
  1309. /*****************************************************************************
  1310. *
  1311. * sysfs attributes
  1312. *
  1313. *****************************************************************************/
  1314. #ifdef CONFIG_IWLWIFI_DEBUG
  1315. /*
  1316. * The following adds a new attribute to the sysfs representation
  1317. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  1318. * used for controlling the debug level.
  1319. *
  1320. * See the level definitions in iwl for details.
  1321. *
  1322. * The debug_level being managed using sysfs below is a per device debug
  1323. * level that is used instead of the global debug level if it (the per
  1324. * device debug level) is set.
  1325. */
  1326. static ssize_t show_debug_level(struct device *d,
  1327. struct device_attribute *attr, char *buf)
  1328. {
  1329. struct iwl_priv *priv = dev_get_drvdata(d);
  1330. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  1331. }
  1332. static ssize_t store_debug_level(struct device *d,
  1333. struct device_attribute *attr,
  1334. const char *buf, size_t count)
  1335. {
  1336. struct iwl_priv *priv = dev_get_drvdata(d);
  1337. unsigned long val;
  1338. int ret;
  1339. ret = strict_strtoul(buf, 0, &val);
  1340. if (ret)
  1341. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  1342. else {
  1343. priv->debug_level = val;
  1344. if (iwl_alloc_traffic_mem(priv))
  1345. IWL_ERR(priv,
  1346. "Not enough memory to generate traffic log\n");
  1347. }
  1348. return strnlen(buf, count);
  1349. }
  1350. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  1351. show_debug_level, store_debug_level);
  1352. #endif /* CONFIG_IWLWIFI_DEBUG */
  1353. static ssize_t show_temperature(struct device *d,
  1354. struct device_attribute *attr, char *buf)
  1355. {
  1356. struct iwl_priv *priv = dev_get_drvdata(d);
  1357. if (!iwl_is_alive(priv))
  1358. return -EAGAIN;
  1359. return sprintf(buf, "%d\n", priv->temperature);
  1360. }
  1361. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  1362. static ssize_t show_tx_power(struct device *d,
  1363. struct device_attribute *attr, char *buf)
  1364. {
  1365. struct iwl_priv *priv = dev_get_drvdata(d);
  1366. if (!iwl_is_ready_rf(priv))
  1367. return sprintf(buf, "off\n");
  1368. else
  1369. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  1370. }
  1371. static ssize_t store_tx_power(struct device *d,
  1372. struct device_attribute *attr,
  1373. const char *buf, size_t count)
  1374. {
  1375. struct iwl_priv *priv = dev_get_drvdata(d);
  1376. unsigned long val;
  1377. int ret;
  1378. ret = strict_strtoul(buf, 10, &val);
  1379. if (ret)
  1380. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  1381. else {
  1382. ret = iwl_set_tx_power(priv, val, false);
  1383. if (ret)
  1384. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  1385. ret);
  1386. else
  1387. ret = count;
  1388. }
  1389. return ret;
  1390. }
  1391. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  1392. static struct attribute *iwl_sysfs_entries[] = {
  1393. &dev_attr_temperature.attr,
  1394. &dev_attr_tx_power.attr,
  1395. #ifdef CONFIG_IWLWIFI_DEBUG
  1396. &dev_attr_debug_level.attr,
  1397. #endif
  1398. NULL
  1399. };
  1400. static struct attribute_group iwl_attribute_group = {
  1401. .name = NULL, /* put in device directory */
  1402. .attrs = iwl_sysfs_entries,
  1403. };
  1404. /******************************************************************************
  1405. *
  1406. * uCode download functions
  1407. *
  1408. ******************************************************************************/
  1409. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1410. {
  1411. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1412. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1413. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1414. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1415. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1416. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1417. }
  1418. static void iwl_nic_start(struct iwl_priv *priv)
  1419. {
  1420. /* Remove all resets to allow NIC to operate */
  1421. iwl_write32(priv, CSR_RESET, 0);
  1422. }
  1423. struct iwlagn_ucode_capabilities {
  1424. u32 max_probe_length;
  1425. u32 standard_phy_calibration_size;
  1426. };
  1427. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
  1428. static int iwl_mac_setup_register(struct iwl_priv *priv,
  1429. struct iwlagn_ucode_capabilities *capa);
  1430. #define UCODE_EXPERIMENTAL_INDEX 100
  1431. #define UCODE_EXPERIMENTAL_TAG "exp"
  1432. static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
  1433. {
  1434. const char *name_pre = priv->cfg->fw_name_pre;
  1435. char tag[8];
  1436. if (first) {
  1437. #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
  1438. priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
  1439. strcpy(tag, UCODE_EXPERIMENTAL_TAG);
  1440. } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
  1441. #endif
  1442. priv->fw_index = priv->cfg->ucode_api_max;
  1443. sprintf(tag, "%d", priv->fw_index);
  1444. } else {
  1445. priv->fw_index--;
  1446. sprintf(tag, "%d", priv->fw_index);
  1447. }
  1448. if (priv->fw_index < priv->cfg->ucode_api_min) {
  1449. IWL_ERR(priv, "no suitable firmware found!\n");
  1450. return -ENOENT;
  1451. }
  1452. sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
  1453. IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
  1454. (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
  1455. ? "EXPERIMENTAL " : "",
  1456. priv->firmware_name);
  1457. return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
  1458. &priv->pci_dev->dev, GFP_KERNEL, priv,
  1459. iwl_ucode_callback);
  1460. }
  1461. struct iwlagn_firmware_pieces {
  1462. const void *inst, *data, *init, *init_data, *boot;
  1463. size_t inst_size, data_size, init_size, init_data_size, boot_size;
  1464. u32 build;
  1465. u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
  1466. u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
  1467. };
  1468. static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
  1469. const struct firmware *ucode_raw,
  1470. struct iwlagn_firmware_pieces *pieces)
  1471. {
  1472. struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
  1473. u32 api_ver, hdr_size;
  1474. const u8 *src;
  1475. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1476. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1477. switch (api_ver) {
  1478. default:
  1479. /*
  1480. * 4965 doesn't revision the firmware file format
  1481. * along with the API version, it always uses v1
  1482. * file format.
  1483. */
  1484. if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
  1485. CSR_HW_REV_TYPE_4965) {
  1486. hdr_size = 28;
  1487. if (ucode_raw->size < hdr_size) {
  1488. IWL_ERR(priv, "File size too small!\n");
  1489. return -EINVAL;
  1490. }
  1491. pieces->build = le32_to_cpu(ucode->u.v2.build);
  1492. pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
  1493. pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
  1494. pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
  1495. pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
  1496. pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
  1497. src = ucode->u.v2.data;
  1498. break;
  1499. }
  1500. /* fall through for 4965 */
  1501. case 0:
  1502. case 1:
  1503. case 2:
  1504. hdr_size = 24;
  1505. if (ucode_raw->size < hdr_size) {
  1506. IWL_ERR(priv, "File size too small!\n");
  1507. return -EINVAL;
  1508. }
  1509. pieces->build = 0;
  1510. pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
  1511. pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
  1512. pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
  1513. pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
  1514. pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
  1515. src = ucode->u.v1.data;
  1516. break;
  1517. }
  1518. /* Verify size of file vs. image size info in file's header */
  1519. if (ucode_raw->size != hdr_size + pieces->inst_size +
  1520. pieces->data_size + pieces->init_size +
  1521. pieces->init_data_size + pieces->boot_size) {
  1522. IWL_ERR(priv,
  1523. "uCode file size %d does not match expected size\n",
  1524. (int)ucode_raw->size);
  1525. return -EINVAL;
  1526. }
  1527. pieces->inst = src;
  1528. src += pieces->inst_size;
  1529. pieces->data = src;
  1530. src += pieces->data_size;
  1531. pieces->init = src;
  1532. src += pieces->init_size;
  1533. pieces->init_data = src;
  1534. src += pieces->init_data_size;
  1535. pieces->boot = src;
  1536. src += pieces->boot_size;
  1537. return 0;
  1538. }
  1539. static int iwlagn_wanted_ucode_alternative = 1;
  1540. static int iwlagn_load_firmware(struct iwl_priv *priv,
  1541. const struct firmware *ucode_raw,
  1542. struct iwlagn_firmware_pieces *pieces,
  1543. struct iwlagn_ucode_capabilities *capa)
  1544. {
  1545. struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
  1546. struct iwl_ucode_tlv *tlv;
  1547. size_t len = ucode_raw->size;
  1548. const u8 *data;
  1549. int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
  1550. u64 alternatives;
  1551. u32 tlv_len;
  1552. enum iwl_ucode_tlv_type tlv_type;
  1553. const u8 *tlv_data;
  1554. if (len < sizeof(*ucode)) {
  1555. IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
  1556. return -EINVAL;
  1557. }
  1558. if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
  1559. IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
  1560. le32_to_cpu(ucode->magic));
  1561. return -EINVAL;
  1562. }
  1563. /*
  1564. * Check which alternatives are present, and "downgrade"
  1565. * when the chosen alternative is not present, warning
  1566. * the user when that happens. Some files may not have
  1567. * any alternatives, so don't warn in that case.
  1568. */
  1569. alternatives = le64_to_cpu(ucode->alternatives);
  1570. tmp = wanted_alternative;
  1571. if (wanted_alternative > 63)
  1572. wanted_alternative = 63;
  1573. while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
  1574. wanted_alternative--;
  1575. if (wanted_alternative && wanted_alternative != tmp)
  1576. IWL_WARN(priv,
  1577. "uCode alternative %d not available, choosing %d\n",
  1578. tmp, wanted_alternative);
  1579. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1580. pieces->build = le32_to_cpu(ucode->build);
  1581. data = ucode->data;
  1582. len -= sizeof(*ucode);
  1583. while (len >= sizeof(*tlv)) {
  1584. u16 tlv_alt;
  1585. len -= sizeof(*tlv);
  1586. tlv = (void *)data;
  1587. tlv_len = le32_to_cpu(tlv->length);
  1588. tlv_type = le16_to_cpu(tlv->type);
  1589. tlv_alt = le16_to_cpu(tlv->alternative);
  1590. tlv_data = tlv->data;
  1591. if (len < tlv_len) {
  1592. IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
  1593. len, tlv_len);
  1594. return -EINVAL;
  1595. }
  1596. len -= ALIGN(tlv_len, 4);
  1597. data += sizeof(*tlv) + ALIGN(tlv_len, 4);
  1598. /*
  1599. * Alternative 0 is always valid.
  1600. *
  1601. * Skip alternative TLVs that are not selected.
  1602. */
  1603. if (tlv_alt != 0 && tlv_alt != wanted_alternative)
  1604. continue;
  1605. switch (tlv_type) {
  1606. case IWL_UCODE_TLV_INST:
  1607. pieces->inst = tlv_data;
  1608. pieces->inst_size = tlv_len;
  1609. break;
  1610. case IWL_UCODE_TLV_DATA:
  1611. pieces->data = tlv_data;
  1612. pieces->data_size = tlv_len;
  1613. break;
  1614. case IWL_UCODE_TLV_INIT:
  1615. pieces->init = tlv_data;
  1616. pieces->init_size = tlv_len;
  1617. break;
  1618. case IWL_UCODE_TLV_INIT_DATA:
  1619. pieces->init_data = tlv_data;
  1620. pieces->init_data_size = tlv_len;
  1621. break;
  1622. case IWL_UCODE_TLV_BOOT:
  1623. pieces->boot = tlv_data;
  1624. pieces->boot_size = tlv_len;
  1625. break;
  1626. case IWL_UCODE_TLV_PROBE_MAX_LEN:
  1627. if (tlv_len != sizeof(u32))
  1628. goto invalid_tlv_len;
  1629. capa->max_probe_length =
  1630. le32_to_cpup((__le32 *)tlv_data);
  1631. break;
  1632. case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
  1633. if (tlv_len != sizeof(u32))
  1634. goto invalid_tlv_len;
  1635. pieces->init_evtlog_ptr =
  1636. le32_to_cpup((__le32 *)tlv_data);
  1637. break;
  1638. case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
  1639. if (tlv_len != sizeof(u32))
  1640. goto invalid_tlv_len;
  1641. pieces->init_evtlog_size =
  1642. le32_to_cpup((__le32 *)tlv_data);
  1643. break;
  1644. case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
  1645. if (tlv_len != sizeof(u32))
  1646. goto invalid_tlv_len;
  1647. pieces->init_errlog_ptr =
  1648. le32_to_cpup((__le32 *)tlv_data);
  1649. break;
  1650. case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
  1651. if (tlv_len != sizeof(u32))
  1652. goto invalid_tlv_len;
  1653. pieces->inst_evtlog_ptr =
  1654. le32_to_cpup((__le32 *)tlv_data);
  1655. break;
  1656. case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
  1657. if (tlv_len != sizeof(u32))
  1658. goto invalid_tlv_len;
  1659. pieces->inst_evtlog_size =
  1660. le32_to_cpup((__le32 *)tlv_data);
  1661. break;
  1662. case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
  1663. if (tlv_len != sizeof(u32))
  1664. goto invalid_tlv_len;
  1665. pieces->inst_errlog_ptr =
  1666. le32_to_cpup((__le32 *)tlv_data);
  1667. break;
  1668. case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
  1669. if (tlv_len)
  1670. goto invalid_tlv_len;
  1671. priv->enhance_sensitivity_table = true;
  1672. break;
  1673. case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
  1674. if (tlv_len != sizeof(u32))
  1675. goto invalid_tlv_len;
  1676. capa->standard_phy_calibration_size =
  1677. le32_to_cpup((__le32 *)tlv_data);
  1678. break;
  1679. default:
  1680. IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
  1681. break;
  1682. }
  1683. }
  1684. if (len) {
  1685. IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
  1686. iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
  1687. return -EINVAL;
  1688. }
  1689. return 0;
  1690. invalid_tlv_len:
  1691. IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
  1692. iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
  1693. return -EINVAL;
  1694. }
  1695. /**
  1696. * iwl_ucode_callback - callback when firmware was loaded
  1697. *
  1698. * If loaded successfully, copies the firmware into buffers
  1699. * for the card to fetch (via DMA).
  1700. */
  1701. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
  1702. {
  1703. struct iwl_priv *priv = context;
  1704. struct iwl_ucode_header *ucode;
  1705. int err;
  1706. struct iwlagn_firmware_pieces pieces;
  1707. const unsigned int api_max = priv->cfg->ucode_api_max;
  1708. const unsigned int api_min = priv->cfg->ucode_api_min;
  1709. u32 api_ver;
  1710. char buildstr[25];
  1711. u32 build;
  1712. struct iwlagn_ucode_capabilities ucode_capa = {
  1713. .max_probe_length = 200,
  1714. .standard_phy_calibration_size =
  1715. IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE,
  1716. };
  1717. memset(&pieces, 0, sizeof(pieces));
  1718. if (!ucode_raw) {
  1719. if (priv->fw_index <= priv->cfg->ucode_api_max)
  1720. IWL_ERR(priv,
  1721. "request for firmware file '%s' failed.\n",
  1722. priv->firmware_name);
  1723. goto try_again;
  1724. }
  1725. IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
  1726. priv->firmware_name, ucode_raw->size);
  1727. /* Make sure that we got at least the API version number */
  1728. if (ucode_raw->size < 4) {
  1729. IWL_ERR(priv, "File size way too small!\n");
  1730. goto try_again;
  1731. }
  1732. /* Data from ucode file: header followed by uCode images */
  1733. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1734. if (ucode->ver)
  1735. err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
  1736. else
  1737. err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
  1738. &ucode_capa);
  1739. if (err)
  1740. goto try_again;
  1741. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1742. build = pieces.build;
  1743. /*
  1744. * api_ver should match the api version forming part of the
  1745. * firmware filename ... but we don't check for that and only rely
  1746. * on the API version read from firmware header from here on forward
  1747. */
  1748. if (api_ver < api_min || api_ver > api_max) {
  1749. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1750. "Driver supports v%u, firmware is v%u.\n",
  1751. api_max, api_ver);
  1752. goto try_again;
  1753. }
  1754. if (api_ver != api_max)
  1755. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1756. "got v%u. New firmware can be obtained "
  1757. "from http://www.intellinuxwireless.org.\n",
  1758. api_max, api_ver);
  1759. if (build)
  1760. sprintf(buildstr, " build %u%s", build,
  1761. (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
  1762. ? " (EXP)" : "");
  1763. else
  1764. buildstr[0] = '\0';
  1765. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
  1766. IWL_UCODE_MAJOR(priv->ucode_ver),
  1767. IWL_UCODE_MINOR(priv->ucode_ver),
  1768. IWL_UCODE_API(priv->ucode_ver),
  1769. IWL_UCODE_SERIAL(priv->ucode_ver),
  1770. buildstr);
  1771. snprintf(priv->hw->wiphy->fw_version,
  1772. sizeof(priv->hw->wiphy->fw_version),
  1773. "%u.%u.%u.%u%s",
  1774. IWL_UCODE_MAJOR(priv->ucode_ver),
  1775. IWL_UCODE_MINOR(priv->ucode_ver),
  1776. IWL_UCODE_API(priv->ucode_ver),
  1777. IWL_UCODE_SERIAL(priv->ucode_ver),
  1778. buildstr);
  1779. /*
  1780. * For any of the failures below (before allocating pci memory)
  1781. * we will try to load a version with a smaller API -- maybe the
  1782. * user just got a corrupted version of the latest API.
  1783. */
  1784. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1785. priv->ucode_ver);
  1786. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
  1787. pieces.inst_size);
  1788. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
  1789. pieces.data_size);
  1790. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
  1791. pieces.init_size);
  1792. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
  1793. pieces.init_data_size);
  1794. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
  1795. pieces.boot_size);
  1796. /* Verify that uCode images will fit in card's SRAM */
  1797. if (pieces.inst_size > priv->hw_params.max_inst_size) {
  1798. IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
  1799. pieces.inst_size);
  1800. goto try_again;
  1801. }
  1802. if (pieces.data_size > priv->hw_params.max_data_size) {
  1803. IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
  1804. pieces.data_size);
  1805. goto try_again;
  1806. }
  1807. if (pieces.init_size > priv->hw_params.max_inst_size) {
  1808. IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
  1809. pieces.init_size);
  1810. goto try_again;
  1811. }
  1812. if (pieces.init_data_size > priv->hw_params.max_data_size) {
  1813. IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
  1814. pieces.init_data_size);
  1815. goto try_again;
  1816. }
  1817. if (pieces.boot_size > priv->hw_params.max_bsm_size) {
  1818. IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
  1819. pieces.boot_size);
  1820. goto try_again;
  1821. }
  1822. /* Allocate ucode buffers for card's bus-master loading ... */
  1823. /* Runtime instructions and 2 copies of data:
  1824. * 1) unmodified from disk
  1825. * 2) backup cache for save/restore during power-downs */
  1826. priv->ucode_code.len = pieces.inst_size;
  1827. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1828. priv->ucode_data.len = pieces.data_size;
  1829. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1830. priv->ucode_data_backup.len = pieces.data_size;
  1831. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1832. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1833. !priv->ucode_data_backup.v_addr)
  1834. goto err_pci_alloc;
  1835. /* Initialization instructions and data */
  1836. if (pieces.init_size && pieces.init_data_size) {
  1837. priv->ucode_init.len = pieces.init_size;
  1838. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1839. priv->ucode_init_data.len = pieces.init_data_size;
  1840. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1841. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1842. goto err_pci_alloc;
  1843. }
  1844. /* Bootstrap (instructions only, no data) */
  1845. if (pieces.boot_size) {
  1846. priv->ucode_boot.len = pieces.boot_size;
  1847. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1848. if (!priv->ucode_boot.v_addr)
  1849. goto err_pci_alloc;
  1850. }
  1851. /* Now that we can no longer fail, copy information */
  1852. /*
  1853. * The (size - 16) / 12 formula is based on the information recorded
  1854. * for each event, which is of mode 1 (including timestamp) for all
  1855. * new microcodes that include this information.
  1856. */
  1857. priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
  1858. if (pieces.init_evtlog_size)
  1859. priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
  1860. else
  1861. priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size;
  1862. priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
  1863. priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
  1864. if (pieces.inst_evtlog_size)
  1865. priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
  1866. else
  1867. priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size;
  1868. priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
  1869. /* Copy images into buffers for card's bus-master reads ... */
  1870. /* Runtime instructions (first block of data in file) */
  1871. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
  1872. pieces.inst_size);
  1873. memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
  1874. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1875. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1876. /*
  1877. * Runtime data
  1878. * NOTE: Copy into backup buffer will be done in iwl_up()
  1879. */
  1880. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
  1881. pieces.data_size);
  1882. memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
  1883. memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
  1884. /* Initialization instructions */
  1885. if (pieces.init_size) {
  1886. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1887. pieces.init_size);
  1888. memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
  1889. }
  1890. /* Initialization data */
  1891. if (pieces.init_data_size) {
  1892. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1893. pieces.init_data_size);
  1894. memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
  1895. pieces.init_data_size);
  1896. }
  1897. /* Bootstrap instructions */
  1898. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
  1899. pieces.boot_size);
  1900. memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
  1901. /*
  1902. * figure out the offset of chain noise reset and gain commands
  1903. * base on the size of standard phy calibration commands table size
  1904. */
  1905. if (ucode_capa.standard_phy_calibration_size >
  1906. IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
  1907. ucode_capa.standard_phy_calibration_size =
  1908. IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
  1909. priv->_agn.phy_calib_chain_noise_reset_cmd =
  1910. ucode_capa.standard_phy_calibration_size;
  1911. priv->_agn.phy_calib_chain_noise_gain_cmd =
  1912. ucode_capa.standard_phy_calibration_size + 1;
  1913. /**************************************************
  1914. * This is still part of probe() in a sense...
  1915. *
  1916. * 9. Setup and register with mac80211 and debugfs
  1917. **************************************************/
  1918. err = iwl_mac_setup_register(priv, &ucode_capa);
  1919. if (err)
  1920. goto out_unbind;
  1921. err = iwl_dbgfs_register(priv, DRV_NAME);
  1922. if (err)
  1923. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  1924. err = sysfs_create_group(&priv->pci_dev->dev.kobj,
  1925. &iwl_attribute_group);
  1926. if (err) {
  1927. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  1928. goto out_unbind;
  1929. }
  1930. /* We have our copies now, allow OS release its copies */
  1931. release_firmware(ucode_raw);
  1932. complete(&priv->_agn.firmware_loading_complete);
  1933. return;
  1934. try_again:
  1935. /* try next, if any */
  1936. if (iwl_request_firmware(priv, false))
  1937. goto out_unbind;
  1938. release_firmware(ucode_raw);
  1939. return;
  1940. err_pci_alloc:
  1941. IWL_ERR(priv, "failed to allocate pci memory\n");
  1942. iwl_dealloc_ucode_pci(priv);
  1943. out_unbind:
  1944. complete(&priv->_agn.firmware_loading_complete);
  1945. device_release_driver(&priv->pci_dev->dev);
  1946. release_firmware(ucode_raw);
  1947. }
  1948. static const char *desc_lookup_text[] = {
  1949. "OK",
  1950. "FAIL",
  1951. "BAD_PARAM",
  1952. "BAD_CHECKSUM",
  1953. "NMI_INTERRUPT_WDG",
  1954. "SYSASSERT",
  1955. "FATAL_ERROR",
  1956. "BAD_COMMAND",
  1957. "HW_ERROR_TUNE_LOCK",
  1958. "HW_ERROR_TEMPERATURE",
  1959. "ILLEGAL_CHAN_FREQ",
  1960. "VCC_NOT_STABLE",
  1961. "FH_ERROR",
  1962. "NMI_INTERRUPT_HOST",
  1963. "NMI_INTERRUPT_ACTION_PT",
  1964. "NMI_INTERRUPT_UNKNOWN",
  1965. "UCODE_VERSION_MISMATCH",
  1966. "HW_ERROR_ABS_LOCK",
  1967. "HW_ERROR_CAL_LOCK_FAIL",
  1968. "NMI_INTERRUPT_INST_ACTION_PT",
  1969. "NMI_INTERRUPT_DATA_ACTION_PT",
  1970. "NMI_TRM_HW_ER",
  1971. "NMI_INTERRUPT_TRM",
  1972. "NMI_INTERRUPT_BREAK_POINT"
  1973. "DEBUG_0",
  1974. "DEBUG_1",
  1975. "DEBUG_2",
  1976. "DEBUG_3",
  1977. };
  1978. static struct { char *name; u8 num; } advanced_lookup[] = {
  1979. { "NMI_INTERRUPT_WDG", 0x34 },
  1980. { "SYSASSERT", 0x35 },
  1981. { "UCODE_VERSION_MISMATCH", 0x37 },
  1982. { "BAD_COMMAND", 0x38 },
  1983. { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
  1984. { "FATAL_ERROR", 0x3D },
  1985. { "NMI_TRM_HW_ERR", 0x46 },
  1986. { "NMI_INTERRUPT_TRM", 0x4C },
  1987. { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
  1988. { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
  1989. { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
  1990. { "NMI_INTERRUPT_HOST", 0x66 },
  1991. { "NMI_INTERRUPT_ACTION_PT", 0x7C },
  1992. { "NMI_INTERRUPT_UNKNOWN", 0x84 },
  1993. { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
  1994. { "ADVANCED_SYSASSERT", 0 },
  1995. };
  1996. static const char *desc_lookup(u32 num)
  1997. {
  1998. int i;
  1999. int max = ARRAY_SIZE(desc_lookup_text);
  2000. if (num < max)
  2001. return desc_lookup_text[num];
  2002. max = ARRAY_SIZE(advanced_lookup) - 1;
  2003. for (i = 0; i < max; i++) {
  2004. if (advanced_lookup[i].num == num)
  2005. break;;
  2006. }
  2007. return advanced_lookup[i].name;
  2008. }
  2009. #define ERROR_START_OFFSET (1 * sizeof(u32))
  2010. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  2011. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  2012. {
  2013. u32 data2, line;
  2014. u32 desc, time, count, base, data1;
  2015. u32 blink1, blink2, ilink1, ilink2;
  2016. u32 pc, hcmd;
  2017. if (priv->ucode_type == UCODE_INIT) {
  2018. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  2019. if (!base)
  2020. base = priv->_agn.init_errlog_ptr;
  2021. } else {
  2022. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  2023. if (!base)
  2024. base = priv->_agn.inst_errlog_ptr;
  2025. }
  2026. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  2027. IWL_ERR(priv,
  2028. "Not valid error log pointer 0x%08X for %s uCode\n",
  2029. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  2030. return;
  2031. }
  2032. count = iwl_read_targ_mem(priv, base);
  2033. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  2034. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  2035. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  2036. priv->status, count);
  2037. }
  2038. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  2039. pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
  2040. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  2041. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  2042. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  2043. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  2044. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  2045. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  2046. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  2047. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  2048. hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
  2049. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  2050. blink1, blink2, ilink1, ilink2);
  2051. IWL_ERR(priv, "Desc Time "
  2052. "data1 data2 line\n");
  2053. IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
  2054. desc_lookup(desc), desc, time, data1, data2, line);
  2055. IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
  2056. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
  2057. pc, blink1, blink2, ilink1, ilink2, hcmd);
  2058. }
  2059. #define EVENT_START_OFFSET (4 * sizeof(u32))
  2060. /**
  2061. * iwl_print_event_log - Dump error event log to syslog
  2062. *
  2063. */
  2064. static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  2065. u32 num_events, u32 mode,
  2066. int pos, char **buf, size_t bufsz)
  2067. {
  2068. u32 i;
  2069. u32 base; /* SRAM byte address of event log header */
  2070. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  2071. u32 ptr; /* SRAM byte address of log data */
  2072. u32 ev, time, data; /* event log data */
  2073. unsigned long reg_flags;
  2074. if (num_events == 0)
  2075. return pos;
  2076. if (priv->ucode_type == UCODE_INIT) {
  2077. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  2078. if (!base)
  2079. base = priv->_agn.init_evtlog_ptr;
  2080. } else {
  2081. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  2082. if (!base)
  2083. base = priv->_agn.inst_evtlog_ptr;
  2084. }
  2085. if (mode == 0)
  2086. event_size = 2 * sizeof(u32);
  2087. else
  2088. event_size = 3 * sizeof(u32);
  2089. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  2090. /* Make sure device is powered up for SRAM reads */
  2091. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  2092. iwl_grab_nic_access(priv);
  2093. /* Set starting address; reads will auto-increment */
  2094. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  2095. rmb();
  2096. /* "time" is actually "data" for mode 0 (no timestamp).
  2097. * place event id # at far right for easier visual parsing. */
  2098. for (i = 0; i < num_events; i++) {
  2099. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  2100. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  2101. if (mode == 0) {
  2102. /* data, ev */
  2103. if (bufsz) {
  2104. pos += scnprintf(*buf + pos, bufsz - pos,
  2105. "EVT_LOG:0x%08x:%04u\n",
  2106. time, ev);
  2107. } else {
  2108. trace_iwlwifi_dev_ucode_event(priv, 0,
  2109. time, ev);
  2110. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
  2111. time, ev);
  2112. }
  2113. } else {
  2114. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  2115. if (bufsz) {
  2116. pos += scnprintf(*buf + pos, bufsz - pos,
  2117. "EVT_LOGT:%010u:0x%08x:%04u\n",
  2118. time, data, ev);
  2119. } else {
  2120. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  2121. time, data, ev);
  2122. trace_iwlwifi_dev_ucode_event(priv, time,
  2123. data, ev);
  2124. }
  2125. }
  2126. }
  2127. /* Allow device to power down */
  2128. iwl_release_nic_access(priv);
  2129. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  2130. return pos;
  2131. }
  2132. /**
  2133. * iwl_print_last_event_logs - Dump the newest # of event log to syslog
  2134. */
  2135. static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  2136. u32 num_wraps, u32 next_entry,
  2137. u32 size, u32 mode,
  2138. int pos, char **buf, size_t bufsz)
  2139. {
  2140. /*
  2141. * display the newest DEFAULT_LOG_ENTRIES entries
  2142. * i.e the entries just before the next ont that uCode would fill.
  2143. */
  2144. if (num_wraps) {
  2145. if (next_entry < size) {
  2146. pos = iwl_print_event_log(priv,
  2147. capacity - (size - next_entry),
  2148. size - next_entry, mode,
  2149. pos, buf, bufsz);
  2150. pos = iwl_print_event_log(priv, 0,
  2151. next_entry, mode,
  2152. pos, buf, bufsz);
  2153. } else
  2154. pos = iwl_print_event_log(priv, next_entry - size,
  2155. size, mode, pos, buf, bufsz);
  2156. } else {
  2157. if (next_entry < size) {
  2158. pos = iwl_print_event_log(priv, 0, next_entry,
  2159. mode, pos, buf, bufsz);
  2160. } else {
  2161. pos = iwl_print_event_log(priv, next_entry - size,
  2162. size, mode, pos, buf, bufsz);
  2163. }
  2164. }
  2165. return pos;
  2166. }
  2167. #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
  2168. int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  2169. char **buf, bool display)
  2170. {
  2171. u32 base; /* SRAM byte address of event log header */
  2172. u32 capacity; /* event log capacity in # entries */
  2173. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  2174. u32 num_wraps; /* # times uCode wrapped to top of log */
  2175. u32 next_entry; /* index of next entry to be written by uCode */
  2176. u32 size; /* # entries that we'll print */
  2177. u32 logsize;
  2178. int pos = 0;
  2179. size_t bufsz = 0;
  2180. if (priv->ucode_type == UCODE_INIT) {
  2181. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  2182. logsize = priv->_agn.init_evtlog_size;
  2183. if (!base)
  2184. base = priv->_agn.init_evtlog_ptr;
  2185. } else {
  2186. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  2187. logsize = priv->_agn.inst_evtlog_size;
  2188. if (!base)
  2189. base = priv->_agn.inst_evtlog_ptr;
  2190. }
  2191. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  2192. IWL_ERR(priv,
  2193. "Invalid event log pointer 0x%08X for %s uCode\n",
  2194. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  2195. return -EINVAL;
  2196. }
  2197. /* event log header */
  2198. capacity = iwl_read_targ_mem(priv, base);
  2199. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  2200. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  2201. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  2202. if (capacity > logsize) {
  2203. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  2204. capacity, logsize);
  2205. capacity = logsize;
  2206. }
  2207. if (next_entry > logsize) {
  2208. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  2209. next_entry, logsize);
  2210. next_entry = logsize;
  2211. }
  2212. size = num_wraps ? capacity : next_entry;
  2213. /* bail out if nothing in log */
  2214. if (size == 0) {
  2215. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  2216. return pos;
  2217. }
  2218. #ifdef CONFIG_IWLWIFI_DEBUG
  2219. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  2220. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  2221. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  2222. #else
  2223. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  2224. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  2225. #endif
  2226. IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
  2227. size);
  2228. #ifdef CONFIG_IWLWIFI_DEBUG
  2229. if (display) {
  2230. if (full_log)
  2231. bufsz = capacity * 48;
  2232. else
  2233. bufsz = size * 48;
  2234. *buf = kmalloc(bufsz, GFP_KERNEL);
  2235. if (!*buf)
  2236. return -ENOMEM;
  2237. }
  2238. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  2239. /*
  2240. * if uCode has wrapped back to top of log,
  2241. * start at the oldest entry,
  2242. * i.e the next one that uCode would fill.
  2243. */
  2244. if (num_wraps)
  2245. pos = iwl_print_event_log(priv, next_entry,
  2246. capacity - next_entry, mode,
  2247. pos, buf, bufsz);
  2248. /* (then/else) start at top of log */
  2249. pos = iwl_print_event_log(priv, 0,
  2250. next_entry, mode, pos, buf, bufsz);
  2251. } else
  2252. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  2253. next_entry, size, mode,
  2254. pos, buf, bufsz);
  2255. #else
  2256. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  2257. next_entry, size, mode,
  2258. pos, buf, bufsz);
  2259. #endif
  2260. return pos;
  2261. }
  2262. static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
  2263. {
  2264. struct iwl_ct_kill_config cmd;
  2265. struct iwl_ct_kill_throttling_config adv_cmd;
  2266. unsigned long flags;
  2267. int ret = 0;
  2268. spin_lock_irqsave(&priv->lock, flags);
  2269. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  2270. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  2271. spin_unlock_irqrestore(&priv->lock, flags);
  2272. priv->thermal_throttle.ct_kill_toggle = false;
  2273. if (priv->cfg->support_ct_kill_exit) {
  2274. adv_cmd.critical_temperature_enter =
  2275. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  2276. adv_cmd.critical_temperature_exit =
  2277. cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
  2278. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  2279. sizeof(adv_cmd), &adv_cmd);
  2280. if (ret)
  2281. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  2282. else
  2283. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  2284. "succeeded, "
  2285. "critical temperature enter is %d,"
  2286. "exit is %d\n",
  2287. priv->hw_params.ct_kill_threshold,
  2288. priv->hw_params.ct_kill_exit_threshold);
  2289. } else {
  2290. cmd.critical_temperature_R =
  2291. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  2292. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  2293. sizeof(cmd), &cmd);
  2294. if (ret)
  2295. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  2296. else
  2297. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  2298. "succeeded, "
  2299. "critical temperature is %d\n",
  2300. priv->hw_params.ct_kill_threshold);
  2301. }
  2302. }
  2303. /**
  2304. * iwl_alive_start - called after REPLY_ALIVE notification received
  2305. * from protocol/runtime uCode (initialization uCode's
  2306. * Alive gets handled by iwl_init_alive_start()).
  2307. */
  2308. static void iwl_alive_start(struct iwl_priv *priv)
  2309. {
  2310. int ret = 0;
  2311. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  2312. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  2313. /* We had an error bringing up the hardware, so take it
  2314. * all the way back down so we can try again */
  2315. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  2316. goto restart;
  2317. }
  2318. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  2319. * This is a paranoid check, because we would not have gotten the
  2320. * "runtime" alive if code weren't properly loaded. */
  2321. if (iwl_verify_ucode(priv)) {
  2322. /* Runtime instruction load was bad;
  2323. * take it all the way back down so we can try again */
  2324. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  2325. goto restart;
  2326. }
  2327. ret = priv->cfg->ops->lib->alive_notify(priv);
  2328. if (ret) {
  2329. IWL_WARN(priv,
  2330. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  2331. goto restart;
  2332. }
  2333. /* After the ALIVE response, we can send host commands to the uCode */
  2334. set_bit(STATUS_ALIVE, &priv->status);
  2335. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  2336. /* Enable timer to monitor the driver queues */
  2337. mod_timer(&priv->monitor_recover,
  2338. jiffies +
  2339. msecs_to_jiffies(priv->cfg->monitor_recover_period));
  2340. }
  2341. if (iwl_is_rfkill(priv))
  2342. return;
  2343. ieee80211_wake_queues(priv->hw);
  2344. priv->active_rate = IWL_RATES_MASK;
  2345. /* Configure Tx antenna selection based on H/W config */
  2346. if (priv->cfg->ops->hcmd->set_tx_ant)
  2347. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  2348. if (iwl_is_associated(priv)) {
  2349. struct iwl_rxon_cmd *active_rxon =
  2350. (struct iwl_rxon_cmd *)&priv->active_rxon;
  2351. /* apply any changes in staging */
  2352. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2353. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2354. } else {
  2355. /* Initialize our rx_config data */
  2356. iwl_connection_init_rx_config(priv, NULL);
  2357. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2358. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2359. }
  2360. /* Configure Bluetooth device coexistence support */
  2361. priv->cfg->ops->hcmd->send_bt_config(priv);
  2362. iwl_reset_run_time_calib(priv);
  2363. /* Configure the adapter for unassociated operation */
  2364. iwlcore_commit_rxon(priv);
  2365. /* At this point, the NIC is initialized and operational */
  2366. iwl_rf_kill_ct_config(priv);
  2367. iwl_leds_init(priv);
  2368. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  2369. set_bit(STATUS_READY, &priv->status);
  2370. wake_up_interruptible(&priv->wait_command_queue);
  2371. iwl_power_update_mode(priv, true);
  2372. IWL_DEBUG_INFO(priv, "Updated power mode\n");
  2373. return;
  2374. restart:
  2375. queue_work(priv->workqueue, &priv->restart);
  2376. }
  2377. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  2378. static void __iwl_down(struct iwl_priv *priv)
  2379. {
  2380. unsigned long flags;
  2381. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  2382. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  2383. if (!exit_pending)
  2384. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2385. /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
  2386. * to prevent rearm timer */
  2387. if (priv->cfg->ops->lib->recover_from_tx_stall)
  2388. del_timer_sync(&priv->monitor_recover);
  2389. iwl_clear_ucode_stations(priv);
  2390. iwl_dealloc_bcast_station(priv);
  2391. iwl_clear_driver_stations(priv);
  2392. /* reset BT coex data */
  2393. priv->bt_traffic_load = 0;
  2394. priv->bt_sco_active = false;
  2395. priv->bt_full_concurrent = false;
  2396. priv->bt_ci_compliance = 0;
  2397. /* Unblock any waiting calls */
  2398. wake_up_interruptible_all(&priv->wait_command_queue);
  2399. /* Wipe out the EXIT_PENDING status bit if we are not actually
  2400. * exiting the module */
  2401. if (!exit_pending)
  2402. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2403. /* stop and reset the on-board processor */
  2404. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2405. /* tell the device to stop sending interrupts */
  2406. spin_lock_irqsave(&priv->lock, flags);
  2407. iwl_disable_interrupts(priv);
  2408. spin_unlock_irqrestore(&priv->lock, flags);
  2409. iwl_synchronize_irq(priv);
  2410. if (priv->mac80211_registered)
  2411. ieee80211_stop_queues(priv->hw);
  2412. /* If we have not previously called iwl_init() then
  2413. * clear all bits but the RF Kill bit and return */
  2414. if (!iwl_is_init(priv)) {
  2415. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2416. STATUS_RF_KILL_HW |
  2417. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2418. STATUS_GEO_CONFIGURED |
  2419. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2420. STATUS_EXIT_PENDING;
  2421. goto exit;
  2422. }
  2423. /* ...otherwise clear out all the status bits but the RF Kill
  2424. * bit and continue taking the NIC down. */
  2425. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2426. STATUS_RF_KILL_HW |
  2427. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2428. STATUS_GEO_CONFIGURED |
  2429. test_bit(STATUS_FW_ERROR, &priv->status) <<
  2430. STATUS_FW_ERROR |
  2431. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2432. STATUS_EXIT_PENDING;
  2433. /* device going down, Stop using ICT table */
  2434. iwl_disable_ict(priv);
  2435. iwlagn_txq_ctx_stop(priv);
  2436. iwlagn_rxq_stop(priv);
  2437. /* Power-down device's busmaster DMA clocks */
  2438. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  2439. udelay(5);
  2440. /* Make sure (redundant) we've released our request to stay awake */
  2441. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2442. /* Stop the device, and put it in low power state */
  2443. priv->cfg->ops->lib->apm_ops.stop(priv);
  2444. exit:
  2445. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  2446. if (priv->ibss_beacon)
  2447. dev_kfree_skb(priv->ibss_beacon);
  2448. priv->ibss_beacon = NULL;
  2449. /* clear out any free frames */
  2450. iwl_clear_free_frames(priv);
  2451. }
  2452. static void iwl_down(struct iwl_priv *priv)
  2453. {
  2454. mutex_lock(&priv->mutex);
  2455. __iwl_down(priv);
  2456. mutex_unlock(&priv->mutex);
  2457. iwl_cancel_deferred_work(priv);
  2458. }
  2459. #define HW_READY_TIMEOUT (50)
  2460. static int iwl_set_hw_ready(struct iwl_priv *priv)
  2461. {
  2462. int ret = 0;
  2463. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  2464. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  2465. /* See if we got it */
  2466. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  2467. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  2468. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  2469. HW_READY_TIMEOUT);
  2470. if (ret != -ETIMEDOUT)
  2471. priv->hw_ready = true;
  2472. else
  2473. priv->hw_ready = false;
  2474. IWL_DEBUG_INFO(priv, "hardware %s\n",
  2475. (priv->hw_ready == 1) ? "ready" : "not ready");
  2476. return ret;
  2477. }
  2478. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  2479. {
  2480. int ret = 0;
  2481. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
  2482. ret = iwl_set_hw_ready(priv);
  2483. if (priv->hw_ready)
  2484. return ret;
  2485. /* If HW is not ready, prepare the conditions to check again */
  2486. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  2487. CSR_HW_IF_CONFIG_REG_PREPARE);
  2488. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  2489. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  2490. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  2491. /* HW should be ready by now, check again. */
  2492. if (ret != -ETIMEDOUT)
  2493. iwl_set_hw_ready(priv);
  2494. return ret;
  2495. }
  2496. #define MAX_HW_RESTARTS 5
  2497. static int __iwl_up(struct iwl_priv *priv)
  2498. {
  2499. int i;
  2500. int ret;
  2501. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  2502. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  2503. return -EIO;
  2504. }
  2505. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  2506. IWL_ERR(priv, "ucode not available for device bringup\n");
  2507. return -EIO;
  2508. }
  2509. ret = iwl_alloc_bcast_station(priv, true);
  2510. if (ret)
  2511. return ret;
  2512. iwl_prepare_card_hw(priv);
  2513. if (!priv->hw_ready) {
  2514. IWL_WARN(priv, "Exit HW not ready\n");
  2515. return -EIO;
  2516. }
  2517. /* If platform's RF_KILL switch is NOT set to KILL */
  2518. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2519. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2520. else
  2521. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2522. if (iwl_is_rfkill(priv)) {
  2523. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  2524. iwl_enable_interrupts(priv);
  2525. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  2526. return 0;
  2527. }
  2528. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2529. ret = iwlagn_hw_nic_init(priv);
  2530. if (ret) {
  2531. IWL_ERR(priv, "Unable to init nic\n");
  2532. return ret;
  2533. }
  2534. /* make sure rfkill handshake bits are cleared */
  2535. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2536. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  2537. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2538. /* clear (again), then enable host interrupts */
  2539. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2540. iwl_enable_interrupts(priv);
  2541. /* really make sure rfkill handshake bits are cleared */
  2542. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2543. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2544. /* Copy original ucode data image from disk into backup cache.
  2545. * This will be used to initialize the on-board processor's
  2546. * data SRAM for a clean start when the runtime program first loads. */
  2547. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  2548. priv->ucode_data.len);
  2549. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  2550. /* load bootstrap state machine,
  2551. * load bootstrap program into processor's memory,
  2552. * prepare to load the "initialize" uCode */
  2553. ret = priv->cfg->ops->lib->load_ucode(priv);
  2554. if (ret) {
  2555. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  2556. ret);
  2557. continue;
  2558. }
  2559. /* start card; "initialize" will load runtime ucode */
  2560. iwl_nic_start(priv);
  2561. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  2562. return 0;
  2563. }
  2564. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2565. __iwl_down(priv);
  2566. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2567. /* tried to restart and config the device for as long as our
  2568. * patience could withstand */
  2569. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  2570. return -EIO;
  2571. }
  2572. /*****************************************************************************
  2573. *
  2574. * Workqueue callbacks
  2575. *
  2576. *****************************************************************************/
  2577. static void iwl_bg_init_alive_start(struct work_struct *data)
  2578. {
  2579. struct iwl_priv *priv =
  2580. container_of(data, struct iwl_priv, init_alive_start.work);
  2581. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2582. return;
  2583. mutex_lock(&priv->mutex);
  2584. priv->cfg->ops->lib->init_alive_start(priv);
  2585. mutex_unlock(&priv->mutex);
  2586. }
  2587. static void iwl_bg_alive_start(struct work_struct *data)
  2588. {
  2589. struct iwl_priv *priv =
  2590. container_of(data, struct iwl_priv, alive_start.work);
  2591. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2592. return;
  2593. /* enable dram interrupt */
  2594. iwl_reset_ict(priv);
  2595. mutex_lock(&priv->mutex);
  2596. iwl_alive_start(priv);
  2597. mutex_unlock(&priv->mutex);
  2598. }
  2599. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  2600. {
  2601. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  2602. run_time_calib_work);
  2603. mutex_lock(&priv->mutex);
  2604. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  2605. test_bit(STATUS_SCANNING, &priv->status)) {
  2606. mutex_unlock(&priv->mutex);
  2607. return;
  2608. }
  2609. if (priv->start_calib) {
  2610. if (priv->cfg->bt_statistics) {
  2611. iwl_chain_noise_calibration(priv,
  2612. (void *)&priv->_agn.statistics_bt);
  2613. iwl_sensitivity_calibration(priv,
  2614. (void *)&priv->_agn.statistics_bt);
  2615. } else {
  2616. iwl_chain_noise_calibration(priv,
  2617. (void *)&priv->_agn.statistics);
  2618. iwl_sensitivity_calibration(priv,
  2619. (void *)&priv->_agn.statistics);
  2620. }
  2621. }
  2622. mutex_unlock(&priv->mutex);
  2623. }
  2624. static void iwl_bg_restart(struct work_struct *data)
  2625. {
  2626. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  2627. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2628. return;
  2629. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  2630. bool bt_sco, bt_full_concurrent;
  2631. u8 bt_ci_compliance;
  2632. u8 bt_load;
  2633. mutex_lock(&priv->mutex);
  2634. priv->vif = NULL;
  2635. priv->is_open = 0;
  2636. /*
  2637. * __iwl_down() will clear the BT status variables,
  2638. * which is correct, but when we restart we really
  2639. * want to keep them so restore them afterwards.
  2640. *
  2641. * The restart process will later pick them up and
  2642. * re-configure the hw when we reconfigure the BT
  2643. * command.
  2644. */
  2645. bt_sco = priv->bt_sco_active;
  2646. bt_full_concurrent = priv->bt_full_concurrent;
  2647. bt_ci_compliance = priv->bt_ci_compliance;
  2648. bt_load = priv->bt_traffic_load;
  2649. __iwl_down(priv);
  2650. priv->bt_sco_active = bt_sco;
  2651. priv->bt_full_concurrent = bt_full_concurrent;
  2652. priv->bt_ci_compliance = bt_ci_compliance;
  2653. priv->bt_traffic_load = bt_load;
  2654. mutex_unlock(&priv->mutex);
  2655. iwl_cancel_deferred_work(priv);
  2656. ieee80211_restart_hw(priv->hw);
  2657. } else {
  2658. iwl_down(priv);
  2659. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2660. return;
  2661. mutex_lock(&priv->mutex);
  2662. __iwl_up(priv);
  2663. mutex_unlock(&priv->mutex);
  2664. }
  2665. }
  2666. static void iwl_bg_rx_replenish(struct work_struct *data)
  2667. {
  2668. struct iwl_priv *priv =
  2669. container_of(data, struct iwl_priv, rx_replenish);
  2670. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2671. return;
  2672. mutex_lock(&priv->mutex);
  2673. iwlagn_rx_replenish(priv);
  2674. mutex_unlock(&priv->mutex);
  2675. }
  2676. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  2677. void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2678. {
  2679. struct ieee80211_conf *conf = NULL;
  2680. int ret = 0;
  2681. if (!vif || !priv->is_open)
  2682. return;
  2683. if (vif->type == NL80211_IFTYPE_AP) {
  2684. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  2685. return;
  2686. }
  2687. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2688. return;
  2689. iwl_scan_cancel_timeout(priv, 200);
  2690. conf = ieee80211_get_hw_conf(priv->hw);
  2691. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2692. iwlcore_commit_rxon(priv);
  2693. ret = iwl_send_rxon_timing(priv, vif);
  2694. if (ret)
  2695. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2696. "Attempting to continue.\n");
  2697. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2698. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2699. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2700. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2701. priv->staging_rxon.assoc_id = cpu_to_le16(vif->bss_conf.aid);
  2702. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  2703. vif->bss_conf.aid, vif->bss_conf.beacon_int);
  2704. if (vif->bss_conf.use_short_preamble)
  2705. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2706. else
  2707. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2708. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2709. if (vif->bss_conf.use_short_slot)
  2710. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2711. else
  2712. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2713. }
  2714. iwlcore_commit_rxon(priv);
  2715. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  2716. vif->bss_conf.aid, priv->active_rxon.bssid_addr);
  2717. switch (vif->type) {
  2718. case NL80211_IFTYPE_STATION:
  2719. break;
  2720. case NL80211_IFTYPE_ADHOC:
  2721. iwl_send_beacon_cmd(priv);
  2722. break;
  2723. default:
  2724. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  2725. __func__, vif->type);
  2726. break;
  2727. }
  2728. /* the chain noise calibration will enabled PM upon completion
  2729. * If chain noise has already been run, then we need to enable
  2730. * power management here */
  2731. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  2732. iwl_power_update_mode(priv, false);
  2733. /* Enable Rx differential gain and sensitivity calibrations */
  2734. iwl_chain_noise_reset(priv);
  2735. priv->start_calib = 1;
  2736. }
  2737. /*****************************************************************************
  2738. *
  2739. * mac80211 entry point functions
  2740. *
  2741. *****************************************************************************/
  2742. #define UCODE_READY_TIMEOUT (4 * HZ)
  2743. /*
  2744. * Not a mac80211 entry point function, but it fits in with all the
  2745. * other mac80211 functions grouped here.
  2746. */
  2747. static int iwl_mac_setup_register(struct iwl_priv *priv,
  2748. struct iwlagn_ucode_capabilities *capa)
  2749. {
  2750. int ret;
  2751. struct ieee80211_hw *hw = priv->hw;
  2752. hw->rate_control_algorithm = "iwl-agn-rs";
  2753. /* Tell mac80211 our characteristics */
  2754. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2755. IEEE80211_HW_AMPDU_AGGREGATION |
  2756. IEEE80211_HW_SPECTRUM_MGMT;
  2757. if (!priv->cfg->broken_powersave)
  2758. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  2759. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  2760. if (priv->cfg->sku & IWL_SKU_N)
  2761. hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
  2762. IEEE80211_HW_SUPPORTS_STATIC_SMPS;
  2763. hw->sta_data_size = sizeof(struct iwl_station_priv);
  2764. hw->vif_data_size = sizeof(struct iwl_vif_priv);
  2765. hw->wiphy->interface_modes =
  2766. BIT(NL80211_IFTYPE_STATION) |
  2767. BIT(NL80211_IFTYPE_ADHOC);
  2768. hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
  2769. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  2770. /*
  2771. * For now, disable PS by default because it affects
  2772. * RX performance significantly.
  2773. */
  2774. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2775. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  2776. /* we create the 802.11 header and a zero-length SSID element */
  2777. hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
  2778. /* Default value; 4 EDCA QOS priorities */
  2779. hw->queues = 4;
  2780. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  2781. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  2782. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2783. &priv->bands[IEEE80211_BAND_2GHZ];
  2784. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  2785. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2786. &priv->bands[IEEE80211_BAND_5GHZ];
  2787. ret = ieee80211_register_hw(priv->hw);
  2788. if (ret) {
  2789. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  2790. return ret;
  2791. }
  2792. priv->mac80211_registered = 1;
  2793. return 0;
  2794. }
  2795. static int iwl_mac_start(struct ieee80211_hw *hw)
  2796. {
  2797. struct iwl_priv *priv = hw->priv;
  2798. int ret;
  2799. IWL_DEBUG_MAC80211(priv, "enter\n");
  2800. /* we should be verifying the device is ready to be opened */
  2801. mutex_lock(&priv->mutex);
  2802. ret = __iwl_up(priv);
  2803. mutex_unlock(&priv->mutex);
  2804. if (ret)
  2805. return ret;
  2806. if (iwl_is_rfkill(priv))
  2807. goto out;
  2808. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2809. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  2810. * mac80211 will not be run successfully. */
  2811. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2812. test_bit(STATUS_READY, &priv->status),
  2813. UCODE_READY_TIMEOUT);
  2814. if (!ret) {
  2815. if (!test_bit(STATUS_READY, &priv->status)) {
  2816. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  2817. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2818. return -ETIMEDOUT;
  2819. }
  2820. }
  2821. iwl_led_start(priv);
  2822. out:
  2823. priv->is_open = 1;
  2824. IWL_DEBUG_MAC80211(priv, "leave\n");
  2825. return 0;
  2826. }
  2827. static void iwl_mac_stop(struct ieee80211_hw *hw)
  2828. {
  2829. struct iwl_priv *priv = hw->priv;
  2830. IWL_DEBUG_MAC80211(priv, "enter\n");
  2831. if (!priv->is_open)
  2832. return;
  2833. priv->is_open = 0;
  2834. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  2835. /* stop mac, cancel any scan request and clear
  2836. * RXON_FILTER_ASSOC_MSK BIT
  2837. */
  2838. mutex_lock(&priv->mutex);
  2839. iwl_scan_cancel_timeout(priv, 100);
  2840. mutex_unlock(&priv->mutex);
  2841. }
  2842. iwl_down(priv);
  2843. flush_workqueue(priv->workqueue);
  2844. /* enable interrupts again in order to receive rfkill changes */
  2845. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2846. iwl_enable_interrupts(priv);
  2847. IWL_DEBUG_MAC80211(priv, "leave\n");
  2848. }
  2849. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2850. {
  2851. struct iwl_priv *priv = hw->priv;
  2852. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2853. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2854. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2855. if (iwlagn_tx_skb(priv, skb))
  2856. dev_kfree_skb_any(skb);
  2857. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2858. return NETDEV_TX_OK;
  2859. }
  2860. void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2861. {
  2862. int ret = 0;
  2863. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2864. return;
  2865. /* The following should be done only at AP bring up */
  2866. if (!iwl_is_associated(priv)) {
  2867. /* RXON - unassoc (to set timing command) */
  2868. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2869. iwlcore_commit_rxon(priv);
  2870. /* RXON Timing */
  2871. ret = iwl_send_rxon_timing(priv, vif);
  2872. if (ret)
  2873. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2874. "Attempting to continue.\n");
  2875. /* AP has all antennas */
  2876. priv->chain_noise_data.active_chains =
  2877. priv->hw_params.valid_rx_ant;
  2878. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2879. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2880. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2881. priv->staging_rxon.assoc_id = 0;
  2882. if (vif->bss_conf.use_short_preamble)
  2883. priv->staging_rxon.flags |=
  2884. RXON_FLG_SHORT_PREAMBLE_MSK;
  2885. else
  2886. priv->staging_rxon.flags &=
  2887. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2888. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2889. if (vif->bss_conf.use_short_slot)
  2890. priv->staging_rxon.flags |=
  2891. RXON_FLG_SHORT_SLOT_MSK;
  2892. else
  2893. priv->staging_rxon.flags &=
  2894. ~RXON_FLG_SHORT_SLOT_MSK;
  2895. }
  2896. /* restore RXON assoc */
  2897. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2898. iwlcore_commit_rxon(priv);
  2899. }
  2900. iwl_send_beacon_cmd(priv);
  2901. /* FIXME - we need to add code here to detect a totally new
  2902. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2903. * clear sta table, add BCAST sta... */
  2904. }
  2905. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2906. struct ieee80211_vif *vif,
  2907. struct ieee80211_key_conf *keyconf,
  2908. struct ieee80211_sta *sta,
  2909. u32 iv32, u16 *phase1key)
  2910. {
  2911. struct iwl_priv *priv = hw->priv;
  2912. IWL_DEBUG_MAC80211(priv, "enter\n");
  2913. iwl_update_tkip_key(priv, keyconf, sta,
  2914. iv32, phase1key);
  2915. IWL_DEBUG_MAC80211(priv, "leave\n");
  2916. }
  2917. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2918. struct ieee80211_vif *vif,
  2919. struct ieee80211_sta *sta,
  2920. struct ieee80211_key_conf *key)
  2921. {
  2922. struct iwl_priv *priv = hw->priv;
  2923. int ret;
  2924. u8 sta_id;
  2925. bool is_default_wep_key = false;
  2926. IWL_DEBUG_MAC80211(priv, "enter\n");
  2927. if (priv->cfg->mod_params->sw_crypto) {
  2928. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2929. return -EOPNOTSUPP;
  2930. }
  2931. sta_id = iwl_sta_id_or_broadcast(priv, sta);
  2932. if (sta_id == IWL_INVALID_STATION)
  2933. return -EINVAL;
  2934. mutex_lock(&priv->mutex);
  2935. iwl_scan_cancel_timeout(priv, 100);
  2936. /*
  2937. * If we are getting WEP group key and we didn't receive any key mapping
  2938. * so far, we are in legacy wep mode (group key only), otherwise we are
  2939. * in 1X mode.
  2940. * In legacy wep mode, we use another host command to the uCode.
  2941. */
  2942. if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
  2943. key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
  2944. !sta) {
  2945. if (cmd == SET_KEY)
  2946. is_default_wep_key = !priv->key_mapping_key;
  2947. else
  2948. is_default_wep_key =
  2949. (key->hw_key_idx == HW_KEY_DEFAULT);
  2950. }
  2951. switch (cmd) {
  2952. case SET_KEY:
  2953. if (is_default_wep_key)
  2954. ret = iwl_set_default_wep_key(priv, key);
  2955. else
  2956. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2957. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2958. break;
  2959. case DISABLE_KEY:
  2960. if (is_default_wep_key)
  2961. ret = iwl_remove_default_wep_key(priv, key);
  2962. else
  2963. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2964. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2965. break;
  2966. default:
  2967. ret = -EINVAL;
  2968. }
  2969. mutex_unlock(&priv->mutex);
  2970. IWL_DEBUG_MAC80211(priv, "leave\n");
  2971. return ret;
  2972. }
  2973. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2974. struct ieee80211_vif *vif,
  2975. enum ieee80211_ampdu_mlme_action action,
  2976. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2977. {
  2978. struct iwl_priv *priv = hw->priv;
  2979. int ret = -EINVAL;
  2980. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2981. sta->addr, tid);
  2982. if (!(priv->cfg->sku & IWL_SKU_N))
  2983. return -EACCES;
  2984. mutex_lock(&priv->mutex);
  2985. switch (action) {
  2986. case IEEE80211_AMPDU_RX_START:
  2987. IWL_DEBUG_HT(priv, "start Rx\n");
  2988. ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
  2989. break;
  2990. case IEEE80211_AMPDU_RX_STOP:
  2991. IWL_DEBUG_HT(priv, "stop Rx\n");
  2992. ret = iwl_sta_rx_agg_stop(priv, sta, tid);
  2993. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2994. ret = 0;
  2995. break;
  2996. case IEEE80211_AMPDU_TX_START:
  2997. IWL_DEBUG_HT(priv, "start Tx\n");
  2998. ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
  2999. if (ret == 0) {
  3000. priv->_agn.agg_tids_count++;
  3001. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  3002. priv->_agn.agg_tids_count);
  3003. }
  3004. break;
  3005. case IEEE80211_AMPDU_TX_STOP:
  3006. IWL_DEBUG_HT(priv, "stop Tx\n");
  3007. ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
  3008. if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
  3009. priv->_agn.agg_tids_count--;
  3010. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  3011. priv->_agn.agg_tids_count);
  3012. }
  3013. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  3014. ret = 0;
  3015. if (priv->cfg->use_rts_for_aggregation) {
  3016. struct iwl_station_priv *sta_priv =
  3017. (void *) sta->drv_priv;
  3018. /*
  3019. * switch off RTS/CTS if it was previously enabled
  3020. */
  3021. sta_priv->lq_sta.lq.general_params.flags &=
  3022. ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
  3023. iwl_send_lq_cmd(priv, &sta_priv->lq_sta.lq,
  3024. CMD_ASYNC, false);
  3025. }
  3026. break;
  3027. case IEEE80211_AMPDU_TX_OPERATIONAL:
  3028. if (priv->cfg->use_rts_for_aggregation) {
  3029. struct iwl_station_priv *sta_priv =
  3030. (void *) sta->drv_priv;
  3031. /*
  3032. * switch to RTS/CTS if it is the prefer protection
  3033. * method for HT traffic
  3034. */
  3035. sta_priv->lq_sta.lq.general_params.flags |=
  3036. LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
  3037. iwl_send_lq_cmd(priv, &sta_priv->lq_sta.lq,
  3038. CMD_ASYNC, false);
  3039. }
  3040. ret = 0;
  3041. break;
  3042. }
  3043. mutex_unlock(&priv->mutex);
  3044. return ret;
  3045. }
  3046. static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
  3047. struct ieee80211_vif *vif,
  3048. enum sta_notify_cmd cmd,
  3049. struct ieee80211_sta *sta)
  3050. {
  3051. struct iwl_priv *priv = hw->priv;
  3052. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  3053. int sta_id;
  3054. switch (cmd) {
  3055. case STA_NOTIFY_SLEEP:
  3056. WARN_ON(!sta_priv->client);
  3057. sta_priv->asleep = true;
  3058. if (atomic_read(&sta_priv->pending_frames) > 0)
  3059. ieee80211_sta_block_awake(hw, sta, true);
  3060. break;
  3061. case STA_NOTIFY_AWAKE:
  3062. WARN_ON(!sta_priv->client);
  3063. if (!sta_priv->asleep)
  3064. break;
  3065. sta_priv->asleep = false;
  3066. sta_id = iwl_sta_id(sta);
  3067. if (sta_id != IWL_INVALID_STATION)
  3068. iwl_sta_modify_ps_wake(priv, sta_id);
  3069. break;
  3070. default:
  3071. break;
  3072. }
  3073. }
  3074. static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
  3075. struct ieee80211_vif *vif,
  3076. struct ieee80211_sta *sta)
  3077. {
  3078. struct iwl_priv *priv = hw->priv;
  3079. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  3080. bool is_ap = vif->type == NL80211_IFTYPE_STATION;
  3081. int ret;
  3082. u8 sta_id;
  3083. IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
  3084. sta->addr);
  3085. mutex_lock(&priv->mutex);
  3086. IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
  3087. sta->addr);
  3088. sta_priv->common.sta_id = IWL_INVALID_STATION;
  3089. atomic_set(&sta_priv->pending_frames, 0);
  3090. if (vif->type == NL80211_IFTYPE_AP)
  3091. sta_priv->client = true;
  3092. ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
  3093. &sta_id);
  3094. if (ret) {
  3095. IWL_ERR(priv, "Unable to add station %pM (%d)\n",
  3096. sta->addr, ret);
  3097. /* Should we return success if return code is EEXIST ? */
  3098. mutex_unlock(&priv->mutex);
  3099. return ret;
  3100. }
  3101. sta_priv->common.sta_id = sta_id;
  3102. /* Initialize rate scaling */
  3103. IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
  3104. sta->addr);
  3105. iwl_rs_rate_init(priv, sta, sta_id);
  3106. mutex_unlock(&priv->mutex);
  3107. return 0;
  3108. }
  3109. static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
  3110. struct ieee80211_channel_switch *ch_switch)
  3111. {
  3112. struct iwl_priv *priv = hw->priv;
  3113. const struct iwl_channel_info *ch_info;
  3114. struct ieee80211_conf *conf = &hw->conf;
  3115. struct ieee80211_channel *channel = ch_switch->channel;
  3116. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  3117. u16 ch;
  3118. unsigned long flags = 0;
  3119. IWL_DEBUG_MAC80211(priv, "enter\n");
  3120. if (iwl_is_rfkill(priv))
  3121. goto out_exit;
  3122. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  3123. test_bit(STATUS_SCANNING, &priv->status))
  3124. goto out_exit;
  3125. if (!iwl_is_associated(priv))
  3126. goto out_exit;
  3127. /* channel switch in progress */
  3128. if (priv->switch_rxon.switch_in_progress == true)
  3129. goto out_exit;
  3130. mutex_lock(&priv->mutex);
  3131. if (priv->cfg->ops->lib->set_channel_switch) {
  3132. ch = channel->hw_value;
  3133. if (le16_to_cpu(priv->active_rxon.channel) != ch) {
  3134. ch_info = iwl_get_channel_info(priv,
  3135. channel->band,
  3136. ch);
  3137. if (!is_channel_valid(ch_info)) {
  3138. IWL_DEBUG_MAC80211(priv, "invalid channel\n");
  3139. goto out;
  3140. }
  3141. spin_lock_irqsave(&priv->lock, flags);
  3142. priv->current_ht_config.smps = conf->smps_mode;
  3143. /* Configure HT40 channels */
  3144. ht_conf->is_ht = conf_is_ht(conf);
  3145. if (ht_conf->is_ht) {
  3146. if (conf_is_ht40_minus(conf)) {
  3147. ht_conf->extension_chan_offset =
  3148. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  3149. ht_conf->is_40mhz = true;
  3150. } else if (conf_is_ht40_plus(conf)) {
  3151. ht_conf->extension_chan_offset =
  3152. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  3153. ht_conf->is_40mhz = true;
  3154. } else {
  3155. ht_conf->extension_chan_offset =
  3156. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  3157. ht_conf->is_40mhz = false;
  3158. }
  3159. } else
  3160. ht_conf->is_40mhz = false;
  3161. if (le16_to_cpu(priv->staging_rxon.channel) != ch)
  3162. priv->staging_rxon.flags = 0;
  3163. iwl_set_rxon_channel(priv, channel);
  3164. iwl_set_rxon_ht(priv, ht_conf);
  3165. iwl_set_flags_for_band(priv, channel->band,
  3166. priv->vif);
  3167. spin_unlock_irqrestore(&priv->lock, flags);
  3168. iwl_set_rate(priv);
  3169. /*
  3170. * at this point, staging_rxon has the
  3171. * configuration for channel switch
  3172. */
  3173. if (priv->cfg->ops->lib->set_channel_switch(priv,
  3174. ch_switch))
  3175. priv->switch_rxon.switch_in_progress = false;
  3176. }
  3177. }
  3178. out:
  3179. mutex_unlock(&priv->mutex);
  3180. out_exit:
  3181. if (!priv->switch_rxon.switch_in_progress)
  3182. ieee80211_chswitch_done(priv->vif, false);
  3183. IWL_DEBUG_MAC80211(priv, "leave\n");
  3184. }
  3185. static void iwlagn_configure_filter(struct ieee80211_hw *hw,
  3186. unsigned int changed_flags,
  3187. unsigned int *total_flags,
  3188. u64 multicast)
  3189. {
  3190. struct iwl_priv *priv = hw->priv;
  3191. __le32 filter_or = 0, filter_nand = 0;
  3192. #define CHK(test, flag) do { \
  3193. if (*total_flags & (test)) \
  3194. filter_or |= (flag); \
  3195. else \
  3196. filter_nand |= (flag); \
  3197. } while (0)
  3198. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  3199. changed_flags, *total_flags);
  3200. CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
  3201. CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
  3202. CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
  3203. #undef CHK
  3204. mutex_lock(&priv->mutex);
  3205. priv->staging_rxon.filter_flags &= ~filter_nand;
  3206. priv->staging_rxon.filter_flags |= filter_or;
  3207. iwlcore_commit_rxon(priv);
  3208. mutex_unlock(&priv->mutex);
  3209. /*
  3210. * Receiving all multicast frames is always enabled by the
  3211. * default flags setup in iwl_connection_init_rx_config()
  3212. * since we currently do not support programming multicast
  3213. * filters into the device.
  3214. */
  3215. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  3216. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  3217. }
  3218. static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
  3219. {
  3220. struct iwl_priv *priv = hw->priv;
  3221. mutex_lock(&priv->mutex);
  3222. IWL_DEBUG_MAC80211(priv, "enter\n");
  3223. /* do not support "flush" */
  3224. if (!priv->cfg->ops->lib->txfifo_flush)
  3225. goto done;
  3226. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3227. IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
  3228. goto done;
  3229. }
  3230. if (iwl_is_rfkill(priv)) {
  3231. IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
  3232. goto done;
  3233. }
  3234. /*
  3235. * mac80211 will not push any more frames for transmit
  3236. * until the flush is completed
  3237. */
  3238. if (drop) {
  3239. IWL_DEBUG_MAC80211(priv, "send flush command\n");
  3240. if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
  3241. IWL_ERR(priv, "flush request fail\n");
  3242. goto done;
  3243. }
  3244. }
  3245. IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
  3246. iwlagn_wait_tx_queue_empty(priv);
  3247. done:
  3248. mutex_unlock(&priv->mutex);
  3249. IWL_DEBUG_MAC80211(priv, "leave\n");
  3250. }
  3251. /*****************************************************************************
  3252. *
  3253. * driver setup and teardown
  3254. *
  3255. *****************************************************************************/
  3256. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  3257. {
  3258. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  3259. init_waitqueue_head(&priv->wait_command_queue);
  3260. INIT_WORK(&priv->restart, iwl_bg_restart);
  3261. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  3262. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  3263. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  3264. INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
  3265. INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
  3266. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  3267. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  3268. iwl_setup_scan_deferred_work(priv);
  3269. if (priv->cfg->ops->lib->setup_deferred_work)
  3270. priv->cfg->ops->lib->setup_deferred_work(priv);
  3271. init_timer(&priv->statistics_periodic);
  3272. priv->statistics_periodic.data = (unsigned long)priv;
  3273. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  3274. init_timer(&priv->ucode_trace);
  3275. priv->ucode_trace.data = (unsigned long)priv;
  3276. priv->ucode_trace.function = iwl_bg_ucode_trace;
  3277. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  3278. init_timer(&priv->monitor_recover);
  3279. priv->monitor_recover.data = (unsigned long)priv;
  3280. priv->monitor_recover.function =
  3281. priv->cfg->ops->lib->recover_from_tx_stall;
  3282. }
  3283. if (!priv->cfg->use_isr_legacy)
  3284. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  3285. iwl_irq_tasklet, (unsigned long)priv);
  3286. else
  3287. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  3288. iwl_irq_tasklet_legacy, (unsigned long)priv);
  3289. }
  3290. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  3291. {
  3292. if (priv->cfg->ops->lib->cancel_deferred_work)
  3293. priv->cfg->ops->lib->cancel_deferred_work(priv);
  3294. cancel_delayed_work_sync(&priv->init_alive_start);
  3295. cancel_delayed_work(&priv->scan_check);
  3296. cancel_work_sync(&priv->start_internal_scan);
  3297. cancel_delayed_work(&priv->alive_start);
  3298. cancel_work_sync(&priv->run_time_calib_work);
  3299. cancel_work_sync(&priv->beacon_update);
  3300. cancel_work_sync(&priv->bt_full_concurrency);
  3301. del_timer_sync(&priv->statistics_periodic);
  3302. del_timer_sync(&priv->ucode_trace);
  3303. }
  3304. static void iwl_init_hw_rates(struct iwl_priv *priv,
  3305. struct ieee80211_rate *rates)
  3306. {
  3307. int i;
  3308. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  3309. rates[i].bitrate = iwl_rates[i].ieee * 5;
  3310. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  3311. rates[i].hw_value_short = i;
  3312. rates[i].flags = 0;
  3313. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  3314. /*
  3315. * If CCK != 1M then set short preamble rate flag.
  3316. */
  3317. rates[i].flags |=
  3318. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  3319. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  3320. }
  3321. }
  3322. }
  3323. static int iwl_init_drv(struct iwl_priv *priv)
  3324. {
  3325. int ret;
  3326. priv->ibss_beacon = NULL;
  3327. spin_lock_init(&priv->sta_lock);
  3328. spin_lock_init(&priv->hcmd_lock);
  3329. INIT_LIST_HEAD(&priv->free_frames);
  3330. mutex_init(&priv->mutex);
  3331. mutex_init(&priv->sync_cmd_mutex);
  3332. priv->ieee_channels = NULL;
  3333. priv->ieee_rates = NULL;
  3334. priv->band = IEEE80211_BAND_2GHZ;
  3335. priv->iw_mode = NL80211_IFTYPE_STATION;
  3336. priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
  3337. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  3338. priv->_agn.agg_tids_count = 0;
  3339. /* initialize force reset */
  3340. priv->force_reset[IWL_RF_RESET].reset_duration =
  3341. IWL_DELAY_NEXT_FORCE_RF_RESET;
  3342. priv->force_reset[IWL_FW_RESET].reset_duration =
  3343. IWL_DELAY_NEXT_FORCE_FW_RELOAD;
  3344. /* Choose which receivers/antennas to use */
  3345. if (priv->cfg->ops->hcmd->set_rxon_chain)
  3346. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  3347. iwl_init_scan_params(priv);
  3348. /* Set the tx_power_user_lmt to the lowest power level
  3349. * this value will get overwritten by channel max power avg
  3350. * from eeprom */
  3351. priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
  3352. ret = iwl_init_channel_map(priv);
  3353. if (ret) {
  3354. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  3355. goto err;
  3356. }
  3357. ret = iwlcore_init_geos(priv);
  3358. if (ret) {
  3359. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  3360. goto err_free_channel_map;
  3361. }
  3362. iwl_init_hw_rates(priv, priv->ieee_rates);
  3363. return 0;
  3364. err_free_channel_map:
  3365. iwl_free_channel_map(priv);
  3366. err:
  3367. return ret;
  3368. }
  3369. static void iwl_uninit_drv(struct iwl_priv *priv)
  3370. {
  3371. iwl_calib_free_results(priv);
  3372. iwlcore_free_geos(priv);
  3373. iwl_free_channel_map(priv);
  3374. kfree(priv->scan_cmd);
  3375. }
  3376. static struct ieee80211_ops iwl_hw_ops = {
  3377. .tx = iwl_mac_tx,
  3378. .start = iwl_mac_start,
  3379. .stop = iwl_mac_stop,
  3380. .add_interface = iwl_mac_add_interface,
  3381. .remove_interface = iwl_mac_remove_interface,
  3382. .config = iwl_mac_config,
  3383. .configure_filter = iwlagn_configure_filter,
  3384. .set_key = iwl_mac_set_key,
  3385. .update_tkip_key = iwl_mac_update_tkip_key,
  3386. .conf_tx = iwl_mac_conf_tx,
  3387. .reset_tsf = iwl_mac_reset_tsf,
  3388. .bss_info_changed = iwl_bss_info_changed,
  3389. .ampdu_action = iwl_mac_ampdu_action,
  3390. .hw_scan = iwl_mac_hw_scan,
  3391. .sta_notify = iwl_mac_sta_notify,
  3392. .sta_add = iwlagn_mac_sta_add,
  3393. .sta_remove = iwl_mac_sta_remove,
  3394. .channel_switch = iwl_mac_channel_switch,
  3395. .flush = iwl_mac_flush,
  3396. .tx_last_beacon = iwl_mac_tx_last_beacon,
  3397. };
  3398. static void iwl_hw_detect(struct iwl_priv *priv)
  3399. {
  3400. priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
  3401. priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
  3402. pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
  3403. IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
  3404. }
  3405. static int iwl_set_hw_params(struct iwl_priv *priv)
  3406. {
  3407. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  3408. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  3409. if (priv->cfg->mod_params->amsdu_size_8K)
  3410. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
  3411. else
  3412. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
  3413. priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
  3414. if (priv->cfg->mod_params->disable_11n)
  3415. priv->cfg->sku &= ~IWL_SKU_N;
  3416. /* Device-specific setup */
  3417. return priv->cfg->ops->lib->set_hw_params(priv);
  3418. }
  3419. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  3420. {
  3421. int err = 0;
  3422. struct iwl_priv *priv;
  3423. struct ieee80211_hw *hw;
  3424. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  3425. unsigned long flags;
  3426. u16 pci_cmd, num_mac;
  3427. /************************
  3428. * 1. Allocating HW data
  3429. ************************/
  3430. /* Disabling hardware scan means that mac80211 will perform scans
  3431. * "the hard way", rather than using device's scan. */
  3432. if (cfg->mod_params->disable_hw_scan) {
  3433. if (iwl_debug_level & IWL_DL_INFO)
  3434. dev_printk(KERN_DEBUG, &(pdev->dev),
  3435. "Disabling hw_scan\n");
  3436. iwl_hw_ops.hw_scan = NULL;
  3437. }
  3438. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  3439. if (!hw) {
  3440. err = -ENOMEM;
  3441. goto out;
  3442. }
  3443. priv = hw->priv;
  3444. /* At this point both hw and priv are allocated. */
  3445. SET_IEEE80211_DEV(hw, &pdev->dev);
  3446. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  3447. priv->cfg = cfg;
  3448. priv->pci_dev = pdev;
  3449. priv->inta_mask = CSR_INI_SET_MASK;
  3450. /* is antenna coupling more than 35dB ? */
  3451. priv->bt_ant_couple_ok =
  3452. (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
  3453. true : false;
  3454. if (iwl_alloc_traffic_mem(priv))
  3455. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  3456. /**************************
  3457. * 2. Initializing PCI bus
  3458. **************************/
  3459. pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
  3460. PCIE_LINK_STATE_CLKPM);
  3461. if (pci_enable_device(pdev)) {
  3462. err = -ENODEV;
  3463. goto out_ieee80211_free_hw;
  3464. }
  3465. pci_set_master(pdev);
  3466. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  3467. if (!err)
  3468. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  3469. if (err) {
  3470. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3471. if (!err)
  3472. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3473. /* both attempts failed: */
  3474. if (err) {
  3475. IWL_WARN(priv, "No suitable DMA available.\n");
  3476. goto out_pci_disable_device;
  3477. }
  3478. }
  3479. err = pci_request_regions(pdev, DRV_NAME);
  3480. if (err)
  3481. goto out_pci_disable_device;
  3482. pci_set_drvdata(pdev, priv);
  3483. /***********************
  3484. * 3. Read REV register
  3485. ***********************/
  3486. priv->hw_base = pci_iomap(pdev, 0, 0);
  3487. if (!priv->hw_base) {
  3488. err = -ENODEV;
  3489. goto out_pci_release_regions;
  3490. }
  3491. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  3492. (unsigned long long) pci_resource_len(pdev, 0));
  3493. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  3494. /* these spin locks will be used in apm_ops.init and EEPROM access
  3495. * we should init now
  3496. */
  3497. spin_lock_init(&priv->reg_lock);
  3498. spin_lock_init(&priv->lock);
  3499. /*
  3500. * stop and reset the on-board processor just in case it is in a
  3501. * strange state ... like being left stranded by a primary kernel
  3502. * and this is now the kdump kernel trying to start up
  3503. */
  3504. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  3505. iwl_hw_detect(priv);
  3506. IWL_INFO(priv, "Detected %s, REV=0x%X\n",
  3507. priv->cfg->name, priv->hw_rev);
  3508. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  3509. * PCI Tx retries from interfering with C3 CPU state */
  3510. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  3511. iwl_prepare_card_hw(priv);
  3512. if (!priv->hw_ready) {
  3513. IWL_WARN(priv, "Failed, HW not ready\n");
  3514. goto out_iounmap;
  3515. }
  3516. /*****************
  3517. * 4. Read EEPROM
  3518. *****************/
  3519. /* Read the EEPROM */
  3520. err = iwl_eeprom_init(priv);
  3521. if (err) {
  3522. IWL_ERR(priv, "Unable to init EEPROM\n");
  3523. goto out_iounmap;
  3524. }
  3525. err = iwl_eeprom_check_version(priv);
  3526. if (err)
  3527. goto out_free_eeprom;
  3528. /* extract MAC Address */
  3529. iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
  3530. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
  3531. priv->hw->wiphy->addresses = priv->addresses;
  3532. priv->hw->wiphy->n_addresses = 1;
  3533. num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
  3534. if (num_mac > 1) {
  3535. memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
  3536. ETH_ALEN);
  3537. priv->addresses[1].addr[5]++;
  3538. priv->hw->wiphy->n_addresses++;
  3539. }
  3540. /************************
  3541. * 5. Setup HW constants
  3542. ************************/
  3543. if (iwl_set_hw_params(priv)) {
  3544. IWL_ERR(priv, "failed to set hw parameters\n");
  3545. goto out_free_eeprom;
  3546. }
  3547. /*******************
  3548. * 6. Setup priv
  3549. *******************/
  3550. err = iwl_init_drv(priv);
  3551. if (err)
  3552. goto out_free_eeprom;
  3553. /* At this point both hw and priv are initialized. */
  3554. /********************
  3555. * 7. Setup services
  3556. ********************/
  3557. spin_lock_irqsave(&priv->lock, flags);
  3558. iwl_disable_interrupts(priv);
  3559. spin_unlock_irqrestore(&priv->lock, flags);
  3560. pci_enable_msi(priv->pci_dev);
  3561. iwl_alloc_isr_ict(priv);
  3562. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  3563. IRQF_SHARED, DRV_NAME, priv);
  3564. if (err) {
  3565. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  3566. goto out_disable_msi;
  3567. }
  3568. iwl_setup_deferred_work(priv);
  3569. iwl_setup_rx_handlers(priv);
  3570. /*********************************************
  3571. * 8. Enable interrupts and read RFKILL state
  3572. *********************************************/
  3573. /* enable interrupts if needed: hw bug w/a */
  3574. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  3575. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  3576. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  3577. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  3578. }
  3579. iwl_enable_interrupts(priv);
  3580. /* If platform's RF_KILL switch is NOT set to KILL */
  3581. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  3582. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3583. else
  3584. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3585. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  3586. test_bit(STATUS_RF_KILL_HW, &priv->status));
  3587. iwl_power_initialize(priv);
  3588. iwl_tt_initialize(priv);
  3589. init_completion(&priv->_agn.firmware_loading_complete);
  3590. err = iwl_request_firmware(priv, true);
  3591. if (err)
  3592. goto out_destroy_workqueue;
  3593. return 0;
  3594. out_destroy_workqueue:
  3595. destroy_workqueue(priv->workqueue);
  3596. priv->workqueue = NULL;
  3597. free_irq(priv->pci_dev->irq, priv);
  3598. iwl_free_isr_ict(priv);
  3599. out_disable_msi:
  3600. pci_disable_msi(priv->pci_dev);
  3601. iwl_uninit_drv(priv);
  3602. out_free_eeprom:
  3603. iwl_eeprom_free(priv);
  3604. out_iounmap:
  3605. pci_iounmap(pdev, priv->hw_base);
  3606. out_pci_release_regions:
  3607. pci_set_drvdata(pdev, NULL);
  3608. pci_release_regions(pdev);
  3609. out_pci_disable_device:
  3610. pci_disable_device(pdev);
  3611. out_ieee80211_free_hw:
  3612. iwl_free_traffic_mem(priv);
  3613. ieee80211_free_hw(priv->hw);
  3614. out:
  3615. return err;
  3616. }
  3617. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  3618. {
  3619. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3620. unsigned long flags;
  3621. if (!priv)
  3622. return;
  3623. wait_for_completion(&priv->_agn.firmware_loading_complete);
  3624. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3625. iwl_dbgfs_unregister(priv);
  3626. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3627. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  3628. * to be called and iwl_down since we are removing the device
  3629. * we need to set STATUS_EXIT_PENDING bit.
  3630. */
  3631. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3632. if (priv->mac80211_registered) {
  3633. ieee80211_unregister_hw(priv->hw);
  3634. priv->mac80211_registered = 0;
  3635. } else {
  3636. iwl_down(priv);
  3637. }
  3638. /*
  3639. * Make sure device is reset to low power before unloading driver.
  3640. * This may be redundant with iwl_down(), but there are paths to
  3641. * run iwl_down() without calling apm_ops.stop(), and there are
  3642. * paths to avoid running iwl_down() at all before leaving driver.
  3643. * This (inexpensive) call *makes sure* device is reset.
  3644. */
  3645. priv->cfg->ops->lib->apm_ops.stop(priv);
  3646. iwl_tt_exit(priv);
  3647. /* make sure we flush any pending irq or
  3648. * tasklet for the driver
  3649. */
  3650. spin_lock_irqsave(&priv->lock, flags);
  3651. iwl_disable_interrupts(priv);
  3652. spin_unlock_irqrestore(&priv->lock, flags);
  3653. iwl_synchronize_irq(priv);
  3654. iwl_dealloc_ucode_pci(priv);
  3655. if (priv->rxq.bd)
  3656. iwlagn_rx_queue_free(priv, &priv->rxq);
  3657. iwlagn_hw_txq_ctx_free(priv);
  3658. iwl_eeprom_free(priv);
  3659. /*netif_stop_queue(dev); */
  3660. flush_workqueue(priv->workqueue);
  3661. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  3662. * priv->workqueue... so we can't take down the workqueue
  3663. * until now... */
  3664. destroy_workqueue(priv->workqueue);
  3665. priv->workqueue = NULL;
  3666. iwl_free_traffic_mem(priv);
  3667. free_irq(priv->pci_dev->irq, priv);
  3668. pci_disable_msi(priv->pci_dev);
  3669. pci_iounmap(pdev, priv->hw_base);
  3670. pci_release_regions(pdev);
  3671. pci_disable_device(pdev);
  3672. pci_set_drvdata(pdev, NULL);
  3673. iwl_uninit_drv(priv);
  3674. iwl_free_isr_ict(priv);
  3675. if (priv->ibss_beacon)
  3676. dev_kfree_skb(priv->ibss_beacon);
  3677. ieee80211_free_hw(priv->hw);
  3678. }
  3679. /*****************************************************************************
  3680. *
  3681. * driver and module entry point
  3682. *
  3683. *****************************************************************************/
  3684. /* Hardware specific file defines the PCI IDs table for that hardware module */
  3685. static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
  3686. #ifdef CONFIG_IWL4965
  3687. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  3688. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  3689. #endif /* CONFIG_IWL4965 */
  3690. #ifdef CONFIG_IWL5000
  3691. /* 5100 Series WiFi */
  3692. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  3693. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  3694. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  3695. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  3696. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  3697. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3698. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  3699. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  3700. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  3701. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  3702. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  3703. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  3704. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  3705. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3706. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  3707. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  3708. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  3709. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  3710. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  3711. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  3712. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  3713. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3714. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  3715. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  3716. /* 5300 Series WiFi */
  3717. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  3718. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  3719. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  3720. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  3721. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  3722. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  3723. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  3724. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  3725. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  3726. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  3727. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  3728. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  3729. /* 5350 Series WiFi/WiMax */
  3730. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  3731. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  3732. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  3733. /* 5150 Series Wifi/WiMax */
  3734. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  3735. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  3736. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  3737. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  3738. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  3739. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  3740. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  3741. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  3742. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  3743. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  3744. /* 6x00 Series */
  3745. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  3746. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  3747. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  3748. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  3749. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  3750. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  3751. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  3752. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  3753. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  3754. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  3755. /* 6x00 Series Gen2a */
  3756. {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
  3757. {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
  3758. {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
  3759. {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
  3760. {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
  3761. {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
  3762. {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
  3763. {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
  3764. {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
  3765. {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
  3766. {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
  3767. {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
  3768. {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
  3769. {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
  3770. /* 6x00 Series Gen2b */
  3771. {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
  3772. {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
  3773. {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
  3774. {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
  3775. {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
  3776. {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
  3777. {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
  3778. {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
  3779. {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
  3780. {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
  3781. {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
  3782. {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
  3783. {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
  3784. {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
  3785. {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
  3786. {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
  3787. {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
  3788. {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
  3789. {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
  3790. {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
  3791. {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
  3792. {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
  3793. {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
  3794. {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
  3795. {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
  3796. {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
  3797. {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
  3798. {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
  3799. /* 6x50 WiFi/WiMax Series */
  3800. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  3801. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  3802. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  3803. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  3804. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  3805. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  3806. /* 6x50 WiFi/WiMax Series Gen2 */
  3807. {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
  3808. {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
  3809. {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
  3810. {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
  3811. {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
  3812. {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
  3813. /* 1000 Series WiFi */
  3814. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  3815. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  3816. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  3817. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  3818. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  3819. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  3820. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  3821. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  3822. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  3823. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  3824. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  3825. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  3826. #endif /* CONFIG_IWL5000 */
  3827. {0}
  3828. };
  3829. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  3830. static struct pci_driver iwl_driver = {
  3831. .name = DRV_NAME,
  3832. .id_table = iwl_hw_card_ids,
  3833. .probe = iwl_pci_probe,
  3834. .remove = __devexit_p(iwl_pci_remove),
  3835. #ifdef CONFIG_PM
  3836. .suspend = iwl_pci_suspend,
  3837. .resume = iwl_pci_resume,
  3838. #endif
  3839. };
  3840. static int __init iwl_init(void)
  3841. {
  3842. int ret;
  3843. pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3844. pr_info(DRV_COPYRIGHT "\n");
  3845. ret = iwlagn_rate_control_register();
  3846. if (ret) {
  3847. pr_err("Unable to register rate control algorithm: %d\n", ret);
  3848. return ret;
  3849. }
  3850. ret = pci_register_driver(&iwl_driver);
  3851. if (ret) {
  3852. pr_err("Unable to initialize PCI module\n");
  3853. goto error_register;
  3854. }
  3855. return ret;
  3856. error_register:
  3857. iwlagn_rate_control_unregister();
  3858. return ret;
  3859. }
  3860. static void __exit iwl_exit(void)
  3861. {
  3862. pci_unregister_driver(&iwl_driver);
  3863. iwlagn_rate_control_unregister();
  3864. }
  3865. module_exit(iwl_exit);
  3866. module_init(iwl_init);
  3867. #ifdef CONFIG_IWLWIFI_DEBUG
  3868. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  3869. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  3870. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3871. MODULE_PARM_DESC(debug, "debug output mask");
  3872. #endif
  3873. module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
  3874. MODULE_PARM_DESC(swcrypto50,
  3875. "using crypto in software (default 0 [hardware]) (deprecated)");
  3876. module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
  3877. MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
  3878. module_param_named(queues_num50,
  3879. iwlagn_mod_params.num_of_queues, int, S_IRUGO);
  3880. MODULE_PARM_DESC(queues_num50,
  3881. "number of hw queues in 50xx series (deprecated)");
  3882. module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
  3883. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  3884. module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
  3885. MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
  3886. module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
  3887. MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
  3888. module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
  3889. int, S_IRUGO);
  3890. MODULE_PARM_DESC(amsdu_size_8K50,
  3891. "enable 8K amsdu size in 50XX series (deprecated)");
  3892. module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
  3893. int, S_IRUGO);
  3894. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
  3895. module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
  3896. MODULE_PARM_DESC(fw_restart50,
  3897. "restart firmware in case of error (deprecated)");
  3898. module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
  3899. MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
  3900. module_param_named(
  3901. disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
  3902. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  3903. module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
  3904. S_IRUGO);
  3905. MODULE_PARM_DESC(ucode_alternative,
  3906. "specify ucode alternative to use from ucode file");
  3907. module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
  3908. MODULE_PARM_DESC(antenna_coupling,
  3909. "specify antenna coupling in dB (defualt: 0 dB)");