async_tx.c 11 KB

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  1. /*
  2. * core routines for the asynchronous memory transfer/transform api
  3. *
  4. * Copyright © 2006, Intel Corporation.
  5. *
  6. * Dan Williams <dan.j.williams@intel.com>
  7. *
  8. * with architecture considerations by:
  9. * Neil Brown <neilb@suse.de>
  10. * Jeff Garzik <jeff@garzik.org>
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms and conditions of the GNU General Public License,
  14. * version 2, as published by the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope it will be useful, but WITHOUT
  17. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  19. * more details.
  20. *
  21. * You should have received a copy of the GNU General Public License along with
  22. * this program; if not, write to the Free Software Foundation, Inc.,
  23. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  24. *
  25. */
  26. #include <linux/rculist.h>
  27. #include <linux/kernel.h>
  28. #include <linux/async_tx.h>
  29. #ifdef CONFIG_DMA_ENGINE
  30. static enum dma_state_client
  31. dma_channel_add_remove(struct dma_client *client,
  32. struct dma_chan *chan, enum dma_state state);
  33. static struct dma_client async_tx_dma = {
  34. .event_callback = dma_channel_add_remove,
  35. /* .cap_mask == 0 defaults to all channels */
  36. };
  37. /**
  38. * async_tx_lock - protect modification of async_tx_master_list and serialize
  39. * rebalance operations
  40. */
  41. static DEFINE_SPINLOCK(async_tx_lock);
  42. static LIST_HEAD(async_tx_master_list);
  43. /* async_tx_issue_pending_all - start all transactions on all channels */
  44. void async_tx_issue_pending_all(void)
  45. {
  46. struct dma_chan_ref *ref;
  47. rcu_read_lock();
  48. list_for_each_entry_rcu(ref, &async_tx_master_list, node)
  49. ref->chan->device->device_issue_pending(ref->chan);
  50. rcu_read_unlock();
  51. }
  52. EXPORT_SYMBOL_GPL(async_tx_issue_pending_all);
  53. static void
  54. free_dma_chan_ref(struct rcu_head *rcu)
  55. {
  56. struct dma_chan_ref *ref;
  57. ref = container_of(rcu, struct dma_chan_ref, rcu);
  58. kfree(ref);
  59. }
  60. static void
  61. init_dma_chan_ref(struct dma_chan_ref *ref, struct dma_chan *chan)
  62. {
  63. INIT_LIST_HEAD(&ref->node);
  64. INIT_RCU_HEAD(&ref->rcu);
  65. ref->chan = chan;
  66. atomic_set(&ref->count, 0);
  67. }
  68. static enum dma_state_client
  69. dma_channel_add_remove(struct dma_client *client,
  70. struct dma_chan *chan, enum dma_state state)
  71. {
  72. unsigned long found, flags;
  73. struct dma_chan_ref *master_ref, *ref;
  74. enum dma_state_client ack = DMA_DUP; /* default: take no action */
  75. switch (state) {
  76. case DMA_RESOURCE_AVAILABLE:
  77. found = 0;
  78. rcu_read_lock();
  79. list_for_each_entry_rcu(ref, &async_tx_master_list, node)
  80. if (ref->chan == chan) {
  81. found = 1;
  82. break;
  83. }
  84. rcu_read_unlock();
  85. pr_debug("async_tx: dma resource available [%s]\n",
  86. found ? "old" : "new");
  87. if (!found)
  88. ack = DMA_ACK;
  89. else
  90. break;
  91. /* add the channel to the generic management list */
  92. master_ref = kmalloc(sizeof(*master_ref), GFP_KERNEL);
  93. if (master_ref) {
  94. init_dma_chan_ref(master_ref, chan);
  95. spin_lock_irqsave(&async_tx_lock, flags);
  96. list_add_tail_rcu(&master_ref->node,
  97. &async_tx_master_list);
  98. spin_unlock_irqrestore(&async_tx_lock,
  99. flags);
  100. } else {
  101. printk(KERN_WARNING "async_tx: unable to create"
  102. " new master entry in response to"
  103. " a DMA_RESOURCE_ADDED event"
  104. " (-ENOMEM)\n");
  105. return 0;
  106. }
  107. break;
  108. case DMA_RESOURCE_REMOVED:
  109. found = 0;
  110. spin_lock_irqsave(&async_tx_lock, flags);
  111. list_for_each_entry(ref, &async_tx_master_list, node)
  112. if (ref->chan == chan) {
  113. list_del_rcu(&ref->node);
  114. call_rcu(&ref->rcu, free_dma_chan_ref);
  115. found = 1;
  116. break;
  117. }
  118. spin_unlock_irqrestore(&async_tx_lock, flags);
  119. pr_debug("async_tx: dma resource removed [%s]\n",
  120. found ? "ours" : "not ours");
  121. if (found)
  122. ack = DMA_ACK;
  123. else
  124. break;
  125. break;
  126. case DMA_RESOURCE_SUSPEND:
  127. case DMA_RESOURCE_RESUME:
  128. printk(KERN_WARNING "async_tx: does not support dma channel"
  129. " suspend/resume\n");
  130. break;
  131. default:
  132. BUG();
  133. }
  134. return ack;
  135. }
  136. static int __init async_tx_init(void)
  137. {
  138. dma_async_client_register(&async_tx_dma);
  139. dma_async_client_chan_request(&async_tx_dma);
  140. printk(KERN_INFO "async_tx: api initialized (async)\n");
  141. return 0;
  142. }
  143. static void __exit async_tx_exit(void)
  144. {
  145. dma_async_client_unregister(&async_tx_dma);
  146. }
  147. /**
  148. * __async_tx_find_channel - find a channel to carry out the operation or let
  149. * the transaction execute synchronously
  150. * @depend_tx: transaction dependency
  151. * @tx_type: transaction type
  152. */
  153. struct dma_chan *
  154. __async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx,
  155. enum dma_transaction_type tx_type)
  156. {
  157. /* see if we can keep the chain on one channel */
  158. if (depend_tx &&
  159. dma_has_cap(tx_type, depend_tx->chan->device->cap_mask))
  160. return depend_tx->chan;
  161. return dma_find_channel(tx_type);
  162. }
  163. EXPORT_SYMBOL_GPL(__async_tx_find_channel);
  164. #else
  165. static int __init async_tx_init(void)
  166. {
  167. printk(KERN_INFO "async_tx: api initialized (sync-only)\n");
  168. return 0;
  169. }
  170. static void __exit async_tx_exit(void)
  171. {
  172. do { } while (0);
  173. }
  174. #endif
  175. /**
  176. * async_tx_channel_switch - queue an interrupt descriptor with a dependency
  177. * pre-attached.
  178. * @depend_tx: the operation that must finish before the new operation runs
  179. * @tx: the new operation
  180. */
  181. static void
  182. async_tx_channel_switch(struct dma_async_tx_descriptor *depend_tx,
  183. struct dma_async_tx_descriptor *tx)
  184. {
  185. struct dma_chan *chan;
  186. struct dma_device *device;
  187. struct dma_async_tx_descriptor *intr_tx = (void *) ~0;
  188. /* first check to see if we can still append to depend_tx */
  189. spin_lock_bh(&depend_tx->lock);
  190. if (depend_tx->parent && depend_tx->chan == tx->chan) {
  191. tx->parent = depend_tx;
  192. depend_tx->next = tx;
  193. intr_tx = NULL;
  194. }
  195. spin_unlock_bh(&depend_tx->lock);
  196. if (!intr_tx)
  197. return;
  198. chan = depend_tx->chan;
  199. device = chan->device;
  200. /* see if we can schedule an interrupt
  201. * otherwise poll for completion
  202. */
  203. if (dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  204. intr_tx = device->device_prep_dma_interrupt(chan, 0);
  205. else
  206. intr_tx = NULL;
  207. if (intr_tx) {
  208. intr_tx->callback = NULL;
  209. intr_tx->callback_param = NULL;
  210. tx->parent = intr_tx;
  211. /* safe to set ->next outside the lock since we know we are
  212. * not submitted yet
  213. */
  214. intr_tx->next = tx;
  215. /* check if we need to append */
  216. spin_lock_bh(&depend_tx->lock);
  217. if (depend_tx->parent) {
  218. intr_tx->parent = depend_tx;
  219. depend_tx->next = intr_tx;
  220. async_tx_ack(intr_tx);
  221. intr_tx = NULL;
  222. }
  223. spin_unlock_bh(&depend_tx->lock);
  224. if (intr_tx) {
  225. intr_tx->parent = NULL;
  226. intr_tx->tx_submit(intr_tx);
  227. async_tx_ack(intr_tx);
  228. }
  229. } else {
  230. if (dma_wait_for_async_tx(depend_tx) == DMA_ERROR)
  231. panic("%s: DMA_ERROR waiting for depend_tx\n",
  232. __func__);
  233. tx->tx_submit(tx);
  234. }
  235. }
  236. /**
  237. * submit_disposition - while holding depend_tx->lock we must avoid submitting
  238. * new operations to prevent a circular locking dependency with
  239. * drivers that already hold a channel lock when calling
  240. * async_tx_run_dependencies.
  241. * @ASYNC_TX_SUBMITTED: we were able to append the new operation under the lock
  242. * @ASYNC_TX_CHANNEL_SWITCH: when the lock is dropped schedule a channel switch
  243. * @ASYNC_TX_DIRECT_SUBMIT: when the lock is dropped submit directly
  244. */
  245. enum submit_disposition {
  246. ASYNC_TX_SUBMITTED,
  247. ASYNC_TX_CHANNEL_SWITCH,
  248. ASYNC_TX_DIRECT_SUBMIT,
  249. };
  250. void
  251. async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx,
  252. enum async_tx_flags flags, struct dma_async_tx_descriptor *depend_tx,
  253. dma_async_tx_callback cb_fn, void *cb_param)
  254. {
  255. tx->callback = cb_fn;
  256. tx->callback_param = cb_param;
  257. if (depend_tx) {
  258. enum submit_disposition s;
  259. /* sanity check the dependency chain:
  260. * 1/ if ack is already set then we cannot be sure
  261. * we are referring to the correct operation
  262. * 2/ dependencies are 1:1 i.e. two transactions can
  263. * not depend on the same parent
  264. */
  265. BUG_ON(async_tx_test_ack(depend_tx) || depend_tx->next ||
  266. tx->parent);
  267. /* the lock prevents async_tx_run_dependencies from missing
  268. * the setting of ->next when ->parent != NULL
  269. */
  270. spin_lock_bh(&depend_tx->lock);
  271. if (depend_tx->parent) {
  272. /* we have a parent so we can not submit directly
  273. * if we are staying on the same channel: append
  274. * else: channel switch
  275. */
  276. if (depend_tx->chan == chan) {
  277. tx->parent = depend_tx;
  278. depend_tx->next = tx;
  279. s = ASYNC_TX_SUBMITTED;
  280. } else
  281. s = ASYNC_TX_CHANNEL_SWITCH;
  282. } else {
  283. /* we do not have a parent so we may be able to submit
  284. * directly if we are staying on the same channel
  285. */
  286. if (depend_tx->chan == chan)
  287. s = ASYNC_TX_DIRECT_SUBMIT;
  288. else
  289. s = ASYNC_TX_CHANNEL_SWITCH;
  290. }
  291. spin_unlock_bh(&depend_tx->lock);
  292. switch (s) {
  293. case ASYNC_TX_SUBMITTED:
  294. break;
  295. case ASYNC_TX_CHANNEL_SWITCH:
  296. async_tx_channel_switch(depend_tx, tx);
  297. break;
  298. case ASYNC_TX_DIRECT_SUBMIT:
  299. tx->parent = NULL;
  300. tx->tx_submit(tx);
  301. break;
  302. }
  303. } else {
  304. tx->parent = NULL;
  305. tx->tx_submit(tx);
  306. }
  307. if (flags & ASYNC_TX_ACK)
  308. async_tx_ack(tx);
  309. if (depend_tx && (flags & ASYNC_TX_DEP_ACK))
  310. async_tx_ack(depend_tx);
  311. }
  312. EXPORT_SYMBOL_GPL(async_tx_submit);
  313. /**
  314. * async_trigger_callback - schedules the callback function to be run after
  315. * any dependent operations have been completed.
  316. * @flags: ASYNC_TX_ACK, ASYNC_TX_DEP_ACK
  317. * @depend_tx: 'callback' requires the completion of this transaction
  318. * @cb_fn: function to call after depend_tx completes
  319. * @cb_param: parameter to pass to the callback routine
  320. */
  321. struct dma_async_tx_descriptor *
  322. async_trigger_callback(enum async_tx_flags flags,
  323. struct dma_async_tx_descriptor *depend_tx,
  324. dma_async_tx_callback cb_fn, void *cb_param)
  325. {
  326. struct dma_chan *chan;
  327. struct dma_device *device;
  328. struct dma_async_tx_descriptor *tx;
  329. if (depend_tx) {
  330. chan = depend_tx->chan;
  331. device = chan->device;
  332. /* see if we can schedule an interrupt
  333. * otherwise poll for completion
  334. */
  335. if (device && !dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  336. device = NULL;
  337. tx = device ? device->device_prep_dma_interrupt(chan, 0) : NULL;
  338. } else
  339. tx = NULL;
  340. if (tx) {
  341. pr_debug("%s: (async)\n", __func__);
  342. async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param);
  343. } else {
  344. pr_debug("%s: (sync)\n", __func__);
  345. /* wait for any prerequisite operations */
  346. async_tx_quiesce(&depend_tx);
  347. async_tx_sync_epilog(cb_fn, cb_param);
  348. }
  349. return tx;
  350. }
  351. EXPORT_SYMBOL_GPL(async_trigger_callback);
  352. /**
  353. * async_tx_quiesce - ensure tx is complete and freeable upon return
  354. * @tx - transaction to quiesce
  355. */
  356. void async_tx_quiesce(struct dma_async_tx_descriptor **tx)
  357. {
  358. if (*tx) {
  359. /* if ack is already set then we cannot be sure
  360. * we are referring to the correct operation
  361. */
  362. BUG_ON(async_tx_test_ack(*tx));
  363. if (dma_wait_for_async_tx(*tx) == DMA_ERROR)
  364. panic("DMA_ERROR waiting for transaction\n");
  365. async_tx_ack(*tx);
  366. *tx = NULL;
  367. }
  368. }
  369. EXPORT_SYMBOL_GPL(async_tx_quiesce);
  370. module_init(async_tx_init);
  371. module_exit(async_tx_exit);
  372. MODULE_AUTHOR("Intel Corporation");
  373. MODULE_DESCRIPTION("Asynchronous Bulk Memory Transactions API");
  374. MODULE_LICENSE("GPL");