events.c 37 KB

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  1. /*
  2. * Xen event channels
  3. *
  4. * Xen models interrupts with abstract event channels. Because each
  5. * domain gets 1024 event channels, but NR_IRQ is not that large, we
  6. * must dynamically map irqs<->event channels. The event channels
  7. * interface with the rest of the kernel by defining a xen interrupt
  8. * chip. When an event is received, it is mapped to an irq and sent
  9. * through the normal interrupt processing path.
  10. *
  11. * There are four kinds of events which can be mapped to an event
  12. * channel:
  13. *
  14. * 1. Inter-domain notifications. This includes all the virtual
  15. * device events, since they're driven by front-ends in another domain
  16. * (typically dom0).
  17. * 2. VIRQs, typically used for timers. These are per-cpu events.
  18. * 3. IPIs.
  19. * 4. PIRQs - Hardware interrupts.
  20. *
  21. * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
  22. */
  23. #include <linux/linkage.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/irq.h>
  26. #include <linux/module.h>
  27. #include <linux/string.h>
  28. #include <linux/bootmem.h>
  29. #include <linux/slab.h>
  30. #include <linux/irqnr.h>
  31. #include <linux/pci.h>
  32. #include <asm/desc.h>
  33. #include <asm/ptrace.h>
  34. #include <asm/irq.h>
  35. #include <asm/idle.h>
  36. #include <asm/io_apic.h>
  37. #include <asm/sync_bitops.h>
  38. #include <asm/xen/pci.h>
  39. #include <asm/xen/hypercall.h>
  40. #include <asm/xen/hypervisor.h>
  41. #include <xen/xen.h>
  42. #include <xen/hvm.h>
  43. #include <xen/xen-ops.h>
  44. #include <xen/events.h>
  45. #include <xen/interface/xen.h>
  46. #include <xen/interface/event_channel.h>
  47. #include <xen/interface/hvm/hvm_op.h>
  48. #include <xen/interface/hvm/params.h>
  49. /*
  50. * This lock protects updates to the following mapping and reference-count
  51. * arrays. The lock does not need to be acquired to read the mapping tables.
  52. */
  53. static DEFINE_SPINLOCK(irq_mapping_update_lock);
  54. static LIST_HEAD(xen_irq_list_head);
  55. /* IRQ <-> VIRQ mapping. */
  56. static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
  57. /* IRQ <-> IPI mapping */
  58. static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
  59. /* Interrupt types. */
  60. enum xen_irq_type {
  61. IRQT_UNBOUND = 0,
  62. IRQT_PIRQ,
  63. IRQT_VIRQ,
  64. IRQT_IPI,
  65. IRQT_EVTCHN
  66. };
  67. /*
  68. * Packed IRQ information:
  69. * type - enum xen_irq_type
  70. * event channel - irq->event channel mapping
  71. * cpu - cpu this event channel is bound to
  72. * index - type-specific information:
  73. * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
  74. * guest, or GSI (real passthrough IRQ) of the device.
  75. * VIRQ - virq number
  76. * IPI - IPI vector
  77. * EVTCHN -
  78. */
  79. struct irq_info
  80. {
  81. struct list_head list;
  82. enum xen_irq_type type; /* type */
  83. unsigned irq;
  84. unsigned short evtchn; /* event channel */
  85. unsigned short cpu; /* cpu bound */
  86. union {
  87. unsigned short virq;
  88. enum ipi_vector ipi;
  89. struct {
  90. unsigned short pirq;
  91. unsigned short gsi;
  92. unsigned char vector;
  93. unsigned char flags;
  94. uint16_t domid;
  95. } pirq;
  96. } u;
  97. };
  98. #define PIRQ_NEEDS_EOI (1 << 0)
  99. #define PIRQ_SHAREABLE (1 << 1)
  100. static int *evtchn_to_irq;
  101. static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG],
  102. cpu_evtchn_mask);
  103. /* Xen will never allocate port zero for any purpose. */
  104. #define VALID_EVTCHN(chn) ((chn) != 0)
  105. static struct irq_chip xen_dynamic_chip;
  106. static struct irq_chip xen_percpu_chip;
  107. static struct irq_chip xen_pirq_chip;
  108. /* Get info for IRQ */
  109. static struct irq_info *info_for_irq(unsigned irq)
  110. {
  111. return irq_get_handler_data(irq);
  112. }
  113. /* Constructors for packed IRQ information. */
  114. static void xen_irq_info_common_init(struct irq_info *info,
  115. unsigned irq,
  116. enum xen_irq_type type,
  117. unsigned short evtchn,
  118. unsigned short cpu)
  119. {
  120. BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
  121. info->type = type;
  122. info->irq = irq;
  123. info->evtchn = evtchn;
  124. info->cpu = cpu;
  125. evtchn_to_irq[evtchn] = irq;
  126. }
  127. static void xen_irq_info_evtchn_init(unsigned irq,
  128. unsigned short evtchn)
  129. {
  130. struct irq_info *info = info_for_irq(irq);
  131. xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
  132. }
  133. static void xen_irq_info_ipi_init(unsigned cpu,
  134. unsigned irq,
  135. unsigned short evtchn,
  136. enum ipi_vector ipi)
  137. {
  138. struct irq_info *info = info_for_irq(irq);
  139. xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
  140. info->u.ipi = ipi;
  141. per_cpu(ipi_to_irq, cpu)[ipi] = irq;
  142. }
  143. static void xen_irq_info_virq_init(unsigned cpu,
  144. unsigned irq,
  145. unsigned short evtchn,
  146. unsigned short virq)
  147. {
  148. struct irq_info *info = info_for_irq(irq);
  149. xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
  150. info->u.virq = virq;
  151. per_cpu(virq_to_irq, cpu)[virq] = irq;
  152. }
  153. static void xen_irq_info_pirq_init(unsigned irq,
  154. unsigned short evtchn,
  155. unsigned short pirq,
  156. unsigned short gsi,
  157. unsigned short vector,
  158. uint16_t domid,
  159. unsigned char flags)
  160. {
  161. struct irq_info *info = info_for_irq(irq);
  162. xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
  163. info->u.pirq.pirq = pirq;
  164. info->u.pirq.gsi = gsi;
  165. info->u.pirq.vector = vector;
  166. info->u.pirq.domid = domid;
  167. info->u.pirq.flags = flags;
  168. }
  169. /*
  170. * Accessors for packed IRQ information.
  171. */
  172. static unsigned int evtchn_from_irq(unsigned irq)
  173. {
  174. if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
  175. return 0;
  176. return info_for_irq(irq)->evtchn;
  177. }
  178. unsigned irq_from_evtchn(unsigned int evtchn)
  179. {
  180. return evtchn_to_irq[evtchn];
  181. }
  182. EXPORT_SYMBOL_GPL(irq_from_evtchn);
  183. static enum ipi_vector ipi_from_irq(unsigned irq)
  184. {
  185. struct irq_info *info = info_for_irq(irq);
  186. BUG_ON(info == NULL);
  187. BUG_ON(info->type != IRQT_IPI);
  188. return info->u.ipi;
  189. }
  190. static unsigned virq_from_irq(unsigned irq)
  191. {
  192. struct irq_info *info = info_for_irq(irq);
  193. BUG_ON(info == NULL);
  194. BUG_ON(info->type != IRQT_VIRQ);
  195. return info->u.virq;
  196. }
  197. static unsigned pirq_from_irq(unsigned irq)
  198. {
  199. struct irq_info *info = info_for_irq(irq);
  200. BUG_ON(info == NULL);
  201. BUG_ON(info->type != IRQT_PIRQ);
  202. return info->u.pirq.pirq;
  203. }
  204. static enum xen_irq_type type_from_irq(unsigned irq)
  205. {
  206. return info_for_irq(irq)->type;
  207. }
  208. static unsigned cpu_from_irq(unsigned irq)
  209. {
  210. return info_for_irq(irq)->cpu;
  211. }
  212. static unsigned int cpu_from_evtchn(unsigned int evtchn)
  213. {
  214. int irq = evtchn_to_irq[evtchn];
  215. unsigned ret = 0;
  216. if (irq != -1)
  217. ret = cpu_from_irq(irq);
  218. return ret;
  219. }
  220. static bool pirq_needs_eoi(unsigned irq)
  221. {
  222. struct irq_info *info = info_for_irq(irq);
  223. BUG_ON(info->type != IRQT_PIRQ);
  224. return info->u.pirq.flags & PIRQ_NEEDS_EOI;
  225. }
  226. static inline unsigned long active_evtchns(unsigned int cpu,
  227. struct shared_info *sh,
  228. unsigned int idx)
  229. {
  230. return (sh->evtchn_pending[idx] &
  231. per_cpu(cpu_evtchn_mask, cpu)[idx] &
  232. ~sh->evtchn_mask[idx]);
  233. }
  234. static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
  235. {
  236. int irq = evtchn_to_irq[chn];
  237. BUG_ON(irq == -1);
  238. #ifdef CONFIG_SMP
  239. cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
  240. #endif
  241. clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq)));
  242. set_bit(chn, per_cpu(cpu_evtchn_mask, cpu));
  243. info_for_irq(irq)->cpu = cpu;
  244. }
  245. static void init_evtchn_cpu_bindings(void)
  246. {
  247. int i;
  248. #ifdef CONFIG_SMP
  249. struct irq_info *info;
  250. /* By default all event channels notify CPU#0. */
  251. list_for_each_entry(info, &xen_irq_list_head, list) {
  252. struct irq_desc *desc = irq_to_desc(info->irq);
  253. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  254. }
  255. #endif
  256. for_each_possible_cpu(i)
  257. memset(per_cpu(cpu_evtchn_mask, i),
  258. (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
  259. }
  260. static inline void clear_evtchn(int port)
  261. {
  262. struct shared_info *s = HYPERVISOR_shared_info;
  263. sync_clear_bit(port, &s->evtchn_pending[0]);
  264. }
  265. static inline void set_evtchn(int port)
  266. {
  267. struct shared_info *s = HYPERVISOR_shared_info;
  268. sync_set_bit(port, &s->evtchn_pending[0]);
  269. }
  270. static inline int test_evtchn(int port)
  271. {
  272. struct shared_info *s = HYPERVISOR_shared_info;
  273. return sync_test_bit(port, &s->evtchn_pending[0]);
  274. }
  275. /**
  276. * notify_remote_via_irq - send event to remote end of event channel via irq
  277. * @irq: irq of event channel to send event to
  278. *
  279. * Unlike notify_remote_via_evtchn(), this is safe to use across
  280. * save/restore. Notifications on a broken connection are silently
  281. * dropped.
  282. */
  283. void notify_remote_via_irq(int irq)
  284. {
  285. int evtchn = evtchn_from_irq(irq);
  286. if (VALID_EVTCHN(evtchn))
  287. notify_remote_via_evtchn(evtchn);
  288. }
  289. EXPORT_SYMBOL_GPL(notify_remote_via_irq);
  290. static void mask_evtchn(int port)
  291. {
  292. struct shared_info *s = HYPERVISOR_shared_info;
  293. sync_set_bit(port, &s->evtchn_mask[0]);
  294. }
  295. static void unmask_evtchn(int port)
  296. {
  297. struct shared_info *s = HYPERVISOR_shared_info;
  298. unsigned int cpu = get_cpu();
  299. BUG_ON(!irqs_disabled());
  300. /* Slow path (hypercall) if this is a non-local port. */
  301. if (unlikely(cpu != cpu_from_evtchn(port))) {
  302. struct evtchn_unmask unmask = { .port = port };
  303. (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
  304. } else {
  305. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  306. sync_clear_bit(port, &s->evtchn_mask[0]);
  307. /*
  308. * The following is basically the equivalent of
  309. * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
  310. * the interrupt edge' if the channel is masked.
  311. */
  312. if (sync_test_bit(port, &s->evtchn_pending[0]) &&
  313. !sync_test_and_set_bit(port / BITS_PER_LONG,
  314. &vcpu_info->evtchn_pending_sel))
  315. vcpu_info->evtchn_upcall_pending = 1;
  316. }
  317. put_cpu();
  318. }
  319. static void xen_irq_init(unsigned irq)
  320. {
  321. struct irq_info *info;
  322. struct irq_desc *desc = irq_to_desc(irq);
  323. #ifdef CONFIG_SMP
  324. /* By default all event channels notify CPU#0. */
  325. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  326. #endif
  327. info = kzalloc(sizeof(*info), GFP_KERNEL);
  328. if (info == NULL)
  329. panic("Unable to allocate metadata for IRQ%d\n", irq);
  330. info->type = IRQT_UNBOUND;
  331. irq_set_handler_data(irq, info);
  332. list_add_tail(&info->list, &xen_irq_list_head);
  333. }
  334. static int __must_check xen_allocate_irq_dynamic(void)
  335. {
  336. int first = 0;
  337. int irq;
  338. #ifdef CONFIG_X86_IO_APIC
  339. /*
  340. * For an HVM guest or domain 0 which see "real" (emulated or
  341. * actual respectively) GSIs we allocate dynamic IRQs
  342. * e.g. those corresponding to event channels or MSIs
  343. * etc. from the range above those "real" GSIs to avoid
  344. * collisions.
  345. */
  346. if (xen_initial_domain() || xen_hvm_domain())
  347. first = get_nr_irqs_gsi();
  348. #endif
  349. irq = irq_alloc_desc_from(first, -1);
  350. xen_irq_init(irq);
  351. return irq;
  352. }
  353. static int __must_check xen_allocate_irq_gsi(unsigned gsi)
  354. {
  355. int irq;
  356. /*
  357. * A PV guest has no concept of a GSI (since it has no ACPI
  358. * nor access to/knowledge of the physical APICs). Therefore
  359. * all IRQs are dynamically allocated from the entire IRQ
  360. * space.
  361. */
  362. if (xen_pv_domain() && !xen_initial_domain())
  363. return xen_allocate_irq_dynamic();
  364. /* Legacy IRQ descriptors are already allocated by the arch. */
  365. if (gsi < NR_IRQS_LEGACY)
  366. irq = gsi;
  367. else
  368. irq = irq_alloc_desc_at(gsi, -1);
  369. xen_irq_init(irq);
  370. return irq;
  371. }
  372. static void xen_free_irq(unsigned irq)
  373. {
  374. struct irq_info *info = irq_get_handler_data(irq);
  375. list_del(&info->list);
  376. irq_set_handler_data(irq, NULL);
  377. kfree(info);
  378. /* Legacy IRQ descriptors are managed by the arch. */
  379. if (irq < NR_IRQS_LEGACY)
  380. return;
  381. irq_free_desc(irq);
  382. }
  383. static void pirq_unmask_notify(int irq)
  384. {
  385. struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
  386. if (unlikely(pirq_needs_eoi(irq))) {
  387. int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
  388. WARN_ON(rc);
  389. }
  390. }
  391. static void pirq_query_unmask(int irq)
  392. {
  393. struct physdev_irq_status_query irq_status;
  394. struct irq_info *info = info_for_irq(irq);
  395. BUG_ON(info->type != IRQT_PIRQ);
  396. irq_status.irq = pirq_from_irq(irq);
  397. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  398. irq_status.flags = 0;
  399. info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
  400. if (irq_status.flags & XENIRQSTAT_needs_eoi)
  401. info->u.pirq.flags |= PIRQ_NEEDS_EOI;
  402. }
  403. static bool probing_irq(int irq)
  404. {
  405. struct irq_desc *desc = irq_to_desc(irq);
  406. return desc && desc->action == NULL;
  407. }
  408. static unsigned int __startup_pirq(unsigned int irq)
  409. {
  410. struct evtchn_bind_pirq bind_pirq;
  411. struct irq_info *info = info_for_irq(irq);
  412. int evtchn = evtchn_from_irq(irq);
  413. int rc;
  414. BUG_ON(info->type != IRQT_PIRQ);
  415. if (VALID_EVTCHN(evtchn))
  416. goto out;
  417. bind_pirq.pirq = pirq_from_irq(irq);
  418. /* NB. We are happy to share unless we are probing. */
  419. bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
  420. BIND_PIRQ__WILL_SHARE : 0;
  421. rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
  422. if (rc != 0) {
  423. if (!probing_irq(irq))
  424. printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
  425. irq);
  426. return 0;
  427. }
  428. evtchn = bind_pirq.port;
  429. pirq_query_unmask(irq);
  430. evtchn_to_irq[evtchn] = irq;
  431. bind_evtchn_to_cpu(evtchn, 0);
  432. info->evtchn = evtchn;
  433. out:
  434. unmask_evtchn(evtchn);
  435. pirq_unmask_notify(irq);
  436. return 0;
  437. }
  438. static unsigned int startup_pirq(struct irq_data *data)
  439. {
  440. return __startup_pirq(data->irq);
  441. }
  442. static void shutdown_pirq(struct irq_data *data)
  443. {
  444. struct evtchn_close close;
  445. unsigned int irq = data->irq;
  446. struct irq_info *info = info_for_irq(irq);
  447. int evtchn = evtchn_from_irq(irq);
  448. BUG_ON(info->type != IRQT_PIRQ);
  449. if (!VALID_EVTCHN(evtchn))
  450. return;
  451. mask_evtchn(evtchn);
  452. close.port = evtchn;
  453. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  454. BUG();
  455. bind_evtchn_to_cpu(evtchn, 0);
  456. evtchn_to_irq[evtchn] = -1;
  457. info->evtchn = 0;
  458. }
  459. static void enable_pirq(struct irq_data *data)
  460. {
  461. startup_pirq(data);
  462. }
  463. static void disable_pirq(struct irq_data *data)
  464. {
  465. }
  466. static void ack_pirq(struct irq_data *data)
  467. {
  468. int evtchn = evtchn_from_irq(data->irq);
  469. irq_move_irq(data);
  470. if (VALID_EVTCHN(evtchn)) {
  471. mask_evtchn(evtchn);
  472. clear_evtchn(evtchn);
  473. }
  474. }
  475. static int find_irq_by_gsi(unsigned gsi)
  476. {
  477. struct irq_info *info;
  478. list_for_each_entry(info, &xen_irq_list_head, list) {
  479. if (info->type != IRQT_PIRQ)
  480. continue;
  481. if (info->u.pirq.gsi == gsi)
  482. return info->irq;
  483. }
  484. return -1;
  485. }
  486. int xen_allocate_pirq_gsi(unsigned gsi)
  487. {
  488. return gsi;
  489. }
  490. /*
  491. * Do not make any assumptions regarding the relationship between the
  492. * IRQ number returned here and the Xen pirq argument.
  493. *
  494. * Note: We don't assign an event channel until the irq actually started
  495. * up. Return an existing irq if we've already got one for the gsi.
  496. */
  497. int xen_bind_pirq_gsi_to_irq(unsigned gsi,
  498. unsigned pirq, int shareable, char *name)
  499. {
  500. int irq = -1;
  501. struct physdev_irq irq_op;
  502. spin_lock(&irq_mapping_update_lock);
  503. irq = find_irq_by_gsi(gsi);
  504. if (irq != -1) {
  505. printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
  506. irq, gsi);
  507. goto out; /* XXX need refcount? */
  508. }
  509. irq = xen_allocate_irq_gsi(gsi);
  510. if (irq < 0)
  511. goto out;
  512. irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_level_irq,
  513. name);
  514. irq_op.irq = irq;
  515. irq_op.vector = 0;
  516. /* Only the privileged domain can do this. For non-priv, the pcifront
  517. * driver provides a PCI bus that does the call to do exactly
  518. * this in the priv domain. */
  519. if (xen_initial_domain() &&
  520. HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
  521. xen_free_irq(irq);
  522. irq = -ENOSPC;
  523. goto out;
  524. }
  525. xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector, DOMID_SELF,
  526. shareable ? PIRQ_SHAREABLE : 0);
  527. out:
  528. spin_unlock(&irq_mapping_update_lock);
  529. return irq;
  530. }
  531. #ifdef CONFIG_PCI_MSI
  532. int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
  533. {
  534. int rc;
  535. struct physdev_get_free_pirq op_get_free_pirq;
  536. op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
  537. rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
  538. WARN_ONCE(rc == -ENOSYS,
  539. "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
  540. return rc ? -1 : op_get_free_pirq.pirq;
  541. }
  542. int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
  543. int pirq, int vector, const char *name,
  544. domid_t domid)
  545. {
  546. int irq, ret;
  547. spin_lock(&irq_mapping_update_lock);
  548. irq = xen_allocate_irq_dynamic();
  549. if (irq == -1)
  550. goto out;
  551. irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_level_irq,
  552. name);
  553. xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, domid, 0);
  554. ret = irq_set_msi_desc(irq, msidesc);
  555. if (ret < 0)
  556. goto error_irq;
  557. out:
  558. spin_unlock(&irq_mapping_update_lock);
  559. return irq;
  560. error_irq:
  561. spin_unlock(&irq_mapping_update_lock);
  562. xen_free_irq(irq);
  563. return -1;
  564. }
  565. #endif
  566. int xen_destroy_irq(int irq)
  567. {
  568. struct irq_desc *desc;
  569. struct physdev_unmap_pirq unmap_irq;
  570. struct irq_info *info = info_for_irq(irq);
  571. int rc = -ENOENT;
  572. spin_lock(&irq_mapping_update_lock);
  573. desc = irq_to_desc(irq);
  574. if (!desc)
  575. goto out;
  576. if (xen_initial_domain()) {
  577. unmap_irq.pirq = info->u.pirq.pirq;
  578. unmap_irq.domid = info->u.pirq.domid;
  579. rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
  580. if (rc) {
  581. printk(KERN_WARNING "unmap irq failed %d\n", rc);
  582. goto out;
  583. }
  584. }
  585. xen_free_irq(irq);
  586. out:
  587. spin_unlock(&irq_mapping_update_lock);
  588. return rc;
  589. }
  590. int xen_irq_from_pirq(unsigned pirq)
  591. {
  592. int irq;
  593. struct irq_info *info;
  594. spin_lock(&irq_mapping_update_lock);
  595. list_for_each_entry(info, &xen_irq_list_head, list) {
  596. if (info == NULL || info->type != IRQT_PIRQ)
  597. continue;
  598. irq = info->irq;
  599. if (info->u.pirq.pirq == pirq)
  600. goto out;
  601. }
  602. irq = -1;
  603. out:
  604. spin_unlock(&irq_mapping_update_lock);
  605. return irq;
  606. }
  607. int bind_evtchn_to_irq(unsigned int evtchn)
  608. {
  609. int irq;
  610. spin_lock(&irq_mapping_update_lock);
  611. irq = evtchn_to_irq[evtchn];
  612. if (irq == -1) {
  613. irq = xen_allocate_irq_dynamic();
  614. if (irq == -1)
  615. goto out;
  616. irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
  617. handle_fasteoi_irq, "event");
  618. xen_irq_info_evtchn_init(irq, evtchn);
  619. }
  620. out:
  621. spin_unlock(&irq_mapping_update_lock);
  622. return irq;
  623. }
  624. EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
  625. static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
  626. {
  627. struct evtchn_bind_ipi bind_ipi;
  628. int evtchn, irq;
  629. spin_lock(&irq_mapping_update_lock);
  630. irq = per_cpu(ipi_to_irq, cpu)[ipi];
  631. if (irq == -1) {
  632. irq = xen_allocate_irq_dynamic();
  633. if (irq < 0)
  634. goto out;
  635. irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
  636. handle_percpu_irq, "ipi");
  637. bind_ipi.vcpu = cpu;
  638. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  639. &bind_ipi) != 0)
  640. BUG();
  641. evtchn = bind_ipi.port;
  642. xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
  643. bind_evtchn_to_cpu(evtchn, cpu);
  644. }
  645. out:
  646. spin_unlock(&irq_mapping_update_lock);
  647. return irq;
  648. }
  649. static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
  650. unsigned int remote_port)
  651. {
  652. struct evtchn_bind_interdomain bind_interdomain;
  653. int err;
  654. bind_interdomain.remote_dom = remote_domain;
  655. bind_interdomain.remote_port = remote_port;
  656. err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
  657. &bind_interdomain);
  658. return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
  659. }
  660. int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
  661. {
  662. struct evtchn_bind_virq bind_virq;
  663. int evtchn, irq;
  664. spin_lock(&irq_mapping_update_lock);
  665. irq = per_cpu(virq_to_irq, cpu)[virq];
  666. if (irq == -1) {
  667. irq = xen_allocate_irq_dynamic();
  668. if (irq == -1)
  669. goto out;
  670. irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
  671. handle_percpu_irq, "virq");
  672. bind_virq.virq = virq;
  673. bind_virq.vcpu = cpu;
  674. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  675. &bind_virq) != 0)
  676. BUG();
  677. evtchn = bind_virq.port;
  678. xen_irq_info_virq_init(cpu, irq, evtchn, virq);
  679. bind_evtchn_to_cpu(evtchn, cpu);
  680. }
  681. out:
  682. spin_unlock(&irq_mapping_update_lock);
  683. return irq;
  684. }
  685. static void unbind_from_irq(unsigned int irq)
  686. {
  687. struct evtchn_close close;
  688. int evtchn = evtchn_from_irq(irq);
  689. spin_lock(&irq_mapping_update_lock);
  690. if (VALID_EVTCHN(evtchn)) {
  691. close.port = evtchn;
  692. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  693. BUG();
  694. switch (type_from_irq(irq)) {
  695. case IRQT_VIRQ:
  696. per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
  697. [virq_from_irq(irq)] = -1;
  698. break;
  699. case IRQT_IPI:
  700. per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
  701. [ipi_from_irq(irq)] = -1;
  702. break;
  703. default:
  704. break;
  705. }
  706. /* Closed ports are implicitly re-bound to VCPU0. */
  707. bind_evtchn_to_cpu(evtchn, 0);
  708. evtchn_to_irq[evtchn] = -1;
  709. }
  710. BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
  711. xen_free_irq(irq);
  712. spin_unlock(&irq_mapping_update_lock);
  713. }
  714. int bind_evtchn_to_irqhandler(unsigned int evtchn,
  715. irq_handler_t handler,
  716. unsigned long irqflags,
  717. const char *devname, void *dev_id)
  718. {
  719. unsigned int irq;
  720. int retval;
  721. irq = bind_evtchn_to_irq(evtchn);
  722. if (irq < 0)
  723. return irq;
  724. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  725. if (retval != 0) {
  726. unbind_from_irq(irq);
  727. return retval;
  728. }
  729. return irq;
  730. }
  731. EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
  732. int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
  733. unsigned int remote_port,
  734. irq_handler_t handler,
  735. unsigned long irqflags,
  736. const char *devname,
  737. void *dev_id)
  738. {
  739. int irq, retval;
  740. irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
  741. if (irq < 0)
  742. return irq;
  743. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  744. if (retval != 0) {
  745. unbind_from_irq(irq);
  746. return retval;
  747. }
  748. return irq;
  749. }
  750. EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
  751. int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
  752. irq_handler_t handler,
  753. unsigned long irqflags, const char *devname, void *dev_id)
  754. {
  755. unsigned int irq;
  756. int retval;
  757. irq = bind_virq_to_irq(virq, cpu);
  758. if (irq < 0)
  759. return irq;
  760. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  761. if (retval != 0) {
  762. unbind_from_irq(irq);
  763. return retval;
  764. }
  765. return irq;
  766. }
  767. EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
  768. int bind_ipi_to_irqhandler(enum ipi_vector ipi,
  769. unsigned int cpu,
  770. irq_handler_t handler,
  771. unsigned long irqflags,
  772. const char *devname,
  773. void *dev_id)
  774. {
  775. int irq, retval;
  776. irq = bind_ipi_to_irq(ipi, cpu);
  777. if (irq < 0)
  778. return irq;
  779. irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME;
  780. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  781. if (retval != 0) {
  782. unbind_from_irq(irq);
  783. return retval;
  784. }
  785. return irq;
  786. }
  787. void unbind_from_irqhandler(unsigned int irq, void *dev_id)
  788. {
  789. free_irq(irq, dev_id);
  790. unbind_from_irq(irq);
  791. }
  792. EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
  793. void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
  794. {
  795. int irq = per_cpu(ipi_to_irq, cpu)[vector];
  796. BUG_ON(irq < 0);
  797. notify_remote_via_irq(irq);
  798. }
  799. irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
  800. {
  801. struct shared_info *sh = HYPERVISOR_shared_info;
  802. int cpu = smp_processor_id();
  803. unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
  804. int i;
  805. unsigned long flags;
  806. static DEFINE_SPINLOCK(debug_lock);
  807. struct vcpu_info *v;
  808. spin_lock_irqsave(&debug_lock, flags);
  809. printk("\nvcpu %d\n ", cpu);
  810. for_each_online_cpu(i) {
  811. int pending;
  812. v = per_cpu(xen_vcpu, i);
  813. pending = (get_irq_regs() && i == cpu)
  814. ? xen_irqs_disabled(get_irq_regs())
  815. : v->evtchn_upcall_mask;
  816. printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
  817. pending, v->evtchn_upcall_pending,
  818. (int)(sizeof(v->evtchn_pending_sel)*2),
  819. v->evtchn_pending_sel);
  820. }
  821. v = per_cpu(xen_vcpu, cpu);
  822. printk("\npending:\n ");
  823. for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
  824. printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
  825. sh->evtchn_pending[i],
  826. i % 8 == 0 ? "\n " : " ");
  827. printk("\nglobal mask:\n ");
  828. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  829. printk("%0*lx%s",
  830. (int)(sizeof(sh->evtchn_mask[0])*2),
  831. sh->evtchn_mask[i],
  832. i % 8 == 0 ? "\n " : " ");
  833. printk("\nglobally unmasked:\n ");
  834. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  835. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  836. sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
  837. i % 8 == 0 ? "\n " : " ");
  838. printk("\nlocal cpu%d mask:\n ", cpu);
  839. for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
  840. printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
  841. cpu_evtchn[i],
  842. i % 8 == 0 ? "\n " : " ");
  843. printk("\nlocally unmasked:\n ");
  844. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
  845. unsigned long pending = sh->evtchn_pending[i]
  846. & ~sh->evtchn_mask[i]
  847. & cpu_evtchn[i];
  848. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  849. pending, i % 8 == 0 ? "\n " : " ");
  850. }
  851. printk("\npending list:\n");
  852. for (i = 0; i < NR_EVENT_CHANNELS; i++) {
  853. if (sync_test_bit(i, sh->evtchn_pending)) {
  854. int word_idx = i / BITS_PER_LONG;
  855. printk(" %d: event %d -> irq %d%s%s%s\n",
  856. cpu_from_evtchn(i), i,
  857. evtchn_to_irq[i],
  858. sync_test_bit(word_idx, &v->evtchn_pending_sel)
  859. ? "" : " l2-clear",
  860. !sync_test_bit(i, sh->evtchn_mask)
  861. ? "" : " globally-masked",
  862. sync_test_bit(i, cpu_evtchn)
  863. ? "" : " locally-masked");
  864. }
  865. }
  866. spin_unlock_irqrestore(&debug_lock, flags);
  867. return IRQ_HANDLED;
  868. }
  869. static DEFINE_PER_CPU(unsigned, xed_nesting_count);
  870. static DEFINE_PER_CPU(unsigned int, current_word_idx);
  871. static DEFINE_PER_CPU(unsigned int, current_bit_idx);
  872. /*
  873. * Mask out the i least significant bits of w
  874. */
  875. #define MASK_LSBS(w, i) (w & ((~0UL) << i))
  876. /*
  877. * Search the CPUs pending events bitmasks. For each one found, map
  878. * the event number to an irq, and feed it into do_IRQ() for
  879. * handling.
  880. *
  881. * Xen uses a two-level bitmap to speed searching. The first level is
  882. * a bitset of words which contain pending event bits. The second
  883. * level is a bitset of pending events themselves.
  884. */
  885. static void __xen_evtchn_do_upcall(void)
  886. {
  887. int start_word_idx, start_bit_idx;
  888. int word_idx, bit_idx;
  889. int i;
  890. int cpu = get_cpu();
  891. struct shared_info *s = HYPERVISOR_shared_info;
  892. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  893. unsigned count;
  894. do {
  895. unsigned long pending_words;
  896. vcpu_info->evtchn_upcall_pending = 0;
  897. if (__this_cpu_inc_return(xed_nesting_count) - 1)
  898. goto out;
  899. #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
  900. /* Clear master flag /before/ clearing selector flag. */
  901. wmb();
  902. #endif
  903. pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
  904. start_word_idx = __this_cpu_read(current_word_idx);
  905. start_bit_idx = __this_cpu_read(current_bit_idx);
  906. word_idx = start_word_idx;
  907. for (i = 0; pending_words != 0; i++) {
  908. unsigned long pending_bits;
  909. unsigned long words;
  910. words = MASK_LSBS(pending_words, word_idx);
  911. /*
  912. * If we masked out all events, wrap to beginning.
  913. */
  914. if (words == 0) {
  915. word_idx = 0;
  916. bit_idx = 0;
  917. continue;
  918. }
  919. word_idx = __ffs(words);
  920. pending_bits = active_evtchns(cpu, s, word_idx);
  921. bit_idx = 0; /* usually scan entire word from start */
  922. if (word_idx == start_word_idx) {
  923. /* We scan the starting word in two parts */
  924. if (i == 0)
  925. /* 1st time: start in the middle */
  926. bit_idx = start_bit_idx;
  927. else
  928. /* 2nd time: mask bits done already */
  929. bit_idx &= (1UL << start_bit_idx) - 1;
  930. }
  931. do {
  932. unsigned long bits;
  933. int port, irq;
  934. struct irq_desc *desc;
  935. bits = MASK_LSBS(pending_bits, bit_idx);
  936. /* If we masked out all events, move on. */
  937. if (bits == 0)
  938. break;
  939. bit_idx = __ffs(bits);
  940. /* Process port. */
  941. port = (word_idx * BITS_PER_LONG) + bit_idx;
  942. irq = evtchn_to_irq[port];
  943. mask_evtchn(port);
  944. clear_evtchn(port);
  945. if (irq != -1) {
  946. desc = irq_to_desc(irq);
  947. if (desc)
  948. generic_handle_irq_desc(irq, desc);
  949. }
  950. bit_idx = (bit_idx + 1) % BITS_PER_LONG;
  951. /* Next caller starts at last processed + 1 */
  952. __this_cpu_write(current_word_idx,
  953. bit_idx ? word_idx :
  954. (word_idx+1) % BITS_PER_LONG);
  955. __this_cpu_write(current_bit_idx, bit_idx);
  956. } while (bit_idx != 0);
  957. /* Scan start_l1i twice; all others once. */
  958. if ((word_idx != start_word_idx) || (i != 0))
  959. pending_words &= ~(1UL << word_idx);
  960. word_idx = (word_idx + 1) % BITS_PER_LONG;
  961. }
  962. BUG_ON(!irqs_disabled());
  963. count = __this_cpu_read(xed_nesting_count);
  964. __this_cpu_write(xed_nesting_count, 0);
  965. } while (count != 1 || vcpu_info->evtchn_upcall_pending);
  966. out:
  967. put_cpu();
  968. }
  969. void xen_evtchn_do_upcall(struct pt_regs *regs)
  970. {
  971. struct pt_regs *old_regs = set_irq_regs(regs);
  972. exit_idle();
  973. irq_enter();
  974. __xen_evtchn_do_upcall();
  975. irq_exit();
  976. set_irq_regs(old_regs);
  977. }
  978. void xen_hvm_evtchn_do_upcall(void)
  979. {
  980. __xen_evtchn_do_upcall();
  981. }
  982. EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
  983. /* Rebind a new event channel to an existing irq. */
  984. void rebind_evtchn_irq(int evtchn, int irq)
  985. {
  986. struct irq_info *info = info_for_irq(irq);
  987. /* Make sure the irq is masked, since the new event channel
  988. will also be masked. */
  989. disable_irq(irq);
  990. spin_lock(&irq_mapping_update_lock);
  991. /* After resume the irq<->evtchn mappings are all cleared out */
  992. BUG_ON(evtchn_to_irq[evtchn] != -1);
  993. /* Expect irq to have been bound before,
  994. so there should be a proper type */
  995. BUG_ON(info->type == IRQT_UNBOUND);
  996. xen_irq_info_evtchn_init(irq, evtchn);
  997. spin_unlock(&irq_mapping_update_lock);
  998. /* new event channels are always bound to cpu 0 */
  999. irq_set_affinity(irq, cpumask_of(0));
  1000. /* Unmask the event channel. */
  1001. enable_irq(irq);
  1002. }
  1003. /* Rebind an evtchn so that it gets delivered to a specific cpu */
  1004. static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
  1005. {
  1006. struct evtchn_bind_vcpu bind_vcpu;
  1007. int evtchn = evtchn_from_irq(irq);
  1008. if (!VALID_EVTCHN(evtchn))
  1009. return -1;
  1010. /*
  1011. * Events delivered via platform PCI interrupts are always
  1012. * routed to vcpu 0 and hence cannot be rebound.
  1013. */
  1014. if (xen_hvm_domain() && !xen_have_vector_callback)
  1015. return -1;
  1016. /* Send future instances of this interrupt to other vcpu. */
  1017. bind_vcpu.port = evtchn;
  1018. bind_vcpu.vcpu = tcpu;
  1019. /*
  1020. * If this fails, it usually just indicates that we're dealing with a
  1021. * virq or IPI channel, which don't actually need to be rebound. Ignore
  1022. * it, but don't do the xenlinux-level rebind in that case.
  1023. */
  1024. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
  1025. bind_evtchn_to_cpu(evtchn, tcpu);
  1026. return 0;
  1027. }
  1028. static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
  1029. bool force)
  1030. {
  1031. unsigned tcpu = cpumask_first(dest);
  1032. return rebind_irq_to_cpu(data->irq, tcpu);
  1033. }
  1034. int resend_irq_on_evtchn(unsigned int irq)
  1035. {
  1036. int masked, evtchn = evtchn_from_irq(irq);
  1037. struct shared_info *s = HYPERVISOR_shared_info;
  1038. if (!VALID_EVTCHN(evtchn))
  1039. return 1;
  1040. masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
  1041. sync_set_bit(evtchn, s->evtchn_pending);
  1042. if (!masked)
  1043. unmask_evtchn(evtchn);
  1044. return 1;
  1045. }
  1046. static void enable_dynirq(struct irq_data *data)
  1047. {
  1048. int evtchn = evtchn_from_irq(data->irq);
  1049. if (VALID_EVTCHN(evtchn))
  1050. unmask_evtchn(evtchn);
  1051. }
  1052. static void disable_dynirq(struct irq_data *data)
  1053. {
  1054. int evtchn = evtchn_from_irq(data->irq);
  1055. if (VALID_EVTCHN(evtchn))
  1056. mask_evtchn(evtchn);
  1057. }
  1058. static void ack_dynirq(struct irq_data *data)
  1059. {
  1060. int evtchn = evtchn_from_irq(data->irq);
  1061. irq_move_masked_irq(data);
  1062. if (VALID_EVTCHN(evtchn))
  1063. unmask_evtchn(evtchn);
  1064. }
  1065. static int retrigger_dynirq(struct irq_data *data)
  1066. {
  1067. int evtchn = evtchn_from_irq(data->irq);
  1068. struct shared_info *sh = HYPERVISOR_shared_info;
  1069. int ret = 0;
  1070. if (VALID_EVTCHN(evtchn)) {
  1071. int masked;
  1072. masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
  1073. sync_set_bit(evtchn, sh->evtchn_pending);
  1074. if (!masked)
  1075. unmask_evtchn(evtchn);
  1076. ret = 1;
  1077. }
  1078. return ret;
  1079. }
  1080. static void restore_pirqs(void)
  1081. {
  1082. int pirq, rc, irq, gsi;
  1083. struct physdev_map_pirq map_irq;
  1084. struct irq_info *info;
  1085. list_for_each_entry(info, &xen_irq_list_head, list) {
  1086. if (info->type != IRQT_PIRQ)
  1087. continue;
  1088. pirq = info->u.pirq.pirq;
  1089. gsi = info->u.pirq.gsi;
  1090. irq = info->irq;
  1091. /* save/restore of PT devices doesn't work, so at this point the
  1092. * only devices present are GSI based emulated devices */
  1093. if (!gsi)
  1094. continue;
  1095. map_irq.domid = DOMID_SELF;
  1096. map_irq.type = MAP_PIRQ_TYPE_GSI;
  1097. map_irq.index = gsi;
  1098. map_irq.pirq = pirq;
  1099. rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
  1100. if (rc) {
  1101. printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
  1102. gsi, irq, pirq, rc);
  1103. xen_free_irq(irq);
  1104. continue;
  1105. }
  1106. printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
  1107. __startup_pirq(irq);
  1108. }
  1109. }
  1110. static void restore_cpu_virqs(unsigned int cpu)
  1111. {
  1112. struct evtchn_bind_virq bind_virq;
  1113. int virq, irq, evtchn;
  1114. for (virq = 0; virq < NR_VIRQS; virq++) {
  1115. if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
  1116. continue;
  1117. BUG_ON(virq_from_irq(irq) != virq);
  1118. /* Get a new binding from Xen. */
  1119. bind_virq.virq = virq;
  1120. bind_virq.vcpu = cpu;
  1121. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  1122. &bind_virq) != 0)
  1123. BUG();
  1124. evtchn = bind_virq.port;
  1125. /* Record the new mapping. */
  1126. xen_irq_info_virq_init(cpu, irq, evtchn, virq);
  1127. bind_evtchn_to_cpu(evtchn, cpu);
  1128. }
  1129. }
  1130. static void restore_cpu_ipis(unsigned int cpu)
  1131. {
  1132. struct evtchn_bind_ipi bind_ipi;
  1133. int ipi, irq, evtchn;
  1134. for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
  1135. if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
  1136. continue;
  1137. BUG_ON(ipi_from_irq(irq) != ipi);
  1138. /* Get a new binding from Xen. */
  1139. bind_ipi.vcpu = cpu;
  1140. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  1141. &bind_ipi) != 0)
  1142. BUG();
  1143. evtchn = bind_ipi.port;
  1144. /* Record the new mapping. */
  1145. xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
  1146. bind_evtchn_to_cpu(evtchn, cpu);
  1147. }
  1148. }
  1149. /* Clear an irq's pending state, in preparation for polling on it */
  1150. void xen_clear_irq_pending(int irq)
  1151. {
  1152. int evtchn = evtchn_from_irq(irq);
  1153. if (VALID_EVTCHN(evtchn))
  1154. clear_evtchn(evtchn);
  1155. }
  1156. EXPORT_SYMBOL(xen_clear_irq_pending);
  1157. void xen_set_irq_pending(int irq)
  1158. {
  1159. int evtchn = evtchn_from_irq(irq);
  1160. if (VALID_EVTCHN(evtchn))
  1161. set_evtchn(evtchn);
  1162. }
  1163. bool xen_test_irq_pending(int irq)
  1164. {
  1165. int evtchn = evtchn_from_irq(irq);
  1166. bool ret = false;
  1167. if (VALID_EVTCHN(evtchn))
  1168. ret = test_evtchn(evtchn);
  1169. return ret;
  1170. }
  1171. /* Poll waiting for an irq to become pending with timeout. In the usual case,
  1172. * the irq will be disabled so it won't deliver an interrupt. */
  1173. void xen_poll_irq_timeout(int irq, u64 timeout)
  1174. {
  1175. evtchn_port_t evtchn = evtchn_from_irq(irq);
  1176. if (VALID_EVTCHN(evtchn)) {
  1177. struct sched_poll poll;
  1178. poll.nr_ports = 1;
  1179. poll.timeout = timeout;
  1180. set_xen_guest_handle(poll.ports, &evtchn);
  1181. if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
  1182. BUG();
  1183. }
  1184. }
  1185. EXPORT_SYMBOL(xen_poll_irq_timeout);
  1186. /* Poll waiting for an irq to become pending. In the usual case, the
  1187. * irq will be disabled so it won't deliver an interrupt. */
  1188. void xen_poll_irq(int irq)
  1189. {
  1190. xen_poll_irq_timeout(irq, 0 /* no timeout */);
  1191. }
  1192. void xen_irq_resume(void)
  1193. {
  1194. unsigned int cpu, evtchn;
  1195. struct irq_info *info;
  1196. init_evtchn_cpu_bindings();
  1197. /* New event-channel space is not 'live' yet. */
  1198. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1199. mask_evtchn(evtchn);
  1200. /* No IRQ <-> event-channel mappings. */
  1201. list_for_each_entry(info, &xen_irq_list_head, list)
  1202. info->evtchn = 0; /* zap event-channel binding */
  1203. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1204. evtchn_to_irq[evtchn] = -1;
  1205. for_each_possible_cpu(cpu) {
  1206. restore_cpu_virqs(cpu);
  1207. restore_cpu_ipis(cpu);
  1208. }
  1209. restore_pirqs();
  1210. }
  1211. static struct irq_chip xen_dynamic_chip __read_mostly = {
  1212. .name = "xen-dyn",
  1213. .irq_disable = disable_dynirq,
  1214. .irq_mask = disable_dynirq,
  1215. .irq_unmask = enable_dynirq,
  1216. .irq_eoi = ack_dynirq,
  1217. .irq_set_affinity = set_affinity_irq,
  1218. .irq_retrigger = retrigger_dynirq,
  1219. };
  1220. static struct irq_chip xen_pirq_chip __read_mostly = {
  1221. .name = "xen-pirq",
  1222. .irq_startup = startup_pirq,
  1223. .irq_shutdown = shutdown_pirq,
  1224. .irq_enable = enable_pirq,
  1225. .irq_unmask = enable_pirq,
  1226. .irq_disable = disable_pirq,
  1227. .irq_mask = disable_pirq,
  1228. .irq_ack = ack_pirq,
  1229. .irq_set_affinity = set_affinity_irq,
  1230. .irq_retrigger = retrigger_dynirq,
  1231. };
  1232. static struct irq_chip xen_percpu_chip __read_mostly = {
  1233. .name = "xen-percpu",
  1234. .irq_disable = disable_dynirq,
  1235. .irq_mask = disable_dynirq,
  1236. .irq_unmask = enable_dynirq,
  1237. .irq_ack = ack_dynirq,
  1238. };
  1239. int xen_set_callback_via(uint64_t via)
  1240. {
  1241. struct xen_hvm_param a;
  1242. a.domid = DOMID_SELF;
  1243. a.index = HVM_PARAM_CALLBACK_IRQ;
  1244. a.value = via;
  1245. return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
  1246. }
  1247. EXPORT_SYMBOL_GPL(xen_set_callback_via);
  1248. #ifdef CONFIG_XEN_PVHVM
  1249. /* Vector callbacks are better than PCI interrupts to receive event
  1250. * channel notifications because we can receive vector callbacks on any
  1251. * vcpu and we don't need PCI support or APIC interactions. */
  1252. void xen_callback_vector(void)
  1253. {
  1254. int rc;
  1255. uint64_t callback_via;
  1256. if (xen_have_vector_callback) {
  1257. callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
  1258. rc = xen_set_callback_via(callback_via);
  1259. if (rc) {
  1260. printk(KERN_ERR "Request for Xen HVM callback vector"
  1261. " failed.\n");
  1262. xen_have_vector_callback = 0;
  1263. return;
  1264. }
  1265. printk(KERN_INFO "Xen HVM callback vector for event delivery is "
  1266. "enabled\n");
  1267. /* in the restore case the vector has already been allocated */
  1268. if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
  1269. alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
  1270. }
  1271. }
  1272. #else
  1273. void xen_callback_vector(void) {}
  1274. #endif
  1275. void __init xen_init_IRQ(void)
  1276. {
  1277. int i;
  1278. evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
  1279. GFP_KERNEL);
  1280. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1281. evtchn_to_irq[i] = -1;
  1282. init_evtchn_cpu_bindings();
  1283. /* No event channels are 'live' right now. */
  1284. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1285. mask_evtchn(i);
  1286. if (xen_hvm_domain()) {
  1287. xen_callback_vector();
  1288. native_init_IRQ();
  1289. /* pci_xen_hvm_init must be called after native_init_IRQ so that
  1290. * __acpi_register_gsi can point at the right function */
  1291. pci_xen_hvm_init();
  1292. } else {
  1293. irq_ctx_init(smp_processor_id());
  1294. if (xen_initial_domain())
  1295. xen_setup_pirqs();
  1296. }
  1297. }