tsi108_eth.c 46 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706
  1. /*******************************************************************************
  2. Copyright(c) 2006 Tundra Semiconductor Corporation.
  3. This program is free software; you can redistribute it and/or modify it
  4. under the terms of the GNU General Public License as published by the Free
  5. Software Foundation; either version 2 of the License, or (at your option)
  6. any later version.
  7. This program is distributed in the hope that it will be useful, but WITHOUT
  8. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  9. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  10. more details.
  11. You should have received a copy of the GNU General Public License along with
  12. this program; if not, write to the Free Software Foundation, Inc., 59
  13. Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  14. *******************************************************************************/
  15. /* This driver is based on the driver code originally developed
  16. * for the Intel IOC80314 (ForestLake) Gigabit Ethernet by
  17. * scott.wood@timesys.com * Copyright (C) 2003 TimeSys Corporation
  18. *
  19. * Currently changes from original version are:
  20. * - porting to Tsi108-based platform and kernel 2.6 (kong.lai@tundra.com)
  21. * - modifications to handle two ports independently and support for
  22. * additional PHY devices (alexandre.bounine@tundra.com)
  23. * - Get hardware information from platform device. (tie-fei.zang@freescale.com)
  24. *
  25. */
  26. #include <linux/module.h>
  27. #include <linux/types.h>
  28. #include <linux/init.h>
  29. #include <linux/net.h>
  30. #include <linux/netdevice.h>
  31. #include <linux/etherdevice.h>
  32. #include <linux/skbuff.h>
  33. #include <linux/slab.h>
  34. #include <linux/spinlock.h>
  35. #include <linux/delay.h>
  36. #include <linux/crc32.h>
  37. #include <linux/mii.h>
  38. #include <linux/device.h>
  39. #include <linux/pci.h>
  40. #include <linux/rtnetlink.h>
  41. #include <linux/timer.h>
  42. #include <linux/platform_device.h>
  43. #include <linux/etherdevice.h>
  44. #include <asm/system.h>
  45. #include <asm/io.h>
  46. #include <asm/tsi108.h>
  47. #include "tsi108_eth.h"
  48. #define MII_READ_DELAY 10000 /* max link wait time in msec */
  49. #define TSI108_RXRING_LEN 256
  50. /* NOTE: The driver currently does not support receiving packets
  51. * larger than the buffer size, so don't decrease this (unless you
  52. * want to add such support).
  53. */
  54. #define TSI108_RXBUF_SIZE 1536
  55. #define TSI108_TXRING_LEN 256
  56. #define TSI108_TX_INT_FREQ 64
  57. /* Check the phy status every half a second. */
  58. #define CHECK_PHY_INTERVAL (HZ/2)
  59. static int tsi108_init_one(struct platform_device *pdev);
  60. static int tsi108_ether_remove(struct platform_device *pdev);
  61. struct tsi108_prv_data {
  62. void __iomem *regs; /* Base of normal regs */
  63. void __iomem *phyregs; /* Base of register bank used for PHY access */
  64. struct net_device *dev;
  65. struct napi_struct napi;
  66. unsigned int phy; /* Index of PHY for this interface */
  67. unsigned int irq_num;
  68. unsigned int id;
  69. unsigned int phy_type;
  70. struct timer_list timer;/* Timer that triggers the check phy function */
  71. unsigned int rxtail; /* Next entry in rxring to read */
  72. unsigned int rxhead; /* Next entry in rxring to give a new buffer */
  73. unsigned int rxfree; /* Number of free, allocated RX buffers */
  74. unsigned int rxpending; /* Non-zero if there are still descriptors
  75. * to be processed from a previous descriptor
  76. * interrupt condition that has been cleared */
  77. unsigned int txtail; /* Next TX descriptor to check status on */
  78. unsigned int txhead; /* Next TX descriptor to use */
  79. /* Number of free TX descriptors. This could be calculated from
  80. * rxhead and rxtail if one descriptor were left unused to disambiguate
  81. * full and empty conditions, but it's simpler to just keep track
  82. * explicitly. */
  83. unsigned int txfree;
  84. unsigned int phy_ok; /* The PHY is currently powered on. */
  85. /* PHY status (duplex is 1 for half, 2 for full,
  86. * so that the default 0 indicates that neither has
  87. * yet been configured). */
  88. unsigned int link_up;
  89. unsigned int speed;
  90. unsigned int duplex;
  91. tx_desc *txring;
  92. rx_desc *rxring;
  93. struct sk_buff *txskbs[TSI108_TXRING_LEN];
  94. struct sk_buff *rxskbs[TSI108_RXRING_LEN];
  95. dma_addr_t txdma, rxdma;
  96. /* txlock nests in misclock and phy_lock */
  97. spinlock_t txlock, misclock;
  98. /* stats is used to hold the upper bits of each hardware counter,
  99. * and tmpstats is used to hold the full values for returning
  100. * to the caller of get_stats(). They must be separate in case
  101. * an overflow interrupt occurs before the stats are consumed.
  102. */
  103. struct net_device_stats stats;
  104. struct net_device_stats tmpstats;
  105. /* These stats are kept separate in hardware, thus require individual
  106. * fields for handling carry. They are combined in get_stats.
  107. */
  108. unsigned long rx_fcs; /* Add to rx_frame_errors */
  109. unsigned long rx_short_fcs; /* Add to rx_frame_errors */
  110. unsigned long rx_long_fcs; /* Add to rx_frame_errors */
  111. unsigned long rx_underruns; /* Add to rx_length_errors */
  112. unsigned long rx_overruns; /* Add to rx_length_errors */
  113. unsigned long tx_coll_abort; /* Add to tx_aborted_errors/collisions */
  114. unsigned long tx_pause_drop; /* Add to tx_aborted_errors */
  115. unsigned long mc_hash[16];
  116. u32 msg_enable; /* debug message level */
  117. struct mii_if_info mii_if;
  118. unsigned int init_media;
  119. };
  120. /* Structure for a device driver */
  121. static struct platform_driver tsi_eth_driver = {
  122. .probe = tsi108_init_one,
  123. .remove = tsi108_ether_remove,
  124. .driver = {
  125. .name = "tsi-ethernet",
  126. },
  127. };
  128. static void tsi108_timed_checker(unsigned long dev_ptr);
  129. static void dump_eth_one(struct net_device *dev)
  130. {
  131. struct tsi108_prv_data *data = netdev_priv(dev);
  132. printk("Dumping %s...\n", dev->name);
  133. printk("intstat %x intmask %x phy_ok %d"
  134. " link %d speed %d duplex %d\n",
  135. TSI_READ(TSI108_EC_INTSTAT),
  136. TSI_READ(TSI108_EC_INTMASK), data->phy_ok,
  137. data->link_up, data->speed, data->duplex);
  138. printk("TX: head %d, tail %d, free %d, stat %x, estat %x, err %x\n",
  139. data->txhead, data->txtail, data->txfree,
  140. TSI_READ(TSI108_EC_TXSTAT),
  141. TSI_READ(TSI108_EC_TXESTAT),
  142. TSI_READ(TSI108_EC_TXERR));
  143. printk("RX: head %d, tail %d, free %d, stat %x,"
  144. " estat %x, err %x, pending %d\n\n",
  145. data->rxhead, data->rxtail, data->rxfree,
  146. TSI_READ(TSI108_EC_RXSTAT),
  147. TSI_READ(TSI108_EC_RXESTAT),
  148. TSI_READ(TSI108_EC_RXERR), data->rxpending);
  149. }
  150. /* Synchronization is needed between the thread and up/down events.
  151. * Note that the PHY is accessed through the same registers for both
  152. * interfaces, so this can't be made interface-specific.
  153. */
  154. static DEFINE_SPINLOCK(phy_lock);
  155. static int tsi108_read_mii(struct tsi108_prv_data *data, int reg)
  156. {
  157. unsigned i;
  158. TSI_WRITE_PHY(TSI108_MAC_MII_ADDR,
  159. (data->phy << TSI108_MAC_MII_ADDR_PHY) |
  160. (reg << TSI108_MAC_MII_ADDR_REG));
  161. TSI_WRITE_PHY(TSI108_MAC_MII_CMD, 0);
  162. TSI_WRITE_PHY(TSI108_MAC_MII_CMD, TSI108_MAC_MII_CMD_READ);
  163. for (i = 0; i < 100; i++) {
  164. if (!(TSI_READ_PHY(TSI108_MAC_MII_IND) &
  165. (TSI108_MAC_MII_IND_NOTVALID | TSI108_MAC_MII_IND_BUSY)))
  166. break;
  167. udelay(10);
  168. }
  169. if (i == 100)
  170. return 0xffff;
  171. else
  172. return (TSI_READ_PHY(TSI108_MAC_MII_DATAIN));
  173. }
  174. static void tsi108_write_mii(struct tsi108_prv_data *data,
  175. int reg, u16 val)
  176. {
  177. unsigned i = 100;
  178. TSI_WRITE_PHY(TSI108_MAC_MII_ADDR,
  179. (data->phy << TSI108_MAC_MII_ADDR_PHY) |
  180. (reg << TSI108_MAC_MII_ADDR_REG));
  181. TSI_WRITE_PHY(TSI108_MAC_MII_DATAOUT, val);
  182. while (i--) {
  183. if(!(TSI_READ_PHY(TSI108_MAC_MII_IND) &
  184. TSI108_MAC_MII_IND_BUSY))
  185. break;
  186. udelay(10);
  187. }
  188. }
  189. static int tsi108_mdio_read(struct net_device *dev, int addr, int reg)
  190. {
  191. struct tsi108_prv_data *data = netdev_priv(dev);
  192. return tsi108_read_mii(data, reg);
  193. }
  194. static void tsi108_mdio_write(struct net_device *dev, int addr, int reg, int val)
  195. {
  196. struct tsi108_prv_data *data = netdev_priv(dev);
  197. tsi108_write_mii(data, reg, val);
  198. }
  199. static inline void tsi108_write_tbi(struct tsi108_prv_data *data,
  200. int reg, u16 val)
  201. {
  202. unsigned i = 1000;
  203. TSI_WRITE(TSI108_MAC_MII_ADDR,
  204. (0x1e << TSI108_MAC_MII_ADDR_PHY)
  205. | (reg << TSI108_MAC_MII_ADDR_REG));
  206. TSI_WRITE(TSI108_MAC_MII_DATAOUT, val);
  207. while(i--) {
  208. if(!(TSI_READ(TSI108_MAC_MII_IND) & TSI108_MAC_MII_IND_BUSY))
  209. return;
  210. udelay(10);
  211. }
  212. printk(KERN_ERR "%s function time out \n", __FUNCTION__);
  213. }
  214. static int mii_speed(struct mii_if_info *mii)
  215. {
  216. int advert, lpa, val, media;
  217. int lpa2 = 0;
  218. int speed;
  219. if (!mii_link_ok(mii))
  220. return 0;
  221. val = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_BMSR);
  222. if ((val & BMSR_ANEGCOMPLETE) == 0)
  223. return 0;
  224. advert = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_ADVERTISE);
  225. lpa = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_LPA);
  226. media = mii_nway_result(advert & lpa);
  227. if (mii->supports_gmii)
  228. lpa2 = mii->mdio_read(mii->dev, mii->phy_id, MII_STAT1000);
  229. speed = lpa2 & (LPA_1000FULL | LPA_1000HALF) ? 1000 :
  230. (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 100 : 10);
  231. return speed;
  232. }
  233. static void tsi108_check_phy(struct net_device *dev)
  234. {
  235. struct tsi108_prv_data *data = netdev_priv(dev);
  236. u32 mac_cfg2_reg, portctrl_reg;
  237. u32 duplex;
  238. u32 speed;
  239. unsigned long flags;
  240. /* Do a dummy read, as for some reason the first read
  241. * after a link becomes up returns link down, even if
  242. * it's been a while since the link came up.
  243. */
  244. spin_lock_irqsave(&phy_lock, flags);
  245. if (!data->phy_ok)
  246. goto out;
  247. tsi108_read_mii(data, MII_BMSR);
  248. duplex = mii_check_media(&data->mii_if, netif_msg_link(data), data->init_media);
  249. data->init_media = 0;
  250. if (netif_carrier_ok(dev)) {
  251. speed = mii_speed(&data->mii_if);
  252. if ((speed != data->speed) || duplex) {
  253. mac_cfg2_reg = TSI_READ(TSI108_MAC_CFG2);
  254. portctrl_reg = TSI_READ(TSI108_EC_PORTCTRL);
  255. mac_cfg2_reg &= ~TSI108_MAC_CFG2_IFACE_MASK;
  256. if (speed == 1000) {
  257. mac_cfg2_reg |= TSI108_MAC_CFG2_GIG;
  258. portctrl_reg &= ~TSI108_EC_PORTCTRL_NOGIG;
  259. } else {
  260. mac_cfg2_reg |= TSI108_MAC_CFG2_NOGIG;
  261. portctrl_reg |= TSI108_EC_PORTCTRL_NOGIG;
  262. }
  263. data->speed = speed;
  264. if (data->mii_if.full_duplex) {
  265. mac_cfg2_reg |= TSI108_MAC_CFG2_FULLDUPLEX;
  266. portctrl_reg &= ~TSI108_EC_PORTCTRL_HALFDUPLEX;
  267. data->duplex = 2;
  268. } else {
  269. mac_cfg2_reg &= ~TSI108_MAC_CFG2_FULLDUPLEX;
  270. portctrl_reg |= TSI108_EC_PORTCTRL_HALFDUPLEX;
  271. data->duplex = 1;
  272. }
  273. TSI_WRITE(TSI108_MAC_CFG2, mac_cfg2_reg);
  274. TSI_WRITE(TSI108_EC_PORTCTRL, portctrl_reg);
  275. if (data->link_up == 0) {
  276. /* The manual says it can take 3-4 usecs for the speed change
  277. * to take effect.
  278. */
  279. udelay(5);
  280. spin_lock(&data->txlock);
  281. if (is_valid_ether_addr(dev->dev_addr) && data->txfree)
  282. netif_wake_queue(dev);
  283. data->link_up = 1;
  284. spin_unlock(&data->txlock);
  285. }
  286. }
  287. } else {
  288. if (data->link_up == 1) {
  289. netif_stop_queue(dev);
  290. data->link_up = 0;
  291. printk(KERN_NOTICE "%s : link is down\n", dev->name);
  292. }
  293. goto out;
  294. }
  295. out:
  296. spin_unlock_irqrestore(&phy_lock, flags);
  297. }
  298. static inline void
  299. tsi108_stat_carry_one(int carry, int carry_bit, int carry_shift,
  300. unsigned long *upper)
  301. {
  302. if (carry & carry_bit)
  303. *upper += carry_shift;
  304. }
  305. static void tsi108_stat_carry(struct net_device *dev)
  306. {
  307. struct tsi108_prv_data *data = netdev_priv(dev);
  308. u32 carry1, carry2;
  309. spin_lock_irq(&data->misclock);
  310. carry1 = TSI_READ(TSI108_STAT_CARRY1);
  311. carry2 = TSI_READ(TSI108_STAT_CARRY2);
  312. TSI_WRITE(TSI108_STAT_CARRY1, carry1);
  313. TSI_WRITE(TSI108_STAT_CARRY2, carry2);
  314. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXBYTES,
  315. TSI108_STAT_RXBYTES_CARRY, &data->stats.rx_bytes);
  316. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXPKTS,
  317. TSI108_STAT_RXPKTS_CARRY,
  318. &data->stats.rx_packets);
  319. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXFCS,
  320. TSI108_STAT_RXFCS_CARRY, &data->rx_fcs);
  321. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXMCAST,
  322. TSI108_STAT_RXMCAST_CARRY,
  323. &data->stats.multicast);
  324. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXALIGN,
  325. TSI108_STAT_RXALIGN_CARRY,
  326. &data->stats.rx_frame_errors);
  327. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXLENGTH,
  328. TSI108_STAT_RXLENGTH_CARRY,
  329. &data->stats.rx_length_errors);
  330. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXRUNT,
  331. TSI108_STAT_RXRUNT_CARRY, &data->rx_underruns);
  332. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXJUMBO,
  333. TSI108_STAT_RXJUMBO_CARRY, &data->rx_overruns);
  334. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXFRAG,
  335. TSI108_STAT_RXFRAG_CARRY, &data->rx_short_fcs);
  336. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXJABBER,
  337. TSI108_STAT_RXJABBER_CARRY, &data->rx_long_fcs);
  338. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXDROP,
  339. TSI108_STAT_RXDROP_CARRY,
  340. &data->stats.rx_missed_errors);
  341. tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXBYTES,
  342. TSI108_STAT_TXBYTES_CARRY, &data->stats.tx_bytes);
  343. tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXPKTS,
  344. TSI108_STAT_TXPKTS_CARRY,
  345. &data->stats.tx_packets);
  346. tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXEXDEF,
  347. TSI108_STAT_TXEXDEF_CARRY,
  348. &data->stats.tx_aborted_errors);
  349. tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXEXCOL,
  350. TSI108_STAT_TXEXCOL_CARRY, &data->tx_coll_abort);
  351. tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXTCOL,
  352. TSI108_STAT_TXTCOL_CARRY,
  353. &data->stats.collisions);
  354. tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXPAUSE,
  355. TSI108_STAT_TXPAUSEDROP_CARRY,
  356. &data->tx_pause_drop);
  357. spin_unlock_irq(&data->misclock);
  358. }
  359. /* Read a stat counter atomically with respect to carries.
  360. * data->misclock must be held.
  361. */
  362. static inline unsigned long
  363. tsi108_read_stat(struct tsi108_prv_data * data, int reg, int carry_bit,
  364. int carry_shift, unsigned long *upper)
  365. {
  366. int carryreg;
  367. unsigned long val;
  368. if (reg < 0xb0)
  369. carryreg = TSI108_STAT_CARRY1;
  370. else
  371. carryreg = TSI108_STAT_CARRY2;
  372. again:
  373. val = TSI_READ(reg) | *upper;
  374. /* Check to see if it overflowed, but the interrupt hasn't
  375. * been serviced yet. If so, handle the carry here, and
  376. * try again.
  377. */
  378. if (unlikely(TSI_READ(carryreg) & carry_bit)) {
  379. *upper += carry_shift;
  380. TSI_WRITE(carryreg, carry_bit);
  381. goto again;
  382. }
  383. return val;
  384. }
  385. static struct net_device_stats *tsi108_get_stats(struct net_device *dev)
  386. {
  387. unsigned long excol;
  388. struct tsi108_prv_data *data = netdev_priv(dev);
  389. spin_lock_irq(&data->misclock);
  390. data->tmpstats.rx_packets =
  391. tsi108_read_stat(data, TSI108_STAT_RXPKTS,
  392. TSI108_STAT_CARRY1_RXPKTS,
  393. TSI108_STAT_RXPKTS_CARRY, &data->stats.rx_packets);
  394. data->tmpstats.tx_packets =
  395. tsi108_read_stat(data, TSI108_STAT_TXPKTS,
  396. TSI108_STAT_CARRY2_TXPKTS,
  397. TSI108_STAT_TXPKTS_CARRY, &data->stats.tx_packets);
  398. data->tmpstats.rx_bytes =
  399. tsi108_read_stat(data, TSI108_STAT_RXBYTES,
  400. TSI108_STAT_CARRY1_RXBYTES,
  401. TSI108_STAT_RXBYTES_CARRY, &data->stats.rx_bytes);
  402. data->tmpstats.tx_bytes =
  403. tsi108_read_stat(data, TSI108_STAT_TXBYTES,
  404. TSI108_STAT_CARRY2_TXBYTES,
  405. TSI108_STAT_TXBYTES_CARRY, &data->stats.tx_bytes);
  406. data->tmpstats.multicast =
  407. tsi108_read_stat(data, TSI108_STAT_RXMCAST,
  408. TSI108_STAT_CARRY1_RXMCAST,
  409. TSI108_STAT_RXMCAST_CARRY, &data->stats.multicast);
  410. excol = tsi108_read_stat(data, TSI108_STAT_TXEXCOL,
  411. TSI108_STAT_CARRY2_TXEXCOL,
  412. TSI108_STAT_TXEXCOL_CARRY,
  413. &data->tx_coll_abort);
  414. data->tmpstats.collisions =
  415. tsi108_read_stat(data, TSI108_STAT_TXTCOL,
  416. TSI108_STAT_CARRY2_TXTCOL,
  417. TSI108_STAT_TXTCOL_CARRY, &data->stats.collisions);
  418. data->tmpstats.collisions += excol;
  419. data->tmpstats.rx_length_errors =
  420. tsi108_read_stat(data, TSI108_STAT_RXLENGTH,
  421. TSI108_STAT_CARRY1_RXLENGTH,
  422. TSI108_STAT_RXLENGTH_CARRY,
  423. &data->stats.rx_length_errors);
  424. data->tmpstats.rx_length_errors +=
  425. tsi108_read_stat(data, TSI108_STAT_RXRUNT,
  426. TSI108_STAT_CARRY1_RXRUNT,
  427. TSI108_STAT_RXRUNT_CARRY, &data->rx_underruns);
  428. data->tmpstats.rx_length_errors +=
  429. tsi108_read_stat(data, TSI108_STAT_RXJUMBO,
  430. TSI108_STAT_CARRY1_RXJUMBO,
  431. TSI108_STAT_RXJUMBO_CARRY, &data->rx_overruns);
  432. data->tmpstats.rx_frame_errors =
  433. tsi108_read_stat(data, TSI108_STAT_RXALIGN,
  434. TSI108_STAT_CARRY1_RXALIGN,
  435. TSI108_STAT_RXALIGN_CARRY,
  436. &data->stats.rx_frame_errors);
  437. data->tmpstats.rx_frame_errors +=
  438. tsi108_read_stat(data, TSI108_STAT_RXFCS,
  439. TSI108_STAT_CARRY1_RXFCS, TSI108_STAT_RXFCS_CARRY,
  440. &data->rx_fcs);
  441. data->tmpstats.rx_frame_errors +=
  442. tsi108_read_stat(data, TSI108_STAT_RXFRAG,
  443. TSI108_STAT_CARRY1_RXFRAG,
  444. TSI108_STAT_RXFRAG_CARRY, &data->rx_short_fcs);
  445. data->tmpstats.rx_missed_errors =
  446. tsi108_read_stat(data, TSI108_STAT_RXDROP,
  447. TSI108_STAT_CARRY1_RXDROP,
  448. TSI108_STAT_RXDROP_CARRY,
  449. &data->stats.rx_missed_errors);
  450. /* These three are maintained by software. */
  451. data->tmpstats.rx_fifo_errors = data->stats.rx_fifo_errors;
  452. data->tmpstats.rx_crc_errors = data->stats.rx_crc_errors;
  453. data->tmpstats.tx_aborted_errors =
  454. tsi108_read_stat(data, TSI108_STAT_TXEXDEF,
  455. TSI108_STAT_CARRY2_TXEXDEF,
  456. TSI108_STAT_TXEXDEF_CARRY,
  457. &data->stats.tx_aborted_errors);
  458. data->tmpstats.tx_aborted_errors +=
  459. tsi108_read_stat(data, TSI108_STAT_TXPAUSEDROP,
  460. TSI108_STAT_CARRY2_TXPAUSE,
  461. TSI108_STAT_TXPAUSEDROP_CARRY,
  462. &data->tx_pause_drop);
  463. data->tmpstats.tx_aborted_errors += excol;
  464. data->tmpstats.tx_errors = data->tmpstats.tx_aborted_errors;
  465. data->tmpstats.rx_errors = data->tmpstats.rx_length_errors +
  466. data->tmpstats.rx_crc_errors +
  467. data->tmpstats.rx_frame_errors +
  468. data->tmpstats.rx_fifo_errors + data->tmpstats.rx_missed_errors;
  469. spin_unlock_irq(&data->misclock);
  470. return &data->tmpstats;
  471. }
  472. static void tsi108_restart_rx(struct tsi108_prv_data * data, struct net_device *dev)
  473. {
  474. TSI_WRITE(TSI108_EC_RXQ_PTRHIGH,
  475. TSI108_EC_RXQ_PTRHIGH_VALID);
  476. TSI_WRITE(TSI108_EC_RXCTRL, TSI108_EC_RXCTRL_GO
  477. | TSI108_EC_RXCTRL_QUEUE0);
  478. }
  479. static void tsi108_restart_tx(struct tsi108_prv_data * data)
  480. {
  481. TSI_WRITE(TSI108_EC_TXQ_PTRHIGH,
  482. TSI108_EC_TXQ_PTRHIGH_VALID);
  483. TSI_WRITE(TSI108_EC_TXCTRL, TSI108_EC_TXCTRL_IDLEINT |
  484. TSI108_EC_TXCTRL_GO | TSI108_EC_TXCTRL_QUEUE0);
  485. }
  486. /* txlock must be held by caller, with IRQs disabled, and
  487. * with permission to re-enable them when the lock is dropped.
  488. */
  489. static void tsi108_complete_tx(struct net_device *dev)
  490. {
  491. struct tsi108_prv_data *data = netdev_priv(dev);
  492. int tx;
  493. struct sk_buff *skb;
  494. int release = 0;
  495. while (!data->txfree || data->txhead != data->txtail) {
  496. tx = data->txtail;
  497. if (data->txring[tx].misc & TSI108_TX_OWN)
  498. break;
  499. skb = data->txskbs[tx];
  500. if (!(data->txring[tx].misc & TSI108_TX_OK))
  501. printk("%s: bad tx packet, misc %x\n",
  502. dev->name, data->txring[tx].misc);
  503. data->txtail = (data->txtail + 1) % TSI108_TXRING_LEN;
  504. data->txfree++;
  505. if (data->txring[tx].misc & TSI108_TX_EOF) {
  506. dev_kfree_skb_any(skb);
  507. release++;
  508. }
  509. }
  510. if (release) {
  511. if (is_valid_ether_addr(dev->dev_addr) && data->link_up)
  512. netif_wake_queue(dev);
  513. }
  514. }
  515. static int tsi108_send_packet(struct sk_buff * skb, struct net_device *dev)
  516. {
  517. struct tsi108_prv_data *data = netdev_priv(dev);
  518. int frags = skb_shinfo(skb)->nr_frags + 1;
  519. int i;
  520. if (!data->phy_ok && net_ratelimit())
  521. printk(KERN_ERR "%s: Transmit while PHY is down!\n", dev->name);
  522. if (!data->link_up) {
  523. printk(KERN_ERR "%s: Transmit while link is down!\n",
  524. dev->name);
  525. netif_stop_queue(dev);
  526. return NETDEV_TX_BUSY;
  527. }
  528. if (data->txfree < MAX_SKB_FRAGS + 1) {
  529. netif_stop_queue(dev);
  530. if (net_ratelimit())
  531. printk(KERN_ERR "%s: Transmit with full tx ring!\n",
  532. dev->name);
  533. return NETDEV_TX_BUSY;
  534. }
  535. if (data->txfree - frags < MAX_SKB_FRAGS + 1) {
  536. netif_stop_queue(dev);
  537. }
  538. spin_lock_irq(&data->txlock);
  539. for (i = 0; i < frags; i++) {
  540. int misc = 0;
  541. int tx = data->txhead;
  542. /* This is done to mark every TSI108_TX_INT_FREQ tx buffers with
  543. * the interrupt bit. TX descriptor-complete interrupts are
  544. * enabled when the queue fills up, and masked when there is
  545. * still free space. This way, when saturating the outbound
  546. * link, the tx interrupts are kept to a reasonable level.
  547. * When the queue is not full, reclamation of skbs still occurs
  548. * as new packets are transmitted, or on a queue-empty
  549. * interrupt.
  550. */
  551. if ((tx % TSI108_TX_INT_FREQ == 0) &&
  552. ((TSI108_TXRING_LEN - data->txfree) >= TSI108_TX_INT_FREQ))
  553. misc = TSI108_TX_INT;
  554. data->txskbs[tx] = skb;
  555. if (i == 0) {
  556. data->txring[tx].buf0 = dma_map_single(NULL, skb->data,
  557. skb->len - skb->data_len, DMA_TO_DEVICE);
  558. data->txring[tx].len = skb->len - skb->data_len;
  559. misc |= TSI108_TX_SOF;
  560. } else {
  561. skb_frag_t *frag = &skb_shinfo(skb)->frags[i - 1];
  562. data->txring[tx].buf0 =
  563. dma_map_page(NULL, frag->page, frag->page_offset,
  564. frag->size, DMA_TO_DEVICE);
  565. data->txring[tx].len = frag->size;
  566. }
  567. if (i == frags - 1)
  568. misc |= TSI108_TX_EOF;
  569. if (netif_msg_pktdata(data)) {
  570. int i;
  571. printk("%s: Tx Frame contents (%d)\n", dev->name,
  572. skb->len);
  573. for (i = 0; i < skb->len; i++)
  574. printk(" %2.2x", skb->data[i]);
  575. printk(".\n");
  576. }
  577. data->txring[tx].misc = misc | TSI108_TX_OWN;
  578. data->txhead = (data->txhead + 1) % TSI108_TXRING_LEN;
  579. data->txfree--;
  580. }
  581. tsi108_complete_tx(dev);
  582. /* This must be done after the check for completed tx descriptors,
  583. * so that the tail pointer is correct.
  584. */
  585. if (!(TSI_READ(TSI108_EC_TXSTAT) & TSI108_EC_TXSTAT_QUEUE0))
  586. tsi108_restart_tx(data);
  587. spin_unlock_irq(&data->txlock);
  588. return NETDEV_TX_OK;
  589. }
  590. static int tsi108_complete_rx(struct net_device *dev, int budget)
  591. {
  592. struct tsi108_prv_data *data = netdev_priv(dev);
  593. int done = 0;
  594. while (data->rxfree && done != budget) {
  595. int rx = data->rxtail;
  596. struct sk_buff *skb;
  597. if (data->rxring[rx].misc & TSI108_RX_OWN)
  598. break;
  599. skb = data->rxskbs[rx];
  600. data->rxtail = (data->rxtail + 1) % TSI108_RXRING_LEN;
  601. data->rxfree--;
  602. done++;
  603. if (data->rxring[rx].misc & TSI108_RX_BAD) {
  604. spin_lock_irq(&data->misclock);
  605. if (data->rxring[rx].misc & TSI108_RX_CRC)
  606. data->stats.rx_crc_errors++;
  607. if (data->rxring[rx].misc & TSI108_RX_OVER)
  608. data->stats.rx_fifo_errors++;
  609. spin_unlock_irq(&data->misclock);
  610. dev_kfree_skb_any(skb);
  611. continue;
  612. }
  613. if (netif_msg_pktdata(data)) {
  614. int i;
  615. printk("%s: Rx Frame contents (%d)\n",
  616. dev->name, data->rxring[rx].len);
  617. for (i = 0; i < data->rxring[rx].len; i++)
  618. printk(" %2.2x", skb->data[i]);
  619. printk(".\n");
  620. }
  621. skb_put(skb, data->rxring[rx].len);
  622. skb->protocol = eth_type_trans(skb, dev);
  623. netif_receive_skb(skb);
  624. dev->last_rx = jiffies;
  625. }
  626. return done;
  627. }
  628. static int tsi108_refill_rx(struct net_device *dev, int budget)
  629. {
  630. struct tsi108_prv_data *data = netdev_priv(dev);
  631. int done = 0;
  632. while (data->rxfree != TSI108_RXRING_LEN && done != budget) {
  633. int rx = data->rxhead;
  634. struct sk_buff *skb;
  635. data->rxskbs[rx] = skb = dev_alloc_skb(TSI108_RXBUF_SIZE + 2);
  636. if (!skb)
  637. break;
  638. skb_reserve(skb, 2); /* Align the data on a 4-byte boundary. */
  639. data->rxring[rx].buf0 = dma_map_single(NULL, skb->data,
  640. TSI108_RX_SKB_SIZE,
  641. DMA_FROM_DEVICE);
  642. /* Sometimes the hardware sets blen to zero after packet
  643. * reception, even though the manual says that it's only ever
  644. * modified by the driver.
  645. */
  646. data->rxring[rx].blen = TSI108_RX_SKB_SIZE;
  647. data->rxring[rx].misc = TSI108_RX_OWN | TSI108_RX_INT;
  648. data->rxhead = (data->rxhead + 1) % TSI108_RXRING_LEN;
  649. data->rxfree++;
  650. done++;
  651. }
  652. if (done != 0 && !(TSI_READ(TSI108_EC_RXSTAT) &
  653. TSI108_EC_RXSTAT_QUEUE0))
  654. tsi108_restart_rx(data, dev);
  655. return done;
  656. }
  657. static int tsi108_poll(struct napi_struct *napi, int budget)
  658. {
  659. struct tsi108_prv_data *data = container_of(napi, struct tsi108_prv_data, napi);
  660. struct net_device *dev = data->dev;
  661. u32 estat = TSI_READ(TSI108_EC_RXESTAT);
  662. u32 intstat = TSI_READ(TSI108_EC_INTSTAT);
  663. int num_received = 0, num_filled = 0;
  664. intstat &= TSI108_INT_RXQUEUE0 | TSI108_INT_RXTHRESH |
  665. TSI108_INT_RXOVERRUN | TSI108_INT_RXERROR | TSI108_INT_RXWAIT;
  666. TSI_WRITE(TSI108_EC_RXESTAT, estat);
  667. TSI_WRITE(TSI108_EC_INTSTAT, intstat);
  668. if (data->rxpending || (estat & TSI108_EC_RXESTAT_Q0_DESCINT))
  669. num_received = tsi108_complete_rx(dev, budget);
  670. /* This should normally fill no more slots than the number of
  671. * packets received in tsi108_complete_rx(). The exception
  672. * is when we previously ran out of memory for RX SKBs. In that
  673. * case, it's helpful to obey the budget, not only so that the
  674. * CPU isn't hogged, but so that memory (which may still be low)
  675. * is not hogged by one device.
  676. *
  677. * A work unit is considered to be two SKBs to allow us to catch
  678. * up when the ring has shrunk due to out-of-memory but we're
  679. * still removing the full budget's worth of packets each time.
  680. */
  681. if (data->rxfree < TSI108_RXRING_LEN)
  682. num_filled = tsi108_refill_rx(dev, budget * 2);
  683. if (intstat & TSI108_INT_RXERROR) {
  684. u32 err = TSI_READ(TSI108_EC_RXERR);
  685. TSI_WRITE(TSI108_EC_RXERR, err);
  686. if (err) {
  687. if (net_ratelimit())
  688. printk(KERN_DEBUG "%s: RX error %x\n",
  689. dev->name, err);
  690. if (!(TSI_READ(TSI108_EC_RXSTAT) &
  691. TSI108_EC_RXSTAT_QUEUE0))
  692. tsi108_restart_rx(data, dev);
  693. }
  694. }
  695. if (intstat & TSI108_INT_RXOVERRUN) {
  696. spin_lock_irq(&data->misclock);
  697. data->stats.rx_fifo_errors++;
  698. spin_unlock_irq(&data->misclock);
  699. }
  700. if (num_received < budget) {
  701. data->rxpending = 0;
  702. netif_rx_complete(dev, napi);
  703. TSI_WRITE(TSI108_EC_INTMASK,
  704. TSI_READ(TSI108_EC_INTMASK)
  705. & ~(TSI108_INT_RXQUEUE0
  706. | TSI108_INT_RXTHRESH |
  707. TSI108_INT_RXOVERRUN |
  708. TSI108_INT_RXERROR |
  709. TSI108_INT_RXWAIT));
  710. } else {
  711. data->rxpending = 1;
  712. }
  713. return num_received;
  714. }
  715. static void tsi108_rx_int(struct net_device *dev)
  716. {
  717. struct tsi108_prv_data *data = netdev_priv(dev);
  718. /* A race could cause dev to already be scheduled, so it's not an
  719. * error if that happens (and interrupts shouldn't be re-masked,
  720. * because that can cause harmful races, if poll has already
  721. * unmasked them but not cleared LINK_STATE_SCHED).
  722. *
  723. * This can happen if this code races with tsi108_poll(), which masks
  724. * the interrupts after tsi108_irq_one() read the mask, but before
  725. * netif_rx_schedule is called. It could also happen due to calls
  726. * from tsi108_check_rxring().
  727. */
  728. if (netif_rx_schedule_prep(dev, &data->napi)) {
  729. /* Mask, rather than ack, the receive interrupts. The ack
  730. * will happen in tsi108_poll().
  731. */
  732. TSI_WRITE(TSI108_EC_INTMASK,
  733. TSI_READ(TSI108_EC_INTMASK) |
  734. TSI108_INT_RXQUEUE0
  735. | TSI108_INT_RXTHRESH |
  736. TSI108_INT_RXOVERRUN | TSI108_INT_RXERROR |
  737. TSI108_INT_RXWAIT);
  738. __netif_rx_schedule(dev, &data->napi);
  739. } else {
  740. if (!netif_running(dev)) {
  741. /* This can happen if an interrupt occurs while the
  742. * interface is being brought down, as the START
  743. * bit is cleared before the stop function is called.
  744. *
  745. * In this case, the interrupts must be masked, or
  746. * they will continue indefinitely.
  747. *
  748. * There's a race here if the interface is brought down
  749. * and then up in rapid succession, as the device could
  750. * be made running after the above check and before
  751. * the masking below. This will only happen if the IRQ
  752. * thread has a lower priority than the task brining
  753. * up the interface. Fixing this race would likely
  754. * require changes in generic code.
  755. */
  756. TSI_WRITE(TSI108_EC_INTMASK,
  757. TSI_READ
  758. (TSI108_EC_INTMASK) |
  759. TSI108_INT_RXQUEUE0 |
  760. TSI108_INT_RXTHRESH |
  761. TSI108_INT_RXOVERRUN |
  762. TSI108_INT_RXERROR |
  763. TSI108_INT_RXWAIT);
  764. }
  765. }
  766. }
  767. /* If the RX ring has run out of memory, try periodically
  768. * to allocate some more, as otherwise poll would never
  769. * get called (apart from the initial end-of-queue condition).
  770. *
  771. * This is called once per second (by default) from the thread.
  772. */
  773. static void tsi108_check_rxring(struct net_device *dev)
  774. {
  775. struct tsi108_prv_data *data = netdev_priv(dev);
  776. /* A poll is scheduled, as opposed to caling tsi108_refill_rx
  777. * directly, so as to keep the receive path single-threaded
  778. * (and thus not needing a lock).
  779. */
  780. if (netif_running(dev) && data->rxfree < TSI108_RXRING_LEN / 4)
  781. tsi108_rx_int(dev);
  782. }
  783. static void tsi108_tx_int(struct net_device *dev)
  784. {
  785. struct tsi108_prv_data *data = netdev_priv(dev);
  786. u32 estat = TSI_READ(TSI108_EC_TXESTAT);
  787. TSI_WRITE(TSI108_EC_TXESTAT, estat);
  788. TSI_WRITE(TSI108_EC_INTSTAT, TSI108_INT_TXQUEUE0 |
  789. TSI108_INT_TXIDLE | TSI108_INT_TXERROR);
  790. if (estat & TSI108_EC_TXESTAT_Q0_ERR) {
  791. u32 err = TSI_READ(TSI108_EC_TXERR);
  792. TSI_WRITE(TSI108_EC_TXERR, err);
  793. if (err && net_ratelimit())
  794. printk(KERN_ERR "%s: TX error %x\n", dev->name, err);
  795. }
  796. if (estat & (TSI108_EC_TXESTAT_Q0_DESCINT | TSI108_EC_TXESTAT_Q0_EOQ)) {
  797. spin_lock(&data->txlock);
  798. tsi108_complete_tx(dev);
  799. spin_unlock(&data->txlock);
  800. }
  801. }
  802. static irqreturn_t tsi108_irq(int irq, void *dev_id)
  803. {
  804. struct net_device *dev = dev_id;
  805. struct tsi108_prv_data *data = netdev_priv(dev);
  806. u32 stat = TSI_READ(TSI108_EC_INTSTAT);
  807. if (!(stat & TSI108_INT_ANY))
  808. return IRQ_NONE; /* Not our interrupt */
  809. stat &= ~TSI_READ(TSI108_EC_INTMASK);
  810. if (stat & (TSI108_INT_TXQUEUE0 | TSI108_INT_TXIDLE |
  811. TSI108_INT_TXERROR))
  812. tsi108_tx_int(dev);
  813. if (stat & (TSI108_INT_RXQUEUE0 | TSI108_INT_RXTHRESH |
  814. TSI108_INT_RXWAIT | TSI108_INT_RXOVERRUN |
  815. TSI108_INT_RXERROR))
  816. tsi108_rx_int(dev);
  817. if (stat & TSI108_INT_SFN) {
  818. if (net_ratelimit())
  819. printk(KERN_DEBUG "%s: SFN error\n", dev->name);
  820. TSI_WRITE(TSI108_EC_INTSTAT, TSI108_INT_SFN);
  821. }
  822. if (stat & TSI108_INT_STATCARRY) {
  823. tsi108_stat_carry(dev);
  824. TSI_WRITE(TSI108_EC_INTSTAT, TSI108_INT_STATCARRY);
  825. }
  826. return IRQ_HANDLED;
  827. }
  828. static void tsi108_stop_ethernet(struct net_device *dev)
  829. {
  830. struct tsi108_prv_data *data = netdev_priv(dev);
  831. int i = 1000;
  832. /* Disable all TX and RX queues ... */
  833. TSI_WRITE(TSI108_EC_TXCTRL, 0);
  834. TSI_WRITE(TSI108_EC_RXCTRL, 0);
  835. /* ...and wait for them to become idle */
  836. while(i--) {
  837. if(!(TSI_READ(TSI108_EC_TXSTAT) & TSI108_EC_TXSTAT_ACTIVE))
  838. break;
  839. udelay(10);
  840. }
  841. i = 1000;
  842. while(i--){
  843. if(!(TSI_READ(TSI108_EC_RXSTAT) & TSI108_EC_RXSTAT_ACTIVE))
  844. return;
  845. udelay(10);
  846. }
  847. printk(KERN_ERR "%s function time out \n", __FUNCTION__);
  848. }
  849. static void tsi108_reset_ether(struct tsi108_prv_data * data)
  850. {
  851. TSI_WRITE(TSI108_MAC_CFG1, TSI108_MAC_CFG1_SOFTRST);
  852. udelay(100);
  853. TSI_WRITE(TSI108_MAC_CFG1, 0);
  854. TSI_WRITE(TSI108_EC_PORTCTRL, TSI108_EC_PORTCTRL_STATRST);
  855. udelay(100);
  856. TSI_WRITE(TSI108_EC_PORTCTRL,
  857. TSI_READ(TSI108_EC_PORTCTRL) &
  858. ~TSI108_EC_PORTCTRL_STATRST);
  859. TSI_WRITE(TSI108_EC_TXCFG, TSI108_EC_TXCFG_RST);
  860. udelay(100);
  861. TSI_WRITE(TSI108_EC_TXCFG,
  862. TSI_READ(TSI108_EC_TXCFG) &
  863. ~TSI108_EC_TXCFG_RST);
  864. TSI_WRITE(TSI108_EC_RXCFG, TSI108_EC_RXCFG_RST);
  865. udelay(100);
  866. TSI_WRITE(TSI108_EC_RXCFG,
  867. TSI_READ(TSI108_EC_RXCFG) &
  868. ~TSI108_EC_RXCFG_RST);
  869. TSI_WRITE(TSI108_MAC_MII_MGMT_CFG,
  870. TSI_READ(TSI108_MAC_MII_MGMT_CFG) |
  871. TSI108_MAC_MII_MGMT_RST);
  872. udelay(100);
  873. TSI_WRITE(TSI108_MAC_MII_MGMT_CFG,
  874. (TSI_READ(TSI108_MAC_MII_MGMT_CFG) &
  875. ~(TSI108_MAC_MII_MGMT_RST |
  876. TSI108_MAC_MII_MGMT_CLK)) | 0x07);
  877. }
  878. static int tsi108_get_mac(struct net_device *dev)
  879. {
  880. struct tsi108_prv_data *data = netdev_priv(dev);
  881. u32 word1 = TSI_READ(TSI108_MAC_ADDR1);
  882. u32 word2 = TSI_READ(TSI108_MAC_ADDR2);
  883. /* Note that the octets are reversed from what the manual says,
  884. * producing an even weirder ordering...
  885. */
  886. if (word2 == 0 && word1 == 0) {
  887. dev->dev_addr[0] = 0x00;
  888. dev->dev_addr[1] = 0x06;
  889. dev->dev_addr[2] = 0xd2;
  890. dev->dev_addr[3] = 0x00;
  891. dev->dev_addr[4] = 0x00;
  892. if (0x8 == data->phy)
  893. dev->dev_addr[5] = 0x01;
  894. else
  895. dev->dev_addr[5] = 0x02;
  896. word2 = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 24);
  897. word1 = (dev->dev_addr[2] << 0) | (dev->dev_addr[3] << 8) |
  898. (dev->dev_addr[4] << 16) | (dev->dev_addr[5] << 24);
  899. TSI_WRITE(TSI108_MAC_ADDR1, word1);
  900. TSI_WRITE(TSI108_MAC_ADDR2, word2);
  901. } else {
  902. dev->dev_addr[0] = (word2 >> 16) & 0xff;
  903. dev->dev_addr[1] = (word2 >> 24) & 0xff;
  904. dev->dev_addr[2] = (word1 >> 0) & 0xff;
  905. dev->dev_addr[3] = (word1 >> 8) & 0xff;
  906. dev->dev_addr[4] = (word1 >> 16) & 0xff;
  907. dev->dev_addr[5] = (word1 >> 24) & 0xff;
  908. }
  909. if (!is_valid_ether_addr(dev->dev_addr)) {
  910. printk("KERN_ERR: word1: %08x, word2: %08x\n", word1, word2);
  911. return -EINVAL;
  912. }
  913. return 0;
  914. }
  915. static int tsi108_set_mac(struct net_device *dev, void *addr)
  916. {
  917. struct tsi108_prv_data *data = netdev_priv(dev);
  918. u32 word1, word2;
  919. int i;
  920. if (!is_valid_ether_addr(addr))
  921. return -EINVAL;
  922. for (i = 0; i < 6; i++)
  923. /* +2 is for the offset of the HW addr type */
  924. dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
  925. word2 = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 24);
  926. word1 = (dev->dev_addr[2] << 0) | (dev->dev_addr[3] << 8) |
  927. (dev->dev_addr[4] << 16) | (dev->dev_addr[5] << 24);
  928. spin_lock_irq(&data->misclock);
  929. TSI_WRITE(TSI108_MAC_ADDR1, word1);
  930. TSI_WRITE(TSI108_MAC_ADDR2, word2);
  931. spin_lock(&data->txlock);
  932. if (data->txfree && data->link_up)
  933. netif_wake_queue(dev);
  934. spin_unlock(&data->txlock);
  935. spin_unlock_irq(&data->misclock);
  936. return 0;
  937. }
  938. /* Protected by dev->xmit_lock. */
  939. static void tsi108_set_rx_mode(struct net_device *dev)
  940. {
  941. struct tsi108_prv_data *data = netdev_priv(dev);
  942. u32 rxcfg = TSI_READ(TSI108_EC_RXCFG);
  943. if (dev->flags & IFF_PROMISC) {
  944. rxcfg &= ~(TSI108_EC_RXCFG_UC_HASH | TSI108_EC_RXCFG_MC_HASH);
  945. rxcfg |= TSI108_EC_RXCFG_UFE | TSI108_EC_RXCFG_MFE;
  946. goto out;
  947. }
  948. rxcfg &= ~(TSI108_EC_RXCFG_UFE | TSI108_EC_RXCFG_MFE);
  949. if (dev->flags & IFF_ALLMULTI || dev->mc_count) {
  950. int i;
  951. struct dev_mc_list *mc = dev->mc_list;
  952. rxcfg |= TSI108_EC_RXCFG_MFE | TSI108_EC_RXCFG_MC_HASH;
  953. memset(data->mc_hash, 0, sizeof(data->mc_hash));
  954. while (mc) {
  955. u32 hash, crc;
  956. if (mc->dmi_addrlen == 6) {
  957. crc = ether_crc(6, mc->dmi_addr);
  958. hash = crc >> 23;
  959. __set_bit(hash, &data->mc_hash[0]);
  960. } else {
  961. printk(KERN_ERR
  962. "%s: got multicast address of length %d "
  963. "instead of 6.\n", dev->name,
  964. mc->dmi_addrlen);
  965. }
  966. mc = mc->next;
  967. }
  968. TSI_WRITE(TSI108_EC_HASHADDR,
  969. TSI108_EC_HASHADDR_AUTOINC |
  970. TSI108_EC_HASHADDR_MCAST);
  971. for (i = 0; i < 16; i++) {
  972. /* The manual says that the hardware may drop
  973. * back-to-back writes to the data register.
  974. */
  975. udelay(1);
  976. TSI_WRITE(TSI108_EC_HASHDATA,
  977. data->mc_hash[i]);
  978. }
  979. }
  980. out:
  981. TSI_WRITE(TSI108_EC_RXCFG, rxcfg);
  982. }
  983. static void tsi108_init_phy(struct net_device *dev)
  984. {
  985. struct tsi108_prv_data *data = netdev_priv(dev);
  986. u32 i = 0;
  987. u16 phyval = 0;
  988. unsigned long flags;
  989. spin_lock_irqsave(&phy_lock, flags);
  990. tsi108_write_mii(data, MII_BMCR, BMCR_RESET);
  991. while (i--){
  992. if(!(tsi108_read_mii(data, MII_BMCR) & BMCR_RESET))
  993. break;
  994. udelay(10);
  995. }
  996. if (i == 0)
  997. printk(KERN_ERR "%s function time out \n", __FUNCTION__);
  998. if (data->phy_type == TSI108_PHY_BCM54XX) {
  999. tsi108_write_mii(data, 0x09, 0x0300);
  1000. tsi108_write_mii(data, 0x10, 0x1020);
  1001. tsi108_write_mii(data, 0x1c, 0x8c00);
  1002. }
  1003. tsi108_write_mii(data,
  1004. MII_BMCR,
  1005. BMCR_ANENABLE | BMCR_ANRESTART);
  1006. while (tsi108_read_mii(data, MII_BMCR) & BMCR_ANRESTART)
  1007. cpu_relax();
  1008. /* Set G/MII mode and receive clock select in TBI control #2. The
  1009. * second port won't work if this isn't done, even though we don't
  1010. * use TBI mode.
  1011. */
  1012. tsi108_write_tbi(data, 0x11, 0x30);
  1013. /* FIXME: It seems to take more than 2 back-to-back reads to the
  1014. * PHY_STAT register before the link up status bit is set.
  1015. */
  1016. data->link_up = 1;
  1017. while (!((phyval = tsi108_read_mii(data, MII_BMSR)) &
  1018. BMSR_LSTATUS)) {
  1019. if (i++ > (MII_READ_DELAY / 10)) {
  1020. data->link_up = 0;
  1021. break;
  1022. }
  1023. spin_unlock_irqrestore(&phy_lock, flags);
  1024. msleep(10);
  1025. spin_lock_irqsave(&phy_lock, flags);
  1026. }
  1027. printk(KERN_DEBUG "PHY_STAT reg contains %08x\n", phyval);
  1028. data->phy_ok = 1;
  1029. data->init_media = 1;
  1030. spin_unlock_irqrestore(&phy_lock, flags);
  1031. }
  1032. static void tsi108_kill_phy(struct net_device *dev)
  1033. {
  1034. struct tsi108_prv_data *data = netdev_priv(dev);
  1035. unsigned long flags;
  1036. spin_lock_irqsave(&phy_lock, flags);
  1037. tsi108_write_mii(data, MII_BMCR, BMCR_PDOWN);
  1038. data->phy_ok = 0;
  1039. spin_unlock_irqrestore(&phy_lock, flags);
  1040. }
  1041. static int tsi108_open(struct net_device *dev)
  1042. {
  1043. int i;
  1044. struct tsi108_prv_data *data = netdev_priv(dev);
  1045. unsigned int rxring_size = TSI108_RXRING_LEN * sizeof(rx_desc);
  1046. unsigned int txring_size = TSI108_TXRING_LEN * sizeof(tx_desc);
  1047. i = request_irq(data->irq_num, tsi108_irq, 0, dev->name, dev);
  1048. if (i != 0) {
  1049. printk(KERN_ERR "tsi108_eth%d: Could not allocate IRQ%d.\n",
  1050. data->id, data->irq_num);
  1051. return i;
  1052. } else {
  1053. dev->irq = data->irq_num;
  1054. printk(KERN_NOTICE
  1055. "tsi108_open : Port %d Assigned IRQ %d to %s\n",
  1056. data->id, dev->irq, dev->name);
  1057. }
  1058. data->rxring = dma_alloc_coherent(NULL, rxring_size,
  1059. &data->rxdma, GFP_KERNEL);
  1060. if (!data->rxring) {
  1061. printk(KERN_DEBUG
  1062. "TSI108_ETH: failed to allocate memory for rxring!\n");
  1063. return -ENOMEM;
  1064. } else {
  1065. memset(data->rxring, 0, rxring_size);
  1066. }
  1067. data->txring = dma_alloc_coherent(NULL, txring_size,
  1068. &data->txdma, GFP_KERNEL);
  1069. if (!data->txring) {
  1070. printk(KERN_DEBUG
  1071. "TSI108_ETH: failed to allocate memory for txring!\n");
  1072. pci_free_consistent(0, rxring_size, data->rxring, data->rxdma);
  1073. return -ENOMEM;
  1074. } else {
  1075. memset(data->txring, 0, txring_size);
  1076. }
  1077. for (i = 0; i < TSI108_RXRING_LEN; i++) {
  1078. data->rxring[i].next0 = data->rxdma + (i + 1) * sizeof(rx_desc);
  1079. data->rxring[i].blen = TSI108_RXBUF_SIZE;
  1080. data->rxring[i].vlan = 0;
  1081. }
  1082. data->rxring[TSI108_RXRING_LEN - 1].next0 = data->rxdma;
  1083. data->rxtail = 0;
  1084. data->rxhead = 0;
  1085. for (i = 0; i < TSI108_RXRING_LEN; i++) {
  1086. struct sk_buff *skb = dev_alloc_skb(TSI108_RXBUF_SIZE + NET_IP_ALIGN);
  1087. if (!skb) {
  1088. /* Bah. No memory for now, but maybe we'll get
  1089. * some more later.
  1090. * For now, we'll live with the smaller ring.
  1091. */
  1092. printk(KERN_WARNING
  1093. "%s: Could only allocate %d receive skb(s).\n",
  1094. dev->name, i);
  1095. data->rxhead = i;
  1096. break;
  1097. }
  1098. data->rxskbs[i] = skb;
  1099. /* Align the payload on a 4-byte boundary */
  1100. skb_reserve(skb, 2);
  1101. data->rxskbs[i] = skb;
  1102. data->rxring[i].buf0 = virt_to_phys(data->rxskbs[i]->data);
  1103. data->rxring[i].misc = TSI108_RX_OWN | TSI108_RX_INT;
  1104. }
  1105. data->rxfree = i;
  1106. TSI_WRITE(TSI108_EC_RXQ_PTRLOW, data->rxdma);
  1107. for (i = 0; i < TSI108_TXRING_LEN; i++) {
  1108. data->txring[i].next0 = data->txdma + (i + 1) * sizeof(tx_desc);
  1109. data->txring[i].misc = 0;
  1110. }
  1111. data->txring[TSI108_TXRING_LEN - 1].next0 = data->txdma;
  1112. data->txtail = 0;
  1113. data->txhead = 0;
  1114. data->txfree = TSI108_TXRING_LEN;
  1115. TSI_WRITE(TSI108_EC_TXQ_PTRLOW, data->txdma);
  1116. tsi108_init_phy(dev);
  1117. napi_enable(&data->napi);
  1118. setup_timer(&data->timer, tsi108_timed_checker, (unsigned long)dev);
  1119. mod_timer(&data->timer, jiffies + 1);
  1120. tsi108_restart_rx(data, dev);
  1121. TSI_WRITE(TSI108_EC_INTSTAT, ~0);
  1122. TSI_WRITE(TSI108_EC_INTMASK,
  1123. ~(TSI108_INT_TXQUEUE0 | TSI108_INT_RXERROR |
  1124. TSI108_INT_RXTHRESH | TSI108_INT_RXQUEUE0 |
  1125. TSI108_INT_RXOVERRUN | TSI108_INT_RXWAIT |
  1126. TSI108_INT_SFN | TSI108_INT_STATCARRY));
  1127. TSI_WRITE(TSI108_MAC_CFG1,
  1128. TSI108_MAC_CFG1_RXEN | TSI108_MAC_CFG1_TXEN);
  1129. netif_start_queue(dev);
  1130. return 0;
  1131. }
  1132. static int tsi108_close(struct net_device *dev)
  1133. {
  1134. struct tsi108_prv_data *data = netdev_priv(dev);
  1135. netif_stop_queue(dev);
  1136. napi_disable(&data->napi);
  1137. del_timer_sync(&data->timer);
  1138. tsi108_stop_ethernet(dev);
  1139. tsi108_kill_phy(dev);
  1140. TSI_WRITE(TSI108_EC_INTMASK, ~0);
  1141. TSI_WRITE(TSI108_MAC_CFG1, 0);
  1142. /* Check for any pending TX packets, and drop them. */
  1143. while (!data->txfree || data->txhead != data->txtail) {
  1144. int tx = data->txtail;
  1145. struct sk_buff *skb;
  1146. skb = data->txskbs[tx];
  1147. data->txtail = (data->txtail + 1) % TSI108_TXRING_LEN;
  1148. data->txfree++;
  1149. dev_kfree_skb(skb);
  1150. }
  1151. synchronize_irq(data->irq_num);
  1152. free_irq(data->irq_num, dev);
  1153. /* Discard the RX ring. */
  1154. while (data->rxfree) {
  1155. int rx = data->rxtail;
  1156. struct sk_buff *skb;
  1157. skb = data->rxskbs[rx];
  1158. data->rxtail = (data->rxtail + 1) % TSI108_RXRING_LEN;
  1159. data->rxfree--;
  1160. dev_kfree_skb(skb);
  1161. }
  1162. dma_free_coherent(0,
  1163. TSI108_RXRING_LEN * sizeof(rx_desc),
  1164. data->rxring, data->rxdma);
  1165. dma_free_coherent(0,
  1166. TSI108_TXRING_LEN * sizeof(tx_desc),
  1167. data->txring, data->txdma);
  1168. return 0;
  1169. }
  1170. static void tsi108_init_mac(struct net_device *dev)
  1171. {
  1172. struct tsi108_prv_data *data = netdev_priv(dev);
  1173. TSI_WRITE(TSI108_MAC_CFG2, TSI108_MAC_CFG2_DFLT_PREAMBLE |
  1174. TSI108_MAC_CFG2_PADCRC);
  1175. TSI_WRITE(TSI108_EC_TXTHRESH,
  1176. (192 << TSI108_EC_TXTHRESH_STARTFILL) |
  1177. (192 << TSI108_EC_TXTHRESH_STOPFILL));
  1178. TSI_WRITE(TSI108_STAT_CARRYMASK1,
  1179. ~(TSI108_STAT_CARRY1_RXBYTES |
  1180. TSI108_STAT_CARRY1_RXPKTS |
  1181. TSI108_STAT_CARRY1_RXFCS |
  1182. TSI108_STAT_CARRY1_RXMCAST |
  1183. TSI108_STAT_CARRY1_RXALIGN |
  1184. TSI108_STAT_CARRY1_RXLENGTH |
  1185. TSI108_STAT_CARRY1_RXRUNT |
  1186. TSI108_STAT_CARRY1_RXJUMBO |
  1187. TSI108_STAT_CARRY1_RXFRAG |
  1188. TSI108_STAT_CARRY1_RXJABBER |
  1189. TSI108_STAT_CARRY1_RXDROP));
  1190. TSI_WRITE(TSI108_STAT_CARRYMASK2,
  1191. ~(TSI108_STAT_CARRY2_TXBYTES |
  1192. TSI108_STAT_CARRY2_TXPKTS |
  1193. TSI108_STAT_CARRY2_TXEXDEF |
  1194. TSI108_STAT_CARRY2_TXEXCOL |
  1195. TSI108_STAT_CARRY2_TXTCOL |
  1196. TSI108_STAT_CARRY2_TXPAUSE));
  1197. TSI_WRITE(TSI108_EC_PORTCTRL, TSI108_EC_PORTCTRL_STATEN);
  1198. TSI_WRITE(TSI108_MAC_CFG1, 0);
  1199. TSI_WRITE(TSI108_EC_RXCFG,
  1200. TSI108_EC_RXCFG_SE | TSI108_EC_RXCFG_BFE);
  1201. TSI_WRITE(TSI108_EC_TXQ_CFG, TSI108_EC_TXQ_CFG_DESC_INT |
  1202. TSI108_EC_TXQ_CFG_EOQ_OWN_INT |
  1203. TSI108_EC_TXQ_CFG_WSWP | (TSI108_PBM_PORT <<
  1204. TSI108_EC_TXQ_CFG_SFNPORT));
  1205. TSI_WRITE(TSI108_EC_RXQ_CFG, TSI108_EC_RXQ_CFG_DESC_INT |
  1206. TSI108_EC_RXQ_CFG_EOQ_OWN_INT |
  1207. TSI108_EC_RXQ_CFG_WSWP | (TSI108_PBM_PORT <<
  1208. TSI108_EC_RXQ_CFG_SFNPORT));
  1209. TSI_WRITE(TSI108_EC_TXQ_BUFCFG,
  1210. TSI108_EC_TXQ_BUFCFG_BURST256 |
  1211. TSI108_EC_TXQ_BUFCFG_BSWP | (TSI108_PBM_PORT <<
  1212. TSI108_EC_TXQ_BUFCFG_SFNPORT));
  1213. TSI_WRITE(TSI108_EC_RXQ_BUFCFG,
  1214. TSI108_EC_RXQ_BUFCFG_BURST256 |
  1215. TSI108_EC_RXQ_BUFCFG_BSWP | (TSI108_PBM_PORT <<
  1216. TSI108_EC_RXQ_BUFCFG_SFNPORT));
  1217. TSI_WRITE(TSI108_EC_INTMASK, ~0);
  1218. }
  1219. static int tsi108_do_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  1220. {
  1221. struct tsi108_prv_data *data = netdev_priv(dev);
  1222. return generic_mii_ioctl(&data->mii_if, if_mii(rq), cmd, NULL);
  1223. }
  1224. static int
  1225. tsi108_init_one(struct platform_device *pdev)
  1226. {
  1227. struct net_device *dev = NULL;
  1228. struct tsi108_prv_data *data = NULL;
  1229. hw_info *einfo;
  1230. int err = 0;
  1231. einfo = pdev->dev.platform_data;
  1232. if (NULL == einfo) {
  1233. printk(KERN_ERR "tsi-eth %d: Missing additional data!\n",
  1234. pdev->id);
  1235. return -ENODEV;
  1236. }
  1237. /* Create an ethernet device instance */
  1238. dev = alloc_etherdev(sizeof(struct tsi108_prv_data));
  1239. if (!dev) {
  1240. printk("tsi108_eth: Could not allocate a device structure\n");
  1241. return -ENOMEM;
  1242. }
  1243. printk("tsi108_eth%d: probe...\n", pdev->id);
  1244. data = netdev_priv(dev);
  1245. data->dev = dev;
  1246. pr_debug("tsi108_eth%d:regs:phyresgs:phy:irq_num=0x%x:0x%x:0x%x:0x%x\n",
  1247. pdev->id, einfo->regs, einfo->phyregs,
  1248. einfo->phy, einfo->irq_num);
  1249. data->regs = ioremap(einfo->regs, 0x400);
  1250. if (NULL == data->regs) {
  1251. err = -ENOMEM;
  1252. goto regs_fail;
  1253. }
  1254. data->phyregs = ioremap(einfo->phyregs, 0x400);
  1255. if (NULL == data->phyregs) {
  1256. err = -ENOMEM;
  1257. goto regs_fail;
  1258. }
  1259. /* MII setup */
  1260. data->mii_if.dev = dev;
  1261. data->mii_if.mdio_read = tsi108_mdio_read;
  1262. data->mii_if.mdio_write = tsi108_mdio_write;
  1263. data->mii_if.phy_id = einfo->phy;
  1264. data->mii_if.phy_id_mask = 0x1f;
  1265. data->mii_if.reg_num_mask = 0x1f;
  1266. data->mii_if.supports_gmii = mii_check_gmii_support(&data->mii_if);
  1267. data->phy = einfo->phy;
  1268. data->phy_type = einfo->phy_type;
  1269. data->irq_num = einfo->irq_num;
  1270. data->id = pdev->id;
  1271. dev->open = tsi108_open;
  1272. dev->stop = tsi108_close;
  1273. dev->hard_start_xmit = tsi108_send_packet;
  1274. dev->set_mac_address = tsi108_set_mac;
  1275. dev->set_multicast_list = tsi108_set_rx_mode;
  1276. dev->get_stats = tsi108_get_stats;
  1277. netif_napi_add(dev, &data->napi, tsi108_poll, 64);
  1278. dev->do_ioctl = tsi108_do_ioctl;
  1279. /* Apparently, the Linux networking code won't use scatter-gather
  1280. * if the hardware doesn't do checksums. However, it's faster
  1281. * to checksum in place and use SG, as (among other reasons)
  1282. * the cache won't be dirtied (which then has to be flushed
  1283. * before DMA). The checksumming is done by the driver (via
  1284. * a new function skb_csum_dev() in net/core/skbuff.c).
  1285. */
  1286. dev->features = NETIF_F_HIGHDMA;
  1287. SET_MODULE_OWNER(dev);
  1288. spin_lock_init(&data->txlock);
  1289. spin_lock_init(&data->misclock);
  1290. tsi108_reset_ether(data);
  1291. tsi108_kill_phy(dev);
  1292. if ((err = tsi108_get_mac(dev)) != 0) {
  1293. printk(KERN_ERR "%s: Invalid MAC address. Please correct.\n",
  1294. dev->name);
  1295. goto register_fail;
  1296. }
  1297. tsi108_init_mac(dev);
  1298. err = register_netdev(dev);
  1299. if (err) {
  1300. printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
  1301. dev->name);
  1302. goto register_fail;
  1303. }
  1304. printk(KERN_INFO "%s: Tsi108 Gigabit Ethernet, MAC: "
  1305. "%02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
  1306. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  1307. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
  1308. #ifdef DEBUG
  1309. data->msg_enable = DEBUG;
  1310. dump_eth_one(dev);
  1311. #endif
  1312. return 0;
  1313. register_fail:
  1314. iounmap(data->regs);
  1315. iounmap(data->phyregs);
  1316. regs_fail:
  1317. free_netdev(dev);
  1318. return err;
  1319. }
  1320. /* There's no way to either get interrupts from the PHY when
  1321. * something changes, or to have the Tsi108 automatically communicate
  1322. * with the PHY to reconfigure itself.
  1323. *
  1324. * Thus, we have to do it using a timer.
  1325. */
  1326. static void tsi108_timed_checker(unsigned long dev_ptr)
  1327. {
  1328. struct net_device *dev = (struct net_device *)dev_ptr;
  1329. struct tsi108_prv_data *data = netdev_priv(dev);
  1330. tsi108_check_phy(dev);
  1331. tsi108_check_rxring(dev);
  1332. mod_timer(&data->timer, jiffies + CHECK_PHY_INTERVAL);
  1333. }
  1334. static int tsi108_ether_init(void)
  1335. {
  1336. int ret;
  1337. ret = platform_driver_register (&tsi_eth_driver);
  1338. if (ret < 0){
  1339. printk("tsi108_ether_init: error initializing ethernet "
  1340. "device\n");
  1341. return ret;
  1342. }
  1343. return 0;
  1344. }
  1345. static int tsi108_ether_remove(struct platform_device *pdev)
  1346. {
  1347. struct net_device *dev = platform_get_drvdata(pdev);
  1348. struct tsi108_prv_data *priv = netdev_priv(dev);
  1349. unregister_netdev(dev);
  1350. tsi108_stop_ethernet(dev);
  1351. platform_set_drvdata(pdev, NULL);
  1352. iounmap(priv->regs);
  1353. iounmap(priv->phyregs);
  1354. free_netdev(dev);
  1355. return 0;
  1356. }
  1357. static void tsi108_ether_exit(void)
  1358. {
  1359. platform_driver_unregister(&tsi_eth_driver);
  1360. }
  1361. module_init(tsi108_ether_init);
  1362. module_exit(tsi108_ether_exit);
  1363. MODULE_AUTHOR("Tundra Semiconductor Corporation");
  1364. MODULE_DESCRIPTION("Tsi108 Gigabit Ethernet driver");
  1365. MODULE_LICENSE("GPL");