setup-r8a7779.c 5.7 KB

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  1. /*
  2. * r8a7779 processor support
  3. *
  4. * Copyright (C) 2011 Renesas Solutions Corp.
  5. * Copyright (C) 2011 Magnus Damm
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/init.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/irq.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/delay.h>
  26. #include <linux/input.h>
  27. #include <linux/io.h>
  28. #include <linux/serial_sci.h>
  29. #include <linux/sh_intc.h>
  30. #include <linux/sh_timer.h>
  31. #include <mach/hardware.h>
  32. #include <mach/irqs.h>
  33. #include <mach/r8a7779.h>
  34. #include <mach/common.h>
  35. #include <asm/mach-types.h>
  36. #include <asm/mach/arch.h>
  37. static struct plat_sci_port scif0_platform_data = {
  38. .mapbase = 0xffe40000,
  39. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  40. .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  41. .scbrr_algo_id = SCBRR_ALGO_2,
  42. .type = PORT_SCIF,
  43. .irqs = { gic_spi(88), gic_spi(88),
  44. gic_spi(88), gic_spi(88) },
  45. };
  46. static struct platform_device scif0_device = {
  47. .name = "sh-sci",
  48. .id = 0,
  49. .dev = {
  50. .platform_data = &scif0_platform_data,
  51. },
  52. };
  53. static struct plat_sci_port scif1_platform_data = {
  54. .mapbase = 0xffe41000,
  55. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  56. .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  57. .scbrr_algo_id = SCBRR_ALGO_2,
  58. .type = PORT_SCIF,
  59. .irqs = { gic_spi(89), gic_spi(89),
  60. gic_spi(89), gic_spi(89) },
  61. };
  62. static struct platform_device scif1_device = {
  63. .name = "sh-sci",
  64. .id = 1,
  65. .dev = {
  66. .platform_data = &scif1_platform_data,
  67. },
  68. };
  69. static struct plat_sci_port scif2_platform_data = {
  70. .mapbase = 0xffe42000,
  71. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  72. .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  73. .scbrr_algo_id = SCBRR_ALGO_2,
  74. .type = PORT_SCIF,
  75. .irqs = { gic_spi(90), gic_spi(90),
  76. gic_spi(90), gic_spi(90) },
  77. };
  78. static struct platform_device scif2_device = {
  79. .name = "sh-sci",
  80. .id = 2,
  81. .dev = {
  82. .platform_data = &scif2_platform_data,
  83. },
  84. };
  85. static struct plat_sci_port scif3_platform_data = {
  86. .mapbase = 0xffe43000,
  87. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  88. .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  89. .scbrr_algo_id = SCBRR_ALGO_2,
  90. .type = PORT_SCIF,
  91. .irqs = { gic_spi(91), gic_spi(91),
  92. gic_spi(91), gic_spi(91) },
  93. };
  94. static struct platform_device scif3_device = {
  95. .name = "sh-sci",
  96. .id = 3,
  97. .dev = {
  98. .platform_data = &scif3_platform_data,
  99. },
  100. };
  101. static struct plat_sci_port scif4_platform_data = {
  102. .mapbase = 0xffe44000,
  103. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  104. .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  105. .scbrr_algo_id = SCBRR_ALGO_2,
  106. .type = PORT_SCIF,
  107. .irqs = { gic_spi(92), gic_spi(92),
  108. gic_spi(92), gic_spi(92) },
  109. };
  110. static struct platform_device scif4_device = {
  111. .name = "sh-sci",
  112. .id = 4,
  113. .dev = {
  114. .platform_data = &scif4_platform_data,
  115. },
  116. };
  117. static struct plat_sci_port scif5_platform_data = {
  118. .mapbase = 0xffe45000,
  119. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  120. .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  121. .scbrr_algo_id = SCBRR_ALGO_2,
  122. .type = PORT_SCIF,
  123. .irqs = { gic_spi(93), gic_spi(93),
  124. gic_spi(93), gic_spi(93) },
  125. };
  126. static struct platform_device scif5_device = {
  127. .name = "sh-sci",
  128. .id = 5,
  129. .dev = {
  130. .platform_data = &scif5_platform_data,
  131. },
  132. };
  133. /* TMU */
  134. static struct sh_timer_config tmu00_platform_data = {
  135. .name = "TMU00",
  136. .channel_offset = 0x4,
  137. .timer_bit = 0,
  138. .clockevent_rating = 200,
  139. };
  140. static struct resource tmu00_resources[] = {
  141. [0] = {
  142. .name = "TMU00",
  143. .start = 0xffd80008,
  144. .end = 0xffd80013,
  145. .flags = IORESOURCE_MEM,
  146. },
  147. [1] = {
  148. .start = gic_spi(32),
  149. .flags = IORESOURCE_IRQ,
  150. },
  151. };
  152. static struct platform_device tmu00_device = {
  153. .name = "sh_tmu",
  154. .id = 0,
  155. .dev = {
  156. .platform_data = &tmu00_platform_data,
  157. },
  158. .resource = tmu00_resources,
  159. .num_resources = ARRAY_SIZE(tmu00_resources),
  160. };
  161. static struct sh_timer_config tmu01_platform_data = {
  162. .name = "TMU01",
  163. .channel_offset = 0x10,
  164. .timer_bit = 1,
  165. .clocksource_rating = 200,
  166. };
  167. static struct resource tmu01_resources[] = {
  168. [0] = {
  169. .name = "TMU01",
  170. .start = 0xffd80014,
  171. .end = 0xffd8001f,
  172. .flags = IORESOURCE_MEM,
  173. },
  174. [1] = {
  175. .start = gic_spi(33),
  176. .flags = IORESOURCE_IRQ,
  177. },
  178. };
  179. static struct platform_device tmu01_device = {
  180. .name = "sh_tmu",
  181. .id = 1,
  182. .dev = {
  183. .platform_data = &tmu01_platform_data,
  184. },
  185. .resource = tmu01_resources,
  186. .num_resources = ARRAY_SIZE(tmu01_resources),
  187. };
  188. static struct platform_device *r8a7779_early_devices[] __initdata = {
  189. &scif0_device,
  190. &scif1_device,
  191. &scif2_device,
  192. &scif3_device,
  193. &scif4_device,
  194. &scif5_device,
  195. &tmu00_device,
  196. &tmu01_device,
  197. };
  198. static struct platform_device *r8a7779_late_devices[] __initdata = {
  199. };
  200. void __init r8a7779_add_standard_devices(void)
  201. {
  202. r8a7779_pm_init();
  203. r8a7779_init_pm_domain(&r8a7779_sh4a);
  204. r8a7779_init_pm_domain(&r8a7779_sgx);
  205. r8a7779_init_pm_domain(&r8a7779_vdp1);
  206. r8a7779_init_pm_domain(&r8a7779_impx3);
  207. platform_add_devices(r8a7779_early_devices,
  208. ARRAY_SIZE(r8a7779_early_devices));
  209. platform_add_devices(r8a7779_late_devices,
  210. ARRAY_SIZE(r8a7779_late_devices));
  211. }
  212. void __init r8a7779_add_early_devices(void)
  213. {
  214. early_platform_add_devices(r8a7779_early_devices,
  215. ARRAY_SIZE(r8a7779_early_devices));
  216. }