arcmsr_hba.c 100 KB

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  1. /*
  2. *******************************************************************************
  3. ** O.S : Linux
  4. ** FILE NAME : arcmsr_hba.c
  5. ** BY : Erich Chen
  6. ** Description: SCSI RAID Device Driver for
  7. ** ARECA RAID Host adapter
  8. *******************************************************************************
  9. ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved
  10. **
  11. ** Web site: www.areca.com.tw
  12. ** E-mail: support@areca.com.tw
  13. **
  14. ** This program is free software; you can redistribute it and/or modify
  15. ** it under the terms of the GNU General Public License version 2 as
  16. ** published by the Free Software Foundation.
  17. ** This program is distributed in the hope that it will be useful,
  18. ** but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. ** GNU General Public License for more details.
  21. *******************************************************************************
  22. ** Redistribution and use in source and binary forms, with or without
  23. ** modification, are permitted provided that the following conditions
  24. ** are met:
  25. ** 1. Redistributions of source code must retain the above copyright
  26. ** notice, this list of conditions and the following disclaimer.
  27. ** 2. Redistributions in binary form must reproduce the above copyright
  28. ** notice, this list of conditions and the following disclaimer in the
  29. ** documentation and/or other materials provided with the distribution.
  30. ** 3. The name of the author may not be used to endorse or promote products
  31. ** derived from this software without specific prior written permission.
  32. **
  33. ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  34. ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  35. ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  36. ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  37. ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
  38. ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  39. ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
  40. ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  41. ** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
  42. ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  43. *******************************************************************************
  44. ** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
  45. ** Firmware Specification, see Documentation/scsi/arcmsr_spec.txt
  46. *******************************************************************************
  47. */
  48. #include <linux/module.h>
  49. #include <linux/reboot.h>
  50. #include <linux/spinlock.h>
  51. #include <linux/pci_ids.h>
  52. #include <linux/interrupt.h>
  53. #include <linux/moduleparam.h>
  54. #include <linux/errno.h>
  55. #include <linux/types.h>
  56. #include <linux/delay.h>
  57. #include <linux/dma-mapping.h>
  58. #include <linux/timer.h>
  59. #include <linux/slab.h>
  60. #include <linux/pci.h>
  61. #include <linux/aer.h>
  62. #include <asm/dma.h>
  63. #include <asm/io.h>
  64. #include <asm/system.h>
  65. #include <asm/uaccess.h>
  66. #include <scsi/scsi_host.h>
  67. #include <scsi/scsi.h>
  68. #include <scsi/scsi_cmnd.h>
  69. #include <scsi/scsi_tcq.h>
  70. #include <scsi/scsi_device.h>
  71. #include <scsi/scsi_transport.h>
  72. #include <scsi/scsicam.h>
  73. #include "arcmsr.h"
  74. MODULE_AUTHOR("Nick Cheng <support@areca.com.tw>");
  75. MODULE_DESCRIPTION("ARECA (ARC11xx/12xx/16xx/1880) SATA/SAS RAID Host Bus Adapter");
  76. MODULE_LICENSE("Dual BSD/GPL");
  77. MODULE_VERSION(ARCMSR_DRIVER_VERSION);
  78. static int sleeptime = 10;
  79. static int retrycount = 30;
  80. wait_queue_head_t wait_q;
  81. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
  82. struct scsi_cmnd *cmd);
  83. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
  84. static int arcmsr_abort(struct scsi_cmnd *);
  85. static int arcmsr_bus_reset(struct scsi_cmnd *);
  86. static int arcmsr_bios_param(struct scsi_device *sdev,
  87. struct block_device *bdev, sector_t capacity, int *info);
  88. static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  89. static int arcmsr_probe(struct pci_dev *pdev,
  90. const struct pci_device_id *id);
  91. static void arcmsr_remove(struct pci_dev *pdev);
  92. static void arcmsr_shutdown(struct pci_dev *pdev);
  93. static void arcmsr_iop_init(struct AdapterControlBlock *acb);
  94. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
  95. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
  96. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
  97. static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb);
  98. static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb);
  99. static void arcmsr_request_device_map(unsigned long pacb);
  100. static void arcmsr_request_hba_device_map(struct AdapterControlBlock *acb);
  101. static void arcmsr_request_hbb_device_map(struct AdapterControlBlock *acb);
  102. static void arcmsr_request_hbc_device_map(struct AdapterControlBlock *acb);
  103. static void arcmsr_message_isr_bh_fn(struct work_struct *work);
  104. static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb);
  105. static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
  106. static void arcmsr_hbc_message_isr(struct AdapterControlBlock *pACB);
  107. static void arcmsr_hardware_reset(struct AdapterControlBlock *acb);
  108. static const char *arcmsr_info(struct Scsi_Host *);
  109. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
  110. static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev,
  111. int queue_depth, int reason)
  112. {
  113. if (reason != SCSI_QDEPTH_DEFAULT)
  114. return -EOPNOTSUPP;
  115. if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
  116. queue_depth = ARCMSR_MAX_CMD_PERLUN;
  117. scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, queue_depth);
  118. return queue_depth;
  119. }
  120. static struct scsi_host_template arcmsr_scsi_host_template = {
  121. .module = THIS_MODULE,
  122. .name = "ARCMSR ARECA SATA/SAS RAID Controller"
  123. ARCMSR_DRIVER_VERSION,
  124. .info = arcmsr_info,
  125. .queuecommand = arcmsr_queue_command,
  126. .eh_abort_handler = arcmsr_abort,
  127. .eh_bus_reset_handler = arcmsr_bus_reset,
  128. .bios_param = arcmsr_bios_param,
  129. .change_queue_depth = arcmsr_adjust_disk_queue_depth,
  130. .can_queue = ARCMSR_MAX_FREECCB_NUM,
  131. .this_id = ARCMSR_SCSI_INITIATOR_ID,
  132. .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
  133. .max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
  134. .cmd_per_lun = ARCMSR_MAX_CMD_PERLUN,
  135. .use_clustering = ENABLE_CLUSTERING,
  136. .shost_attrs = arcmsr_host_attrs,
  137. };
  138. static struct pci_device_id arcmsr_device_id_table[] = {
  139. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110)},
  140. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120)},
  141. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130)},
  142. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160)},
  143. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170)},
  144. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200)},
  145. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201)},
  146. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202)},
  147. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210)},
  148. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220)},
  149. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230)},
  150. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260)},
  151. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270)},
  152. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280)},
  153. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380)},
  154. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381)},
  155. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680)},
  156. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681)},
  157. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880)},
  158. {0, 0}, /* Terminating entry */
  159. };
  160. MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
  161. static struct pci_driver arcmsr_pci_driver = {
  162. .name = "arcmsr",
  163. .id_table = arcmsr_device_id_table,
  164. .probe = arcmsr_probe,
  165. .remove = arcmsr_remove,
  166. .shutdown = arcmsr_shutdown,
  167. };
  168. /*
  169. ****************************************************************************
  170. ****************************************************************************
  171. */
  172. int arcmsr_sleep_for_bus_reset(struct scsi_cmnd *cmd)
  173. {
  174. struct Scsi_Host *shost = NULL;
  175. int i, isleep;
  176. shost = cmd->device->host;
  177. isleep = sleeptime / 10;
  178. if (isleep > 0) {
  179. for (i = 0; i < isleep; i++) {
  180. msleep(10000);
  181. }
  182. }
  183. isleep = sleeptime % 10;
  184. if (isleep > 0) {
  185. msleep(isleep*1000);
  186. }
  187. printk(KERN_NOTICE "wake-up\n");
  188. return 0;
  189. }
  190. static void arcmsr_free_hbb_mu(struct AdapterControlBlock *acb)
  191. {
  192. switch (acb->adapter_type) {
  193. case ACB_ADAPTER_TYPE_A:
  194. case ACB_ADAPTER_TYPE_C:
  195. break;
  196. case ACB_ADAPTER_TYPE_B:{
  197. dma_free_coherent(&acb->pdev->dev,
  198. sizeof(struct MessageUnit_B),
  199. acb->pmuB, acb->dma_coherent_handle_hbb_mu);
  200. }
  201. }
  202. }
  203. static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb)
  204. {
  205. struct pci_dev *pdev = acb->pdev;
  206. switch (acb->adapter_type){
  207. case ACB_ADAPTER_TYPE_A:{
  208. acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0));
  209. if (!acb->pmuA) {
  210. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  211. return false;
  212. }
  213. break;
  214. }
  215. case ACB_ADAPTER_TYPE_B:{
  216. void __iomem *mem_base0, *mem_base1;
  217. mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  218. if (!mem_base0) {
  219. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  220. return false;
  221. }
  222. mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
  223. if (!mem_base1) {
  224. iounmap(mem_base0);
  225. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  226. return false;
  227. }
  228. acb->mem_base0 = mem_base0;
  229. acb->mem_base1 = mem_base1;
  230. break;
  231. }
  232. case ACB_ADAPTER_TYPE_C:{
  233. acb->pmuC = ioremap_nocache(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
  234. if (!acb->pmuC) {
  235. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  236. return false;
  237. }
  238. if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
  239. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/
  240. return true;
  241. }
  242. break;
  243. }
  244. }
  245. return true;
  246. }
  247. static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb)
  248. {
  249. switch (acb->adapter_type) {
  250. case ACB_ADAPTER_TYPE_A:{
  251. iounmap(acb->pmuA);
  252. }
  253. break;
  254. case ACB_ADAPTER_TYPE_B:{
  255. iounmap(acb->mem_base0);
  256. iounmap(acb->mem_base1);
  257. }
  258. break;
  259. case ACB_ADAPTER_TYPE_C:{
  260. iounmap(acb->pmuC);
  261. }
  262. }
  263. }
  264. static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
  265. {
  266. irqreturn_t handle_state;
  267. struct AdapterControlBlock *acb = dev_id;
  268. handle_state = arcmsr_interrupt(acb);
  269. return handle_state;
  270. }
  271. static int arcmsr_bios_param(struct scsi_device *sdev,
  272. struct block_device *bdev, sector_t capacity, int *geom)
  273. {
  274. int ret, heads, sectors, cylinders, total_capacity;
  275. unsigned char *buffer;/* return copy of block device's partition table */
  276. buffer = scsi_bios_ptable(bdev);
  277. if (buffer) {
  278. ret = scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]);
  279. kfree(buffer);
  280. if (ret != -1)
  281. return ret;
  282. }
  283. total_capacity = capacity;
  284. heads = 64;
  285. sectors = 32;
  286. cylinders = total_capacity / (heads * sectors);
  287. if (cylinders > 1024) {
  288. heads = 255;
  289. sectors = 63;
  290. cylinders = total_capacity / (heads * sectors);
  291. }
  292. geom[0] = heads;
  293. geom[1] = sectors;
  294. geom[2] = cylinders;
  295. return 0;
  296. }
  297. static void arcmsr_define_adapter_type(struct AdapterControlBlock *acb)
  298. {
  299. struct pci_dev *pdev = acb->pdev;
  300. u16 dev_id;
  301. pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id);
  302. acb->dev_id = dev_id;
  303. switch (dev_id) {
  304. case 0x1880: {
  305. acb->adapter_type = ACB_ADAPTER_TYPE_C;
  306. }
  307. break;
  308. case 0x1201: {
  309. acb->adapter_type = ACB_ADAPTER_TYPE_B;
  310. }
  311. break;
  312. default: acb->adapter_type = ACB_ADAPTER_TYPE_A;
  313. }
  314. }
  315. static uint8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
  316. {
  317. struct MessageUnit_A __iomem *reg = acb->pmuA;
  318. uint32_t Index;
  319. uint8_t Retries = 0x00;
  320. do {
  321. for (Index = 0; Index < 100; Index++) {
  322. if (readl(&reg->outbound_intstatus) &
  323. ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
  324. writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
  325. &reg->outbound_intstatus);
  326. return true;
  327. }
  328. msleep(10);
  329. }/*max 1 seconds*/
  330. } while (Retries++ < 20);/*max 20 sec*/
  331. return false;
  332. }
  333. static uint8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
  334. {
  335. struct MessageUnit_B *reg = acb->pmuB;
  336. uint32_t Index;
  337. uint8_t Retries = 0x00;
  338. do {
  339. for (Index = 0; Index < 100; Index++) {
  340. if (readl(reg->iop2drv_doorbell)
  341. & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
  342. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN
  343. , reg->iop2drv_doorbell);
  344. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
  345. return true;
  346. }
  347. msleep(10);
  348. }/*max 1 seconds*/
  349. } while (Retries++ < 20);/*max 20 sec*/
  350. return false;
  351. }
  352. static uint8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *pACB)
  353. {
  354. struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)pACB->pmuC;
  355. unsigned char Retries = 0x00;
  356. uint32_t Index;
  357. do {
  358. for (Index = 0; Index < 100; Index++) {
  359. if (readl(&phbcmu->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
  360. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &phbcmu->outbound_doorbell_clear);/*clear interrupt*/
  361. return true;
  362. }
  363. /* one us delay */
  364. msleep(10);
  365. } /*max 1 seconds*/
  366. } while (Retries++ < 20); /*max 20 sec*/
  367. return false;
  368. }
  369. static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
  370. {
  371. struct MessageUnit_A __iomem *reg = acb->pmuA;
  372. int retry_count = 30;
  373. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
  374. do {
  375. if (arcmsr_hba_wait_msgint_ready(acb))
  376. break;
  377. else {
  378. retry_count--;
  379. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  380. timeout, retry count down = %d \n", acb->host->host_no, retry_count);
  381. }
  382. } while (retry_count != 0);
  383. }
  384. static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
  385. {
  386. struct MessageUnit_B *reg = acb->pmuB;
  387. int retry_count = 30;
  388. writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell);
  389. do {
  390. if (arcmsr_hbb_wait_msgint_ready(acb))
  391. break;
  392. else {
  393. retry_count--;
  394. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  395. timeout,retry count down = %d \n", acb->host->host_no, retry_count);
  396. }
  397. } while (retry_count != 0);
  398. }
  399. static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *pACB)
  400. {
  401. struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
  402. int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
  403. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
  404. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  405. do {
  406. if (arcmsr_hbc_wait_msgint_ready(pACB)) {
  407. break;
  408. } else {
  409. retry_count--;
  410. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  411. timeout,retry count down = %d \n", pACB->host->host_no, retry_count);
  412. }
  413. } while (retry_count != 0);
  414. return;
  415. }
  416. static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
  417. {
  418. switch (acb->adapter_type) {
  419. case ACB_ADAPTER_TYPE_A: {
  420. arcmsr_flush_hba_cache(acb);
  421. }
  422. break;
  423. case ACB_ADAPTER_TYPE_B: {
  424. arcmsr_flush_hbb_cache(acb);
  425. }
  426. break;
  427. case ACB_ADAPTER_TYPE_C: {
  428. arcmsr_flush_hbc_cache(acb);
  429. }
  430. }
  431. }
  432. static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
  433. {
  434. struct pci_dev *pdev = acb->pdev;
  435. void *dma_coherent;
  436. dma_addr_t dma_coherent_handle;
  437. struct CommandControlBlock *ccb_tmp;
  438. int i = 0, j = 0;
  439. dma_addr_t cdb_phyaddr;
  440. unsigned long roundup_ccbsize = 0, offset;
  441. unsigned long max_xfer_len;
  442. unsigned long max_sg_entrys;
  443. uint32_t firm_config_version;
  444. for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
  445. for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
  446. acb->devstate[i][j] = ARECA_RAID_GONE;
  447. max_xfer_len = ARCMSR_MAX_XFER_LEN;
  448. max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES;
  449. firm_config_version = acb->firm_cfg_version;
  450. if((firm_config_version & 0xFF) >= 3){
  451. max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */
  452. max_sg_entrys = (max_xfer_len/4096);
  453. }
  454. acb->host->max_sectors = max_xfer_len/512;
  455. acb->host->sg_tablesize = max_sg_entrys;
  456. roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
  457. acb->uncache_size = roundup_ccbsize * ARCMSR_MAX_FREECCB_NUM + 32;
  458. dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
  459. if(!dma_coherent){
  460. printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error \n", acb->host->host_no);
  461. return -ENOMEM;
  462. }
  463. acb->dma_coherent = dma_coherent;
  464. acb->dma_coherent_handle = dma_coherent_handle;
  465. memset(dma_coherent, 0, acb->uncache_size);
  466. offset = roundup((unsigned long)dma_coherent, 32) - (unsigned long)dma_coherent;
  467. dma_coherent_handle = dma_coherent_handle + offset;
  468. dma_coherent = (struct CommandControlBlock *)dma_coherent + offset;
  469. ccb_tmp = dma_coherent;
  470. acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
  471. for(i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++){
  472. cdb_phyaddr = dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb);
  473. ccb_tmp->cdb_phyaddr_pattern = ((acb->adapter_type == ACB_ADAPTER_TYPE_C) ? cdb_phyaddr : (cdb_phyaddr >> 5));
  474. acb->pccb_pool[i] = ccb_tmp;
  475. ccb_tmp->acb = acb;
  476. INIT_LIST_HEAD(&ccb_tmp->list);
  477. list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
  478. ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize);
  479. dma_coherent_handle = dma_coherent_handle + roundup_ccbsize;
  480. }
  481. return 0;
  482. }
  483. static void arcmsr_message_isr_bh_fn(struct work_struct *work)
  484. {
  485. struct AdapterControlBlock *acb = container_of(work,struct AdapterControlBlock, arcmsr_do_message_isr_bh);
  486. switch (acb->adapter_type) {
  487. case ACB_ADAPTER_TYPE_A: {
  488. struct MessageUnit_A __iomem *reg = acb->pmuA;
  489. char *acb_dev_map = (char *)acb->device_map;
  490. uint32_t __iomem *signature = (uint32_t __iomem*) (&reg->message_rwbuffer[0]);
  491. char __iomem *devicemap = (char __iomem*) (&reg->message_rwbuffer[21]);
  492. int target, lun;
  493. struct scsi_device *psdev;
  494. char diff;
  495. atomic_inc(&acb->rq_map_token);
  496. if (readl(signature) == ARCMSR_SIGNATURE_GET_CONFIG) {
  497. for(target = 0; target < ARCMSR_MAX_TARGETID -1; target++) {
  498. diff = (*acb_dev_map)^readb(devicemap);
  499. if (diff != 0) {
  500. char temp;
  501. *acb_dev_map = readb(devicemap);
  502. temp =*acb_dev_map;
  503. for(lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
  504. if((temp & 0x01)==1 && (diff & 0x01) == 1) {
  505. scsi_add_device(acb->host, 0, target, lun);
  506. }else if((temp & 0x01) == 0 && (diff & 0x01) == 1) {
  507. psdev = scsi_device_lookup(acb->host, 0, target, lun);
  508. if (psdev != NULL ) {
  509. scsi_remove_device(psdev);
  510. scsi_device_put(psdev);
  511. }
  512. }
  513. temp >>= 1;
  514. diff >>= 1;
  515. }
  516. }
  517. devicemap++;
  518. acb_dev_map++;
  519. }
  520. }
  521. break;
  522. }
  523. case ACB_ADAPTER_TYPE_B: {
  524. struct MessageUnit_B *reg = acb->pmuB;
  525. char *acb_dev_map = (char *)acb->device_map;
  526. uint32_t __iomem *signature = (uint32_t __iomem*)(&reg->message_rwbuffer[0]);
  527. char __iomem *devicemap = (char __iomem*)(&reg->message_rwbuffer[21]);
  528. int target, lun;
  529. struct scsi_device *psdev;
  530. char diff;
  531. atomic_inc(&acb->rq_map_token);
  532. if (readl(signature) == ARCMSR_SIGNATURE_GET_CONFIG) {
  533. for(target = 0; target < ARCMSR_MAX_TARGETID -1; target++) {
  534. diff = (*acb_dev_map)^readb(devicemap);
  535. if (diff != 0) {
  536. char temp;
  537. *acb_dev_map = readb(devicemap);
  538. temp =*acb_dev_map;
  539. for(lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
  540. if((temp & 0x01)==1 && (diff & 0x01) == 1) {
  541. scsi_add_device(acb->host, 0, target, lun);
  542. }else if((temp & 0x01) == 0 && (diff & 0x01) == 1) {
  543. psdev = scsi_device_lookup(acb->host, 0, target, lun);
  544. if (psdev != NULL ) {
  545. scsi_remove_device(psdev);
  546. scsi_device_put(psdev);
  547. }
  548. }
  549. temp >>= 1;
  550. diff >>= 1;
  551. }
  552. }
  553. devicemap++;
  554. acb_dev_map++;
  555. }
  556. }
  557. }
  558. break;
  559. case ACB_ADAPTER_TYPE_C: {
  560. struct MessageUnit_C *reg = acb->pmuC;
  561. char *acb_dev_map = (char *)acb->device_map;
  562. uint32_t __iomem *signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
  563. char __iomem *devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
  564. int target, lun;
  565. struct scsi_device *psdev;
  566. char diff;
  567. atomic_inc(&acb->rq_map_token);
  568. if (readl(signature) == ARCMSR_SIGNATURE_GET_CONFIG) {
  569. for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) {
  570. diff = (*acb_dev_map)^readb(devicemap);
  571. if (diff != 0) {
  572. char temp;
  573. *acb_dev_map = readb(devicemap);
  574. temp = *acb_dev_map;
  575. for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
  576. if ((temp & 0x01) == 1 && (diff & 0x01) == 1) {
  577. scsi_add_device(acb->host, 0, target, lun);
  578. } else if ((temp & 0x01) == 0 && (diff & 0x01) == 1) {
  579. psdev = scsi_device_lookup(acb->host, 0, target, lun);
  580. if (psdev != NULL) {
  581. scsi_remove_device(psdev);
  582. scsi_device_put(psdev);
  583. }
  584. }
  585. temp >>= 1;
  586. diff >>= 1;
  587. }
  588. }
  589. devicemap++;
  590. acb_dev_map++;
  591. }
  592. }
  593. }
  594. }
  595. }
  596. static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  597. {
  598. struct Scsi_Host *host;
  599. struct AdapterControlBlock *acb;
  600. uint8_t bus,dev_fun;
  601. int error;
  602. error = pci_enable_device(pdev);
  603. if(error){
  604. return -ENODEV;
  605. }
  606. host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock));
  607. if(!host){
  608. goto pci_disable_dev;
  609. }
  610. error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  611. if(error){
  612. error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  613. if(error){
  614. printk(KERN_WARNING
  615. "scsi%d: No suitable DMA mask available\n",
  616. host->host_no);
  617. goto scsi_host_release;
  618. }
  619. }
  620. init_waitqueue_head(&wait_q);
  621. bus = pdev->bus->number;
  622. dev_fun = pdev->devfn;
  623. acb = (struct AdapterControlBlock *) host->hostdata;
  624. memset(acb,0,sizeof(struct AdapterControlBlock));
  625. acb->pdev = pdev;
  626. acb->host = host;
  627. host->max_lun = ARCMSR_MAX_TARGETLUN;
  628. host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/
  629. host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/
  630. host->can_queue = ARCMSR_MAX_FREECCB_NUM; /* max simultaneous cmds */
  631. host->cmd_per_lun = ARCMSR_MAX_CMD_PERLUN;
  632. host->this_id = ARCMSR_SCSI_INITIATOR_ID;
  633. host->unique_id = (bus << 8) | dev_fun;
  634. pci_set_drvdata(pdev, host);
  635. pci_set_master(pdev);
  636. error = pci_request_regions(pdev, "arcmsr");
  637. if(error){
  638. goto scsi_host_release;
  639. }
  640. spin_lock_init(&acb->eh_lock);
  641. spin_lock_init(&acb->ccblist_lock);
  642. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  643. ACB_F_MESSAGE_RQBUFFER_CLEARED |
  644. ACB_F_MESSAGE_WQBUFFER_READED);
  645. acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
  646. INIT_LIST_HEAD(&acb->ccb_free_list);
  647. arcmsr_define_adapter_type(acb);
  648. error = arcmsr_remap_pciregion(acb);
  649. if(!error){
  650. goto pci_release_regs;
  651. }
  652. error = arcmsr_get_firmware_spec(acb);
  653. if(!error){
  654. goto unmap_pci_region;
  655. }
  656. error = arcmsr_alloc_ccb_pool(acb);
  657. if(error){
  658. goto free_hbb_mu;
  659. }
  660. arcmsr_iop_init(acb);
  661. error = scsi_add_host(host, &pdev->dev);
  662. if(error){
  663. goto RAID_controller_stop;
  664. }
  665. error = request_irq(pdev->irq, arcmsr_do_interrupt, IRQF_SHARED, "arcmsr", acb);
  666. if(error){
  667. goto scsi_host_remove;
  668. }
  669. host->irq = pdev->irq;
  670. scsi_scan_host(host);
  671. INIT_WORK(&acb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
  672. atomic_set(&acb->rq_map_token, 16);
  673. atomic_set(&acb->ante_token_value, 16);
  674. acb->fw_flag = FW_NORMAL;
  675. init_timer(&acb->eternal_timer);
  676. acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
  677. acb->eternal_timer.data = (unsigned long) acb;
  678. acb->eternal_timer.function = &arcmsr_request_device_map;
  679. add_timer(&acb->eternal_timer);
  680. if(arcmsr_alloc_sysfs_attr(acb))
  681. goto out_free_sysfs;
  682. return 0;
  683. out_free_sysfs:
  684. scsi_host_remove:
  685. scsi_remove_host(host);
  686. RAID_controller_stop:
  687. arcmsr_stop_adapter_bgrb(acb);
  688. arcmsr_flush_adapter_cache(acb);
  689. arcmsr_free_ccb_pool(acb);
  690. free_hbb_mu:
  691. arcmsr_free_hbb_mu(acb);
  692. unmap_pci_region:
  693. arcmsr_unmap_pciregion(acb);
  694. pci_release_regs:
  695. pci_release_regions(pdev);
  696. scsi_host_release:
  697. scsi_host_put(host);
  698. pci_disable_dev:
  699. pci_disable_device(pdev);
  700. return -ENODEV;
  701. }
  702. static uint8_t arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
  703. {
  704. struct MessageUnit_A __iomem *reg = acb->pmuA;
  705. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
  706. if (!arcmsr_hba_wait_msgint_ready(acb)) {
  707. printk(KERN_NOTICE
  708. "arcmsr%d: wait 'abort all outstanding command' timeout \n"
  709. , acb->host->host_no);
  710. return false;
  711. }
  712. return true;
  713. }
  714. static uint8_t arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
  715. {
  716. struct MessageUnit_B *reg = acb->pmuB;
  717. writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell);
  718. if (!arcmsr_hbb_wait_msgint_ready(acb)) {
  719. printk(KERN_NOTICE
  720. "arcmsr%d: wait 'abort all outstanding command' timeout \n"
  721. , acb->host->host_no);
  722. return false;
  723. }
  724. return true;
  725. }
  726. static uint8_t arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *pACB)
  727. {
  728. struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
  729. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
  730. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  731. if (!arcmsr_hbc_wait_msgint_ready(pACB)) {
  732. printk(KERN_NOTICE
  733. "arcmsr%d: wait 'abort all outstanding command' timeout \n"
  734. , pACB->host->host_no);
  735. return false;
  736. }
  737. return true;
  738. }
  739. static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
  740. {
  741. uint8_t rtnval = 0;
  742. switch (acb->adapter_type) {
  743. case ACB_ADAPTER_TYPE_A: {
  744. rtnval = arcmsr_abort_hba_allcmd(acb);
  745. }
  746. break;
  747. case ACB_ADAPTER_TYPE_B: {
  748. rtnval = arcmsr_abort_hbb_allcmd(acb);
  749. }
  750. break;
  751. case ACB_ADAPTER_TYPE_C: {
  752. rtnval = arcmsr_abort_hbc_allcmd(acb);
  753. }
  754. }
  755. return rtnval;
  756. }
  757. static bool arcmsr_hbb_enable_driver_mode(struct AdapterControlBlock *pacb)
  758. {
  759. struct MessageUnit_B *reg = pacb->pmuB;
  760. writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
  761. if (!arcmsr_hbb_wait_msgint_ready(pacb)) {
  762. printk(KERN_ERR "arcmsr%d: can't set driver mode. \n", pacb->host->host_no);
  763. return false;
  764. }
  765. return true;
  766. }
  767. static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
  768. {
  769. struct scsi_cmnd *pcmd = ccb->pcmd;
  770. scsi_dma_unmap(pcmd);
  771. }
  772. static void arcmsr_ccb_complete(struct CommandControlBlock *ccb)
  773. {
  774. struct AdapterControlBlock *acb = ccb->acb;
  775. struct scsi_cmnd *pcmd = ccb->pcmd;
  776. unsigned long flags;
  777. atomic_dec(&acb->ccboutstandingcount);
  778. arcmsr_pci_unmap_dma(ccb);
  779. ccb->startdone = ARCMSR_CCB_DONE;
  780. spin_lock_irqsave(&acb->ccblist_lock, flags);
  781. list_add_tail(&ccb->list, &acb->ccb_free_list);
  782. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  783. pcmd->scsi_done(pcmd);
  784. }
  785. static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
  786. {
  787. struct scsi_cmnd *pcmd = ccb->pcmd;
  788. struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
  789. pcmd->result = DID_OK << 16;
  790. if (sensebuffer) {
  791. int sense_data_length =
  792. sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE
  793. ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE;
  794. memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE);
  795. memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
  796. sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
  797. sensebuffer->Valid = 1;
  798. }
  799. }
  800. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
  801. {
  802. u32 orig_mask = 0;
  803. switch (acb->adapter_type) {
  804. case ACB_ADAPTER_TYPE_A : {
  805. struct MessageUnit_A __iomem *reg = acb->pmuA;
  806. orig_mask = readl(&reg->outbound_intmask);
  807. writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
  808. &reg->outbound_intmask);
  809. }
  810. break;
  811. case ACB_ADAPTER_TYPE_B : {
  812. struct MessageUnit_B *reg = acb->pmuB;
  813. orig_mask = readl(reg->iop2drv_doorbell_mask);
  814. writel(0, reg->iop2drv_doorbell_mask);
  815. }
  816. break;
  817. case ACB_ADAPTER_TYPE_C:{
  818. struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
  819. /* disable all outbound interrupt */
  820. orig_mask = readl(&reg->host_int_mask); /* disable outbound message0 int */
  821. writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
  822. }
  823. break;
  824. }
  825. return orig_mask;
  826. }
  827. static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb,
  828. struct CommandControlBlock *ccb, bool error)
  829. {
  830. uint8_t id, lun;
  831. id = ccb->pcmd->device->id;
  832. lun = ccb->pcmd->device->lun;
  833. if (!error) {
  834. if (acb->devstate[id][lun] == ARECA_RAID_GONE)
  835. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  836. ccb->pcmd->result = DID_OK << 16;
  837. arcmsr_ccb_complete(ccb);
  838. }else{
  839. switch (ccb->arcmsr_cdb.DeviceStatus) {
  840. case ARCMSR_DEV_SELECT_TIMEOUT: {
  841. acb->devstate[id][lun] = ARECA_RAID_GONE;
  842. ccb->pcmd->result = DID_NO_CONNECT << 16;
  843. arcmsr_ccb_complete(ccb);
  844. }
  845. break;
  846. case ARCMSR_DEV_ABORTED:
  847. case ARCMSR_DEV_INIT_FAIL: {
  848. acb->devstate[id][lun] = ARECA_RAID_GONE;
  849. ccb->pcmd->result = DID_BAD_TARGET << 16;
  850. arcmsr_ccb_complete(ccb);
  851. }
  852. break;
  853. case ARCMSR_DEV_CHECK_CONDITION: {
  854. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  855. arcmsr_report_sense_info(ccb);
  856. arcmsr_ccb_complete(ccb);
  857. }
  858. break;
  859. default:
  860. printk(KERN_NOTICE
  861. "arcmsr%d: scsi id = %d lun = %d isr get command error done, \
  862. but got unknown DeviceStatus = 0x%x \n"
  863. , acb->host->host_no
  864. , id
  865. , lun
  866. , ccb->arcmsr_cdb.DeviceStatus);
  867. acb->devstate[id][lun] = ARECA_RAID_GONE;
  868. ccb->pcmd->result = DID_NO_CONNECT << 16;
  869. arcmsr_ccb_complete(ccb);
  870. break;
  871. }
  872. }
  873. }
  874. static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error)
  875. {
  876. int id, lun;
  877. if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
  878. if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
  879. struct scsi_cmnd *abortcmd = pCCB->pcmd;
  880. if (abortcmd) {
  881. id = abortcmd->device->id;
  882. lun = abortcmd->device->lun;
  883. abortcmd->result |= DID_ABORT << 16;
  884. arcmsr_ccb_complete(pCCB);
  885. printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n",
  886. acb->host->host_no, pCCB);
  887. }
  888. return;
  889. }
  890. printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
  891. done acb = '0x%p'"
  892. "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
  893. " ccboutstandingcount = %d \n"
  894. , acb->host->host_no
  895. , acb
  896. , pCCB
  897. , pCCB->acb
  898. , pCCB->startdone
  899. , atomic_read(&acb->ccboutstandingcount));
  900. return;
  901. }
  902. arcmsr_report_ccb_state(acb, pCCB, error);
  903. }
  904. static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
  905. {
  906. int i = 0;
  907. uint32_t flag_ccb;
  908. struct ARCMSR_CDB *pARCMSR_CDB;
  909. bool error;
  910. struct CommandControlBlock *pCCB;
  911. switch (acb->adapter_type) {
  912. case ACB_ADAPTER_TYPE_A: {
  913. struct MessageUnit_A __iomem *reg = acb->pmuA;
  914. uint32_t outbound_intstatus;
  915. outbound_intstatus = readl(&reg->outbound_intstatus) &
  916. acb->outbound_int_enable;
  917. /*clear and abort all outbound posted Q*/
  918. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  919. while(((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF)
  920. && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
  921. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
  922. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  923. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  924. arcmsr_drain_donequeue(acb, pCCB, error);
  925. }
  926. }
  927. break;
  928. case ACB_ADAPTER_TYPE_B: {
  929. struct MessageUnit_B *reg = acb->pmuB;
  930. /*clear all outbound posted Q*/
  931. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, &reg->iop2drv_doorbell); /* clear doorbell interrupt */
  932. for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
  933. if ((flag_ccb = readl(&reg->done_qbuffer[i])) != 0) {
  934. writel(0, &reg->done_qbuffer[i]);
  935. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
  936. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  937. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  938. arcmsr_drain_donequeue(acb, pCCB, error);
  939. }
  940. reg->post_qbuffer[i] = 0;
  941. }
  942. reg->doneq_index = 0;
  943. reg->postq_index = 0;
  944. }
  945. break;
  946. case ACB_ADAPTER_TYPE_C: {
  947. struct MessageUnit_C *reg = acb->pmuC;
  948. struct ARCMSR_CDB *pARCMSR_CDB;
  949. uint32_t flag_ccb, ccb_cdb_phy;
  950. bool error;
  951. struct CommandControlBlock *pCCB;
  952. while ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
  953. /*need to do*/
  954. flag_ccb = readl(&reg->outbound_queueport_low);
  955. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  956. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+ccb_cdb_phy);/*frame must be 32 bytes aligned*/
  957. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  958. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
  959. arcmsr_drain_donequeue(acb, pCCB, error);
  960. }
  961. }
  962. }
  963. }
  964. static void arcmsr_remove(struct pci_dev *pdev)
  965. {
  966. struct Scsi_Host *host = pci_get_drvdata(pdev);
  967. struct AdapterControlBlock *acb =
  968. (struct AdapterControlBlock *) host->hostdata;
  969. int poll_count = 0;
  970. arcmsr_free_sysfs_attr(acb);
  971. scsi_remove_host(host);
  972. flush_scheduled_work();
  973. del_timer_sync(&acb->eternal_timer);
  974. arcmsr_disable_outbound_ints(acb);
  975. arcmsr_stop_adapter_bgrb(acb);
  976. arcmsr_flush_adapter_cache(acb);
  977. acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
  978. acb->acb_flags &= ~ACB_F_IOP_INITED;
  979. for (poll_count = 0; poll_count < ARCMSR_MAX_OUTSTANDING_CMD; poll_count++){
  980. if (!atomic_read(&acb->ccboutstandingcount))
  981. break;
  982. arcmsr_interrupt(acb);/* FIXME: need spinlock */
  983. msleep(25);
  984. }
  985. if (atomic_read(&acb->ccboutstandingcount)) {
  986. int i;
  987. arcmsr_abort_allcmd(acb);
  988. arcmsr_done4abort_postqueue(acb);
  989. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  990. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  991. if (ccb->startdone == ARCMSR_CCB_START) {
  992. ccb->startdone = ARCMSR_CCB_ABORTED;
  993. ccb->pcmd->result = DID_ABORT << 16;
  994. arcmsr_ccb_complete(ccb);
  995. }
  996. }
  997. }
  998. free_irq(pdev->irq, acb);
  999. arcmsr_free_ccb_pool(acb);
  1000. arcmsr_free_hbb_mu(acb);
  1001. arcmsr_unmap_pciregion(acb);
  1002. pci_release_regions(pdev);
  1003. scsi_host_put(host);
  1004. pci_disable_device(pdev);
  1005. pci_set_drvdata(pdev, NULL);
  1006. }
  1007. static void arcmsr_shutdown(struct pci_dev *pdev)
  1008. {
  1009. struct Scsi_Host *host = pci_get_drvdata(pdev);
  1010. struct AdapterControlBlock *acb =
  1011. (struct AdapterControlBlock *)host->hostdata;
  1012. del_timer_sync(&acb->eternal_timer);
  1013. arcmsr_disable_outbound_ints(acb);
  1014. flush_scheduled_work();
  1015. arcmsr_stop_adapter_bgrb(acb);
  1016. arcmsr_flush_adapter_cache(acb);
  1017. }
  1018. static int arcmsr_module_init(void)
  1019. {
  1020. int error = 0;
  1021. error = pci_register_driver(&arcmsr_pci_driver);
  1022. return error;
  1023. }
  1024. static void arcmsr_module_exit(void)
  1025. {
  1026. pci_unregister_driver(&arcmsr_pci_driver);
  1027. }
  1028. module_init(arcmsr_module_init);
  1029. module_exit(arcmsr_module_exit);
  1030. static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
  1031. u32 intmask_org)
  1032. {
  1033. u32 mask;
  1034. switch (acb->adapter_type) {
  1035. case ACB_ADAPTER_TYPE_A: {
  1036. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1037. mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
  1038. ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|
  1039. ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
  1040. writel(mask, &reg->outbound_intmask);
  1041. acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
  1042. }
  1043. break;
  1044. case ACB_ADAPTER_TYPE_B: {
  1045. struct MessageUnit_B *reg = acb->pmuB;
  1046. mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK |
  1047. ARCMSR_IOP2DRV_DATA_READ_OK |
  1048. ARCMSR_IOP2DRV_CDB_DONE |
  1049. ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
  1050. writel(mask, reg->iop2drv_doorbell_mask);
  1051. acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
  1052. }
  1053. break;
  1054. case ACB_ADAPTER_TYPE_C: {
  1055. struct MessageUnit_C *reg = acb->pmuC;
  1056. mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
  1057. writel(intmask_org & mask, &reg->host_int_mask);
  1058. acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
  1059. }
  1060. }
  1061. }
  1062. static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
  1063. struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
  1064. {
  1065. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  1066. int8_t *psge = (int8_t *)&arcmsr_cdb->u;
  1067. __le32 address_lo, address_hi;
  1068. int arccdbsize = 0x30;
  1069. __le32 length = 0;
  1070. int i;
  1071. struct scatterlist *sg;
  1072. int nseg;
  1073. ccb->pcmd = pcmd;
  1074. memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
  1075. arcmsr_cdb->TargetID = pcmd->device->id;
  1076. arcmsr_cdb->LUN = pcmd->device->lun;
  1077. arcmsr_cdb->Function = 1;
  1078. arcmsr_cdb->Context = 0;
  1079. memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
  1080. nseg = scsi_dma_map(pcmd);
  1081. if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0))
  1082. return FAILED;
  1083. scsi_for_each_sg(pcmd, sg, nseg, i) {
  1084. /* Get the physical address of the current data pointer */
  1085. length = cpu_to_le32(sg_dma_len(sg));
  1086. address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
  1087. address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
  1088. if (address_hi == 0) {
  1089. struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
  1090. pdma_sg->address = address_lo;
  1091. pdma_sg->length = length;
  1092. psge += sizeof (struct SG32ENTRY);
  1093. arccdbsize += sizeof (struct SG32ENTRY);
  1094. } else {
  1095. struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
  1096. pdma_sg->addresshigh = address_hi;
  1097. pdma_sg->address = address_lo;
  1098. pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
  1099. psge += sizeof (struct SG64ENTRY);
  1100. arccdbsize += sizeof (struct SG64ENTRY);
  1101. }
  1102. }
  1103. arcmsr_cdb->sgcount = (uint8_t)nseg;
  1104. arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
  1105. arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0);
  1106. if ( arccdbsize > 256)
  1107. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
  1108. if (pcmd->cmnd[0]|WRITE_6 || pcmd->cmnd[0]|WRITE_10 || pcmd->cmnd[0]|WRITE_12 ){
  1109. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
  1110. }
  1111. ccb->arc_cdb_size = arccdbsize;
  1112. return SUCCESS;
  1113. }
  1114. static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
  1115. {
  1116. uint32_t cdb_phyaddr_pattern = ccb->cdb_phyaddr_pattern;
  1117. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  1118. atomic_inc(&acb->ccboutstandingcount);
  1119. ccb->startdone = ARCMSR_CCB_START;
  1120. switch (acb->adapter_type) {
  1121. case ACB_ADAPTER_TYPE_A: {
  1122. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1123. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
  1124. writel(cdb_phyaddr_pattern | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
  1125. &reg->inbound_queueport);
  1126. else {
  1127. writel(cdb_phyaddr_pattern, &reg->inbound_queueport);
  1128. }
  1129. }
  1130. break;
  1131. case ACB_ADAPTER_TYPE_B: {
  1132. struct MessageUnit_B *reg = acb->pmuB;
  1133. uint32_t ending_index, index = reg->postq_index;
  1134. ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
  1135. writel(0, &reg->post_qbuffer[ending_index]);
  1136. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
  1137. writel(cdb_phyaddr_pattern | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,\
  1138. &reg->post_qbuffer[index]);
  1139. } else {
  1140. writel(cdb_phyaddr_pattern, &reg->post_qbuffer[index]);
  1141. }
  1142. index++;
  1143. index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
  1144. reg->postq_index = index;
  1145. writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell);
  1146. }
  1147. break;
  1148. case ACB_ADAPTER_TYPE_C: {
  1149. struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)acb->pmuC;
  1150. uint32_t ccb_post_stamp, arc_cdb_size;
  1151. arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
  1152. ccb_post_stamp = (cdb_phyaddr_pattern | ((arc_cdb_size - 1) >> 6) | 1);
  1153. if (acb->cdb_phyaddr_hi32) {
  1154. writel(acb->cdb_phyaddr_hi32, &phbcmu->inbound_queueport_high);
  1155. writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
  1156. } else {
  1157. writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
  1158. }
  1159. }
  1160. }
  1161. }
  1162. static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
  1163. {
  1164. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1165. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1166. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
  1167. if (!arcmsr_hba_wait_msgint_ready(acb)) {
  1168. printk(KERN_NOTICE
  1169. "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
  1170. , acb->host->host_no);
  1171. }
  1172. }
  1173. static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
  1174. {
  1175. struct MessageUnit_B *reg = acb->pmuB;
  1176. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1177. writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell);
  1178. if (!arcmsr_hbb_wait_msgint_ready(acb)) {
  1179. printk(KERN_NOTICE
  1180. "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
  1181. , acb->host->host_no);
  1182. }
  1183. }
  1184. static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *pACB)
  1185. {
  1186. struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
  1187. pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1188. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
  1189. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  1190. if (!arcmsr_hbc_wait_msgint_ready(pACB)) {
  1191. printk(KERN_NOTICE
  1192. "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
  1193. , pACB->host->host_no);
  1194. }
  1195. return;
  1196. }
  1197. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
  1198. {
  1199. switch (acb->adapter_type) {
  1200. case ACB_ADAPTER_TYPE_A: {
  1201. arcmsr_stop_hba_bgrb(acb);
  1202. }
  1203. break;
  1204. case ACB_ADAPTER_TYPE_B: {
  1205. arcmsr_stop_hbb_bgrb(acb);
  1206. }
  1207. break;
  1208. case ACB_ADAPTER_TYPE_C: {
  1209. arcmsr_stop_hbc_bgrb(acb);
  1210. }
  1211. }
  1212. }
  1213. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
  1214. {
  1215. dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle);
  1216. }
  1217. void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
  1218. {
  1219. switch (acb->adapter_type) {
  1220. case ACB_ADAPTER_TYPE_A: {
  1221. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1222. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  1223. }
  1224. break;
  1225. case ACB_ADAPTER_TYPE_B: {
  1226. struct MessageUnit_B *reg = acb->pmuB;
  1227. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
  1228. }
  1229. break;
  1230. case ACB_ADAPTER_TYPE_C: {
  1231. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1232. writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
  1233. }
  1234. }
  1235. }
  1236. static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
  1237. {
  1238. switch (acb->adapter_type) {
  1239. case ACB_ADAPTER_TYPE_A: {
  1240. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1241. /*
  1242. ** push inbound doorbell tell iop, driver data write ok
  1243. ** and wait reply on next hwinterrupt for next Qbuffer post
  1244. */
  1245. writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &reg->inbound_doorbell);
  1246. }
  1247. break;
  1248. case ACB_ADAPTER_TYPE_B: {
  1249. struct MessageUnit_B *reg = acb->pmuB;
  1250. /*
  1251. ** push inbound doorbell tell iop, driver data write ok
  1252. ** and wait reply on next hwinterrupt for next Qbuffer post
  1253. */
  1254. writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell);
  1255. }
  1256. break;
  1257. case ACB_ADAPTER_TYPE_C: {
  1258. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1259. /*
  1260. ** push inbound doorbell tell iop, driver data write ok
  1261. ** and wait reply on next hwinterrupt for next Qbuffer post
  1262. */
  1263. writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, &reg->inbound_doorbell);
  1264. }
  1265. break;
  1266. }
  1267. }
  1268. struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
  1269. {
  1270. struct QBUFFER __iomem *qbuffer = NULL;
  1271. switch (acb->adapter_type) {
  1272. case ACB_ADAPTER_TYPE_A: {
  1273. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1274. qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
  1275. }
  1276. break;
  1277. case ACB_ADAPTER_TYPE_B: {
  1278. struct MessageUnit_B *reg = acb->pmuB;
  1279. qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
  1280. }
  1281. break;
  1282. case ACB_ADAPTER_TYPE_C: {
  1283. struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)acb->pmuC;
  1284. qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer;
  1285. }
  1286. }
  1287. return qbuffer;
  1288. }
  1289. static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
  1290. {
  1291. struct QBUFFER __iomem *pqbuffer = NULL;
  1292. switch (acb->adapter_type) {
  1293. case ACB_ADAPTER_TYPE_A: {
  1294. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1295. pqbuffer = (struct QBUFFER __iomem *) &reg->message_wbuffer;
  1296. }
  1297. break;
  1298. case ACB_ADAPTER_TYPE_B: {
  1299. struct MessageUnit_B *reg = acb->pmuB;
  1300. pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
  1301. }
  1302. break;
  1303. case ACB_ADAPTER_TYPE_C: {
  1304. struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
  1305. pqbuffer = (struct QBUFFER __iomem *)&reg->message_wbuffer;
  1306. }
  1307. }
  1308. return pqbuffer;
  1309. }
  1310. static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
  1311. {
  1312. struct QBUFFER __iomem *prbuffer;
  1313. struct QBUFFER *pQbuffer;
  1314. uint8_t __iomem *iop_data;
  1315. int32_t my_empty_len, iop_len, rqbuf_firstindex, rqbuf_lastindex;
  1316. rqbuf_lastindex = acb->rqbuf_lastindex;
  1317. rqbuf_firstindex = acb->rqbuf_firstindex;
  1318. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  1319. iop_data = (uint8_t __iomem *)prbuffer->data;
  1320. iop_len = prbuffer->data_len;
  1321. my_empty_len = (rqbuf_firstindex - rqbuf_lastindex - 1) & (ARCMSR_MAX_QBUFFER - 1);
  1322. if (my_empty_len >= iop_len)
  1323. {
  1324. while (iop_len > 0) {
  1325. pQbuffer = (struct QBUFFER *)&acb->rqbuffer[rqbuf_lastindex];
  1326. memcpy(pQbuffer, iop_data, 1);
  1327. rqbuf_lastindex++;
  1328. rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
  1329. iop_data++;
  1330. iop_len--;
  1331. }
  1332. acb->rqbuf_lastindex = rqbuf_lastindex;
  1333. arcmsr_iop_message_read(acb);
  1334. }
  1335. else {
  1336. acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
  1337. }
  1338. }
  1339. static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
  1340. {
  1341. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
  1342. if (acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
  1343. uint8_t *pQbuffer;
  1344. struct QBUFFER __iomem *pwbuffer;
  1345. uint8_t __iomem *iop_data;
  1346. int32_t allxfer_len = 0;
  1347. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  1348. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  1349. iop_data = (uint8_t __iomem *)pwbuffer->data;
  1350. while ((acb->wqbuf_firstindex != acb->wqbuf_lastindex) && \
  1351. (allxfer_len < 124)) {
  1352. pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
  1353. memcpy(iop_data, pQbuffer, 1);
  1354. acb->wqbuf_firstindex++;
  1355. acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
  1356. iop_data++;
  1357. allxfer_len++;
  1358. }
  1359. pwbuffer->data_len = allxfer_len;
  1360. arcmsr_iop_message_wrote(acb);
  1361. }
  1362. if (acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
  1363. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
  1364. }
  1365. }
  1366. static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
  1367. {
  1368. uint32_t outbound_doorbell;
  1369. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1370. outbound_doorbell = readl(&reg->outbound_doorbell);
  1371. writel(outbound_doorbell, &reg->outbound_doorbell);
  1372. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
  1373. arcmsr_iop2drv_data_wrote_handle(acb);
  1374. }
  1375. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
  1376. arcmsr_iop2drv_data_read_handle(acb);
  1377. }
  1378. }
  1379. static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *pACB)
  1380. {
  1381. uint32_t outbound_doorbell;
  1382. struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
  1383. /*
  1384. *******************************************************************
  1385. ** Maybe here we need to check wrqbuffer_lock is lock or not
  1386. ** DOORBELL: din! don!
  1387. ** check if there are any mail need to pack from firmware
  1388. *******************************************************************
  1389. */
  1390. outbound_doorbell = readl(&reg->outbound_doorbell);
  1391. writel(outbound_doorbell, &reg->outbound_doorbell_clear);/*clear interrupt*/
  1392. if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
  1393. arcmsr_iop2drv_data_wrote_handle(pACB);
  1394. }
  1395. if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
  1396. arcmsr_iop2drv_data_read_handle(pACB);
  1397. }
  1398. if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
  1399. arcmsr_hbc_message_isr(pACB); /* messenger of "driver to iop commands" */
  1400. }
  1401. return;
  1402. }
  1403. static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
  1404. {
  1405. uint32_t flag_ccb;
  1406. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1407. struct ARCMSR_CDB *pARCMSR_CDB;
  1408. struct CommandControlBlock *pCCB;
  1409. bool error;
  1410. while ((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) {
  1411. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
  1412. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1413. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  1414. arcmsr_drain_donequeue(acb, pCCB, error);
  1415. }
  1416. }
  1417. static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
  1418. {
  1419. uint32_t index;
  1420. uint32_t flag_ccb;
  1421. struct MessageUnit_B *reg = acb->pmuB;
  1422. struct ARCMSR_CDB *pARCMSR_CDB;
  1423. struct CommandControlBlock *pCCB;
  1424. bool error;
  1425. index = reg->doneq_index;
  1426. while ((flag_ccb = readl(&reg->done_qbuffer[index])) != 0) {
  1427. writel(0, &reg->done_qbuffer[index]);
  1428. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
  1429. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1430. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  1431. arcmsr_drain_donequeue(acb, pCCB, error);
  1432. index++;
  1433. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  1434. reg->doneq_index = index;
  1435. }
  1436. }
  1437. static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
  1438. {
  1439. struct MessageUnit_C *phbcmu;
  1440. struct ARCMSR_CDB *arcmsr_cdb;
  1441. struct CommandControlBlock *ccb;
  1442. uint32_t flag_ccb, ccb_cdb_phy, throttling = 0;
  1443. int error;
  1444. phbcmu = (struct MessageUnit_C *)acb->pmuC;
  1445. /* areca cdb command done */
  1446. /* Use correct offset and size for syncing */
  1447. while (readl(&phbcmu->host_int_status) &
  1448. ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR){
  1449. /* check if command done with no error*/
  1450. flag_ccb = readl(&phbcmu->outbound_queueport_low);
  1451. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);/*frame must be 32 bytes aligned*/
  1452. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
  1453. ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  1454. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
  1455. /* check if command done with no error */
  1456. arcmsr_drain_donequeue(acb, ccb, error);
  1457. if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
  1458. writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING, &phbcmu->inbound_doorbell);
  1459. break;
  1460. }
  1461. throttling++;
  1462. }
  1463. }
  1464. /*
  1465. **********************************************************************************
  1466. ** Handle a message interrupt
  1467. **
  1468. ** The only message interrupt we expect is in response to a query for the current adapter config.
  1469. ** We want this in order to compare the drivemap so that we can detect newly-attached drives.
  1470. **********************************************************************************
  1471. */
  1472. static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb)
  1473. {
  1474. struct MessageUnit_A *reg = acb->pmuA;
  1475. /*clear interrupt and message state*/
  1476. writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, &reg->outbound_intstatus);
  1477. schedule_work(&acb->arcmsr_do_message_isr_bh);
  1478. }
  1479. static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb)
  1480. {
  1481. struct MessageUnit_B *reg = acb->pmuB;
  1482. /*clear interrupt and message state*/
  1483. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  1484. schedule_work(&acb->arcmsr_do_message_isr_bh);
  1485. }
  1486. /*
  1487. **********************************************************************************
  1488. ** Handle a message interrupt
  1489. **
  1490. ** The only message interrupt we expect is in response to a query for the
  1491. ** current adapter config.
  1492. ** We want this in order to compare the drivemap so that we can detect newly-attached drives.
  1493. **********************************************************************************
  1494. */
  1495. static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb)
  1496. {
  1497. struct MessageUnit_C *reg = acb->pmuC;
  1498. /*clear interrupt and message state*/
  1499. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);
  1500. schedule_work(&acb->arcmsr_do_message_isr_bh);
  1501. }
  1502. static int arcmsr_handle_hba_isr(struct AdapterControlBlock *acb)
  1503. {
  1504. uint32_t outbound_intstatus;
  1505. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1506. outbound_intstatus = readl(&reg->outbound_intstatus) &
  1507. acb->outbound_int_enable;
  1508. if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT)) {
  1509. return 1;
  1510. }
  1511. writel(outbound_intstatus, &reg->outbound_intstatus);
  1512. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
  1513. arcmsr_hba_doorbell_isr(acb);
  1514. }
  1515. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
  1516. arcmsr_hba_postqueue_isr(acb);
  1517. }
  1518. if(outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
  1519. /* messenger of "driver to iop commands" */
  1520. arcmsr_hba_message_isr(acb);
  1521. }
  1522. return 0;
  1523. }
  1524. static int arcmsr_handle_hbb_isr(struct AdapterControlBlock *acb)
  1525. {
  1526. uint32_t outbound_doorbell;
  1527. struct MessageUnit_B *reg = acb->pmuB;
  1528. outbound_doorbell = readl(reg->iop2drv_doorbell) &
  1529. acb->outbound_int_enable;
  1530. if (!outbound_doorbell)
  1531. return 1;
  1532. writel(~outbound_doorbell, reg->iop2drv_doorbell);
  1533. /*in case the last action of doorbell interrupt clearance is cached,
  1534. this action can push HW to write down the clear bit*/
  1535. readl(reg->iop2drv_doorbell);
  1536. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
  1537. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
  1538. arcmsr_iop2drv_data_wrote_handle(acb);
  1539. }
  1540. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
  1541. arcmsr_iop2drv_data_read_handle(acb);
  1542. }
  1543. if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
  1544. arcmsr_hbb_postqueue_isr(acb);
  1545. }
  1546. if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
  1547. /* messenger of "driver to iop commands" */
  1548. arcmsr_hbb_message_isr(acb);
  1549. }
  1550. return 0;
  1551. }
  1552. static int arcmsr_handle_hbc_isr(struct AdapterControlBlock *pACB)
  1553. {
  1554. uint32_t host_interrupt_status;
  1555. struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)pACB->pmuC;
  1556. /*
  1557. *********************************************
  1558. ** check outbound intstatus
  1559. *********************************************
  1560. */
  1561. host_interrupt_status = readl(&phbcmu->host_int_status);
  1562. if (!host_interrupt_status) {
  1563. /*it must be share irq*/
  1564. return 1;
  1565. }
  1566. /* MU ioctl transfer doorbell interrupts*/
  1567. if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
  1568. arcmsr_hbc_doorbell_isr(pACB); /* messenger of "ioctl message read write" */
  1569. }
  1570. /* MU post queue interrupts*/
  1571. if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
  1572. arcmsr_hbc_postqueue_isr(pACB); /* messenger of "scsi commands" */
  1573. }
  1574. return 0;
  1575. }
  1576. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
  1577. {
  1578. switch (acb->adapter_type) {
  1579. case ACB_ADAPTER_TYPE_A: {
  1580. if (arcmsr_handle_hba_isr(acb)) {
  1581. return IRQ_NONE;
  1582. }
  1583. }
  1584. break;
  1585. case ACB_ADAPTER_TYPE_B: {
  1586. if (arcmsr_handle_hbb_isr(acb)) {
  1587. return IRQ_NONE;
  1588. }
  1589. }
  1590. break;
  1591. case ACB_ADAPTER_TYPE_C: {
  1592. if (arcmsr_handle_hbc_isr(acb)) {
  1593. return IRQ_NONE;
  1594. }
  1595. }
  1596. }
  1597. return IRQ_HANDLED;
  1598. }
  1599. static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
  1600. {
  1601. if (acb) {
  1602. /* stop adapter background rebuild */
  1603. if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
  1604. uint32_t intmask_org;
  1605. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1606. intmask_org = arcmsr_disable_outbound_ints(acb);
  1607. arcmsr_stop_adapter_bgrb(acb);
  1608. arcmsr_flush_adapter_cache(acb);
  1609. arcmsr_enable_outbound_ints(acb, intmask_org);
  1610. }
  1611. }
  1612. }
  1613. void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *acb)
  1614. {
  1615. int32_t wqbuf_firstindex, wqbuf_lastindex;
  1616. uint8_t *pQbuffer;
  1617. struct QBUFFER __iomem *pwbuffer;
  1618. uint8_t __iomem *iop_data;
  1619. int32_t allxfer_len = 0;
  1620. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  1621. iop_data = (uint8_t __iomem *)pwbuffer->data;
  1622. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
  1623. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  1624. wqbuf_firstindex = acb->wqbuf_firstindex;
  1625. wqbuf_lastindex = acb->wqbuf_lastindex;
  1626. while ((wqbuf_firstindex != wqbuf_lastindex) && (allxfer_len < 124)) {
  1627. pQbuffer = &acb->wqbuffer[wqbuf_firstindex];
  1628. memcpy(iop_data, pQbuffer, 1);
  1629. wqbuf_firstindex++;
  1630. wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
  1631. iop_data++;
  1632. allxfer_len++;
  1633. }
  1634. acb->wqbuf_firstindex = wqbuf_firstindex;
  1635. pwbuffer->data_len = allxfer_len;
  1636. arcmsr_iop_message_wrote(acb);
  1637. }
  1638. }
  1639. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
  1640. struct scsi_cmnd *cmd)
  1641. {
  1642. struct CMD_MESSAGE_FIELD *pcmdmessagefld;
  1643. int retvalue = 0, transfer_len = 0;
  1644. char *buffer;
  1645. struct scatterlist *sg;
  1646. uint32_t controlcode = (uint32_t ) cmd->cmnd[5] << 24 |
  1647. (uint32_t ) cmd->cmnd[6] << 16 |
  1648. (uint32_t ) cmd->cmnd[7] << 8 |
  1649. (uint32_t ) cmd->cmnd[8];
  1650. /* 4 bytes: Areca io control code */
  1651. sg = scsi_sglist(cmd);
  1652. buffer = kmap_atomic(sg_page(sg), KM_IRQ0) + sg->offset;
  1653. if (scsi_sg_count(cmd) > 1) {
  1654. retvalue = ARCMSR_MESSAGE_FAIL;
  1655. goto message_out;
  1656. }
  1657. transfer_len += sg->length;
  1658. if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
  1659. retvalue = ARCMSR_MESSAGE_FAIL;
  1660. goto message_out;
  1661. }
  1662. pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
  1663. switch(controlcode) {
  1664. case ARCMSR_MESSAGE_READ_RQBUFFER: {
  1665. unsigned char *ver_addr;
  1666. uint8_t *pQbuffer, *ptmpQbuffer;
  1667. int32_t allxfer_len = 0;
  1668. ver_addr = kmalloc(1032, GFP_ATOMIC);
  1669. if (!ver_addr) {
  1670. retvalue = ARCMSR_MESSAGE_FAIL;
  1671. goto message_out;
  1672. }
  1673. ptmpQbuffer = ver_addr;
  1674. while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
  1675. && (allxfer_len < 1031)) {
  1676. pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
  1677. memcpy(ptmpQbuffer, pQbuffer, 1);
  1678. acb->rqbuf_firstindex++;
  1679. acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
  1680. ptmpQbuffer++;
  1681. allxfer_len++;
  1682. }
  1683. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1684. struct QBUFFER __iomem *prbuffer;
  1685. uint8_t __iomem *iop_data;
  1686. int32_t iop_len;
  1687. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1688. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  1689. iop_data = prbuffer->data;
  1690. iop_len = readl(&prbuffer->data_len);
  1691. while (iop_len > 0) {
  1692. acb->rqbuffer[acb->rqbuf_lastindex] = readb(iop_data);
  1693. acb->rqbuf_lastindex++;
  1694. acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
  1695. iop_data++;
  1696. iop_len--;
  1697. }
  1698. arcmsr_iop_message_read(acb);
  1699. }
  1700. memcpy(pcmdmessagefld->messagedatabuffer, ver_addr, allxfer_len);
  1701. pcmdmessagefld->cmdmessage.Length = allxfer_len;
  1702. if(acb->fw_flag == FW_DEADLOCK) {
  1703. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  1704. }else{
  1705. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
  1706. }
  1707. kfree(ver_addr);
  1708. }
  1709. break;
  1710. case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
  1711. unsigned char *ver_addr;
  1712. int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
  1713. uint8_t *pQbuffer, *ptmpuserbuffer;
  1714. ver_addr = kmalloc(1032, GFP_ATOMIC);
  1715. if (!ver_addr) {
  1716. retvalue = ARCMSR_MESSAGE_FAIL;
  1717. goto message_out;
  1718. }
  1719. if(acb->fw_flag == FW_DEADLOCK) {
  1720. pcmdmessagefld->cmdmessage.ReturnCode =
  1721. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  1722. }else{
  1723. pcmdmessagefld->cmdmessage.ReturnCode =
  1724. ARCMSR_MESSAGE_RETURNCODE_OK;
  1725. }
  1726. ptmpuserbuffer = ver_addr;
  1727. user_len = pcmdmessagefld->cmdmessage.Length;
  1728. memcpy(ptmpuserbuffer, pcmdmessagefld->messagedatabuffer, user_len);
  1729. wqbuf_lastindex = acb->wqbuf_lastindex;
  1730. wqbuf_firstindex = acb->wqbuf_firstindex;
  1731. if (wqbuf_lastindex != wqbuf_firstindex) {
  1732. struct SENSE_DATA *sensebuffer =
  1733. (struct SENSE_DATA *)cmd->sense_buffer;
  1734. arcmsr_post_ioctldata2iop(acb);
  1735. /* has error report sensedata */
  1736. sensebuffer->ErrorCode = 0x70;
  1737. sensebuffer->SenseKey = ILLEGAL_REQUEST;
  1738. sensebuffer->AdditionalSenseLength = 0x0A;
  1739. sensebuffer->AdditionalSenseCode = 0x20;
  1740. sensebuffer->Valid = 1;
  1741. retvalue = ARCMSR_MESSAGE_FAIL;
  1742. } else {
  1743. my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
  1744. &(ARCMSR_MAX_QBUFFER - 1);
  1745. if (my_empty_len >= user_len) {
  1746. while (user_len > 0) {
  1747. pQbuffer =
  1748. &acb->wqbuffer[acb->wqbuf_lastindex];
  1749. memcpy(pQbuffer, ptmpuserbuffer, 1);
  1750. acb->wqbuf_lastindex++;
  1751. acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
  1752. ptmpuserbuffer++;
  1753. user_len--;
  1754. }
  1755. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
  1756. acb->acb_flags &=
  1757. ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
  1758. arcmsr_post_ioctldata2iop(acb);
  1759. }
  1760. } else {
  1761. /* has error report sensedata */
  1762. struct SENSE_DATA *sensebuffer =
  1763. (struct SENSE_DATA *)cmd->sense_buffer;
  1764. sensebuffer->ErrorCode = 0x70;
  1765. sensebuffer->SenseKey = ILLEGAL_REQUEST;
  1766. sensebuffer->AdditionalSenseLength = 0x0A;
  1767. sensebuffer->AdditionalSenseCode = 0x20;
  1768. sensebuffer->Valid = 1;
  1769. retvalue = ARCMSR_MESSAGE_FAIL;
  1770. }
  1771. }
  1772. kfree(ver_addr);
  1773. }
  1774. break;
  1775. case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
  1776. uint8_t *pQbuffer = acb->rqbuffer;
  1777. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1778. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1779. arcmsr_iop_message_read(acb);
  1780. }
  1781. acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
  1782. acb->rqbuf_firstindex = 0;
  1783. acb->rqbuf_lastindex = 0;
  1784. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  1785. if(acb->fw_flag == FW_DEADLOCK) {
  1786. pcmdmessagefld->cmdmessage.ReturnCode =
  1787. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  1788. }else{
  1789. pcmdmessagefld->cmdmessage.ReturnCode =
  1790. ARCMSR_MESSAGE_RETURNCODE_OK;
  1791. }
  1792. }
  1793. break;
  1794. case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
  1795. uint8_t *pQbuffer = acb->wqbuffer;
  1796. if(acb->fw_flag == FW_DEADLOCK) {
  1797. pcmdmessagefld->cmdmessage.ReturnCode =
  1798. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  1799. }else{
  1800. pcmdmessagefld->cmdmessage.ReturnCode =
  1801. ARCMSR_MESSAGE_RETURNCODE_OK;
  1802. }
  1803. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1804. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1805. arcmsr_iop_message_read(acb);
  1806. }
  1807. acb->acb_flags |=
  1808. (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  1809. ACB_F_MESSAGE_WQBUFFER_READED);
  1810. acb->wqbuf_firstindex = 0;
  1811. acb->wqbuf_lastindex = 0;
  1812. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  1813. }
  1814. break;
  1815. case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
  1816. uint8_t *pQbuffer;
  1817. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1818. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1819. arcmsr_iop_message_read(acb);
  1820. }
  1821. acb->acb_flags |=
  1822. (ACB_F_MESSAGE_WQBUFFER_CLEARED
  1823. | ACB_F_MESSAGE_RQBUFFER_CLEARED
  1824. | ACB_F_MESSAGE_WQBUFFER_READED);
  1825. acb->rqbuf_firstindex = 0;
  1826. acb->rqbuf_lastindex = 0;
  1827. acb->wqbuf_firstindex = 0;
  1828. acb->wqbuf_lastindex = 0;
  1829. pQbuffer = acb->rqbuffer;
  1830. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  1831. pQbuffer = acb->wqbuffer;
  1832. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  1833. if(acb->fw_flag == FW_DEADLOCK) {
  1834. pcmdmessagefld->cmdmessage.ReturnCode =
  1835. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  1836. }else{
  1837. pcmdmessagefld->cmdmessage.ReturnCode =
  1838. ARCMSR_MESSAGE_RETURNCODE_OK;
  1839. }
  1840. }
  1841. break;
  1842. case ARCMSR_MESSAGE_RETURN_CODE_3F: {
  1843. if(acb->fw_flag == FW_DEADLOCK) {
  1844. pcmdmessagefld->cmdmessage.ReturnCode =
  1845. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  1846. }else{
  1847. pcmdmessagefld->cmdmessage.ReturnCode =
  1848. ARCMSR_MESSAGE_RETURNCODE_3F;
  1849. }
  1850. break;
  1851. }
  1852. case ARCMSR_MESSAGE_SAY_HELLO: {
  1853. int8_t *hello_string = "Hello! I am ARCMSR";
  1854. if(acb->fw_flag == FW_DEADLOCK) {
  1855. pcmdmessagefld->cmdmessage.ReturnCode =
  1856. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  1857. }else{
  1858. pcmdmessagefld->cmdmessage.ReturnCode =
  1859. ARCMSR_MESSAGE_RETURNCODE_OK;
  1860. }
  1861. memcpy(pcmdmessagefld->messagedatabuffer, hello_string
  1862. , (int16_t)strlen(hello_string));
  1863. }
  1864. break;
  1865. case ARCMSR_MESSAGE_SAY_GOODBYE:
  1866. if(acb->fw_flag == FW_DEADLOCK) {
  1867. pcmdmessagefld->cmdmessage.ReturnCode =
  1868. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  1869. }
  1870. arcmsr_iop_parking(acb);
  1871. break;
  1872. case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
  1873. if(acb->fw_flag == FW_DEADLOCK) {
  1874. pcmdmessagefld->cmdmessage.ReturnCode =
  1875. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  1876. }
  1877. arcmsr_flush_adapter_cache(acb);
  1878. break;
  1879. default:
  1880. retvalue = ARCMSR_MESSAGE_FAIL;
  1881. }
  1882. message_out:
  1883. sg = scsi_sglist(cmd);
  1884. kunmap_atomic(buffer - sg->offset, KM_IRQ0);
  1885. return retvalue;
  1886. }
  1887. static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
  1888. {
  1889. struct list_head *head = &acb->ccb_free_list;
  1890. struct CommandControlBlock *ccb = NULL;
  1891. unsigned long flags;
  1892. spin_lock_irqsave(&acb->ccblist_lock, flags);
  1893. if (!list_empty(head)) {
  1894. ccb = list_entry(head->next, struct CommandControlBlock, list);
  1895. list_del_init(&ccb->list);
  1896. }else{
  1897. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  1898. return 0;
  1899. }
  1900. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  1901. return ccb;
  1902. }
  1903. static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
  1904. struct scsi_cmnd *cmd)
  1905. {
  1906. switch (cmd->cmnd[0]) {
  1907. case INQUIRY: {
  1908. unsigned char inqdata[36];
  1909. char *buffer;
  1910. struct scatterlist *sg;
  1911. if (cmd->device->lun) {
  1912. cmd->result = (DID_TIME_OUT << 16);
  1913. cmd->scsi_done(cmd);
  1914. return;
  1915. }
  1916. inqdata[0] = TYPE_PROCESSOR;
  1917. /* Periph Qualifier & Periph Dev Type */
  1918. inqdata[1] = 0;
  1919. /* rem media bit & Dev Type Modifier */
  1920. inqdata[2] = 0;
  1921. /* ISO, ECMA, & ANSI versions */
  1922. inqdata[4] = 31;
  1923. /* length of additional data */
  1924. strncpy(&inqdata[8], "Areca ", 8);
  1925. /* Vendor Identification */
  1926. strncpy(&inqdata[16], "RAID controller ", 16);
  1927. /* Product Identification */
  1928. strncpy(&inqdata[32], "R001", 4); /* Product Revision */
  1929. sg = scsi_sglist(cmd);
  1930. buffer = kmap_atomic(sg_page(sg), KM_IRQ0) + sg->offset;
  1931. memcpy(buffer, inqdata, sizeof(inqdata));
  1932. sg = scsi_sglist(cmd);
  1933. kunmap_atomic(buffer - sg->offset, KM_IRQ0);
  1934. cmd->scsi_done(cmd);
  1935. }
  1936. break;
  1937. case WRITE_BUFFER:
  1938. case READ_BUFFER: {
  1939. if (arcmsr_iop_message_xfer(acb, cmd))
  1940. cmd->result = (DID_ERROR << 16);
  1941. cmd->scsi_done(cmd);
  1942. }
  1943. break;
  1944. default:
  1945. cmd->scsi_done(cmd);
  1946. }
  1947. }
  1948. static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd,
  1949. void (* done)(struct scsi_cmnd *))
  1950. {
  1951. struct Scsi_Host *host = cmd->device->host;
  1952. struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
  1953. struct CommandControlBlock *ccb;
  1954. int target = cmd->device->id;
  1955. int lun = cmd->device->lun;
  1956. uint8_t scsicmd = cmd->cmnd[0];
  1957. cmd->scsi_done = done;
  1958. cmd->host_scribble = NULL;
  1959. cmd->result = 0;
  1960. if ((scsicmd == SYNCHRONIZE_CACHE) ||(scsicmd == SEND_DIAGNOSTIC)){
  1961. if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
  1962. cmd->result = (DID_NO_CONNECT << 16);
  1963. }
  1964. cmd->scsi_done(cmd);
  1965. return 0;
  1966. }
  1967. if (target == 16) {
  1968. /* virtual device for iop message transfer */
  1969. arcmsr_handle_virtual_command(acb, cmd);
  1970. return 0;
  1971. }
  1972. if (atomic_read(&acb->ccboutstandingcount) >=
  1973. ARCMSR_MAX_OUTSTANDING_CMD)
  1974. return SCSI_MLQUEUE_HOST_BUSY;
  1975. if ((scsicmd == SCSI_CMD_ARECA_SPECIFIC)) {
  1976. printk(KERN_NOTICE "Receiveing SCSI_CMD_ARECA_SPECIFIC command..\n");
  1977. return 0;
  1978. }
  1979. ccb = arcmsr_get_freeccb(acb);
  1980. if (!ccb)
  1981. return SCSI_MLQUEUE_HOST_BUSY;
  1982. if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) {
  1983. cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1);
  1984. cmd->scsi_done(cmd);
  1985. return 0;
  1986. }
  1987. arcmsr_post_ccb(acb, ccb);
  1988. return 0;
  1989. }
  1990. static DEF_SCSI_QCMD(arcmsr_queue_command)
  1991. static bool arcmsr_get_hba_config(struct AdapterControlBlock *acb)
  1992. {
  1993. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1994. char *acb_firm_model = acb->firm_model;
  1995. char *acb_firm_version = acb->firm_version;
  1996. char *acb_device_map = acb->device_map;
  1997. char __iomem *iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]);
  1998. char __iomem *iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]);
  1999. char __iomem *iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]);
  2000. int count;
  2001. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  2002. if (!arcmsr_hba_wait_msgint_ready(acb)) {
  2003. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  2004. miscellaneous data' timeout \n", acb->host->host_no);
  2005. return false;
  2006. }
  2007. count = 8;
  2008. while (count){
  2009. *acb_firm_model = readb(iop_firm_model);
  2010. acb_firm_model++;
  2011. iop_firm_model++;
  2012. count--;
  2013. }
  2014. count = 16;
  2015. while (count){
  2016. *acb_firm_version = readb(iop_firm_version);
  2017. acb_firm_version++;
  2018. iop_firm_version++;
  2019. count--;
  2020. }
  2021. count=16;
  2022. while(count){
  2023. *acb_device_map = readb(iop_device_map);
  2024. acb_device_map++;
  2025. iop_device_map++;
  2026. count--;
  2027. }
  2028. printk(KERN_NOTICE "Areca RAID Controller%d: F/W %s & Model %s\n",
  2029. acb->host->host_no,
  2030. acb->firm_version,
  2031. acb->firm_model);
  2032. acb->signature = readl(&reg->message_rwbuffer[0]);
  2033. acb->firm_request_len = readl(&reg->message_rwbuffer[1]);
  2034. acb->firm_numbers_queue = readl(&reg->message_rwbuffer[2]);
  2035. acb->firm_sdram_size = readl(&reg->message_rwbuffer[3]);
  2036. acb->firm_hd_channels = readl(&reg->message_rwbuffer[4]);
  2037. acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
  2038. return true;
  2039. }
  2040. static bool arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
  2041. {
  2042. struct MessageUnit_B *reg = acb->pmuB;
  2043. struct pci_dev *pdev = acb->pdev;
  2044. void *dma_coherent;
  2045. dma_addr_t dma_coherent_handle;
  2046. char *acb_firm_model = acb->firm_model;
  2047. char *acb_firm_version = acb->firm_version;
  2048. char *acb_device_map = acb->device_map;
  2049. char __iomem *iop_firm_model;
  2050. /*firm_model,15,60-67*/
  2051. char __iomem *iop_firm_version;
  2052. /*firm_version,17,68-83*/
  2053. char __iomem *iop_device_map;
  2054. /*firm_version,21,84-99*/
  2055. int count;
  2056. dma_coherent = dma_alloc_coherent(&pdev->dev, sizeof(struct MessageUnit_B), &dma_coherent_handle, GFP_KERNEL);
  2057. if (!dma_coherent){
  2058. printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error for hbb mu\n", acb->host->host_no);
  2059. return false;
  2060. }
  2061. acb->dma_coherent_handle_hbb_mu = dma_coherent_handle;
  2062. reg = (struct MessageUnit_B *)dma_coherent;
  2063. acb->pmuB = reg;
  2064. reg->drv2iop_doorbell= (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL);
  2065. reg->drv2iop_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL_MASK);
  2066. reg->iop2drv_doorbell = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL);
  2067. reg->iop2drv_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL_MASK);
  2068. reg->message_wbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_WBUFFER);
  2069. reg->message_rbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RBUFFER);
  2070. reg->message_rwbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RWBUFFER);
  2071. iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]); /*firm_model,15,60-67*/
  2072. iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]); /*firm_version,17,68-83*/
  2073. iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]); /*firm_version,21,84-99*/
  2074. writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
  2075. if (!arcmsr_hbb_wait_msgint_ready(acb)) {
  2076. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  2077. miscellaneous data' timeout \n", acb->host->host_no);
  2078. return false;
  2079. }
  2080. count = 8;
  2081. while (count){
  2082. *acb_firm_model = readb(iop_firm_model);
  2083. acb_firm_model++;
  2084. iop_firm_model++;
  2085. count--;
  2086. }
  2087. count = 16;
  2088. while (count){
  2089. *acb_firm_version = readb(iop_firm_version);
  2090. acb_firm_version++;
  2091. iop_firm_version++;
  2092. count--;
  2093. }
  2094. count = 16;
  2095. while(count){
  2096. *acb_device_map = readb(iop_device_map);
  2097. acb_device_map++;
  2098. iop_device_map++;
  2099. count--;
  2100. }
  2101. printk(KERN_NOTICE "Areca RAID Controller%d: F/W %s & Model %s\n",
  2102. acb->host->host_no,
  2103. acb->firm_version,
  2104. acb->firm_model);
  2105. acb->signature = readl(&reg->message_rwbuffer[1]);
  2106. /*firm_signature,1,00-03*/
  2107. acb->firm_request_len = readl(&reg->message_rwbuffer[2]);
  2108. /*firm_request_len,1,04-07*/
  2109. acb->firm_numbers_queue = readl(&reg->message_rwbuffer[3]);
  2110. /*firm_numbers_queue,2,08-11*/
  2111. acb->firm_sdram_size = readl(&reg->message_rwbuffer[4]);
  2112. /*firm_sdram_size,3,12-15*/
  2113. acb->firm_hd_channels = readl(&reg->message_rwbuffer[5]);
  2114. /*firm_ide_channels,4,16-19*/
  2115. acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
  2116. /*firm_ide_channels,4,16-19*/
  2117. return true;
  2118. }
  2119. static bool arcmsr_get_hbc_config(struct AdapterControlBlock *pACB)
  2120. {
  2121. uint32_t intmask_org, Index, firmware_state = 0;
  2122. struct MessageUnit_C *reg = pACB->pmuC;
  2123. char *acb_firm_model = pACB->firm_model;
  2124. char *acb_firm_version = pACB->firm_version;
  2125. char *iop_firm_model = (char *)(&reg->msgcode_rwbuffer[15]); /*firm_model,15,60-67*/
  2126. char *iop_firm_version = (char *)(&reg->msgcode_rwbuffer[17]); /*firm_version,17,68-83*/
  2127. int count;
  2128. /* disable all outbound interrupt */
  2129. intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
  2130. writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
  2131. /* wait firmware ready */
  2132. do {
  2133. firmware_state = readl(&reg->outbound_msgaddr1);
  2134. } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
  2135. /* post "get config" instruction */
  2136. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  2137. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  2138. /* wait message ready */
  2139. for (Index = 0; Index < 2000; Index++) {
  2140. if (readl(&reg->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
  2141. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);/*clear interrupt*/
  2142. break;
  2143. }
  2144. udelay(10);
  2145. } /*max 1 seconds*/
  2146. if (Index >= 2000) {
  2147. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  2148. miscellaneous data' timeout \n", pACB->host->host_no);
  2149. return false;
  2150. }
  2151. count = 8;
  2152. while (count) {
  2153. *acb_firm_model = readb(iop_firm_model);
  2154. acb_firm_model++;
  2155. iop_firm_model++;
  2156. count--;
  2157. }
  2158. count = 16;
  2159. while (count) {
  2160. *acb_firm_version = readb(iop_firm_version);
  2161. acb_firm_version++;
  2162. iop_firm_version++;
  2163. count--;
  2164. }
  2165. printk(KERN_NOTICE "Areca RAID Controller%d: F/W %s & Model %s\n",
  2166. pACB->host->host_no,
  2167. pACB->firm_version,
  2168. pACB->firm_model);
  2169. pACB->firm_request_len = readl(&reg->msgcode_rwbuffer[1]); /*firm_request_len,1,04-07*/
  2170. pACB->firm_numbers_queue = readl(&reg->msgcode_rwbuffer[2]); /*firm_numbers_queue,2,08-11*/
  2171. pACB->firm_sdram_size = readl(&reg->msgcode_rwbuffer[3]); /*firm_sdram_size,3,12-15*/
  2172. pACB->firm_hd_channels = readl(&reg->msgcode_rwbuffer[4]); /*firm_ide_channels,4,16-19*/
  2173. pACB->firm_cfg_version = readl(&reg->msgcode_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
  2174. /*all interrupt service will be enable at arcmsr_iop_init*/
  2175. return true;
  2176. }
  2177. static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
  2178. {
  2179. if (acb->adapter_type == ACB_ADAPTER_TYPE_A)
  2180. return arcmsr_get_hba_config(acb);
  2181. else if (acb->adapter_type == ACB_ADAPTER_TYPE_B)
  2182. return arcmsr_get_hbb_config(acb);
  2183. else
  2184. return arcmsr_get_hbc_config(acb);
  2185. }
  2186. static int arcmsr_polling_hba_ccbdone(struct AdapterControlBlock *acb,
  2187. struct CommandControlBlock *poll_ccb)
  2188. {
  2189. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2190. struct CommandControlBlock *ccb;
  2191. struct ARCMSR_CDB *arcmsr_cdb;
  2192. uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
  2193. int rtn;
  2194. bool error;
  2195. polling_hba_ccb_retry:
  2196. poll_count++;
  2197. outbound_intstatus = readl(&reg->outbound_intstatus) & acb->outbound_int_enable;
  2198. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  2199. while (1) {
  2200. if ((flag_ccb = readl(&reg->outbound_queueport)) == 0xFFFFFFFF) {
  2201. if (poll_ccb_done){
  2202. rtn = SUCCESS;
  2203. break;
  2204. }else {
  2205. msleep(25);
  2206. if (poll_count > 100){
  2207. rtn = FAILED;
  2208. break;
  2209. }
  2210. goto polling_hba_ccb_retry;
  2211. }
  2212. }
  2213. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
  2214. ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  2215. poll_ccb_done = (ccb == poll_ccb) ? 1:0;
  2216. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  2217. if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
  2218. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  2219. " poll command abort successfully \n"
  2220. , acb->host->host_no
  2221. , ccb->pcmd->device->id
  2222. , ccb->pcmd->device->lun
  2223. , ccb);
  2224. ccb->pcmd->result = DID_ABORT << 16;
  2225. arcmsr_ccb_complete(ccb);
  2226. continue;
  2227. }
  2228. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  2229. " command done ccb = '0x%p'"
  2230. "ccboutstandingcount = %d \n"
  2231. , acb->host->host_no
  2232. , ccb
  2233. , atomic_read(&acb->ccboutstandingcount));
  2234. continue;
  2235. }
  2236. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  2237. arcmsr_report_ccb_state(acb, ccb, error);
  2238. }
  2239. return rtn;
  2240. }
  2241. static int arcmsr_polling_hbb_ccbdone(struct AdapterControlBlock *acb,
  2242. struct CommandControlBlock *poll_ccb)
  2243. {
  2244. struct MessageUnit_B *reg = acb->pmuB;
  2245. struct ARCMSR_CDB *arcmsr_cdb;
  2246. struct CommandControlBlock *ccb;
  2247. uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
  2248. int index, rtn;
  2249. bool error;
  2250. polling_hbb_ccb_retry:
  2251. poll_count++;
  2252. /* clear doorbell interrupt */
  2253. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  2254. while(1){
  2255. index = reg->doneq_index;
  2256. if ((flag_ccb = readl(&reg->done_qbuffer[index])) == 0) {
  2257. if (poll_ccb_done){
  2258. rtn = SUCCESS;
  2259. break;
  2260. }else {
  2261. msleep(25);
  2262. if (poll_count > 100){
  2263. rtn = FAILED;
  2264. break;
  2265. }
  2266. goto polling_hbb_ccb_retry;
  2267. }
  2268. }
  2269. writel(0, &reg->done_qbuffer[index]);
  2270. index++;
  2271. /*if last index number set it to 0 */
  2272. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  2273. reg->doneq_index = index;
  2274. /* check if command done with no error*/
  2275. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
  2276. ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  2277. poll_ccb_done = (ccb == poll_ccb) ? 1:0;
  2278. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  2279. if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
  2280. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  2281. " poll command abort successfully \n"
  2282. ,acb->host->host_no
  2283. ,ccb->pcmd->device->id
  2284. ,ccb->pcmd->device->lun
  2285. ,ccb);
  2286. ccb->pcmd->result = DID_ABORT << 16;
  2287. arcmsr_ccb_complete(ccb);
  2288. continue;
  2289. }
  2290. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  2291. " command done ccb = '0x%p'"
  2292. "ccboutstandingcount = %d \n"
  2293. , acb->host->host_no
  2294. , ccb
  2295. , atomic_read(&acb->ccboutstandingcount));
  2296. continue;
  2297. }
  2298. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  2299. arcmsr_report_ccb_state(acb, ccb, error);
  2300. }
  2301. return rtn;
  2302. }
  2303. static int arcmsr_polling_hbc_ccbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_ccb)
  2304. {
  2305. struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
  2306. uint32_t flag_ccb, ccb_cdb_phy;
  2307. struct ARCMSR_CDB *arcmsr_cdb;
  2308. bool error;
  2309. struct CommandControlBlock *pCCB;
  2310. uint32_t poll_ccb_done = 0, poll_count = 0;
  2311. int rtn;
  2312. polling_hbc_ccb_retry:
  2313. poll_count++;
  2314. while (1) {
  2315. if ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {
  2316. if (poll_ccb_done) {
  2317. rtn = SUCCESS;
  2318. break;
  2319. } else {
  2320. msleep(25);
  2321. if (poll_count > 100) {
  2322. rtn = FAILED;
  2323. break;
  2324. }
  2325. goto polling_hbc_ccb_retry;
  2326. }
  2327. }
  2328. flag_ccb = readl(&reg->outbound_queueport_low);
  2329. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  2330. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);/*frame must be 32 bytes aligned*/
  2331. pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  2332. poll_ccb_done = (pCCB == poll_ccb) ? 1 : 0;
  2333. /* check ifcommand done with no error*/
  2334. if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
  2335. if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
  2336. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  2337. " poll command abort successfully \n"
  2338. , acb->host->host_no
  2339. , pCCB->pcmd->device->id
  2340. , pCCB->pcmd->device->lun
  2341. , pCCB);
  2342. pCCB->pcmd->result = DID_ABORT << 16;
  2343. arcmsr_ccb_complete(pCCB);
  2344. continue;
  2345. }
  2346. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  2347. " command done ccb = '0x%p'"
  2348. "ccboutstandingcount = %d \n"
  2349. , acb->host->host_no
  2350. , pCCB
  2351. , atomic_read(&acb->ccboutstandingcount));
  2352. continue;
  2353. }
  2354. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
  2355. arcmsr_report_ccb_state(acb, pCCB, error);
  2356. }
  2357. return rtn;
  2358. }
  2359. static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
  2360. struct CommandControlBlock *poll_ccb)
  2361. {
  2362. int rtn = 0;
  2363. switch (acb->adapter_type) {
  2364. case ACB_ADAPTER_TYPE_A: {
  2365. rtn = arcmsr_polling_hba_ccbdone(acb, poll_ccb);
  2366. }
  2367. break;
  2368. case ACB_ADAPTER_TYPE_B: {
  2369. rtn = arcmsr_polling_hbb_ccbdone(acb, poll_ccb);
  2370. }
  2371. break;
  2372. case ACB_ADAPTER_TYPE_C: {
  2373. rtn = arcmsr_polling_hbc_ccbdone(acb, poll_ccb);
  2374. }
  2375. }
  2376. return rtn;
  2377. }
  2378. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
  2379. {
  2380. uint32_t cdb_phyaddr, cdb_phyaddr_hi32;
  2381. dma_addr_t dma_coherent_handle;
  2382. /*
  2383. ********************************************************************
  2384. ** here we need to tell iop 331 our freeccb.HighPart
  2385. ** if freeccb.HighPart is not zero
  2386. ********************************************************************
  2387. */
  2388. dma_coherent_handle = acb->dma_coherent_handle;
  2389. cdb_phyaddr = (uint32_t)(dma_coherent_handle);
  2390. cdb_phyaddr_hi32 = (uint32_t)((cdb_phyaddr >> 16) >> 16);
  2391. acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32;
  2392. /*
  2393. ***********************************************************************
  2394. ** if adapter type B, set window of "post command Q"
  2395. ***********************************************************************
  2396. */
  2397. switch (acb->adapter_type) {
  2398. case ACB_ADAPTER_TYPE_A: {
  2399. if (cdb_phyaddr_hi32 != 0) {
  2400. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2401. uint32_t intmask_org;
  2402. intmask_org = arcmsr_disable_outbound_ints(acb);
  2403. writel(ARCMSR_SIGNATURE_SET_CONFIG, \
  2404. &reg->message_rwbuffer[0]);
  2405. writel(cdb_phyaddr_hi32, &reg->message_rwbuffer[1]);
  2406. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
  2407. &reg->inbound_msgaddr0);
  2408. if (!arcmsr_hba_wait_msgint_ready(acb)) {
  2409. printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
  2410. part physical address timeout\n",
  2411. acb->host->host_no);
  2412. return 1;
  2413. }
  2414. arcmsr_enable_outbound_ints(acb, intmask_org);
  2415. }
  2416. }
  2417. break;
  2418. case ACB_ADAPTER_TYPE_B: {
  2419. unsigned long post_queue_phyaddr;
  2420. uint32_t __iomem *rwbuffer;
  2421. struct MessageUnit_B *reg = acb->pmuB;
  2422. uint32_t intmask_org;
  2423. intmask_org = arcmsr_disable_outbound_ints(acb);
  2424. reg->postq_index = 0;
  2425. reg->doneq_index = 0;
  2426. writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell);
  2427. if (!arcmsr_hbb_wait_msgint_ready(acb)) {
  2428. printk(KERN_NOTICE "arcmsr%d:can not set diver mode\n", \
  2429. acb->host->host_no);
  2430. return 1;
  2431. }
  2432. post_queue_phyaddr = acb->dma_coherent_handle_hbb_mu;
  2433. rwbuffer = reg->message_rwbuffer;
  2434. /* driver "set config" signature */
  2435. writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
  2436. /* normal should be zero */
  2437. writel(cdb_phyaddr_hi32, rwbuffer++);
  2438. /* postQ size (256 + 8)*4 */
  2439. writel(post_queue_phyaddr, rwbuffer++);
  2440. /* doneQ size (256 + 8)*4 */
  2441. writel(post_queue_phyaddr + 1056, rwbuffer++);
  2442. /* ccb maxQ size must be --> [(256 + 8)*4]*/
  2443. writel(1056, rwbuffer);
  2444. writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell);
  2445. if (!arcmsr_hbb_wait_msgint_ready(acb)) {
  2446. printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
  2447. timeout \n",acb->host->host_no);
  2448. return 1;
  2449. }
  2450. arcmsr_hbb_enable_driver_mode(acb);
  2451. arcmsr_enable_outbound_ints(acb, intmask_org);
  2452. }
  2453. break;
  2454. case ACB_ADAPTER_TYPE_C: {
  2455. if (cdb_phyaddr_hi32 != 0) {
  2456. struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
  2457. if (cdb_phyaddr_hi32 != 0) {
  2458. unsigned char Retries = 0x00;
  2459. do {
  2460. printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x \n", acb->adapter_index, cdb_phyaddr_hi32);
  2461. } while (Retries++ < 100);
  2462. }
  2463. writel(ARCMSR_SIGNATURE_SET_CONFIG, &reg->msgcode_rwbuffer[0]);
  2464. writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[1]);
  2465. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
  2466. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  2467. if (!arcmsr_hbc_wait_msgint_ready(acb)) {
  2468. printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
  2469. timeout \n", acb->host->host_no);
  2470. return 1;
  2471. }
  2472. }
  2473. }
  2474. }
  2475. return 0;
  2476. }
  2477. static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
  2478. {
  2479. uint32_t firmware_state = 0;
  2480. switch (acb->adapter_type) {
  2481. case ACB_ADAPTER_TYPE_A: {
  2482. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2483. do {
  2484. firmware_state = readl(&reg->outbound_msgaddr1);
  2485. } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
  2486. }
  2487. break;
  2488. case ACB_ADAPTER_TYPE_B: {
  2489. struct MessageUnit_B *reg = acb->pmuB;
  2490. do {
  2491. firmware_state = readl(reg->iop2drv_doorbell);
  2492. } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
  2493. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
  2494. }
  2495. break;
  2496. case ACB_ADAPTER_TYPE_C: {
  2497. struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
  2498. do {
  2499. firmware_state = readl(&reg->outbound_msgaddr1);
  2500. } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
  2501. }
  2502. }
  2503. }
  2504. static void arcmsr_request_hba_device_map(struct AdapterControlBlock *acb)
  2505. {
  2506. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2507. if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
  2508. return;
  2509. } else {
  2510. acb->fw_flag = FW_NORMAL;
  2511. if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)){
  2512. atomic_set(&acb->rq_map_token, 16);
  2513. }
  2514. atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
  2515. if (atomic_dec_and_test(&acb->rq_map_token))
  2516. return;
  2517. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  2518. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  2519. }
  2520. return;
  2521. }
  2522. static void arcmsr_request_hbb_device_map(struct AdapterControlBlock *acb)
  2523. {
  2524. struct MessageUnit_B __iomem *reg = acb->pmuB;
  2525. if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
  2526. return;
  2527. } else {
  2528. acb->fw_flag = FW_NORMAL;
  2529. if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
  2530. atomic_set(&acb->rq_map_token,16);
  2531. }
  2532. atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
  2533. if(atomic_dec_and_test(&acb->rq_map_token))
  2534. return;
  2535. writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
  2536. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  2537. }
  2538. return;
  2539. }
  2540. static void arcmsr_request_hbc_device_map(struct AdapterControlBlock *acb)
  2541. {
  2542. struct MessageUnit_C __iomem *reg = acb->pmuC;
  2543. if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0) || ((acb->acb_flags & ACB_F_ABORT) != 0)) {
  2544. return;
  2545. } else {
  2546. acb->fw_flag = FW_NORMAL;
  2547. if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
  2548. atomic_set(&acb->rq_map_token, 16);
  2549. }
  2550. atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
  2551. if (atomic_dec_and_test(&acb->rq_map_token))
  2552. return;
  2553. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  2554. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  2555. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  2556. }
  2557. return;
  2558. }
  2559. static void arcmsr_request_device_map(unsigned long pacb)
  2560. {
  2561. struct AdapterControlBlock *acb = (struct AdapterControlBlock *)pacb;
  2562. switch (acb->adapter_type) {
  2563. case ACB_ADAPTER_TYPE_A: {
  2564. arcmsr_request_hba_device_map(acb);
  2565. }
  2566. break;
  2567. case ACB_ADAPTER_TYPE_B: {
  2568. arcmsr_request_hbb_device_map(acb);
  2569. }
  2570. break;
  2571. case ACB_ADAPTER_TYPE_C: {
  2572. arcmsr_request_hbc_device_map(acb);
  2573. }
  2574. }
  2575. }
  2576. static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
  2577. {
  2578. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2579. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  2580. writel(ARCMSR_INBOUND_MESG0_START_BGRB, &reg->inbound_msgaddr0);
  2581. if (!arcmsr_hba_wait_msgint_ready(acb)) {
  2582. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  2583. rebulid' timeout \n", acb->host->host_no);
  2584. }
  2585. }
  2586. static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
  2587. {
  2588. struct MessageUnit_B *reg = acb->pmuB;
  2589. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  2590. writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell);
  2591. if (!arcmsr_hbb_wait_msgint_ready(acb)) {
  2592. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  2593. rebulid' timeout \n",acb->host->host_no);
  2594. }
  2595. }
  2596. static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *pACB)
  2597. {
  2598. struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)pACB->pmuC;
  2599. pACB->acb_flags |= ACB_F_MSG_START_BGRB;
  2600. writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0);
  2601. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell);
  2602. if (!arcmsr_hbc_wait_msgint_ready(pACB)) {
  2603. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  2604. rebulid' timeout \n", pACB->host->host_no);
  2605. }
  2606. return;
  2607. }
  2608. static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
  2609. {
  2610. switch (acb->adapter_type) {
  2611. case ACB_ADAPTER_TYPE_A:
  2612. arcmsr_start_hba_bgrb(acb);
  2613. break;
  2614. case ACB_ADAPTER_TYPE_B:
  2615. arcmsr_start_hbb_bgrb(acb);
  2616. break;
  2617. case ACB_ADAPTER_TYPE_C:
  2618. arcmsr_start_hbc_bgrb(acb);
  2619. }
  2620. }
  2621. static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
  2622. {
  2623. switch (acb->adapter_type) {
  2624. case ACB_ADAPTER_TYPE_A: {
  2625. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2626. uint32_t outbound_doorbell;
  2627. /* empty doorbell Qbuffer if door bell ringed */
  2628. outbound_doorbell = readl(&reg->outbound_doorbell);
  2629. /*clear doorbell interrupt */
  2630. writel(outbound_doorbell, &reg->outbound_doorbell);
  2631. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  2632. }
  2633. break;
  2634. case ACB_ADAPTER_TYPE_B: {
  2635. struct MessageUnit_B *reg = acb->pmuB;
  2636. /*clear interrupt and message state*/
  2637. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  2638. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
  2639. /* let IOP know data has been read */
  2640. }
  2641. break;
  2642. case ACB_ADAPTER_TYPE_C: {
  2643. struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
  2644. uint32_t outbound_doorbell;
  2645. /* empty doorbell Qbuffer if door bell ringed */
  2646. outbound_doorbell = readl(&reg->outbound_doorbell);
  2647. writel(outbound_doorbell, &reg->outbound_doorbell_clear);
  2648. writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
  2649. }
  2650. }
  2651. }
  2652. static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
  2653. {
  2654. switch (acb->adapter_type) {
  2655. case ACB_ADAPTER_TYPE_A:
  2656. return;
  2657. case ACB_ADAPTER_TYPE_B:
  2658. {
  2659. struct MessageUnit_B *reg = acb->pmuB;
  2660. writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell);
  2661. if (!arcmsr_hbb_wait_msgint_ready(acb)) {
  2662. printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
  2663. return;
  2664. }
  2665. }
  2666. break;
  2667. case ACB_ADAPTER_TYPE_C:
  2668. return;
  2669. }
  2670. return;
  2671. }
  2672. static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
  2673. {
  2674. uint8_t value[64];
  2675. int i, count = 0;
  2676. struct MessageUnit_A __iomem *pmuA = acb->pmuA;
  2677. struct MessageUnit_C __iomem *pmuC = acb->pmuC;
  2678. u32 temp = 0;
  2679. /* backup pci config data */
  2680. printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
  2681. for (i = 0; i < 64; i++) {
  2682. pci_read_config_byte(acb->pdev, i, &value[i]);
  2683. }
  2684. /* hardware reset signal */
  2685. if ((acb->dev_id == 0x1680)) {
  2686. writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]);
  2687. } else if ((acb->dev_id == 0x1880)) {
  2688. do {
  2689. count++;
  2690. writel(0xF, &pmuC->write_sequence);
  2691. writel(0x4, &pmuC->write_sequence);
  2692. writel(0xB, &pmuC->write_sequence);
  2693. writel(0x2, &pmuC->write_sequence);
  2694. writel(0x7, &pmuC->write_sequence);
  2695. writel(0xD, &pmuC->write_sequence);
  2696. } while ((((temp = readl(&pmuC->host_diagnostic)) | ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
  2697. writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
  2698. } else {
  2699. pci_write_config_byte(acb->pdev, 0x84, 0x20);
  2700. }
  2701. msleep(2000);
  2702. /* write back pci config data */
  2703. for (i = 0; i < 64; i++) {
  2704. pci_write_config_byte(acb->pdev, i, value[i]);
  2705. }
  2706. msleep(1000);
  2707. return;
  2708. }
  2709. static void arcmsr_iop_init(struct AdapterControlBlock *acb)
  2710. {
  2711. uint32_t intmask_org;
  2712. /* disable all outbound interrupt */
  2713. intmask_org = arcmsr_disable_outbound_ints(acb);
  2714. arcmsr_wait_firmware_ready(acb);
  2715. arcmsr_iop_confirm(acb);
  2716. /*start background rebuild*/
  2717. arcmsr_start_adapter_bgrb(acb);
  2718. /* empty doorbell Qbuffer if door bell ringed */
  2719. arcmsr_clear_doorbell_queue_buffer(acb);
  2720. arcmsr_enable_eoi_mode(acb);
  2721. /* enable outbound Post Queue,outbound doorbell Interrupt */
  2722. arcmsr_enable_outbound_ints(acb, intmask_org);
  2723. acb->acb_flags |= ACB_F_IOP_INITED;
  2724. }
  2725. static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb)
  2726. {
  2727. struct CommandControlBlock *ccb;
  2728. uint32_t intmask_org;
  2729. uint8_t rtnval = 0x00;
  2730. int i = 0;
  2731. if (atomic_read(&acb->ccboutstandingcount) != 0) {
  2732. /* disable all outbound interrupt */
  2733. intmask_org = arcmsr_disable_outbound_ints(acb);
  2734. /* talk to iop 331 outstanding command aborted */
  2735. rtnval = arcmsr_abort_allcmd(acb);
  2736. /* clear all outbound posted Q */
  2737. arcmsr_done4abort_postqueue(acb);
  2738. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  2739. ccb = acb->pccb_pool[i];
  2740. if (ccb->startdone == ARCMSR_CCB_START) {
  2741. arcmsr_ccb_complete(ccb);
  2742. }
  2743. }
  2744. atomic_set(&acb->ccboutstandingcount, 0);
  2745. /* enable all outbound interrupt */
  2746. arcmsr_enable_outbound_ints(acb, intmask_org);
  2747. return rtnval;
  2748. }
  2749. return rtnval;
  2750. }
  2751. static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
  2752. {
  2753. struct AdapterControlBlock *acb =
  2754. (struct AdapterControlBlock *)cmd->device->host->hostdata;
  2755. uint32_t intmask_org, outbound_doorbell;
  2756. int retry_count = 0;
  2757. int rtn = FAILED;
  2758. acb = (struct AdapterControlBlock *) cmd->device->host->hostdata;
  2759. printk(KERN_ERR "arcmsr: executing bus reset eh.....num_resets = %d, num_aborts = %d \n", acb->num_resets, acb->num_aborts);
  2760. acb->num_resets++;
  2761. switch(acb->adapter_type){
  2762. case ACB_ADAPTER_TYPE_A:{
  2763. if (acb->acb_flags & ACB_F_BUS_RESET){
  2764. long timeout;
  2765. printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
  2766. timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
  2767. if (timeout) {
  2768. return SUCCESS;
  2769. }
  2770. }
  2771. acb->acb_flags |= ACB_F_BUS_RESET;
  2772. if (!arcmsr_iop_reset(acb)) {
  2773. struct MessageUnit_A __iomem *reg;
  2774. reg = acb->pmuA;
  2775. arcmsr_hardware_reset(acb);
  2776. acb->acb_flags &= ~ACB_F_IOP_INITED;
  2777. sleep_again:
  2778. arcmsr_sleep_for_bus_reset(cmd);
  2779. if ((readl(&reg->outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) {
  2780. printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d \n", acb->host->host_no, retry_count);
  2781. if (retry_count > retrycount) {
  2782. acb->fw_flag = FW_DEADLOCK;
  2783. printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!! \n", acb->host->host_no);
  2784. return FAILED;
  2785. }
  2786. retry_count++;
  2787. goto sleep_again;
  2788. }
  2789. acb->acb_flags |= ACB_F_IOP_INITED;
  2790. /* disable all outbound interrupt */
  2791. intmask_org = arcmsr_disable_outbound_ints(acb);
  2792. arcmsr_get_firmware_spec(acb);
  2793. arcmsr_start_adapter_bgrb(acb);
  2794. /* clear Qbuffer if door bell ringed */
  2795. outbound_doorbell = readl(&reg->outbound_doorbell);
  2796. writel(outbound_doorbell, &reg->outbound_doorbell); /*clear interrupt */
  2797. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  2798. /* enable outbound Post Queue,outbound doorbell Interrupt */
  2799. arcmsr_enable_outbound_ints(acb, intmask_org);
  2800. atomic_set(&acb->rq_map_token, 16);
  2801. atomic_set(&acb->ante_token_value, 16);
  2802. acb->fw_flag = FW_NORMAL;
  2803. init_timer(&acb->eternal_timer);
  2804. acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6*HZ);
  2805. acb->eternal_timer.data = (unsigned long) acb;
  2806. acb->eternal_timer.function = &arcmsr_request_device_map;
  2807. add_timer(&acb->eternal_timer);
  2808. acb->acb_flags &= ~ACB_F_BUS_RESET;
  2809. rtn = SUCCESS;
  2810. printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
  2811. } else {
  2812. acb->acb_flags &= ~ACB_F_BUS_RESET;
  2813. if (atomic_read(&acb->rq_map_token) == 0) {
  2814. atomic_set(&acb->rq_map_token, 16);
  2815. atomic_set(&acb->ante_token_value, 16);
  2816. acb->fw_flag = FW_NORMAL;
  2817. init_timer(&acb->eternal_timer);
  2818. acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6*HZ);
  2819. acb->eternal_timer.data = (unsigned long) acb;
  2820. acb->eternal_timer.function = &arcmsr_request_device_map;
  2821. add_timer(&acb->eternal_timer);
  2822. } else {
  2823. atomic_set(&acb->rq_map_token, 16);
  2824. atomic_set(&acb->ante_token_value, 16);
  2825. acb->fw_flag = FW_NORMAL;
  2826. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
  2827. }
  2828. rtn = SUCCESS;
  2829. }
  2830. break;
  2831. }
  2832. case ACB_ADAPTER_TYPE_B:{
  2833. acb->acb_flags |= ACB_F_BUS_RESET;
  2834. if (!arcmsr_iop_reset(acb)) {
  2835. acb->acb_flags &= ~ACB_F_BUS_RESET;
  2836. rtn = FAILED;
  2837. } else {
  2838. acb->acb_flags &= ~ACB_F_BUS_RESET;
  2839. if (atomic_read(&acb->rq_map_token) == 0) {
  2840. atomic_set(&acb->rq_map_token, 16);
  2841. atomic_set(&acb->ante_token_value, 16);
  2842. acb->fw_flag = FW_NORMAL;
  2843. init_timer(&acb->eternal_timer);
  2844. acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6*HZ);
  2845. acb->eternal_timer.data = (unsigned long) acb;
  2846. acb->eternal_timer.function = &arcmsr_request_device_map;
  2847. add_timer(&acb->eternal_timer);
  2848. } else {
  2849. atomic_set(&acb->rq_map_token, 16);
  2850. atomic_set(&acb->ante_token_value, 16);
  2851. acb->fw_flag = FW_NORMAL;
  2852. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
  2853. }
  2854. rtn = SUCCESS;
  2855. }
  2856. break;
  2857. }
  2858. case ACB_ADAPTER_TYPE_C:{
  2859. if (acb->acb_flags & ACB_F_BUS_RESET) {
  2860. long timeout;
  2861. printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
  2862. timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
  2863. if (timeout) {
  2864. return SUCCESS;
  2865. }
  2866. }
  2867. acb->acb_flags |= ACB_F_BUS_RESET;
  2868. if (!arcmsr_iop_reset(acb)) {
  2869. struct MessageUnit_C __iomem *reg;
  2870. reg = acb->pmuC;
  2871. arcmsr_hardware_reset(acb);
  2872. acb->acb_flags &= ~ACB_F_IOP_INITED;
  2873. sleep:
  2874. arcmsr_sleep_for_bus_reset(cmd);
  2875. if ((readl(&reg->host_diagnostic) & 0x04) != 0) {
  2876. printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d \n", acb->host->host_no, retry_count);
  2877. if (retry_count > retrycount) {
  2878. acb->fw_flag = FW_DEADLOCK;
  2879. printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!! \n", acb->host->host_no);
  2880. return FAILED;
  2881. }
  2882. retry_count++;
  2883. goto sleep;
  2884. }
  2885. acb->acb_flags |= ACB_F_IOP_INITED;
  2886. /* disable all outbound interrupt */
  2887. intmask_org = arcmsr_disable_outbound_ints(acb);
  2888. arcmsr_get_firmware_spec(acb);
  2889. arcmsr_start_adapter_bgrb(acb);
  2890. /* clear Qbuffer if door bell ringed */
  2891. outbound_doorbell = readl(&reg->outbound_doorbell);
  2892. writel(outbound_doorbell, &reg->outbound_doorbell_clear); /*clear interrupt */
  2893. writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
  2894. /* enable outbound Post Queue,outbound doorbell Interrupt */
  2895. arcmsr_enable_outbound_ints(acb, intmask_org);
  2896. atomic_set(&acb->rq_map_token, 16);
  2897. atomic_set(&acb->ante_token_value, 16);
  2898. acb->fw_flag = FW_NORMAL;
  2899. init_timer(&acb->eternal_timer);
  2900. acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
  2901. acb->eternal_timer.data = (unsigned long) acb;
  2902. acb->eternal_timer.function = &arcmsr_request_device_map;
  2903. add_timer(&acb->eternal_timer);
  2904. acb->acb_flags &= ~ACB_F_BUS_RESET;
  2905. rtn = SUCCESS;
  2906. printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
  2907. } else {
  2908. acb->acb_flags &= ~ACB_F_BUS_RESET;
  2909. if (atomic_read(&acb->rq_map_token) == 0) {
  2910. atomic_set(&acb->rq_map_token, 16);
  2911. atomic_set(&acb->ante_token_value, 16);
  2912. acb->fw_flag = FW_NORMAL;
  2913. init_timer(&acb->eternal_timer);
  2914. acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6*HZ);
  2915. acb->eternal_timer.data = (unsigned long) acb;
  2916. acb->eternal_timer.function = &arcmsr_request_device_map;
  2917. add_timer(&acb->eternal_timer);
  2918. } else {
  2919. atomic_set(&acb->rq_map_token, 16);
  2920. atomic_set(&acb->ante_token_value, 16);
  2921. acb->fw_flag = FW_NORMAL;
  2922. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
  2923. }
  2924. rtn = SUCCESS;
  2925. }
  2926. break;
  2927. }
  2928. }
  2929. return rtn;
  2930. }
  2931. static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
  2932. struct CommandControlBlock *ccb)
  2933. {
  2934. int rtn;
  2935. rtn = arcmsr_polling_ccbdone(acb, ccb);
  2936. return rtn;
  2937. }
  2938. static int arcmsr_abort(struct scsi_cmnd *cmd)
  2939. {
  2940. struct AdapterControlBlock *acb =
  2941. (struct AdapterControlBlock *)cmd->device->host->hostdata;
  2942. int i = 0;
  2943. int rtn = FAILED;
  2944. printk(KERN_NOTICE
  2945. "arcmsr%d: abort device command of scsi id = %d lun = %d \n",
  2946. acb->host->host_no, cmd->device->id, cmd->device->lun);
  2947. acb->acb_flags |= ACB_F_ABORT;
  2948. acb->num_aborts++;
  2949. /*
  2950. ************************************************
  2951. ** the all interrupt service routine is locked
  2952. ** we need to handle it as soon as possible and exit
  2953. ************************************************
  2954. */
  2955. if (!atomic_read(&acb->ccboutstandingcount))
  2956. return rtn;
  2957. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  2958. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  2959. if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
  2960. ccb->startdone = ARCMSR_CCB_ABORTED;
  2961. rtn = arcmsr_abort_one_cmd(acb, ccb);
  2962. break;
  2963. }
  2964. }
  2965. acb->acb_flags &= ~ACB_F_ABORT;
  2966. return rtn;
  2967. }
  2968. static const char *arcmsr_info(struct Scsi_Host *host)
  2969. {
  2970. struct AdapterControlBlock *acb =
  2971. (struct AdapterControlBlock *) host->hostdata;
  2972. static char buf[256];
  2973. char *type;
  2974. int raid6 = 1;
  2975. switch (acb->pdev->device) {
  2976. case PCI_DEVICE_ID_ARECA_1110:
  2977. case PCI_DEVICE_ID_ARECA_1200:
  2978. case PCI_DEVICE_ID_ARECA_1202:
  2979. case PCI_DEVICE_ID_ARECA_1210:
  2980. raid6 = 0;
  2981. /*FALLTHRU*/
  2982. case PCI_DEVICE_ID_ARECA_1120:
  2983. case PCI_DEVICE_ID_ARECA_1130:
  2984. case PCI_DEVICE_ID_ARECA_1160:
  2985. case PCI_DEVICE_ID_ARECA_1170:
  2986. case PCI_DEVICE_ID_ARECA_1201:
  2987. case PCI_DEVICE_ID_ARECA_1220:
  2988. case PCI_DEVICE_ID_ARECA_1230:
  2989. case PCI_DEVICE_ID_ARECA_1260:
  2990. case PCI_DEVICE_ID_ARECA_1270:
  2991. case PCI_DEVICE_ID_ARECA_1280:
  2992. type = "SATA";
  2993. break;
  2994. case PCI_DEVICE_ID_ARECA_1380:
  2995. case PCI_DEVICE_ID_ARECA_1381:
  2996. case PCI_DEVICE_ID_ARECA_1680:
  2997. case PCI_DEVICE_ID_ARECA_1681:
  2998. case PCI_DEVICE_ID_ARECA_1880:
  2999. type = "SAS";
  3000. break;
  3001. default:
  3002. type = "X-TYPE";
  3003. break;
  3004. }
  3005. sprintf(buf, "Areca %s Host Adapter RAID Controller%s\n %s",
  3006. type, raid6 ? "( RAID6 capable)" : "",
  3007. ARCMSR_DRIVER_VERSION);
  3008. return buf;
  3009. }