iwl-tx.c 19 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/etherdevice.h>
  30. #include <linux/sched.h>
  31. #include <linux/slab.h>
  32. #include <net/mac80211.h>
  33. #include "iwl-eeprom.h"
  34. #include "iwl-dev.h"
  35. #include "iwl-core.h"
  36. #include "iwl-sta.h"
  37. #include "iwl-io.h"
  38. #include "iwl-helpers.h"
  39. /**
  40. * iwl_legacy_txq_update_write_ptr - Send new write index to hardware
  41. */
  42. void
  43. iwl_legacy_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  44. {
  45. u32 reg = 0;
  46. int txq_id = txq->q.id;
  47. if (txq->need_update == 0)
  48. return;
  49. /* if we're trying to save power */
  50. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  51. /* wake up nic if it's powered down ...
  52. * uCode will wake up, and interrupt us again, so next
  53. * time we'll skip this part. */
  54. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  55. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  56. IWL_DEBUG_INFO(priv,
  57. "Tx queue %d requesting wakeup,"
  58. " GP1 = 0x%x\n", txq_id, reg);
  59. iwl_legacy_set_bit(priv, CSR_GP_CNTRL,
  60. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  61. return;
  62. }
  63. iwl_legacy_write_direct32(priv, HBUS_TARG_WRPTR,
  64. txq->q.write_ptr | (txq_id << 8));
  65. /*
  66. * else not in power-save mode,
  67. * uCode will never sleep when we're
  68. * trying to tx (during RFKILL, we're not trying to tx).
  69. */
  70. } else
  71. iwl_write32(priv, HBUS_TARG_WRPTR,
  72. txq->q.write_ptr | (txq_id << 8));
  73. txq->need_update = 0;
  74. }
  75. EXPORT_SYMBOL(iwl_legacy_txq_update_write_ptr);
  76. /**
  77. * iwl_legacy_tx_queue_free - Deallocate DMA queue.
  78. * @txq: Transmit queue to deallocate.
  79. *
  80. * Empty queue by removing and destroying all BD's.
  81. * Free all buffers.
  82. * 0-fill, but do not free "txq" descriptor structure.
  83. */
  84. void iwl_legacy_tx_queue_free(struct iwl_priv *priv, int txq_id)
  85. {
  86. struct iwl_tx_queue *txq = &priv->txq[txq_id];
  87. struct iwl_queue *q = &txq->q;
  88. struct device *dev = &priv->pci_dev->dev;
  89. int i;
  90. if (q->n_bd == 0)
  91. return;
  92. /* first, empty all BD's */
  93. for (; q->write_ptr != q->read_ptr;
  94. q->read_ptr = iwl_legacy_queue_inc_wrap(q->read_ptr, q->n_bd))
  95. priv->cfg->ops->lib->txq_free_tfd(priv, txq);
  96. /* De-alloc array of command/tx buffers */
  97. for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
  98. kfree(txq->cmd[i]);
  99. /* De-alloc circular buffer of TFDs */
  100. if (txq->q.n_bd)
  101. dma_free_coherent(dev, priv->hw_params.tfd_size *
  102. txq->q.n_bd, txq->tfds, txq->q.dma_addr);
  103. /* De-alloc array of per-TFD driver data */
  104. kfree(txq->txb);
  105. txq->txb = NULL;
  106. /* deallocate arrays */
  107. kfree(txq->cmd);
  108. kfree(txq->meta);
  109. txq->cmd = NULL;
  110. txq->meta = NULL;
  111. /* 0-fill queue descriptor structure */
  112. memset(txq, 0, sizeof(*txq));
  113. }
  114. EXPORT_SYMBOL(iwl_legacy_tx_queue_free);
  115. /**
  116. * iwl_legacy_cmd_queue_free - Deallocate DMA queue.
  117. * @txq: Transmit queue to deallocate.
  118. *
  119. * Empty queue by removing and destroying all BD's.
  120. * Free all buffers.
  121. * 0-fill, but do not free "txq" descriptor structure.
  122. */
  123. void iwl_legacy_cmd_queue_free(struct iwl_priv *priv)
  124. {
  125. struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
  126. struct iwl_queue *q = &txq->q;
  127. struct device *dev = &priv->pci_dev->dev;
  128. int i;
  129. bool huge = false;
  130. if (q->n_bd == 0)
  131. return;
  132. for (; q->read_ptr != q->write_ptr;
  133. q->read_ptr = iwl_legacy_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  134. /* we have no way to tell if it is a huge cmd ATM */
  135. i = iwl_legacy_get_cmd_index(q, q->read_ptr, 0);
  136. if (txq->meta[i].flags & CMD_SIZE_HUGE) {
  137. huge = true;
  138. continue;
  139. }
  140. pci_unmap_single(priv->pci_dev,
  141. dma_unmap_addr(&txq->meta[i], mapping),
  142. dma_unmap_len(&txq->meta[i], len),
  143. PCI_DMA_BIDIRECTIONAL);
  144. }
  145. if (huge) {
  146. i = q->n_window;
  147. pci_unmap_single(priv->pci_dev,
  148. dma_unmap_addr(&txq->meta[i], mapping),
  149. dma_unmap_len(&txq->meta[i], len),
  150. PCI_DMA_BIDIRECTIONAL);
  151. }
  152. /* De-alloc array of command/tx buffers */
  153. for (i = 0; i <= TFD_CMD_SLOTS; i++)
  154. kfree(txq->cmd[i]);
  155. /* De-alloc circular buffer of TFDs */
  156. if (txq->q.n_bd)
  157. dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd,
  158. txq->tfds, txq->q.dma_addr);
  159. /* deallocate arrays */
  160. kfree(txq->cmd);
  161. kfree(txq->meta);
  162. txq->cmd = NULL;
  163. txq->meta = NULL;
  164. /* 0-fill queue descriptor structure */
  165. memset(txq, 0, sizeof(*txq));
  166. }
  167. EXPORT_SYMBOL(iwl_legacy_cmd_queue_free);
  168. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  169. * DMA services
  170. *
  171. * Theory of operation
  172. *
  173. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  174. * of buffer descriptors, each of which points to one or more data buffers for
  175. * the device to read from or fill. Driver and device exchange status of each
  176. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  177. * entries in each circular buffer, to protect against confusing empty and full
  178. * queue states.
  179. *
  180. * The device reads or writes the data in the queues via the device's several
  181. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  182. *
  183. * For Tx queue, there are low mark and high mark limits. If, after queuing
  184. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  185. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  186. * Tx queue resumed.
  187. *
  188. * See more detailed info in iwl-4965-hw.h.
  189. ***************************************************/
  190. int iwl_legacy_queue_space(const struct iwl_queue *q)
  191. {
  192. int s = q->read_ptr - q->write_ptr;
  193. if (q->read_ptr > q->write_ptr)
  194. s -= q->n_bd;
  195. if (s <= 0)
  196. s += q->n_window;
  197. /* keep some reserve to not confuse empty and full situations */
  198. s -= 2;
  199. if (s < 0)
  200. s = 0;
  201. return s;
  202. }
  203. EXPORT_SYMBOL(iwl_legacy_queue_space);
  204. /**
  205. * iwl_legacy_queue_init - Initialize queue's high/low-water and read/write indexes
  206. */
  207. static int iwl_legacy_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
  208. int count, int slots_num, u32 id)
  209. {
  210. q->n_bd = count;
  211. q->n_window = slots_num;
  212. q->id = id;
  213. /* count must be power-of-two size, otherwise iwl_legacy_queue_inc_wrap
  214. * and iwl_legacy_queue_dec_wrap are broken. */
  215. BUG_ON(!is_power_of_2(count));
  216. /* slots_num must be power-of-two size, otherwise
  217. * iwl_legacy_get_cmd_index is broken. */
  218. BUG_ON(!is_power_of_2(slots_num));
  219. q->low_mark = q->n_window / 4;
  220. if (q->low_mark < 4)
  221. q->low_mark = 4;
  222. q->high_mark = q->n_window / 8;
  223. if (q->high_mark < 2)
  224. q->high_mark = 2;
  225. q->write_ptr = q->read_ptr = 0;
  226. return 0;
  227. }
  228. /**
  229. * iwl_legacy_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  230. */
  231. static int iwl_legacy_tx_queue_alloc(struct iwl_priv *priv,
  232. struct iwl_tx_queue *txq, u32 id)
  233. {
  234. struct device *dev = &priv->pci_dev->dev;
  235. size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
  236. /* Driver private data, only for Tx (not command) queues,
  237. * not shared with device. */
  238. if (id != priv->cmd_queue) {
  239. txq->txb = kzalloc(sizeof(txq->txb[0]) *
  240. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  241. if (!txq->txb) {
  242. IWL_ERR(priv, "kmalloc for auxiliary BD "
  243. "structures failed\n");
  244. goto error;
  245. }
  246. } else {
  247. txq->txb = NULL;
  248. }
  249. /* Circular buffer of transmit frame descriptors (TFDs),
  250. * shared with device */
  251. txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr,
  252. GFP_KERNEL);
  253. if (!txq->tfds) {
  254. IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
  255. goto error;
  256. }
  257. txq->q.id = id;
  258. return 0;
  259. error:
  260. kfree(txq->txb);
  261. txq->txb = NULL;
  262. return -ENOMEM;
  263. }
  264. /**
  265. * iwl_legacy_tx_queue_init - Allocate and initialize one tx/cmd queue
  266. */
  267. int iwl_legacy_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
  268. int slots_num, u32 txq_id)
  269. {
  270. int i, len;
  271. int ret;
  272. int actual_slots = slots_num;
  273. /*
  274. * Alloc buffer array for commands (Tx or other types of commands).
  275. * For the command queue (#4/#9), allocate command space + one big
  276. * command for scan, since scan command is very huge; the system will
  277. * not have two scans at the same time, so only one is needed.
  278. * For normal Tx queues (all other queues), no super-size command
  279. * space is needed.
  280. */
  281. if (txq_id == priv->cmd_queue)
  282. actual_slots++;
  283. txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
  284. GFP_KERNEL);
  285. txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots,
  286. GFP_KERNEL);
  287. if (!txq->meta || !txq->cmd)
  288. goto out_free_arrays;
  289. len = sizeof(struct iwl_device_cmd);
  290. for (i = 0; i < actual_slots; i++) {
  291. /* only happens for cmd queue */
  292. if (i == slots_num)
  293. len = IWL_MAX_CMD_SIZE;
  294. txq->cmd[i] = kmalloc(len, GFP_KERNEL);
  295. if (!txq->cmd[i])
  296. goto err;
  297. }
  298. /* Alloc driver data array and TFD circular buffer */
  299. ret = iwl_legacy_tx_queue_alloc(priv, txq, txq_id);
  300. if (ret)
  301. goto err;
  302. txq->need_update = 0;
  303. /*
  304. * For the default queues 0-3, set up the swq_id
  305. * already -- all others need to get one later
  306. * (if they need one at all).
  307. */
  308. if (txq_id < 4)
  309. iwl_legacy_set_swq_id(txq, txq_id, txq_id);
  310. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  311. * iwl_legacy_queue_inc_wrap and iwl_legacy_queue_dec_wrap are broken. */
  312. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  313. /* Initialize queue's high/low-water marks, and head/tail indexes */
  314. iwl_legacy_queue_init(priv, &txq->q,
  315. TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  316. /* Tell device where to find queue */
  317. priv->cfg->ops->lib->txq_init(priv, txq);
  318. return 0;
  319. err:
  320. for (i = 0; i < actual_slots; i++)
  321. kfree(txq->cmd[i]);
  322. out_free_arrays:
  323. kfree(txq->meta);
  324. kfree(txq->cmd);
  325. return -ENOMEM;
  326. }
  327. EXPORT_SYMBOL(iwl_legacy_tx_queue_init);
  328. void iwl_legacy_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq,
  329. int slots_num, u32 txq_id)
  330. {
  331. int actual_slots = slots_num;
  332. if (txq_id == priv->cmd_queue)
  333. actual_slots++;
  334. memset(txq->meta, 0, sizeof(struct iwl_cmd_meta) * actual_slots);
  335. txq->need_update = 0;
  336. /* Initialize queue's high/low-water marks, and head/tail indexes */
  337. iwl_legacy_queue_init(priv, &txq->q,
  338. TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  339. /* Tell device where to find queue */
  340. priv->cfg->ops->lib->txq_init(priv, txq);
  341. }
  342. EXPORT_SYMBOL(iwl_legacy_tx_queue_reset);
  343. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  344. /**
  345. * iwl_legacy_enqueue_hcmd - enqueue a uCode command
  346. * @priv: device private data point
  347. * @cmd: a point to the ucode command structure
  348. *
  349. * The function returns < 0 values to indicate the operation is
  350. * failed. On success, it turns the index (> 0) of command in the
  351. * command queue.
  352. */
  353. int iwl_legacy_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
  354. {
  355. struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
  356. struct iwl_queue *q = &txq->q;
  357. struct iwl_device_cmd *out_cmd;
  358. struct iwl_cmd_meta *out_meta;
  359. dma_addr_t phys_addr;
  360. unsigned long flags;
  361. int len;
  362. u32 idx;
  363. u16 fix_size;
  364. cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
  365. fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  366. /* If any of the command structures end up being larger than
  367. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  368. * we will need to increase the size of the TFD entries
  369. * Also, check to see if command buffer should not exceed the size
  370. * of device_cmd and max_cmd_size. */
  371. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  372. !(cmd->flags & CMD_SIZE_HUGE));
  373. BUG_ON(fix_size > IWL_MAX_CMD_SIZE);
  374. if (iwl_legacy_is_rfkill(priv) || iwl_legacy_is_ctkill(priv)) {
  375. IWL_WARN(priv, "Not sending command - %s KILL\n",
  376. iwl_legacy_is_rfkill(priv) ? "RF" : "CT");
  377. return -EIO;
  378. }
  379. if (iwl_legacy_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
  380. IWL_ERR(priv, "No space in command queue\n");
  381. IWL_ERR(priv, "Restarting adapter due to queue full\n");
  382. queue_work(priv->workqueue, &priv->restart);
  383. return -ENOSPC;
  384. }
  385. spin_lock_irqsave(&priv->hcmd_lock, flags);
  386. /* If this is a huge cmd, mark the huge flag also on the meta.flags
  387. * of the _original_ cmd. This is used for DMA mapping clean up.
  388. */
  389. if (cmd->flags & CMD_SIZE_HUGE) {
  390. idx = iwl_legacy_get_cmd_index(q, q->write_ptr, 0);
  391. txq->meta[idx].flags = CMD_SIZE_HUGE;
  392. }
  393. idx = iwl_legacy_get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
  394. out_cmd = txq->cmd[idx];
  395. out_meta = &txq->meta[idx];
  396. memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
  397. out_meta->flags = cmd->flags;
  398. if (cmd->flags & CMD_WANT_SKB)
  399. out_meta->source = cmd;
  400. if (cmd->flags & CMD_ASYNC)
  401. out_meta->callback = cmd->callback;
  402. out_cmd->hdr.cmd = cmd->id;
  403. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  404. /* At this point, the out_cmd now has all of the incoming cmd
  405. * information */
  406. out_cmd->hdr.flags = 0;
  407. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(priv->cmd_queue) |
  408. INDEX_TO_SEQ(q->write_ptr));
  409. if (cmd->flags & CMD_SIZE_HUGE)
  410. out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
  411. len = sizeof(struct iwl_device_cmd);
  412. if (idx == TFD_CMD_SLOTS)
  413. len = IWL_MAX_CMD_SIZE;
  414. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  415. switch (out_cmd->hdr.cmd) {
  416. case REPLY_TX_LINK_QUALITY_CMD:
  417. case SENSITIVITY_CMD:
  418. IWL_DEBUG_HC_DUMP(priv,
  419. "Sending command %s (#%x), seq: 0x%04X, "
  420. "%d bytes at %d[%d]:%d\n",
  421. iwl_legacy_get_cmd_string(out_cmd->hdr.cmd),
  422. out_cmd->hdr.cmd,
  423. le16_to_cpu(out_cmd->hdr.sequence), fix_size,
  424. q->write_ptr, idx, priv->cmd_queue);
  425. break;
  426. default:
  427. IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
  428. "%d bytes at %d[%d]:%d\n",
  429. iwl_legacy_get_cmd_string(out_cmd->hdr.cmd),
  430. out_cmd->hdr.cmd,
  431. le16_to_cpu(out_cmd->hdr.sequence), fix_size,
  432. q->write_ptr, idx, priv->cmd_queue);
  433. }
  434. #endif
  435. txq->need_update = 1;
  436. if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
  437. /* Set up entry in queue's byte count circular buffer */
  438. priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
  439. phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
  440. fix_size, PCI_DMA_BIDIRECTIONAL);
  441. dma_unmap_addr_set(out_meta, mapping, phys_addr);
  442. dma_unmap_len_set(out_meta, len, fix_size);
  443. trace_iwlwifi_legacy_dev_hcmd(priv, &out_cmd->hdr,
  444. fix_size, cmd->flags);
  445. priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
  446. phys_addr, fix_size, 1,
  447. U32_PAD(cmd->len));
  448. /* Increment and update queue's write index */
  449. q->write_ptr = iwl_legacy_queue_inc_wrap(q->write_ptr, q->n_bd);
  450. iwl_legacy_txq_update_write_ptr(priv, txq);
  451. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  452. return idx;
  453. }
  454. /**
  455. * iwl_legacy_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
  456. *
  457. * When FW advances 'R' index, all entries between old and new 'R' index
  458. * need to be reclaimed. As result, some free space forms. If there is
  459. * enough free space (> low mark), wake the stack that feeds us.
  460. */
  461. static void iwl_legacy_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
  462. int idx, int cmd_idx)
  463. {
  464. struct iwl_tx_queue *txq = &priv->txq[txq_id];
  465. struct iwl_queue *q = &txq->q;
  466. int nfreed = 0;
  467. if ((idx >= q->n_bd) || (iwl_legacy_queue_used(q, idx) == 0)) {
  468. IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
  469. "is out of range [0-%d] %d %d.\n", txq_id,
  470. idx, q->n_bd, q->write_ptr, q->read_ptr);
  471. return;
  472. }
  473. for (idx = iwl_legacy_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
  474. q->read_ptr = iwl_legacy_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  475. if (nfreed++ > 0) {
  476. IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
  477. q->write_ptr, q->read_ptr);
  478. queue_work(priv->workqueue, &priv->restart);
  479. }
  480. }
  481. }
  482. /**
  483. * iwl_legacy_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  484. * @rxb: Rx buffer to reclaim
  485. *
  486. * If an Rx buffer has an async callback associated with it the callback
  487. * will be executed. The attached skb (if present) will only be freed
  488. * if the callback returns 1
  489. */
  490. void
  491. iwl_legacy_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  492. {
  493. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  494. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  495. int txq_id = SEQ_TO_QUEUE(sequence);
  496. int index = SEQ_TO_INDEX(sequence);
  497. int cmd_index;
  498. bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  499. struct iwl_device_cmd *cmd;
  500. struct iwl_cmd_meta *meta;
  501. struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
  502. /* If a Tx command is being handled and it isn't in the actual
  503. * command queue then there a command routing bug has been introduced
  504. * in the queue management code. */
  505. if (WARN(txq_id != priv->cmd_queue,
  506. "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
  507. txq_id, priv->cmd_queue, sequence,
  508. priv->txq[priv->cmd_queue].q.read_ptr,
  509. priv->txq[priv->cmd_queue].q.write_ptr)) {
  510. iwl_print_hex_error(priv, pkt, 32);
  511. return;
  512. }
  513. /* If this is a huge cmd, clear the huge flag on the meta.flags
  514. * of the _original_ cmd. So that iwl_legacy_cmd_queue_free won't unmap
  515. * the DMA buffer for the scan (huge) command.
  516. */
  517. if (huge) {
  518. cmd_index = iwl_legacy_get_cmd_index(&txq->q, index, 0);
  519. txq->meta[cmd_index].flags = 0;
  520. }
  521. cmd_index = iwl_legacy_get_cmd_index(&txq->q, index, huge);
  522. cmd = txq->cmd[cmd_index];
  523. meta = &txq->meta[cmd_index];
  524. pci_unmap_single(priv->pci_dev,
  525. dma_unmap_addr(meta, mapping),
  526. dma_unmap_len(meta, len),
  527. PCI_DMA_BIDIRECTIONAL);
  528. /* Input error checking is done when commands are added to queue. */
  529. if (meta->flags & CMD_WANT_SKB) {
  530. meta->source->reply_page = (unsigned long)rxb_addr(rxb);
  531. rxb->page = NULL;
  532. } else if (meta->callback)
  533. meta->callback(priv, cmd, pkt);
  534. iwl_legacy_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
  535. if (!(meta->flags & CMD_ASYNC)) {
  536. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  537. IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n",
  538. iwl_legacy_get_cmd_string(cmd->hdr.cmd));
  539. wake_up_interruptible(&priv->wait_command_queue);
  540. }
  541. meta->flags = 0;
  542. }
  543. EXPORT_SYMBOL(iwl_legacy_tx_cmd_complete);