fm801.c 42 KB

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  1. /*
  2. * The driver for the ForteMedia FM801 based soundcards
  3. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  4. *
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. #include <sound/driver.h>
  22. #include <linux/delay.h>
  23. #include <linux/init.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/pci.h>
  26. #include <linux/slab.h>
  27. #include <linux/moduleparam.h>
  28. #include <sound/core.h>
  29. #include <sound/pcm.h>
  30. #include <sound/ac97_codec.h>
  31. #include <sound/mpu401.h>
  32. #include <sound/opl3.h>
  33. #include <sound/initval.h>
  34. #include <asm/io.h>
  35. #if (defined(CONFIG_SND_FM801_TEA575X) || defined(CONFIG_SND_FM801_TEA575X_MODULE)) && (defined(CONFIG_VIDEO_DEV) || defined(CONFIG_VIDEO_DEV_MODULE))
  36. #include <sound/tea575x-tuner.h>
  37. #define TEA575X_RADIO 1
  38. #endif
  39. MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  40. MODULE_DESCRIPTION("ForteMedia FM801");
  41. MODULE_LICENSE("GPL");
  42. MODULE_SUPPORTED_DEVICE("{{ForteMedia,FM801},"
  43. "{Genius,SoundMaker Live 5.1}}");
  44. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  45. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  46. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  47. /*
  48. * Enable TEA575x tuner
  49. * 1 = MediaForte 256-PCS
  50. * 2 = MediaForte 256-PCPR
  51. * 3 = MediaForte 64-PCR
  52. * High 16-bits are video (radio) device number + 1
  53. */
  54. static int tea575x_tuner[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0 };
  55. module_param_array(index, int, NULL, 0444);
  56. MODULE_PARM_DESC(index, "Index value for the FM801 soundcard.");
  57. module_param_array(id, charp, NULL, 0444);
  58. MODULE_PARM_DESC(id, "ID string for the FM801 soundcard.");
  59. module_param_array(enable, bool, NULL, 0444);
  60. MODULE_PARM_DESC(enable, "Enable FM801 soundcard.");
  61. module_param_array(tea575x_tuner, int, NULL, 0444);
  62. MODULE_PARM_DESC(tea575x_tuner, "Enable TEA575x tuner.");
  63. /*
  64. * Direct registers
  65. */
  66. #define FM801_REG(chip, reg) (chip->port + FM801_##reg)
  67. #define FM801_PCM_VOL 0x00 /* PCM Output Volume */
  68. #define FM801_FM_VOL 0x02 /* FM Output Volume */
  69. #define FM801_I2S_VOL 0x04 /* I2S Volume */
  70. #define FM801_REC_SRC 0x06 /* Record Source */
  71. #define FM801_PLY_CTRL 0x08 /* Playback Control */
  72. #define FM801_PLY_COUNT 0x0a /* Playback Count */
  73. #define FM801_PLY_BUF1 0x0c /* Playback Bufer I */
  74. #define FM801_PLY_BUF2 0x10 /* Playback Buffer II */
  75. #define FM801_CAP_CTRL 0x14 /* Capture Control */
  76. #define FM801_CAP_COUNT 0x16 /* Capture Count */
  77. #define FM801_CAP_BUF1 0x18 /* Capture Buffer I */
  78. #define FM801_CAP_BUF2 0x1c /* Capture Buffer II */
  79. #define FM801_CODEC_CTRL 0x22 /* Codec Control */
  80. #define FM801_I2S_MODE 0x24 /* I2S Mode Control */
  81. #define FM801_VOLUME 0x26 /* Volume Up/Down/Mute Status */
  82. #define FM801_I2C_CTRL 0x29 /* I2C Control */
  83. #define FM801_AC97_CMD 0x2a /* AC'97 Command */
  84. #define FM801_AC97_DATA 0x2c /* AC'97 Data */
  85. #define FM801_MPU401_DATA 0x30 /* MPU401 Data */
  86. #define FM801_MPU401_CMD 0x31 /* MPU401 Command */
  87. #define FM801_GPIO_CTRL 0x52 /* General Purpose I/O Control */
  88. #define FM801_GEN_CTRL 0x54 /* General Control */
  89. #define FM801_IRQ_MASK 0x56 /* Interrupt Mask */
  90. #define FM801_IRQ_STATUS 0x5a /* Interrupt Status */
  91. #define FM801_OPL3_BANK0 0x68 /* OPL3 Status Read / Bank 0 Write */
  92. #define FM801_OPL3_DATA0 0x69 /* OPL3 Data 0 Write */
  93. #define FM801_OPL3_BANK1 0x6a /* OPL3 Bank 1 Write */
  94. #define FM801_OPL3_DATA1 0x6b /* OPL3 Bank 1 Write */
  95. #define FM801_POWERDOWN 0x70 /* Blocks Power Down Control */
  96. #define FM801_AC97_ADDR_SHIFT 10
  97. /* playback and record control register bits */
  98. #define FM801_BUF1_LAST (1<<1)
  99. #define FM801_BUF2_LAST (1<<2)
  100. #define FM801_START (1<<5)
  101. #define FM801_PAUSE (1<<6)
  102. #define FM801_IMMED_STOP (1<<7)
  103. #define FM801_RATE_SHIFT 8
  104. #define FM801_RATE_MASK (15 << FM801_RATE_SHIFT)
  105. #define FM801_CHANNELS_4 (1<<12) /* playback only */
  106. #define FM801_CHANNELS_6 (2<<12) /* playback only */
  107. #define FM801_CHANNELS_6MS (3<<12) /* playback only */
  108. #define FM801_CHANNELS_MASK (3<<12)
  109. #define FM801_16BIT (1<<14)
  110. #define FM801_STEREO (1<<15)
  111. /* IRQ status bits */
  112. #define FM801_IRQ_PLAYBACK (1<<8)
  113. #define FM801_IRQ_CAPTURE (1<<9)
  114. #define FM801_IRQ_VOLUME (1<<14)
  115. #define FM801_IRQ_MPU (1<<15)
  116. /* GPIO control register */
  117. #define FM801_GPIO_GP0 (1<<0) /* read/write */
  118. #define FM801_GPIO_GP1 (1<<1)
  119. #define FM801_GPIO_GP2 (1<<2)
  120. #define FM801_GPIO_GP3 (1<<3)
  121. #define FM801_GPIO_GP(x) (1<<(0+(x)))
  122. #define FM801_GPIO_GD0 (1<<8) /* directions: 1 = input, 0 = output*/
  123. #define FM801_GPIO_GD1 (1<<9)
  124. #define FM801_GPIO_GD2 (1<<10)
  125. #define FM801_GPIO_GD3 (1<<11)
  126. #define FM801_GPIO_GD(x) (1<<(8+(x)))
  127. #define FM801_GPIO_GS0 (1<<12) /* function select: */
  128. #define FM801_GPIO_GS1 (1<<13) /* 1 = GPIO */
  129. #define FM801_GPIO_GS2 (1<<14) /* 0 = other (S/PDIF, VOL) */
  130. #define FM801_GPIO_GS3 (1<<15)
  131. #define FM801_GPIO_GS(x) (1<<(12+(x)))
  132. /*
  133. */
  134. typedef struct _snd_fm801 fm801_t;
  135. struct _snd_fm801 {
  136. int irq;
  137. unsigned long port; /* I/O port number */
  138. unsigned int multichannel: 1, /* multichannel support */
  139. secondary: 1; /* secondary codec */
  140. unsigned char secondary_addr; /* address of the secondary codec */
  141. unsigned short ply_ctrl; /* playback control */
  142. unsigned short cap_ctrl; /* capture control */
  143. unsigned long ply_buffer;
  144. unsigned int ply_buf;
  145. unsigned int ply_count;
  146. unsigned int ply_size;
  147. unsigned int ply_pos;
  148. unsigned long cap_buffer;
  149. unsigned int cap_buf;
  150. unsigned int cap_count;
  151. unsigned int cap_size;
  152. unsigned int cap_pos;
  153. ac97_bus_t *ac97_bus;
  154. ac97_t *ac97;
  155. ac97_t *ac97_sec;
  156. struct pci_dev *pci;
  157. snd_card_t *card;
  158. snd_pcm_t *pcm;
  159. snd_rawmidi_t *rmidi;
  160. snd_pcm_substream_t *playback_substream;
  161. snd_pcm_substream_t *capture_substream;
  162. unsigned int p_dma_size;
  163. unsigned int c_dma_size;
  164. spinlock_t reg_lock;
  165. snd_info_entry_t *proc_entry;
  166. #ifdef TEA575X_RADIO
  167. tea575x_t tea;
  168. #endif
  169. };
  170. static struct pci_device_id snd_fm801_ids[] = {
  171. { 0x1319, 0x0801, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0, }, /* FM801 */
  172. { 0, }
  173. };
  174. MODULE_DEVICE_TABLE(pci, snd_fm801_ids);
  175. /*
  176. * common I/O routines
  177. */
  178. static int snd_fm801_update_bits(fm801_t *chip, unsigned short reg,
  179. unsigned short mask, unsigned short value)
  180. {
  181. int change;
  182. unsigned long flags;
  183. unsigned short old, new;
  184. spin_lock_irqsave(&chip->reg_lock, flags);
  185. old = inw(chip->port + reg);
  186. new = (old & ~mask) | value;
  187. change = old != new;
  188. if (change)
  189. outw(new, chip->port + reg);
  190. spin_unlock_irqrestore(&chip->reg_lock, flags);
  191. return change;
  192. }
  193. static void snd_fm801_codec_write(ac97_t *ac97,
  194. unsigned short reg,
  195. unsigned short val)
  196. {
  197. fm801_t *chip = ac97->private_data;
  198. int idx;
  199. /*
  200. * Wait until the codec interface is not ready..
  201. */
  202. for (idx = 0; idx < 100; idx++) {
  203. if (!(inw(FM801_REG(chip, AC97_CMD)) & (1<<9)))
  204. goto ok1;
  205. udelay(10);
  206. }
  207. snd_printk("AC'97 interface is busy (1)\n");
  208. return;
  209. ok1:
  210. /* write data and address */
  211. outw(val, FM801_REG(chip, AC97_DATA));
  212. outw(reg | (ac97->addr << FM801_AC97_ADDR_SHIFT), FM801_REG(chip, AC97_CMD));
  213. /*
  214. * Wait until the write command is not completed..
  215. */
  216. for (idx = 0; idx < 1000; idx++) {
  217. if (!(inw(FM801_REG(chip, AC97_CMD)) & (1<<9)))
  218. return;
  219. udelay(10);
  220. }
  221. snd_printk("AC'97 interface #%d is busy (2)\n", ac97->num);
  222. }
  223. static unsigned short snd_fm801_codec_read(ac97_t *ac97, unsigned short reg)
  224. {
  225. fm801_t *chip = ac97->private_data;
  226. int idx;
  227. /*
  228. * Wait until the codec interface is not ready..
  229. */
  230. for (idx = 0; idx < 100; idx++) {
  231. if (!(inw(FM801_REG(chip, AC97_CMD)) & (1<<9)))
  232. goto ok1;
  233. udelay(10);
  234. }
  235. snd_printk("AC'97 interface is busy (1)\n");
  236. return 0;
  237. ok1:
  238. /* read command */
  239. outw(reg | (ac97->addr << FM801_AC97_ADDR_SHIFT) | (1<<7), FM801_REG(chip, AC97_CMD));
  240. for (idx = 0; idx < 100; idx++) {
  241. if (!(inw(FM801_REG(chip, AC97_CMD)) & (1<<9)))
  242. goto ok2;
  243. udelay(10);
  244. }
  245. snd_printk("AC'97 interface #%d is busy (2)\n", ac97->num);
  246. return 0;
  247. ok2:
  248. for (idx = 0; idx < 1000; idx++) {
  249. if (inw(FM801_REG(chip, AC97_CMD)) & (1<<8))
  250. goto ok3;
  251. udelay(10);
  252. }
  253. snd_printk("AC'97 interface #%d is not valid (2)\n", ac97->num);
  254. return 0;
  255. ok3:
  256. return inw(FM801_REG(chip, AC97_DATA));
  257. }
  258. static unsigned int rates[] = {
  259. 5500, 8000, 9600, 11025,
  260. 16000, 19200, 22050, 32000,
  261. 38400, 44100, 48000
  262. };
  263. static snd_pcm_hw_constraint_list_t hw_constraints_rates = {
  264. .count = ARRAY_SIZE(rates),
  265. .list = rates,
  266. .mask = 0,
  267. };
  268. static unsigned int channels[] = {
  269. 2, 4, 6
  270. };
  271. #define CHANNELS sizeof(channels) / sizeof(channels[0])
  272. static snd_pcm_hw_constraint_list_t hw_constraints_channels = {
  273. .count = CHANNELS,
  274. .list = channels,
  275. .mask = 0,
  276. };
  277. /*
  278. * Sample rate routines
  279. */
  280. static unsigned short snd_fm801_rate_bits(unsigned int rate)
  281. {
  282. unsigned int idx;
  283. for (idx = 0; idx < ARRAY_SIZE(rates); idx++)
  284. if (rates[idx] == rate)
  285. return idx;
  286. snd_BUG();
  287. return ARRAY_SIZE(rates) - 1;
  288. }
  289. /*
  290. * PCM part
  291. */
  292. static int snd_fm801_playback_trigger(snd_pcm_substream_t * substream,
  293. int cmd)
  294. {
  295. fm801_t *chip = snd_pcm_substream_chip(substream);
  296. spin_lock(&chip->reg_lock);
  297. switch (cmd) {
  298. case SNDRV_PCM_TRIGGER_START:
  299. chip->ply_ctrl &= ~(FM801_BUF1_LAST |
  300. FM801_BUF2_LAST |
  301. FM801_PAUSE);
  302. chip->ply_ctrl |= FM801_START |
  303. FM801_IMMED_STOP;
  304. break;
  305. case SNDRV_PCM_TRIGGER_STOP:
  306. chip->ply_ctrl &= ~(FM801_START | FM801_PAUSE);
  307. break;
  308. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  309. chip->ply_ctrl |= FM801_PAUSE;
  310. break;
  311. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  312. chip->ply_ctrl &= ~FM801_PAUSE;
  313. break;
  314. default:
  315. spin_unlock(&chip->reg_lock);
  316. snd_BUG();
  317. return -EINVAL;
  318. }
  319. outw(chip->ply_ctrl, FM801_REG(chip, PLY_CTRL));
  320. spin_unlock(&chip->reg_lock);
  321. return 0;
  322. }
  323. static int snd_fm801_capture_trigger(snd_pcm_substream_t * substream,
  324. int cmd)
  325. {
  326. fm801_t *chip = snd_pcm_substream_chip(substream);
  327. spin_lock(&chip->reg_lock);
  328. switch (cmd) {
  329. case SNDRV_PCM_TRIGGER_START:
  330. chip->cap_ctrl &= ~(FM801_BUF1_LAST |
  331. FM801_BUF2_LAST |
  332. FM801_PAUSE);
  333. chip->cap_ctrl |= FM801_START |
  334. FM801_IMMED_STOP;
  335. break;
  336. case SNDRV_PCM_TRIGGER_STOP:
  337. chip->cap_ctrl &= ~(FM801_START | FM801_PAUSE);
  338. break;
  339. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  340. chip->cap_ctrl |= FM801_PAUSE;
  341. break;
  342. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  343. chip->cap_ctrl &= ~FM801_PAUSE;
  344. break;
  345. default:
  346. spin_unlock(&chip->reg_lock);
  347. snd_BUG();
  348. return -EINVAL;
  349. }
  350. outw(chip->cap_ctrl, FM801_REG(chip, CAP_CTRL));
  351. spin_unlock(&chip->reg_lock);
  352. return 0;
  353. }
  354. static int snd_fm801_hw_params(snd_pcm_substream_t * substream,
  355. snd_pcm_hw_params_t * hw_params)
  356. {
  357. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  358. }
  359. static int snd_fm801_hw_free(snd_pcm_substream_t * substream)
  360. {
  361. return snd_pcm_lib_free_pages(substream);
  362. }
  363. static int snd_fm801_playback_prepare(snd_pcm_substream_t * substream)
  364. {
  365. fm801_t *chip = snd_pcm_substream_chip(substream);
  366. snd_pcm_runtime_t *runtime = substream->runtime;
  367. chip->ply_size = snd_pcm_lib_buffer_bytes(substream);
  368. chip->ply_count = snd_pcm_lib_period_bytes(substream);
  369. spin_lock_irq(&chip->reg_lock);
  370. chip->ply_ctrl &= ~(FM801_START | FM801_16BIT |
  371. FM801_STEREO | FM801_RATE_MASK |
  372. FM801_CHANNELS_MASK);
  373. if (snd_pcm_format_width(runtime->format) == 16)
  374. chip->ply_ctrl |= FM801_16BIT;
  375. if (runtime->channels > 1) {
  376. chip->ply_ctrl |= FM801_STEREO;
  377. if (runtime->channels == 4)
  378. chip->ply_ctrl |= FM801_CHANNELS_4;
  379. else if (runtime->channels == 6)
  380. chip->ply_ctrl |= FM801_CHANNELS_6;
  381. }
  382. chip->ply_ctrl |= snd_fm801_rate_bits(runtime->rate) << FM801_RATE_SHIFT;
  383. chip->ply_buf = 0;
  384. outw(chip->ply_ctrl, FM801_REG(chip, PLY_CTRL));
  385. outw(chip->ply_count - 1, FM801_REG(chip, PLY_COUNT));
  386. chip->ply_buffer = runtime->dma_addr;
  387. chip->ply_pos = 0;
  388. outl(chip->ply_buffer, FM801_REG(chip, PLY_BUF1));
  389. outl(chip->ply_buffer + (chip->ply_count % chip->ply_size), FM801_REG(chip, PLY_BUF2));
  390. spin_unlock_irq(&chip->reg_lock);
  391. return 0;
  392. }
  393. static int snd_fm801_capture_prepare(snd_pcm_substream_t * substream)
  394. {
  395. fm801_t *chip = snd_pcm_substream_chip(substream);
  396. snd_pcm_runtime_t *runtime = substream->runtime;
  397. chip->cap_size = snd_pcm_lib_buffer_bytes(substream);
  398. chip->cap_count = snd_pcm_lib_period_bytes(substream);
  399. spin_lock_irq(&chip->reg_lock);
  400. chip->cap_ctrl &= ~(FM801_START | FM801_16BIT |
  401. FM801_STEREO | FM801_RATE_MASK);
  402. if (snd_pcm_format_width(runtime->format) == 16)
  403. chip->cap_ctrl |= FM801_16BIT;
  404. if (runtime->channels > 1)
  405. chip->cap_ctrl |= FM801_STEREO;
  406. chip->cap_ctrl |= snd_fm801_rate_bits(runtime->rate) << FM801_RATE_SHIFT;
  407. chip->cap_buf = 0;
  408. outw(chip->cap_ctrl, FM801_REG(chip, CAP_CTRL));
  409. outw(chip->cap_count - 1, FM801_REG(chip, CAP_COUNT));
  410. chip->cap_buffer = runtime->dma_addr;
  411. chip->cap_pos = 0;
  412. outl(chip->cap_buffer, FM801_REG(chip, CAP_BUF1));
  413. outl(chip->cap_buffer + (chip->cap_count % chip->cap_size), FM801_REG(chip, CAP_BUF2));
  414. spin_unlock_irq(&chip->reg_lock);
  415. return 0;
  416. }
  417. static snd_pcm_uframes_t snd_fm801_playback_pointer(snd_pcm_substream_t * substream)
  418. {
  419. fm801_t *chip = snd_pcm_substream_chip(substream);
  420. size_t ptr;
  421. if (!(chip->ply_ctrl & FM801_START))
  422. return 0;
  423. spin_lock(&chip->reg_lock);
  424. ptr = chip->ply_pos + (chip->ply_count - 1) - inw(FM801_REG(chip, PLY_COUNT));
  425. if (inw(FM801_REG(chip, IRQ_STATUS)) & FM801_IRQ_PLAYBACK) {
  426. ptr += chip->ply_count;
  427. ptr %= chip->ply_size;
  428. }
  429. spin_unlock(&chip->reg_lock);
  430. return bytes_to_frames(substream->runtime, ptr);
  431. }
  432. static snd_pcm_uframes_t snd_fm801_capture_pointer(snd_pcm_substream_t * substream)
  433. {
  434. fm801_t *chip = snd_pcm_substream_chip(substream);
  435. size_t ptr;
  436. if (!(chip->cap_ctrl & FM801_START))
  437. return 0;
  438. spin_lock(&chip->reg_lock);
  439. ptr = chip->cap_pos + (chip->cap_count - 1) - inw(FM801_REG(chip, CAP_COUNT));
  440. if (inw(FM801_REG(chip, IRQ_STATUS)) & FM801_IRQ_CAPTURE) {
  441. ptr += chip->cap_count;
  442. ptr %= chip->cap_size;
  443. }
  444. spin_unlock(&chip->reg_lock);
  445. return bytes_to_frames(substream->runtime, ptr);
  446. }
  447. static irqreturn_t snd_fm801_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  448. {
  449. fm801_t *chip = dev_id;
  450. unsigned short status;
  451. unsigned int tmp;
  452. status = inw(FM801_REG(chip, IRQ_STATUS));
  453. status &= FM801_IRQ_PLAYBACK|FM801_IRQ_CAPTURE|FM801_IRQ_MPU|FM801_IRQ_VOLUME;
  454. if (! status)
  455. return IRQ_NONE;
  456. /* ack first */
  457. outw(status, FM801_REG(chip, IRQ_STATUS));
  458. if (chip->pcm && (status & FM801_IRQ_PLAYBACK) && chip->playback_substream) {
  459. spin_lock(&chip->reg_lock);
  460. chip->ply_buf++;
  461. chip->ply_pos += chip->ply_count;
  462. chip->ply_pos %= chip->ply_size;
  463. tmp = chip->ply_pos + chip->ply_count;
  464. tmp %= chip->ply_size;
  465. outl(chip->ply_buffer + tmp,
  466. (chip->ply_buf & 1) ?
  467. FM801_REG(chip, PLY_BUF1) :
  468. FM801_REG(chip, PLY_BUF2));
  469. spin_unlock(&chip->reg_lock);
  470. snd_pcm_period_elapsed(chip->playback_substream);
  471. }
  472. if (chip->pcm && (status & FM801_IRQ_CAPTURE) && chip->capture_substream) {
  473. spin_lock(&chip->reg_lock);
  474. chip->cap_buf++;
  475. chip->cap_pos += chip->cap_count;
  476. chip->cap_pos %= chip->cap_size;
  477. tmp = chip->cap_pos + chip->cap_count;
  478. tmp %= chip->cap_size;
  479. outl(chip->cap_buffer + tmp,
  480. (chip->cap_buf & 1) ?
  481. FM801_REG(chip, CAP_BUF1) :
  482. FM801_REG(chip, CAP_BUF2));
  483. spin_unlock(&chip->reg_lock);
  484. snd_pcm_period_elapsed(chip->capture_substream);
  485. }
  486. if (chip->rmidi && (status & FM801_IRQ_MPU))
  487. snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
  488. if (status & FM801_IRQ_VOLUME)
  489. ;/* TODO */
  490. return IRQ_HANDLED;
  491. }
  492. static snd_pcm_hardware_t snd_fm801_playback =
  493. {
  494. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  495. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  496. SNDRV_PCM_INFO_PAUSE |
  497. SNDRV_PCM_INFO_MMAP_VALID),
  498. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  499. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  500. .rate_min = 5500,
  501. .rate_max = 48000,
  502. .channels_min = 1,
  503. .channels_max = 2,
  504. .buffer_bytes_max = (128*1024),
  505. .period_bytes_min = 64,
  506. .period_bytes_max = (128*1024),
  507. .periods_min = 1,
  508. .periods_max = 1024,
  509. .fifo_size = 0,
  510. };
  511. static snd_pcm_hardware_t snd_fm801_capture =
  512. {
  513. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  514. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  515. SNDRV_PCM_INFO_PAUSE |
  516. SNDRV_PCM_INFO_MMAP_VALID),
  517. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  518. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  519. .rate_min = 5500,
  520. .rate_max = 48000,
  521. .channels_min = 1,
  522. .channels_max = 2,
  523. .buffer_bytes_max = (128*1024),
  524. .period_bytes_min = 64,
  525. .period_bytes_max = (128*1024),
  526. .periods_min = 1,
  527. .periods_max = 1024,
  528. .fifo_size = 0,
  529. };
  530. static int snd_fm801_playback_open(snd_pcm_substream_t * substream)
  531. {
  532. fm801_t *chip = snd_pcm_substream_chip(substream);
  533. snd_pcm_runtime_t *runtime = substream->runtime;
  534. int err;
  535. chip->playback_substream = substream;
  536. runtime->hw = snd_fm801_playback;
  537. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  538. if (chip->multichannel) {
  539. runtime->hw.channels_max = 6;
  540. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels);
  541. }
  542. if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
  543. return err;
  544. return 0;
  545. }
  546. static int snd_fm801_capture_open(snd_pcm_substream_t * substream)
  547. {
  548. fm801_t *chip = snd_pcm_substream_chip(substream);
  549. snd_pcm_runtime_t *runtime = substream->runtime;
  550. int err;
  551. chip->capture_substream = substream;
  552. runtime->hw = snd_fm801_capture;
  553. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  554. if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
  555. return err;
  556. return 0;
  557. }
  558. static int snd_fm801_playback_close(snd_pcm_substream_t * substream)
  559. {
  560. fm801_t *chip = snd_pcm_substream_chip(substream);
  561. chip->playback_substream = NULL;
  562. return 0;
  563. }
  564. static int snd_fm801_capture_close(snd_pcm_substream_t * substream)
  565. {
  566. fm801_t *chip = snd_pcm_substream_chip(substream);
  567. chip->capture_substream = NULL;
  568. return 0;
  569. }
  570. static snd_pcm_ops_t snd_fm801_playback_ops = {
  571. .open = snd_fm801_playback_open,
  572. .close = snd_fm801_playback_close,
  573. .ioctl = snd_pcm_lib_ioctl,
  574. .hw_params = snd_fm801_hw_params,
  575. .hw_free = snd_fm801_hw_free,
  576. .prepare = snd_fm801_playback_prepare,
  577. .trigger = snd_fm801_playback_trigger,
  578. .pointer = snd_fm801_playback_pointer,
  579. };
  580. static snd_pcm_ops_t snd_fm801_capture_ops = {
  581. .open = snd_fm801_capture_open,
  582. .close = snd_fm801_capture_close,
  583. .ioctl = snd_pcm_lib_ioctl,
  584. .hw_params = snd_fm801_hw_params,
  585. .hw_free = snd_fm801_hw_free,
  586. .prepare = snd_fm801_capture_prepare,
  587. .trigger = snd_fm801_capture_trigger,
  588. .pointer = snd_fm801_capture_pointer,
  589. };
  590. static void snd_fm801_pcm_free(snd_pcm_t *pcm)
  591. {
  592. fm801_t *chip = pcm->private_data;
  593. chip->pcm = NULL;
  594. snd_pcm_lib_preallocate_free_for_all(pcm);
  595. }
  596. static int __devinit snd_fm801_pcm(fm801_t *chip, int device, snd_pcm_t ** rpcm)
  597. {
  598. snd_pcm_t *pcm;
  599. int err;
  600. if (rpcm)
  601. *rpcm = NULL;
  602. if ((err = snd_pcm_new(chip->card, "FM801", device, 1, 1, &pcm)) < 0)
  603. return err;
  604. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_fm801_playback_ops);
  605. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_fm801_capture_ops);
  606. pcm->private_data = chip;
  607. pcm->private_free = snd_fm801_pcm_free;
  608. pcm->info_flags = 0;
  609. strcpy(pcm->name, "FM801");
  610. chip->pcm = pcm;
  611. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  612. snd_dma_pci_data(chip->pci),
  613. chip->multichannel ? 128*1024 : 64*1024, 128*1024);
  614. if (rpcm)
  615. *rpcm = pcm;
  616. return 0;
  617. }
  618. /*
  619. * TEA5757 radio
  620. */
  621. #ifdef TEA575X_RADIO
  622. /* 256PCS GPIO numbers */
  623. #define TEA_256PCS_DATA 1
  624. #define TEA_256PCS_WRITE_ENABLE 2 /* inverted */
  625. #define TEA_256PCS_BUS_CLOCK 3
  626. static void snd_fm801_tea575x_256pcs_write(tea575x_t *tea, unsigned int val)
  627. {
  628. fm801_t *chip = tea->private_data;
  629. unsigned short reg;
  630. int i = 25;
  631. spin_lock_irq(&chip->reg_lock);
  632. reg = inw(FM801_REG(chip, GPIO_CTRL));
  633. /* use GPIO lines and set write enable bit */
  634. reg |= FM801_GPIO_GS(TEA_256PCS_DATA) |
  635. FM801_GPIO_GS(TEA_256PCS_WRITE_ENABLE) |
  636. FM801_GPIO_GS(TEA_256PCS_BUS_CLOCK);
  637. /* all of lines are in the write direction */
  638. /* clear data and clock lines */
  639. reg &= ~(FM801_GPIO_GD(TEA_256PCS_DATA) |
  640. FM801_GPIO_GD(TEA_256PCS_WRITE_ENABLE) |
  641. FM801_GPIO_GD(TEA_256PCS_BUS_CLOCK) |
  642. FM801_GPIO_GP(TEA_256PCS_DATA) |
  643. FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK) |
  644. FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE));
  645. outw(reg, FM801_REG(chip, GPIO_CTRL));
  646. udelay(1);
  647. while (i--) {
  648. if (val & (1 << i))
  649. reg |= FM801_GPIO_GP(TEA_256PCS_DATA);
  650. else
  651. reg &= ~FM801_GPIO_GP(TEA_256PCS_DATA);
  652. outw(reg, FM801_REG(chip, GPIO_CTRL));
  653. udelay(1);
  654. reg |= FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
  655. outw(reg, FM801_REG(chip, GPIO_CTRL));
  656. reg &= ~FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
  657. outw(reg, FM801_REG(chip, GPIO_CTRL));
  658. udelay(1);
  659. }
  660. /* and reset the write enable bit */
  661. reg |= FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE) |
  662. FM801_GPIO_GP(TEA_256PCS_DATA);
  663. outw(reg, FM801_REG(chip, GPIO_CTRL));
  664. spin_unlock_irq(&chip->reg_lock);
  665. }
  666. static unsigned int snd_fm801_tea575x_256pcs_read(tea575x_t *tea)
  667. {
  668. fm801_t *chip = tea->private_data;
  669. unsigned short reg;
  670. unsigned int val = 0;
  671. int i;
  672. spin_lock_irq(&chip->reg_lock);
  673. reg = inw(FM801_REG(chip, GPIO_CTRL));
  674. /* use GPIO lines, set data direction to input */
  675. reg |= FM801_GPIO_GS(TEA_256PCS_DATA) |
  676. FM801_GPIO_GS(TEA_256PCS_WRITE_ENABLE) |
  677. FM801_GPIO_GS(TEA_256PCS_BUS_CLOCK) |
  678. FM801_GPIO_GD(TEA_256PCS_DATA) |
  679. FM801_GPIO_GP(TEA_256PCS_DATA) |
  680. FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE);
  681. /* all of lines are in the write direction, except data */
  682. /* clear data, write enable and clock lines */
  683. reg &= ~(FM801_GPIO_GD(TEA_256PCS_WRITE_ENABLE) |
  684. FM801_GPIO_GD(TEA_256PCS_BUS_CLOCK) |
  685. FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK));
  686. for (i = 0; i < 24; i++) {
  687. reg &= ~FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
  688. outw(reg, FM801_REG(chip, GPIO_CTRL));
  689. udelay(1);
  690. reg |= FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
  691. outw(reg, FM801_REG(chip, GPIO_CTRL));
  692. udelay(1);
  693. val <<= 1;
  694. if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_256PCS_DATA))
  695. val |= 1;
  696. }
  697. spin_unlock_irq(&chip->reg_lock);
  698. return val;
  699. }
  700. /* 256PCPR GPIO numbers */
  701. #define TEA_256PCPR_BUS_CLOCK 0
  702. #define TEA_256PCPR_DATA 1
  703. #define TEA_256PCPR_WRITE_ENABLE 2 /* inverted */
  704. static void snd_fm801_tea575x_256pcpr_write(tea575x_t *tea, unsigned int val)
  705. {
  706. fm801_t *chip = tea->private_data;
  707. unsigned short reg;
  708. int i = 25;
  709. spin_lock_irq(&chip->reg_lock);
  710. reg = inw(FM801_REG(chip, GPIO_CTRL));
  711. /* use GPIO lines and set write enable bit */
  712. reg |= FM801_GPIO_GS(TEA_256PCPR_DATA) |
  713. FM801_GPIO_GS(TEA_256PCPR_WRITE_ENABLE) |
  714. FM801_GPIO_GS(TEA_256PCPR_BUS_CLOCK);
  715. /* all of lines are in the write direction */
  716. /* clear data and clock lines */
  717. reg &= ~(FM801_GPIO_GD(TEA_256PCPR_DATA) |
  718. FM801_GPIO_GD(TEA_256PCPR_WRITE_ENABLE) |
  719. FM801_GPIO_GD(TEA_256PCPR_BUS_CLOCK) |
  720. FM801_GPIO_GP(TEA_256PCPR_DATA) |
  721. FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK) |
  722. FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE));
  723. outw(reg, FM801_REG(chip, GPIO_CTRL));
  724. udelay(1);
  725. while (i--) {
  726. if (val & (1 << i))
  727. reg |= FM801_GPIO_GP(TEA_256PCPR_DATA);
  728. else
  729. reg &= ~FM801_GPIO_GP(TEA_256PCPR_DATA);
  730. outw(reg, FM801_REG(chip, GPIO_CTRL));
  731. udelay(1);
  732. reg |= FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
  733. outw(reg, FM801_REG(chip, GPIO_CTRL));
  734. reg &= ~FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
  735. outw(reg, FM801_REG(chip, GPIO_CTRL));
  736. udelay(1);
  737. }
  738. /* and reset the write enable bit */
  739. reg |= FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE) |
  740. FM801_GPIO_GP(TEA_256PCPR_DATA);
  741. outw(reg, FM801_REG(chip, GPIO_CTRL));
  742. spin_unlock_irq(&chip->reg_lock);
  743. }
  744. static unsigned int snd_fm801_tea575x_256pcpr_read(tea575x_t *tea)
  745. {
  746. fm801_t *chip = tea->private_data;
  747. unsigned short reg;
  748. unsigned int val = 0;
  749. int i;
  750. spin_lock_irq(&chip->reg_lock);
  751. reg = inw(FM801_REG(chip, GPIO_CTRL));
  752. /* use GPIO lines, set data direction to input */
  753. reg |= FM801_GPIO_GS(TEA_256PCPR_DATA) |
  754. FM801_GPIO_GS(TEA_256PCPR_WRITE_ENABLE) |
  755. FM801_GPIO_GS(TEA_256PCPR_BUS_CLOCK) |
  756. FM801_GPIO_GD(TEA_256PCPR_DATA) |
  757. FM801_GPIO_GP(TEA_256PCPR_DATA) |
  758. FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE);
  759. /* all of lines are in the write direction, except data */
  760. /* clear data, write enable and clock lines */
  761. reg &= ~(FM801_GPIO_GD(TEA_256PCPR_WRITE_ENABLE) |
  762. FM801_GPIO_GD(TEA_256PCPR_BUS_CLOCK) |
  763. FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK));
  764. for (i = 0; i < 24; i++) {
  765. reg &= ~FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
  766. outw(reg, FM801_REG(chip, GPIO_CTRL));
  767. udelay(1);
  768. reg |= FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
  769. outw(reg, FM801_REG(chip, GPIO_CTRL));
  770. udelay(1);
  771. val <<= 1;
  772. if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_256PCPR_DATA))
  773. val |= 1;
  774. }
  775. spin_unlock_irq(&chip->reg_lock);
  776. return val;
  777. }
  778. /* 64PCR GPIO numbers */
  779. #define TEA_64PCR_BUS_CLOCK 0
  780. #define TEA_64PCR_WRITE_ENABLE 1 /* inverted */
  781. #define TEA_64PCR_DATA 2
  782. static void snd_fm801_tea575x_64pcr_write(tea575x_t *tea, unsigned int val)
  783. {
  784. fm801_t *chip = tea->private_data;
  785. unsigned short reg;
  786. int i = 25;
  787. spin_lock_irq(&chip->reg_lock);
  788. reg = inw(FM801_REG(chip, GPIO_CTRL));
  789. /* use GPIO lines and set write enable bit */
  790. reg |= FM801_GPIO_GS(TEA_64PCR_DATA) |
  791. FM801_GPIO_GS(TEA_64PCR_WRITE_ENABLE) |
  792. FM801_GPIO_GS(TEA_64PCR_BUS_CLOCK);
  793. /* all of lines are in the write direction */
  794. /* clear data and clock lines */
  795. reg &= ~(FM801_GPIO_GD(TEA_64PCR_DATA) |
  796. FM801_GPIO_GD(TEA_64PCR_WRITE_ENABLE) |
  797. FM801_GPIO_GD(TEA_64PCR_BUS_CLOCK) |
  798. FM801_GPIO_GP(TEA_64PCR_DATA) |
  799. FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK) |
  800. FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE));
  801. outw(reg, FM801_REG(chip, GPIO_CTRL));
  802. udelay(1);
  803. while (i--) {
  804. if (val & (1 << i))
  805. reg |= FM801_GPIO_GP(TEA_64PCR_DATA);
  806. else
  807. reg &= ~FM801_GPIO_GP(TEA_64PCR_DATA);
  808. outw(reg, FM801_REG(chip, GPIO_CTRL));
  809. udelay(1);
  810. reg |= FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
  811. outw(reg, FM801_REG(chip, GPIO_CTRL));
  812. reg &= ~FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
  813. outw(reg, FM801_REG(chip, GPIO_CTRL));
  814. udelay(1);
  815. }
  816. /* and reset the write enable bit */
  817. reg |= FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE) |
  818. FM801_GPIO_GP(TEA_64PCR_DATA);
  819. outw(reg, FM801_REG(chip, GPIO_CTRL));
  820. spin_unlock_irq(&chip->reg_lock);
  821. }
  822. static unsigned int snd_fm801_tea575x_64pcr_read(tea575x_t *tea)
  823. {
  824. fm801_t *chip = tea->private_data;
  825. unsigned short reg;
  826. unsigned int val = 0;
  827. int i;
  828. spin_lock_irq(&chip->reg_lock);
  829. reg = inw(FM801_REG(chip, GPIO_CTRL));
  830. /* use GPIO lines, set data direction to input */
  831. reg |= FM801_GPIO_GS(TEA_64PCR_DATA) |
  832. FM801_GPIO_GS(TEA_64PCR_WRITE_ENABLE) |
  833. FM801_GPIO_GS(TEA_64PCR_BUS_CLOCK) |
  834. FM801_GPIO_GD(TEA_64PCR_DATA) |
  835. FM801_GPIO_GP(TEA_64PCR_DATA) |
  836. FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE);
  837. /* all of lines are in the write direction, except data */
  838. /* clear data, write enable and clock lines */
  839. reg &= ~(FM801_GPIO_GD(TEA_64PCR_WRITE_ENABLE) |
  840. FM801_GPIO_GD(TEA_64PCR_BUS_CLOCK) |
  841. FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK));
  842. for (i = 0; i < 24; i++) {
  843. reg &= ~FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
  844. outw(reg, FM801_REG(chip, GPIO_CTRL));
  845. udelay(1);
  846. reg |= FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
  847. outw(reg, FM801_REG(chip, GPIO_CTRL));
  848. udelay(1);
  849. val <<= 1;
  850. if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_64PCR_DATA))
  851. val |= 1;
  852. }
  853. spin_unlock_irq(&chip->reg_lock);
  854. return val;
  855. }
  856. static struct snd_tea575x_ops snd_fm801_tea_ops[3] = {
  857. {
  858. /* 1 = MediaForte 256-PCS */
  859. .write = snd_fm801_tea575x_256pcs_write,
  860. .read = snd_fm801_tea575x_256pcs_read,
  861. },
  862. {
  863. /* 2 = MediaForte 256-PCPR */
  864. .write = snd_fm801_tea575x_256pcpr_write,
  865. .read = snd_fm801_tea575x_256pcpr_read,
  866. },
  867. {
  868. /* 3 = MediaForte 64-PCR */
  869. .write = snd_fm801_tea575x_64pcr_write,
  870. .read = snd_fm801_tea575x_64pcr_read,
  871. }
  872. };
  873. #endif
  874. /*
  875. * Mixer routines
  876. */
  877. #define FM801_SINGLE(xname, reg, shift, mask, invert) \
  878. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_fm801_info_single, \
  879. .get = snd_fm801_get_single, .put = snd_fm801_put_single, \
  880. .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
  881. static int snd_fm801_info_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  882. {
  883. int mask = (kcontrol->private_value >> 16) & 0xff;
  884. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  885. uinfo->count = 1;
  886. uinfo->value.integer.min = 0;
  887. uinfo->value.integer.max = mask;
  888. return 0;
  889. }
  890. static int snd_fm801_get_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  891. {
  892. fm801_t *chip = snd_kcontrol_chip(kcontrol);
  893. int reg = kcontrol->private_value & 0xff;
  894. int shift = (kcontrol->private_value >> 8) & 0xff;
  895. int mask = (kcontrol->private_value >> 16) & 0xff;
  896. int invert = (kcontrol->private_value >> 24) & 0xff;
  897. ucontrol->value.integer.value[0] = (inw(chip->port + reg) >> shift) & mask;
  898. if (invert)
  899. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  900. return 0;
  901. }
  902. static int snd_fm801_put_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  903. {
  904. fm801_t *chip = snd_kcontrol_chip(kcontrol);
  905. int reg = kcontrol->private_value & 0xff;
  906. int shift = (kcontrol->private_value >> 8) & 0xff;
  907. int mask = (kcontrol->private_value >> 16) & 0xff;
  908. int invert = (kcontrol->private_value >> 24) & 0xff;
  909. unsigned short val;
  910. val = (ucontrol->value.integer.value[0] & mask);
  911. if (invert)
  912. val = mask - val;
  913. return snd_fm801_update_bits(chip, reg, mask << shift, val << shift);
  914. }
  915. #define FM801_DOUBLE(xname, reg, shift_left, shift_right, mask, invert) \
  916. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_fm801_info_double, \
  917. .get = snd_fm801_get_double, .put = snd_fm801_put_double, \
  918. .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24) }
  919. static int snd_fm801_info_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  920. {
  921. int mask = (kcontrol->private_value >> 16) & 0xff;
  922. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  923. uinfo->count = 2;
  924. uinfo->value.integer.min = 0;
  925. uinfo->value.integer.max = mask;
  926. return 0;
  927. }
  928. static int snd_fm801_get_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  929. {
  930. fm801_t *chip = snd_kcontrol_chip(kcontrol);
  931. int reg = kcontrol->private_value & 0xff;
  932. int shift_left = (kcontrol->private_value >> 8) & 0x0f;
  933. int shift_right = (kcontrol->private_value >> 12) & 0x0f;
  934. int mask = (kcontrol->private_value >> 16) & 0xff;
  935. int invert = (kcontrol->private_value >> 24) & 0xff;
  936. spin_lock_irq(&chip->reg_lock);
  937. ucontrol->value.integer.value[0] = (inw(chip->port + reg) >> shift_left) & mask;
  938. ucontrol->value.integer.value[1] = (inw(chip->port + reg) >> shift_right) & mask;
  939. spin_unlock_irq(&chip->reg_lock);
  940. if (invert) {
  941. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  942. ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
  943. }
  944. return 0;
  945. }
  946. static int snd_fm801_put_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  947. {
  948. fm801_t *chip = snd_kcontrol_chip(kcontrol);
  949. int reg = kcontrol->private_value & 0xff;
  950. int shift_left = (kcontrol->private_value >> 8) & 0x0f;
  951. int shift_right = (kcontrol->private_value >> 12) & 0x0f;
  952. int mask = (kcontrol->private_value >> 16) & 0xff;
  953. int invert = (kcontrol->private_value >> 24) & 0xff;
  954. unsigned short val1, val2;
  955. val1 = ucontrol->value.integer.value[0] & mask;
  956. val2 = ucontrol->value.integer.value[1] & mask;
  957. if (invert) {
  958. val1 = mask - val1;
  959. val2 = mask - val2;
  960. }
  961. return snd_fm801_update_bits(chip, reg,
  962. (mask << shift_left) | (mask << shift_right),
  963. (val1 << shift_left ) | (val2 << shift_right));
  964. }
  965. static int snd_fm801_info_mux(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  966. {
  967. static char *texts[5] = {
  968. "AC97 Primary", "FM", "I2S", "PCM", "AC97 Secondary"
  969. };
  970. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  971. uinfo->count = 1;
  972. uinfo->value.enumerated.items = 5;
  973. if (uinfo->value.enumerated.item > 4)
  974. uinfo->value.enumerated.item = 4;
  975. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  976. return 0;
  977. }
  978. static int snd_fm801_get_mux(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  979. {
  980. fm801_t *chip = snd_kcontrol_chip(kcontrol);
  981. unsigned short val;
  982. val = inw(FM801_REG(chip, REC_SRC)) & 7;
  983. if (val > 4)
  984. val = 4;
  985. ucontrol->value.enumerated.item[0] = val;
  986. return 0;
  987. }
  988. static int snd_fm801_put_mux(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  989. {
  990. fm801_t *chip = snd_kcontrol_chip(kcontrol);
  991. unsigned short val;
  992. if ((val = ucontrol->value.enumerated.item[0]) > 4)
  993. return -EINVAL;
  994. return snd_fm801_update_bits(chip, FM801_REC_SRC, 7, val);
  995. }
  996. #define FM801_CONTROLS (sizeof(snd_fm801_controls)/sizeof(snd_kcontrol_new_t))
  997. static snd_kcontrol_new_t snd_fm801_controls[] __devinitdata = {
  998. FM801_DOUBLE("Wave Playback Volume", FM801_PCM_VOL, 0, 8, 31, 1),
  999. FM801_SINGLE("Wave Playback Switch", FM801_PCM_VOL, 15, 1, 1),
  1000. FM801_DOUBLE("I2S Playback Volume", FM801_I2S_VOL, 0, 8, 31, 1),
  1001. FM801_SINGLE("I2S Playback Switch", FM801_I2S_VOL, 15, 1, 1),
  1002. FM801_DOUBLE("FM Playback Volume", FM801_FM_VOL, 0, 8, 31, 1),
  1003. FM801_SINGLE("FM Playback Switch", FM801_FM_VOL, 15, 1, 1),
  1004. {
  1005. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1006. .name = "Digital Capture Source",
  1007. .info = snd_fm801_info_mux,
  1008. .get = snd_fm801_get_mux,
  1009. .put = snd_fm801_put_mux,
  1010. }
  1011. };
  1012. #define FM801_CONTROLS_MULTI (sizeof(snd_fm801_controls_multi)/sizeof(snd_kcontrol_new_t))
  1013. static snd_kcontrol_new_t snd_fm801_controls_multi[] __devinitdata = {
  1014. FM801_SINGLE("AC97 2ch->4ch Copy Switch", FM801_CODEC_CTRL, 7, 1, 0),
  1015. FM801_SINGLE("AC97 18-bit Switch", FM801_CODEC_CTRL, 10, 1, 0),
  1016. FM801_SINGLE("IEC958 Capture Switch", FM801_I2S_MODE, 8, 1, 0),
  1017. FM801_SINGLE("IEC958 Raw Data Playback Switch", FM801_I2S_MODE, 9, 1, 0),
  1018. FM801_SINGLE("IEC958 Raw Data Capture Switch", FM801_I2S_MODE, 10, 1, 0),
  1019. FM801_SINGLE("IEC958 Playback Switch", FM801_GEN_CTRL, 2, 1, 0),
  1020. };
  1021. static void snd_fm801_mixer_free_ac97_bus(ac97_bus_t *bus)
  1022. {
  1023. fm801_t *chip = bus->private_data;
  1024. chip->ac97_bus = NULL;
  1025. }
  1026. static void snd_fm801_mixer_free_ac97(ac97_t *ac97)
  1027. {
  1028. fm801_t *chip = ac97->private_data;
  1029. if (ac97->num == 0) {
  1030. chip->ac97 = NULL;
  1031. } else {
  1032. chip->ac97_sec = NULL;
  1033. }
  1034. }
  1035. static int __devinit snd_fm801_mixer(fm801_t *chip)
  1036. {
  1037. ac97_template_t ac97;
  1038. unsigned int i;
  1039. int err;
  1040. static ac97_bus_ops_t ops = {
  1041. .write = snd_fm801_codec_write,
  1042. .read = snd_fm801_codec_read,
  1043. };
  1044. if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
  1045. return err;
  1046. chip->ac97_bus->private_free = snd_fm801_mixer_free_ac97_bus;
  1047. memset(&ac97, 0, sizeof(ac97));
  1048. ac97.private_data = chip;
  1049. ac97.private_free = snd_fm801_mixer_free_ac97;
  1050. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
  1051. return err;
  1052. if (chip->secondary) {
  1053. ac97.num = 1;
  1054. ac97.addr = chip->secondary_addr;
  1055. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_sec)) < 0)
  1056. return err;
  1057. }
  1058. for (i = 0; i < FM801_CONTROLS; i++)
  1059. snd_ctl_add(chip->card, snd_ctl_new1(&snd_fm801_controls[i], chip));
  1060. if (chip->multichannel) {
  1061. for (i = 0; i < FM801_CONTROLS_MULTI; i++)
  1062. snd_ctl_add(chip->card, snd_ctl_new1(&snd_fm801_controls_multi[i], chip));
  1063. }
  1064. return 0;
  1065. }
  1066. /*
  1067. * initialization routines
  1068. */
  1069. static int snd_fm801_free(fm801_t *chip)
  1070. {
  1071. unsigned short cmdw;
  1072. if (chip->irq < 0)
  1073. goto __end_hw;
  1074. /* interrupt setup - mask everything */
  1075. cmdw = inw(FM801_REG(chip, IRQ_MASK));
  1076. cmdw |= 0x00c3;
  1077. outw(cmdw, FM801_REG(chip, IRQ_MASK));
  1078. __end_hw:
  1079. #ifdef TEA575X_RADIO
  1080. snd_tea575x_exit(&chip->tea);
  1081. #endif
  1082. if (chip->irq >= 0)
  1083. free_irq(chip->irq, (void *)chip);
  1084. pci_release_regions(chip->pci);
  1085. pci_disable_device(chip->pci);
  1086. kfree(chip);
  1087. return 0;
  1088. }
  1089. static int snd_fm801_dev_free(snd_device_t *device)
  1090. {
  1091. fm801_t *chip = device->device_data;
  1092. return snd_fm801_free(chip);
  1093. }
  1094. static int __devinit snd_fm801_create(snd_card_t * card,
  1095. struct pci_dev * pci,
  1096. int tea575x_tuner,
  1097. fm801_t ** rchip)
  1098. {
  1099. fm801_t *chip;
  1100. unsigned char rev, id;
  1101. unsigned short cmdw;
  1102. unsigned long timeout;
  1103. int err;
  1104. static snd_device_ops_t ops = {
  1105. .dev_free = snd_fm801_dev_free,
  1106. };
  1107. *rchip = NULL;
  1108. if ((err = pci_enable_device(pci)) < 0)
  1109. return err;
  1110. chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
  1111. if (chip == NULL) {
  1112. pci_disable_device(pci);
  1113. return -ENOMEM;
  1114. }
  1115. spin_lock_init(&chip->reg_lock);
  1116. chip->card = card;
  1117. chip->pci = pci;
  1118. chip->irq = -1;
  1119. if ((err = pci_request_regions(pci, "FM801")) < 0) {
  1120. kfree(chip);
  1121. pci_disable_device(pci);
  1122. return err;
  1123. }
  1124. chip->port = pci_resource_start(pci, 0);
  1125. if (request_irq(pci->irq, snd_fm801_interrupt, SA_INTERRUPT|SA_SHIRQ, "FM801", (void *)chip)) {
  1126. snd_printk("unable to grab IRQ %d\n", chip->irq);
  1127. snd_fm801_free(chip);
  1128. return -EBUSY;
  1129. }
  1130. chip->irq = pci->irq;
  1131. pci_set_master(pci);
  1132. pci_read_config_byte(pci, PCI_REVISION_ID, &rev);
  1133. if (rev >= 0xb1) /* FM801-AU */
  1134. chip->multichannel = 1;
  1135. /* codec cold reset + AC'97 warm reset */
  1136. outw((1<<5)|(1<<6), FM801_REG(chip, CODEC_CTRL));
  1137. inw(FM801_REG(chip, CODEC_CTRL)); /* flush posting data */
  1138. udelay(100);
  1139. outw(0, FM801_REG(chip, CODEC_CTRL));
  1140. timeout = (jiffies + (3 * HZ) / 4) + 1; /* min 750ms */
  1141. outw((1<<7) | (0 << FM801_AC97_ADDR_SHIFT), FM801_REG(chip, AC97_CMD));
  1142. udelay(5);
  1143. do {
  1144. if ((inw(FM801_REG(chip, AC97_CMD)) & (3<<8)) == (1<<8))
  1145. goto __ac97_secondary;
  1146. set_current_state(TASK_UNINTERRUPTIBLE);
  1147. schedule_timeout(1);
  1148. } while (time_after(timeout, jiffies));
  1149. snd_printk("Primary AC'97 codec not found\n");
  1150. snd_fm801_free(chip);
  1151. return -EIO;
  1152. __ac97_secondary:
  1153. if (!chip->multichannel) /* lookup is not required */
  1154. goto __ac97_ok;
  1155. for (id = 3; id > 0; id--) { /* my card has the secondary codec */
  1156. /* at address #3, so the loop is inverted */
  1157. timeout = jiffies + HZ / 20;
  1158. outw((1<<7) | (id << FM801_AC97_ADDR_SHIFT) | AC97_VENDOR_ID1, FM801_REG(chip, AC97_CMD));
  1159. udelay(5);
  1160. do {
  1161. if ((inw(FM801_REG(chip, AC97_CMD)) & (3<<8)) == (1<<8)) {
  1162. cmdw = inw(FM801_REG(chip, AC97_DATA));
  1163. if (cmdw != 0xffff && cmdw != 0) {
  1164. chip->secondary = 1;
  1165. chip->secondary_addr = id;
  1166. goto __ac97_ok;
  1167. }
  1168. }
  1169. set_current_state(TASK_UNINTERRUPTIBLE);
  1170. schedule_timeout(1);
  1171. } while (time_after(timeout, jiffies));
  1172. }
  1173. /* the recovery phase, it seems that probing for non-existing codec might */
  1174. /* cause timeout problems */
  1175. timeout = (jiffies + (3 * HZ) / 4) + 1; /* min 750ms */
  1176. outw((1<<7) | (0 << FM801_AC97_ADDR_SHIFT), FM801_REG(chip, AC97_CMD));
  1177. udelay(5);
  1178. do {
  1179. if ((inw(FM801_REG(chip, AC97_CMD)) & (3<<8)) == (1<<8))
  1180. goto __ac97_ok;
  1181. set_current_state(TASK_UNINTERRUPTIBLE);
  1182. schedule_timeout(1);
  1183. } while (time_after(timeout, jiffies));
  1184. snd_printk("Primary AC'97 codec not responding\n");
  1185. snd_fm801_free(chip);
  1186. return -EIO;
  1187. __ac97_ok:
  1188. /* init volume */
  1189. outw(0x0808, FM801_REG(chip, PCM_VOL));
  1190. outw(0x9f1f, FM801_REG(chip, FM_VOL));
  1191. outw(0x8808, FM801_REG(chip, I2S_VOL));
  1192. /* I2S control - I2S mode */
  1193. outw(0x0003, FM801_REG(chip, I2S_MODE));
  1194. /* interrupt setup - unmask MPU, PLAYBACK & CAPTURE */
  1195. cmdw = inw(FM801_REG(chip, IRQ_MASK));
  1196. cmdw &= ~0x0083;
  1197. outw(cmdw, FM801_REG(chip, IRQ_MASK));
  1198. /* interrupt clear */
  1199. outw(FM801_IRQ_PLAYBACK|FM801_IRQ_CAPTURE|FM801_IRQ_MPU, FM801_REG(chip, IRQ_STATUS));
  1200. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1201. snd_fm801_free(chip);
  1202. return err;
  1203. }
  1204. snd_card_set_dev(card, &pci->dev);
  1205. #ifdef TEA575X_RADIO
  1206. if (tea575x_tuner > 0 && (tea575x_tuner & 0xffff) < 4) {
  1207. chip->tea.dev_nr = tea575x_tuner >> 16;
  1208. chip->tea.card = card;
  1209. chip->tea.freq_fixup = 10700;
  1210. chip->tea.private_data = chip;
  1211. chip->tea.ops = &snd_fm801_tea_ops[(tea575x_tuner & 0xffff) - 1];
  1212. snd_tea575x_init(&chip->tea);
  1213. }
  1214. #endif
  1215. *rchip = chip;
  1216. return 0;
  1217. }
  1218. static int __devinit snd_card_fm801_probe(struct pci_dev *pci,
  1219. const struct pci_device_id *pci_id)
  1220. {
  1221. static int dev;
  1222. snd_card_t *card;
  1223. fm801_t *chip;
  1224. opl3_t *opl3;
  1225. int err;
  1226. if (dev >= SNDRV_CARDS)
  1227. return -ENODEV;
  1228. if (!enable[dev]) {
  1229. dev++;
  1230. return -ENOENT;
  1231. }
  1232. card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
  1233. if (card == NULL)
  1234. return -ENOMEM;
  1235. if ((err = snd_fm801_create(card, pci, tea575x_tuner[dev], &chip)) < 0) {
  1236. snd_card_free(card);
  1237. return err;
  1238. }
  1239. strcpy(card->driver, "FM801");
  1240. strcpy(card->shortname, "ForteMedia FM801-");
  1241. strcat(card->shortname, chip->multichannel ? "AU" : "AS");
  1242. sprintf(card->longname, "%s at 0x%lx, irq %i",
  1243. card->shortname, chip->port, chip->irq);
  1244. if ((err = snd_fm801_pcm(chip, 0, NULL)) < 0) {
  1245. snd_card_free(card);
  1246. return err;
  1247. }
  1248. if ((err = snd_fm801_mixer(chip)) < 0) {
  1249. snd_card_free(card);
  1250. return err;
  1251. }
  1252. if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_FM801,
  1253. FM801_REG(chip, MPU401_DATA), 1,
  1254. chip->irq, 0, &chip->rmidi)) < 0) {
  1255. snd_card_free(card);
  1256. return err;
  1257. }
  1258. if ((err = snd_opl3_create(card, FM801_REG(chip, OPL3_BANK0),
  1259. FM801_REG(chip, OPL3_BANK1),
  1260. OPL3_HW_OPL3_FM801, 1, &opl3)) < 0) {
  1261. snd_card_free(card);
  1262. return err;
  1263. }
  1264. if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
  1265. snd_card_free(card);
  1266. return err;
  1267. }
  1268. if ((err = snd_card_register(card)) < 0) {
  1269. snd_card_free(card);
  1270. return err;
  1271. }
  1272. pci_set_drvdata(pci, card);
  1273. dev++;
  1274. return 0;
  1275. }
  1276. static void __devexit snd_card_fm801_remove(struct pci_dev *pci)
  1277. {
  1278. snd_card_free(pci_get_drvdata(pci));
  1279. pci_set_drvdata(pci, NULL);
  1280. }
  1281. static struct pci_driver driver = {
  1282. .name = "FM801",
  1283. .id_table = snd_fm801_ids,
  1284. .probe = snd_card_fm801_probe,
  1285. .remove = __devexit_p(snd_card_fm801_remove),
  1286. };
  1287. static int __init alsa_card_fm801_init(void)
  1288. {
  1289. return pci_module_init(&driver);
  1290. }
  1291. static void __exit alsa_card_fm801_exit(void)
  1292. {
  1293. pci_unregister_driver(&driver);
  1294. }
  1295. module_init(alsa_card_fm801_init)
  1296. module_exit(alsa_card_fm801_exit)