pci.c 17 KB

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  1. /*
  2. * pci.c - Low-Level PCI Access in IA-64
  3. *
  4. * Derived from bios32.c of i386 tree.
  5. *
  6. * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
  7. * David Mosberger-Tang <davidm@hpl.hp.com>
  8. * Bjorn Helgaas <bjorn.helgaas@hp.com>
  9. * Copyright (C) 2004 Silicon Graphics, Inc.
  10. *
  11. * Note: Above list of copyright holders is incomplete...
  12. */
  13. #include <linux/config.h>
  14. #include <linux/acpi.h>
  15. #include <linux/types.h>
  16. #include <linux/kernel.h>
  17. #include <linux/pci.h>
  18. #include <linux/init.h>
  19. #include <linux/ioport.h>
  20. #include <linux/slab.h>
  21. #include <linux/smp_lock.h>
  22. #include <linux/spinlock.h>
  23. #include <asm/machvec.h>
  24. #include <asm/page.h>
  25. #include <asm/segment.h>
  26. #include <asm/system.h>
  27. #include <asm/io.h>
  28. #include <asm/sal.h>
  29. #include <asm/smp.h>
  30. #include <asm/irq.h>
  31. #include <asm/hw_irq.h>
  32. static int pci_routeirq;
  33. /*
  34. * Low-level SAL-based PCI configuration access functions. Note that SAL
  35. * calls are already serialized (via sal_lock), so we don't need another
  36. * synchronization mechanism here.
  37. */
  38. #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
  39. (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
  40. /* SAL 3.2 adds support for extended config space. */
  41. #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
  42. (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
  43. static int
  44. pci_sal_read (unsigned int seg, unsigned int bus, unsigned int devfn,
  45. int reg, int len, u32 *value)
  46. {
  47. u64 addr, data = 0;
  48. int mode, result;
  49. if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  50. return -EINVAL;
  51. if ((seg | reg) <= 255) {
  52. addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  53. mode = 0;
  54. } else {
  55. addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  56. mode = 1;
  57. }
  58. result = ia64_sal_pci_config_read(addr, mode, len, &data);
  59. if (result != 0)
  60. return -EINVAL;
  61. *value = (u32) data;
  62. return 0;
  63. }
  64. static int
  65. pci_sal_write (unsigned int seg, unsigned int bus, unsigned int devfn,
  66. int reg, int len, u32 value)
  67. {
  68. u64 addr;
  69. int mode, result;
  70. if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  71. return -EINVAL;
  72. if ((seg | reg) <= 255) {
  73. addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  74. mode = 0;
  75. } else {
  76. addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  77. mode = 1;
  78. }
  79. result = ia64_sal_pci_config_write(addr, mode, len, value);
  80. if (result != 0)
  81. return -EINVAL;
  82. return 0;
  83. }
  84. static struct pci_raw_ops pci_sal_ops = {
  85. .read = pci_sal_read,
  86. .write = pci_sal_write
  87. };
  88. struct pci_raw_ops *raw_pci_ops = &pci_sal_ops;
  89. static int
  90. pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
  91. {
  92. return raw_pci_ops->read(pci_domain_nr(bus), bus->number,
  93. devfn, where, size, value);
  94. }
  95. static int
  96. pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
  97. {
  98. return raw_pci_ops->write(pci_domain_nr(bus), bus->number,
  99. devfn, where, size, value);
  100. }
  101. struct pci_ops pci_root_ops = {
  102. .read = pci_read,
  103. .write = pci_write,
  104. };
  105. #ifdef CONFIG_NUMA
  106. extern acpi_status acpi_map_iosapic(acpi_handle, u32, void *, void **);
  107. static void acpi_map_iosapics(void)
  108. {
  109. acpi_get_devices(NULL, acpi_map_iosapic, NULL, NULL);
  110. }
  111. #else
  112. static void acpi_map_iosapics(void)
  113. {
  114. return;
  115. }
  116. #endif /* CONFIG_NUMA */
  117. static int __init
  118. pci_acpi_init (void)
  119. {
  120. struct pci_dev *dev = NULL;
  121. printk(KERN_INFO "PCI: Using ACPI for IRQ routing\n");
  122. acpi_map_iosapics();
  123. if (pci_routeirq) {
  124. /*
  125. * PCI IRQ routing is set up by pci_enable_device(), but we
  126. * also do it here in case there are still broken drivers that
  127. * don't use pci_enable_device().
  128. */
  129. printk(KERN_INFO "PCI: Routing interrupts for all devices because \"pci=routeirq\" specified\n");
  130. for_each_pci_dev(dev)
  131. acpi_pci_irq_enable(dev);
  132. } else
  133. printk(KERN_INFO "PCI: If a device doesn't work, try \"pci=routeirq\". If it helps, post a report\n");
  134. return 0;
  135. }
  136. subsys_initcall(pci_acpi_init);
  137. /* Called by ACPI when it finds a new root bus. */
  138. static struct pci_controller * __devinit
  139. alloc_pci_controller (int seg)
  140. {
  141. struct pci_controller *controller;
  142. controller = kmalloc(sizeof(*controller), GFP_KERNEL);
  143. if (!controller)
  144. return NULL;
  145. memset(controller, 0, sizeof(*controller));
  146. controller->segment = seg;
  147. return controller;
  148. }
  149. static u64 __devinit
  150. add_io_space (struct acpi_resource_address64 *addr)
  151. {
  152. u64 offset;
  153. int sparse = 0;
  154. int i;
  155. if (addr->address_translation_offset == 0)
  156. return IO_SPACE_BASE(0); /* part of legacy IO space */
  157. if (addr->attribute.io.translation_attribute == ACPI_SPARSE_TRANSLATION)
  158. sparse = 1;
  159. offset = (u64) ioremap(addr->address_translation_offset, 0);
  160. for (i = 0; i < num_io_spaces; i++)
  161. if (io_space[i].mmio_base == offset &&
  162. io_space[i].sparse == sparse)
  163. return IO_SPACE_BASE(i);
  164. if (num_io_spaces == MAX_IO_SPACES) {
  165. printk("Too many IO port spaces\n");
  166. return ~0;
  167. }
  168. i = num_io_spaces++;
  169. io_space[i].mmio_base = offset;
  170. io_space[i].sparse = sparse;
  171. return IO_SPACE_BASE(i);
  172. }
  173. static acpi_status __devinit
  174. count_window (struct acpi_resource *resource, void *data)
  175. {
  176. unsigned int *windows = (unsigned int *) data;
  177. struct acpi_resource_address64 addr;
  178. acpi_status status;
  179. status = acpi_resource_to_address64(resource, &addr);
  180. if (ACPI_SUCCESS(status))
  181. if (addr.resource_type == ACPI_MEMORY_RANGE ||
  182. addr.resource_type == ACPI_IO_RANGE)
  183. (*windows)++;
  184. return AE_OK;
  185. }
  186. struct pci_root_info {
  187. struct pci_controller *controller;
  188. char *name;
  189. };
  190. static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
  191. {
  192. struct pci_root_info *info = data;
  193. struct pci_window *window;
  194. struct acpi_resource_address64 addr;
  195. acpi_status status;
  196. unsigned long flags, offset = 0;
  197. struct resource *root;
  198. status = acpi_resource_to_address64(res, &addr);
  199. if (!ACPI_SUCCESS(status))
  200. return AE_OK;
  201. if (!addr.address_length)
  202. return AE_OK;
  203. if (addr.resource_type == ACPI_MEMORY_RANGE) {
  204. flags = IORESOURCE_MEM;
  205. root = &iomem_resource;
  206. offset = addr.address_translation_offset;
  207. } else if (addr.resource_type == ACPI_IO_RANGE) {
  208. flags = IORESOURCE_IO;
  209. root = &ioport_resource;
  210. offset = add_io_space(&addr);
  211. if (offset == ~0)
  212. return AE_OK;
  213. } else
  214. return AE_OK;
  215. window = &info->controller->window[info->controller->windows++];
  216. window->resource.name = info->name;
  217. window->resource.flags = flags;
  218. window->resource.start = addr.min_address_range + offset;
  219. window->resource.end = addr.max_address_range + offset;
  220. window->resource.child = NULL;
  221. window->offset = offset;
  222. if (insert_resource(root, &window->resource)) {
  223. printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n",
  224. window->resource.start, window->resource.end,
  225. root->name, info->name);
  226. }
  227. return AE_OK;
  228. }
  229. static void __devinit
  230. pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl)
  231. {
  232. int i, j;
  233. j = 0;
  234. for (i = 0; i < ctrl->windows; i++) {
  235. struct resource *res = &ctrl->window[i].resource;
  236. /* HP's firmware has a hack to work around a Windows bug.
  237. * Ignore these tiny memory ranges */
  238. if ((res->flags & IORESOURCE_MEM) &&
  239. (res->end - res->start < 16))
  240. continue;
  241. if (j >= PCI_BUS_NUM_RESOURCES) {
  242. printk("Ignoring range [%lx-%lx] (%lx)\n", res->start,
  243. res->end, res->flags);
  244. continue;
  245. }
  246. bus->resource[j++] = res;
  247. }
  248. }
  249. struct pci_bus * __devinit
  250. pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
  251. {
  252. struct pci_root_info info;
  253. struct pci_controller *controller;
  254. unsigned int windows = 0;
  255. struct pci_bus *pbus;
  256. char *name;
  257. controller = alloc_pci_controller(domain);
  258. if (!controller)
  259. goto out1;
  260. controller->acpi_handle = device->handle;
  261. acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
  262. &windows);
  263. controller->window = kmalloc(sizeof(*controller->window) * windows,
  264. GFP_KERNEL);
  265. if (!controller->window)
  266. goto out2;
  267. name = kmalloc(16, GFP_KERNEL);
  268. if (!name)
  269. goto out3;
  270. sprintf(name, "PCI Bus %04x:%02x", domain, bus);
  271. info.controller = controller;
  272. info.name = name;
  273. acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window,
  274. &info);
  275. pbus = pci_scan_bus(bus, &pci_root_ops, controller);
  276. if (pbus)
  277. pcibios_setup_root_windows(pbus, controller);
  278. return pbus;
  279. out3:
  280. kfree(controller->window);
  281. out2:
  282. kfree(controller);
  283. out1:
  284. return NULL;
  285. }
  286. void pcibios_resource_to_bus(struct pci_dev *dev,
  287. struct pci_bus_region *region, struct resource *res)
  288. {
  289. struct pci_controller *controller = PCI_CONTROLLER(dev);
  290. unsigned long offset = 0;
  291. int i;
  292. for (i = 0; i < controller->windows; i++) {
  293. struct pci_window *window = &controller->window[i];
  294. if (!(window->resource.flags & res->flags))
  295. continue;
  296. if (window->resource.start > res->start)
  297. continue;
  298. if (window->resource.end < res->end)
  299. continue;
  300. offset = window->offset;
  301. break;
  302. }
  303. region->start = res->start - offset;
  304. region->end = res->end - offset;
  305. }
  306. EXPORT_SYMBOL(pcibios_resource_to_bus);
  307. void pcibios_bus_to_resource(struct pci_dev *dev,
  308. struct resource *res, struct pci_bus_region *region)
  309. {
  310. struct pci_controller *controller = PCI_CONTROLLER(dev);
  311. unsigned long offset = 0;
  312. int i;
  313. for (i = 0; i < controller->windows; i++) {
  314. struct pci_window *window = &controller->window[i];
  315. if (!(window->resource.flags & res->flags))
  316. continue;
  317. if (window->resource.start - window->offset > region->start)
  318. continue;
  319. if (window->resource.end - window->offset < region->end)
  320. continue;
  321. offset = window->offset;
  322. break;
  323. }
  324. res->start = region->start + offset;
  325. res->end = region->end + offset;
  326. }
  327. static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
  328. {
  329. struct pci_bus_region region;
  330. int i;
  331. int limit = (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) ? \
  332. PCI_BRIDGE_RESOURCES : PCI_NUM_RESOURCES;
  333. for (i = 0; i < limit; i++) {
  334. if (!dev->resource[i].flags)
  335. continue;
  336. region.start = dev->resource[i].start;
  337. region.end = dev->resource[i].end;
  338. pcibios_bus_to_resource(dev, &dev->resource[i], &region);
  339. pci_claim_resource(dev, i);
  340. }
  341. }
  342. /*
  343. * Called after each bus is probed, but before its children are examined.
  344. */
  345. void __devinit
  346. pcibios_fixup_bus (struct pci_bus *b)
  347. {
  348. struct pci_dev *dev;
  349. list_for_each_entry(dev, &b->devices, bus_list)
  350. pcibios_fixup_device_resources(dev);
  351. return;
  352. }
  353. void __devinit
  354. pcibios_update_irq (struct pci_dev *dev, int irq)
  355. {
  356. pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
  357. /* ??? FIXME -- record old value for shutdown. */
  358. }
  359. static inline int
  360. pcibios_enable_resources (struct pci_dev *dev, int mask)
  361. {
  362. u16 cmd, old_cmd;
  363. int idx;
  364. struct resource *r;
  365. if (!dev)
  366. return -EINVAL;
  367. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  368. old_cmd = cmd;
  369. for (idx=0; idx<6; idx++) {
  370. /* Only set up the desired resources. */
  371. if (!(mask & (1 << idx)))
  372. continue;
  373. r = &dev->resource[idx];
  374. if (!r->start && r->end) {
  375. printk(KERN_ERR
  376. "PCI: Device %s not available because of resource collisions\n",
  377. pci_name(dev));
  378. return -EINVAL;
  379. }
  380. if (r->flags & IORESOURCE_IO)
  381. cmd |= PCI_COMMAND_IO;
  382. if (r->flags & IORESOURCE_MEM)
  383. cmd |= PCI_COMMAND_MEMORY;
  384. }
  385. if (dev->resource[PCI_ROM_RESOURCE].start)
  386. cmd |= PCI_COMMAND_MEMORY;
  387. if (cmd != old_cmd) {
  388. printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
  389. pci_write_config_word(dev, PCI_COMMAND, cmd);
  390. }
  391. return 0;
  392. }
  393. int
  394. pcibios_enable_device (struct pci_dev *dev, int mask)
  395. {
  396. int ret;
  397. ret = pcibios_enable_resources(dev, mask);
  398. if (ret < 0)
  399. return ret;
  400. return acpi_pci_irq_enable(dev);
  401. }
  402. #ifdef CONFIG_ACPI_DEALLOCATE_IRQ
  403. void
  404. pcibios_disable_device (struct pci_dev *dev)
  405. {
  406. acpi_pci_irq_disable(dev);
  407. }
  408. #endif /* CONFIG_ACPI_DEALLOCATE_IRQ */
  409. void
  410. pcibios_align_resource (void *data, struct resource *res,
  411. unsigned long size, unsigned long align)
  412. {
  413. }
  414. /*
  415. * PCI BIOS setup, always defaults to SAL interface
  416. */
  417. char * __init
  418. pcibios_setup (char *str)
  419. {
  420. if (!strcmp(str, "routeirq"))
  421. pci_routeirq = 1;
  422. return NULL;
  423. }
  424. int
  425. pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
  426. enum pci_mmap_state mmap_state, int write_combine)
  427. {
  428. /*
  429. * I/O space cannot be accessed via normal processor loads and
  430. * stores on this platform.
  431. */
  432. if (mmap_state == pci_mmap_io)
  433. /*
  434. * XXX we could relax this for I/O spaces for which ACPI
  435. * indicates that the space is 1-to-1 mapped. But at the
  436. * moment, we don't support multiple PCI address spaces and
  437. * the legacy I/O space is not 1-to-1 mapped, so this is moot.
  438. */
  439. return -EINVAL;
  440. /*
  441. * Leave vm_pgoff as-is, the PCI space address is the physical
  442. * address on this platform.
  443. */
  444. vma->vm_flags |= (VM_SHM | VM_RESERVED | VM_IO);
  445. if (write_combine && efi_range_is_wc(vma->vm_start,
  446. vma->vm_end - vma->vm_start))
  447. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  448. else
  449. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  450. if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  451. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  452. return -EAGAIN;
  453. return 0;
  454. }
  455. /**
  456. * ia64_pci_get_legacy_mem - generic legacy mem routine
  457. * @bus: bus to get legacy memory base address for
  458. *
  459. * Find the base of legacy memory for @bus. This is typically the first
  460. * megabyte of bus address space for @bus or is simply 0 on platforms whose
  461. * chipsets support legacy I/O and memory routing. Returns the base address
  462. * or an error pointer if an error occurred.
  463. *
  464. * This is the ia64 generic version of this routine. Other platforms
  465. * are free to override it with a machine vector.
  466. */
  467. char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
  468. {
  469. return (char *)__IA64_UNCACHED_OFFSET;
  470. }
  471. /**
  472. * pci_mmap_legacy_page_range - map legacy memory space to userland
  473. * @bus: bus whose legacy space we're mapping
  474. * @vma: vma passed in by mmap
  475. *
  476. * Map legacy memory space for this device back to userspace using a machine
  477. * vector to get the base address.
  478. */
  479. int
  480. pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma)
  481. {
  482. char *addr;
  483. addr = pci_get_legacy_mem(bus);
  484. if (IS_ERR(addr))
  485. return PTR_ERR(addr);
  486. vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
  487. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  488. vma->vm_flags |= (VM_SHM | VM_RESERVED | VM_IO);
  489. if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  490. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  491. return -EAGAIN;
  492. return 0;
  493. }
  494. /**
  495. * ia64_pci_legacy_read - read from legacy I/O space
  496. * @bus: bus to read
  497. * @port: legacy port value
  498. * @val: caller allocated storage for returned value
  499. * @size: number of bytes to read
  500. *
  501. * Simply reads @size bytes from @port and puts the result in @val.
  502. *
  503. * Again, this (and the write routine) are generic versions that can be
  504. * overridden by the platform. This is necessary on platforms that don't
  505. * support legacy I/O routing or that hard fail on legacy I/O timeouts.
  506. */
  507. int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
  508. {
  509. int ret = size;
  510. switch (size) {
  511. case 1:
  512. *val = inb(port);
  513. break;
  514. case 2:
  515. *val = inw(port);
  516. break;
  517. case 4:
  518. *val = inl(port);
  519. break;
  520. default:
  521. ret = -EINVAL;
  522. break;
  523. }
  524. return ret;
  525. }
  526. /**
  527. * ia64_pci_legacy_write - perform a legacy I/O write
  528. * @bus: bus pointer
  529. * @port: port to write
  530. * @val: value to write
  531. * @size: number of bytes to write from @val
  532. *
  533. * Simply writes @size bytes of @val to @port.
  534. */
  535. int ia64_pci_legacy_write(struct pci_dev *bus, u16 port, u32 val, u8 size)
  536. {
  537. int ret = 0;
  538. switch (size) {
  539. case 1:
  540. outb(val, port);
  541. break;
  542. case 2:
  543. outw(val, port);
  544. break;
  545. case 4:
  546. outl(val, port);
  547. break;
  548. default:
  549. ret = -EINVAL;
  550. break;
  551. }
  552. return ret;
  553. }
  554. /**
  555. * pci_cacheline_size - determine cacheline size for PCI devices
  556. * @dev: void
  557. *
  558. * We want to use the line-size of the outer-most cache. We assume
  559. * that this line-size is the same for all CPUs.
  560. *
  561. * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
  562. *
  563. * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
  564. */
  565. static unsigned long
  566. pci_cacheline_size (void)
  567. {
  568. u64 levels, unique_caches;
  569. s64 status;
  570. pal_cache_config_info_t cci;
  571. static u8 cacheline_size;
  572. if (cacheline_size)
  573. return cacheline_size;
  574. status = ia64_pal_cache_summary(&levels, &unique_caches);
  575. if (status != 0) {
  576. printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
  577. __FUNCTION__, status);
  578. return SMP_CACHE_BYTES;
  579. }
  580. status = ia64_pal_cache_config_info(levels - 1, /* cache_type (data_or_unified)= */ 2,
  581. &cci);
  582. if (status != 0) {
  583. printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed (status=%ld)\n",
  584. __FUNCTION__, status);
  585. return SMP_CACHE_BYTES;
  586. }
  587. cacheline_size = 1 << cci.pcci_line_size;
  588. return cacheline_size;
  589. }
  590. /**
  591. * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi()
  592. * @dev: the PCI device for which MWI is enabled
  593. *
  594. * For ia64, we can get the cacheline sizes from PAL.
  595. *
  596. * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
  597. */
  598. int
  599. pcibios_prep_mwi (struct pci_dev *dev)
  600. {
  601. unsigned long desired_linesize, current_linesize;
  602. int rc = 0;
  603. u8 pci_linesize;
  604. desired_linesize = pci_cacheline_size();
  605. pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_linesize);
  606. current_linesize = 4 * pci_linesize;
  607. if (desired_linesize != current_linesize) {
  608. printk(KERN_WARNING "PCI: slot %s has incorrect PCI cache line size of %lu bytes,",
  609. pci_name(dev), current_linesize);
  610. if (current_linesize > desired_linesize) {
  611. printk(" expected %lu bytes instead\n", desired_linesize);
  612. rc = -EINVAL;
  613. } else {
  614. printk(" correcting to %lu\n", desired_linesize);
  615. pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, desired_linesize / 4);
  616. }
  617. }
  618. return rc;
  619. }
  620. int pci_vector_resources(int last, int nr_released)
  621. {
  622. int count = nr_released;
  623. count += (IA64_LAST_DEVICE_VECTOR - last);
  624. return count;
  625. }