core.c 7.8 KB

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  1. /*
  2. * linux/arch/arm/mach-clps7500/core.c
  3. *
  4. * Copyright (C) 1998 Russell King
  5. * Copyright (C) 1999 Nexus Electronics Ltd
  6. *
  7. * Extra MM routines for CL7500 architecture
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/types.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/list.h>
  13. #include <linux/sched.h>
  14. #include <linux/init.h>
  15. #include <linux/device.h>
  16. #include <linux/serial_8250.h>
  17. #include <asm/mach/arch.h>
  18. #include <asm/mach/map.h>
  19. #include <asm/mach/irq.h>
  20. #include <asm/mach/time.h>
  21. #include <asm/hardware.h>
  22. #include <asm/hardware/iomd.h>
  23. #include <asm/io.h>
  24. #include <asm/irq.h>
  25. #include <asm/mach-types.h>
  26. static void cl7500_ack_irq_a(unsigned int irq)
  27. {
  28. unsigned int val, mask;
  29. mask = 1 << irq;
  30. val = iomd_readb(IOMD_IRQMASKA);
  31. iomd_writeb(val & ~mask, IOMD_IRQMASKA);
  32. iomd_writeb(mask, IOMD_IRQCLRA);
  33. }
  34. static void cl7500_mask_irq_a(unsigned int irq)
  35. {
  36. unsigned int val, mask;
  37. mask = 1 << irq;
  38. val = iomd_readb(IOMD_IRQMASKA);
  39. iomd_writeb(val & ~mask, IOMD_IRQMASKA);
  40. }
  41. static void cl7500_unmask_irq_a(unsigned int irq)
  42. {
  43. unsigned int val, mask;
  44. mask = 1 << irq;
  45. val = iomd_readb(IOMD_IRQMASKA);
  46. iomd_writeb(val | mask, IOMD_IRQMASKA);
  47. }
  48. static struct irqchip clps7500_a_chip = {
  49. .ack = cl7500_ack_irq_a,
  50. .mask = cl7500_mask_irq_a,
  51. .unmask = cl7500_unmask_irq_a,
  52. };
  53. static void cl7500_mask_irq_b(unsigned int irq)
  54. {
  55. unsigned int val, mask;
  56. mask = 1 << (irq & 7);
  57. val = iomd_readb(IOMD_IRQMASKB);
  58. iomd_writeb(val & ~mask, IOMD_IRQMASKB);
  59. }
  60. static void cl7500_unmask_irq_b(unsigned int irq)
  61. {
  62. unsigned int val, mask;
  63. mask = 1 << (irq & 7);
  64. val = iomd_readb(IOMD_IRQMASKB);
  65. iomd_writeb(val | mask, IOMD_IRQMASKB);
  66. }
  67. static struct irqchip clps7500_b_chip = {
  68. .ack = cl7500_mask_irq_b,
  69. .mask = cl7500_mask_irq_b,
  70. .unmask = cl7500_unmask_irq_b,
  71. };
  72. static void cl7500_mask_irq_c(unsigned int irq)
  73. {
  74. unsigned int val, mask;
  75. mask = 1 << (irq & 7);
  76. val = iomd_readb(IOMD_IRQMASKC);
  77. iomd_writeb(val & ~mask, IOMD_IRQMASKC);
  78. }
  79. static void cl7500_unmask_irq_c(unsigned int irq)
  80. {
  81. unsigned int val, mask;
  82. mask = 1 << (irq & 7);
  83. val = iomd_readb(IOMD_IRQMASKC);
  84. iomd_writeb(val | mask, IOMD_IRQMASKC);
  85. }
  86. static struct irqchip clps7500_c_chip = {
  87. .ack = cl7500_mask_irq_c,
  88. .mask = cl7500_mask_irq_c,
  89. .unmask = cl7500_unmask_irq_c,
  90. };
  91. static void cl7500_mask_irq_d(unsigned int irq)
  92. {
  93. unsigned int val, mask;
  94. mask = 1 << (irq & 7);
  95. val = iomd_readb(IOMD_IRQMASKD);
  96. iomd_writeb(val & ~mask, IOMD_IRQMASKD);
  97. }
  98. static void cl7500_unmask_irq_d(unsigned int irq)
  99. {
  100. unsigned int val, mask;
  101. mask = 1 << (irq & 7);
  102. val = iomd_readb(IOMD_IRQMASKD);
  103. iomd_writeb(val | mask, IOMD_IRQMASKD);
  104. }
  105. static struct irqchip clps7500_d_chip = {
  106. .ack = cl7500_mask_irq_d,
  107. .mask = cl7500_mask_irq_d,
  108. .unmask = cl7500_unmask_irq_d,
  109. };
  110. static void cl7500_mask_irq_dma(unsigned int irq)
  111. {
  112. unsigned int val, mask;
  113. mask = 1 << (irq & 7);
  114. val = iomd_readb(IOMD_DMAMASK);
  115. iomd_writeb(val & ~mask, IOMD_DMAMASK);
  116. }
  117. static void cl7500_unmask_irq_dma(unsigned int irq)
  118. {
  119. unsigned int val, mask;
  120. mask = 1 << (irq & 7);
  121. val = iomd_readb(IOMD_DMAMASK);
  122. iomd_writeb(val | mask, IOMD_DMAMASK);
  123. }
  124. static struct irqchip clps7500_dma_chip = {
  125. .ack = cl7500_mask_irq_dma,
  126. .mask = cl7500_mask_irq_dma,
  127. .unmask = cl7500_unmask_irq_dma,
  128. };
  129. static void cl7500_mask_irq_fiq(unsigned int irq)
  130. {
  131. unsigned int val, mask;
  132. mask = 1 << (irq & 7);
  133. val = iomd_readb(IOMD_FIQMASK);
  134. iomd_writeb(val & ~mask, IOMD_FIQMASK);
  135. }
  136. static void cl7500_unmask_irq_fiq(unsigned int irq)
  137. {
  138. unsigned int val, mask;
  139. mask = 1 << (irq & 7);
  140. val = iomd_readb(IOMD_FIQMASK);
  141. iomd_writeb(val | mask, IOMD_FIQMASK);
  142. }
  143. static struct irqchip clps7500_fiq_chip = {
  144. .ack = cl7500_mask_irq_fiq,
  145. .mask = cl7500_mask_irq_fiq,
  146. .unmask = cl7500_unmask_irq_fiq,
  147. };
  148. static void cl7500_no_action(unsigned int irq)
  149. {
  150. }
  151. static struct irqchip clps7500_no_chip = {
  152. .ack = cl7500_no_action,
  153. .mask = cl7500_no_action,
  154. .unmask = cl7500_no_action,
  155. };
  156. static struct irqaction irq_isa = { no_action, 0, CPU_MASK_NONE, "isa", NULL, NULL };
  157. static void __init clps7500_init_irq(void)
  158. {
  159. unsigned int irq, flags;
  160. iomd_writeb(0, IOMD_IRQMASKA);
  161. iomd_writeb(0, IOMD_IRQMASKB);
  162. iomd_writeb(0, IOMD_FIQMASK);
  163. iomd_writeb(0, IOMD_DMAMASK);
  164. for (irq = 0; irq < NR_IRQS; irq++) {
  165. flags = IRQF_VALID;
  166. if (irq <= 6 || (irq >= 9 && irq <= 15) ||
  167. (irq >= 48 && irq <= 55))
  168. flags |= IRQF_PROBE;
  169. switch (irq) {
  170. case 0 ... 7:
  171. set_irq_chip(irq, &clps7500_a_chip);
  172. set_irq_handler(irq, do_level_IRQ);
  173. set_irq_flags(irq, flags);
  174. break;
  175. case 8 ... 15:
  176. set_irq_chip(irq, &clps7500_b_chip);
  177. set_irq_handler(irq, do_level_IRQ);
  178. set_irq_flags(irq, flags);
  179. break;
  180. case 16 ... 22:
  181. set_irq_chip(irq, &clps7500_dma_chip);
  182. set_irq_handler(irq, do_level_IRQ);
  183. set_irq_flags(irq, flags);
  184. break;
  185. case 24 ... 31:
  186. set_irq_chip(irq, &clps7500_c_chip);
  187. set_irq_handler(irq, do_level_IRQ);
  188. set_irq_flags(irq, flags);
  189. break;
  190. case 40 ... 47:
  191. set_irq_chip(irq, &clps7500_d_chip);
  192. set_irq_handler(irq, do_level_IRQ);
  193. set_irq_flags(irq, flags);
  194. break;
  195. case 48 ... 55:
  196. set_irq_chip(irq, &clps7500_no_chip);
  197. set_irq_handler(irq, do_level_IRQ);
  198. set_irq_flags(irq, flags);
  199. break;
  200. case 64 ... 72:
  201. set_irq_chip(irq, &clps7500_fiq_chip);
  202. set_irq_handler(irq, do_level_IRQ);
  203. set_irq_flags(irq, flags);
  204. break;
  205. }
  206. }
  207. setup_irq(IRQ_ISA, &irq_isa);
  208. }
  209. static struct map_desc cl7500_io_desc[] __initdata = {
  210. { IO_BASE, IO_START, IO_SIZE, MT_DEVICE }, /* IO space */
  211. { ISA_BASE, ISA_START, ISA_SIZE, MT_DEVICE }, /* ISA space */
  212. { FLASH_BASE, FLASH_START, FLASH_SIZE, MT_DEVICE }, /* Flash */
  213. { LED_BASE, LED_START, LED_SIZE, MT_DEVICE } /* LED */
  214. };
  215. static void __init clps7500_map_io(void)
  216. {
  217. iotable_init(cl7500_io_desc, ARRAY_SIZE(cl7500_io_desc));
  218. }
  219. extern void ioctime_init(void);
  220. extern unsigned long ioc_timer_gettimeoffset(void);
  221. static irqreturn_t
  222. clps7500_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  223. {
  224. write_seqlock(&xtime_lock);
  225. timer_tick(regs);
  226. /* Why not using do_leds interface?? */
  227. {
  228. /* Twinkle the lights. */
  229. static int count, state = 0xff00;
  230. if (count-- == 0) {
  231. state ^= 0x100;
  232. count = 25;
  233. *((volatile unsigned int *)LED_ADDRESS) = state;
  234. }
  235. }
  236. write_sequnlock(&xtime_lock);
  237. return IRQ_HANDLED;
  238. }
  239. static struct irqaction clps7500_timer_irq = {
  240. .name = "CLPS7500 Timer Tick",
  241. .flags = SA_INTERRUPT,
  242. .handler = clps7500_timer_interrupt
  243. };
  244. /*
  245. * Set up timer interrupt.
  246. */
  247. static void __init clps7500_timer_init(void)
  248. {
  249. ioctime_init();
  250. setup_irq(IRQ_TIMER, &clps7500_timer_irq);
  251. }
  252. static struct sys_timer clps7500_timer = {
  253. .init = clps7500_timer_init,
  254. .offset = ioc_timer_gettimeoffset,
  255. };
  256. static struct plat_serial8250_port serial_platform_data[] = {
  257. {
  258. .mapbase = 0x03010fe0,
  259. .irq = 10,
  260. .uartclk = 1843200,
  261. .regshift = 2,
  262. .iotype = UPIO_MEM,
  263. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST,
  264. },
  265. {
  266. .mapbase = 0x03010be0,
  267. .irq = 0,
  268. .uartclk = 1843200,
  269. .regshift = 2,
  270. .iotype = UPIO_MEM,
  271. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST,
  272. },
  273. {
  274. .iobase = ISASLOT_IO + 0x2e8,
  275. .irq = 41,
  276. .uartclk = 1843200,
  277. .regshift = 0,
  278. .iotype = UPIO_PORT,
  279. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  280. },
  281. {
  282. .iobase = ISASLOT_IO + 0x3e8,
  283. .irq = 40,
  284. .uartclk = 1843200,
  285. .regshift = 0,
  286. .iotype = UPIO_PORT,
  287. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  288. },
  289. { },
  290. };
  291. static struct platform_device serial_device = {
  292. .name = "serial8250",
  293. .id = 0,
  294. .dev = {
  295. .platform_data = serial_platform_data,
  296. },
  297. };
  298. static void __init clps7500_init(void)
  299. {
  300. platform_device_register(&serial_device);
  301. }
  302. MACHINE_START(CLPS7500, "CL-PS7500")
  303. MAINTAINER("Philip Blundell")
  304. BOOT_MEM(0x10000000, 0x03000000, 0xe0000000)
  305. MAPIO(clps7500_map_io)
  306. INITIRQ(clps7500_init_irq)
  307. .init_machine = clps7500_init,
  308. .timer = &clps7500_timer,
  309. MACHINE_END