e1000_main.c 121 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355
  1. /*******************************************************************************
  2. Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
  3. This program is free software; you can redistribute it and/or modify it
  4. under the terms of the GNU General Public License as published by the Free
  5. Software Foundation; either version 2 of the License, or (at your option)
  6. any later version.
  7. This program is distributed in the hope that it will be useful, but WITHOUT
  8. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  9. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  10. more details.
  11. You should have received a copy of the GNU General Public License along with
  12. this program; if not, write to the Free Software Foundation, Inc., 59
  13. Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  14. The full GNU General Public License is included in this distribution in the
  15. file called LICENSE.
  16. Contact Information:
  17. Linux NICS <linux.nics@intel.com>
  18. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  19. *******************************************************************************/
  20. #include "e1000.h"
  21. /* Change Log
  22. * 6.0.58 4/20/05
  23. * o Accepted ethtool cleanup patch from Stephen Hemminger
  24. * 6.0.44+ 2/15/05
  25. * o applied Anton's patch to resolve tx hang in hardware
  26. * o Applied Andrew Mortons patch - e1000 stops working after resume
  27. */
  28. char e1000_driver_name[] = "e1000";
  29. char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
  30. #ifndef CONFIG_E1000_NAPI
  31. #define DRIVERNAPI
  32. #else
  33. #define DRIVERNAPI "-NAPI"
  34. #endif
  35. #define DRV_VERSION "6.0.60-k2"DRIVERNAPI
  36. char e1000_driver_version[] = DRV_VERSION;
  37. char e1000_copyright[] = "Copyright (c) 1999-2005 Intel Corporation.";
  38. /* e1000_pci_tbl - PCI Device ID Table
  39. *
  40. * Last entry must be all 0s
  41. *
  42. * Macro expands to...
  43. * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
  44. */
  45. static struct pci_device_id e1000_pci_tbl[] = {
  46. INTEL_E1000_ETHERNET_DEVICE(0x1000),
  47. INTEL_E1000_ETHERNET_DEVICE(0x1001),
  48. INTEL_E1000_ETHERNET_DEVICE(0x1004),
  49. INTEL_E1000_ETHERNET_DEVICE(0x1008),
  50. INTEL_E1000_ETHERNET_DEVICE(0x1009),
  51. INTEL_E1000_ETHERNET_DEVICE(0x100C),
  52. INTEL_E1000_ETHERNET_DEVICE(0x100D),
  53. INTEL_E1000_ETHERNET_DEVICE(0x100E),
  54. INTEL_E1000_ETHERNET_DEVICE(0x100F),
  55. INTEL_E1000_ETHERNET_DEVICE(0x1010),
  56. INTEL_E1000_ETHERNET_DEVICE(0x1011),
  57. INTEL_E1000_ETHERNET_DEVICE(0x1012),
  58. INTEL_E1000_ETHERNET_DEVICE(0x1013),
  59. INTEL_E1000_ETHERNET_DEVICE(0x1014),
  60. INTEL_E1000_ETHERNET_DEVICE(0x1015),
  61. INTEL_E1000_ETHERNET_DEVICE(0x1016),
  62. INTEL_E1000_ETHERNET_DEVICE(0x1017),
  63. INTEL_E1000_ETHERNET_DEVICE(0x1018),
  64. INTEL_E1000_ETHERNET_DEVICE(0x1019),
  65. INTEL_E1000_ETHERNET_DEVICE(0x101A),
  66. INTEL_E1000_ETHERNET_DEVICE(0x101D),
  67. INTEL_E1000_ETHERNET_DEVICE(0x101E),
  68. INTEL_E1000_ETHERNET_DEVICE(0x1026),
  69. INTEL_E1000_ETHERNET_DEVICE(0x1027),
  70. INTEL_E1000_ETHERNET_DEVICE(0x1028),
  71. INTEL_E1000_ETHERNET_DEVICE(0x1075),
  72. INTEL_E1000_ETHERNET_DEVICE(0x1076),
  73. INTEL_E1000_ETHERNET_DEVICE(0x1077),
  74. INTEL_E1000_ETHERNET_DEVICE(0x1078),
  75. INTEL_E1000_ETHERNET_DEVICE(0x1079),
  76. INTEL_E1000_ETHERNET_DEVICE(0x107A),
  77. INTEL_E1000_ETHERNET_DEVICE(0x107B),
  78. INTEL_E1000_ETHERNET_DEVICE(0x107C),
  79. INTEL_E1000_ETHERNET_DEVICE(0x108A),
  80. INTEL_E1000_ETHERNET_DEVICE(0x108B),
  81. INTEL_E1000_ETHERNET_DEVICE(0x108C),
  82. INTEL_E1000_ETHERNET_DEVICE(0x1099),
  83. /* required last entry */
  84. {0,}
  85. };
  86. MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
  87. int e1000_up(struct e1000_adapter *adapter);
  88. void e1000_down(struct e1000_adapter *adapter);
  89. void e1000_reset(struct e1000_adapter *adapter);
  90. int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx);
  91. int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
  92. int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
  93. void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
  94. void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
  95. int e1000_setup_tx_resources(struct e1000_adapter *adapter,
  96. struct e1000_tx_ring *txdr);
  97. int e1000_setup_rx_resources(struct e1000_adapter *adapter,
  98. struct e1000_rx_ring *rxdr);
  99. void e1000_free_tx_resources(struct e1000_adapter *adapter,
  100. struct e1000_tx_ring *tx_ring);
  101. void e1000_free_rx_resources(struct e1000_adapter *adapter,
  102. struct e1000_rx_ring *rx_ring);
  103. void e1000_update_stats(struct e1000_adapter *adapter);
  104. /* Local Function Prototypes */
  105. static int e1000_init_module(void);
  106. static void e1000_exit_module(void);
  107. static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
  108. static void __devexit e1000_remove(struct pci_dev *pdev);
  109. static int e1000_alloc_queues(struct e1000_adapter *adapter);
  110. #ifdef CONFIG_E1000_MQ
  111. static void e1000_setup_queue_mapping(struct e1000_adapter *adapter);
  112. #endif
  113. static int e1000_sw_init(struct e1000_adapter *adapter);
  114. static int e1000_open(struct net_device *netdev);
  115. static int e1000_close(struct net_device *netdev);
  116. static void e1000_configure_tx(struct e1000_adapter *adapter);
  117. static void e1000_configure_rx(struct e1000_adapter *adapter);
  118. static void e1000_setup_rctl(struct e1000_adapter *adapter);
  119. static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
  120. static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
  121. static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
  122. struct e1000_tx_ring *tx_ring);
  123. static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
  124. struct e1000_rx_ring *rx_ring);
  125. static void e1000_set_multi(struct net_device *netdev);
  126. static void e1000_update_phy_info(unsigned long data);
  127. static void e1000_watchdog(unsigned long data);
  128. static void e1000_watchdog_task(struct e1000_adapter *adapter);
  129. static void e1000_82547_tx_fifo_stall(unsigned long data);
  130. static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
  131. static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
  132. static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
  133. static int e1000_set_mac(struct net_device *netdev, void *p);
  134. static irqreturn_t e1000_intr(int irq, void *data, struct pt_regs *regs);
  135. static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
  136. struct e1000_tx_ring *tx_ring);
  137. #ifdef CONFIG_E1000_NAPI
  138. static int e1000_clean(struct net_device *poll_dev, int *budget);
  139. static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
  140. struct e1000_rx_ring *rx_ring,
  141. int *work_done, int work_to_do);
  142. static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
  143. struct e1000_rx_ring *rx_ring,
  144. int *work_done, int work_to_do);
  145. #else
  146. static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
  147. struct e1000_rx_ring *rx_ring);
  148. static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
  149. struct e1000_rx_ring *rx_ring);
  150. #endif
  151. static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
  152. struct e1000_rx_ring *rx_ring);
  153. static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
  154. struct e1000_rx_ring *rx_ring);
  155. static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
  156. static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
  157. int cmd);
  158. void e1000_set_ethtool_ops(struct net_device *netdev);
  159. static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
  160. static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
  161. static void e1000_tx_timeout(struct net_device *dev);
  162. static void e1000_tx_timeout_task(struct net_device *dev);
  163. static void e1000_smartspeed(struct e1000_adapter *adapter);
  164. static inline int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
  165. struct sk_buff *skb);
  166. static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
  167. static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
  168. static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
  169. static void e1000_restore_vlan(struct e1000_adapter *adapter);
  170. static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
  171. #ifdef CONFIG_PM
  172. static int e1000_resume(struct pci_dev *pdev);
  173. #endif
  174. #ifdef CONFIG_NET_POLL_CONTROLLER
  175. /* for netdump / net console */
  176. static void e1000_netpoll (struct net_device *netdev);
  177. #endif
  178. #ifdef CONFIG_E1000_MQ
  179. /* for multiple Rx queues */
  180. void e1000_rx_schedule(void *data);
  181. #endif
  182. /* Exported from other modules */
  183. extern void e1000_check_options(struct e1000_adapter *adapter);
  184. static struct pci_driver e1000_driver = {
  185. .name = e1000_driver_name,
  186. .id_table = e1000_pci_tbl,
  187. .probe = e1000_probe,
  188. .remove = __devexit_p(e1000_remove),
  189. /* Power Managment Hooks */
  190. #ifdef CONFIG_PM
  191. .suspend = e1000_suspend,
  192. .resume = e1000_resume
  193. #endif
  194. };
  195. MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
  196. MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
  197. MODULE_LICENSE("GPL");
  198. MODULE_VERSION(DRV_VERSION);
  199. static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
  200. module_param(debug, int, 0);
  201. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  202. /**
  203. * e1000_init_module - Driver Registration Routine
  204. *
  205. * e1000_init_module is the first routine called when the driver is
  206. * loaded. All it does is register with the PCI subsystem.
  207. **/
  208. static int __init
  209. e1000_init_module(void)
  210. {
  211. int ret;
  212. printk(KERN_INFO "%s - version %s\n",
  213. e1000_driver_string, e1000_driver_version);
  214. printk(KERN_INFO "%s\n", e1000_copyright);
  215. ret = pci_module_init(&e1000_driver);
  216. return ret;
  217. }
  218. module_init(e1000_init_module);
  219. /**
  220. * e1000_exit_module - Driver Exit Cleanup Routine
  221. *
  222. * e1000_exit_module is called just before the driver is removed
  223. * from memory.
  224. **/
  225. static void __exit
  226. e1000_exit_module(void)
  227. {
  228. pci_unregister_driver(&e1000_driver);
  229. }
  230. module_exit(e1000_exit_module);
  231. /**
  232. * e1000_irq_disable - Mask off interrupt generation on the NIC
  233. * @adapter: board private structure
  234. **/
  235. static inline void
  236. e1000_irq_disable(struct e1000_adapter *adapter)
  237. {
  238. atomic_inc(&adapter->irq_sem);
  239. E1000_WRITE_REG(&adapter->hw, IMC, ~0);
  240. E1000_WRITE_FLUSH(&adapter->hw);
  241. synchronize_irq(adapter->pdev->irq);
  242. }
  243. /**
  244. * e1000_irq_enable - Enable default interrupt generation settings
  245. * @adapter: board private structure
  246. **/
  247. static inline void
  248. e1000_irq_enable(struct e1000_adapter *adapter)
  249. {
  250. if(likely(atomic_dec_and_test(&adapter->irq_sem))) {
  251. E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
  252. E1000_WRITE_FLUSH(&adapter->hw);
  253. }
  254. }
  255. void
  256. e1000_update_mng_vlan(struct e1000_adapter *adapter)
  257. {
  258. struct net_device *netdev = adapter->netdev;
  259. uint16_t vid = adapter->hw.mng_cookie.vlan_id;
  260. uint16_t old_vid = adapter->mng_vlan_id;
  261. if(adapter->vlgrp) {
  262. if(!adapter->vlgrp->vlan_devices[vid]) {
  263. if(adapter->hw.mng_cookie.status &
  264. E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
  265. e1000_vlan_rx_add_vid(netdev, vid);
  266. adapter->mng_vlan_id = vid;
  267. } else
  268. adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
  269. if((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
  270. (vid != old_vid) &&
  271. !adapter->vlgrp->vlan_devices[old_vid])
  272. e1000_vlan_rx_kill_vid(netdev, old_vid);
  273. }
  274. }
  275. }
  276. int
  277. e1000_up(struct e1000_adapter *adapter)
  278. {
  279. struct net_device *netdev = adapter->netdev;
  280. int i, err;
  281. /* hardware has been reset, we need to reload some things */
  282. /* Reset the PHY if it was previously powered down */
  283. if(adapter->hw.media_type == e1000_media_type_copper) {
  284. uint16_t mii_reg;
  285. e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
  286. if(mii_reg & MII_CR_POWER_DOWN)
  287. e1000_phy_reset(&adapter->hw);
  288. }
  289. e1000_set_multi(netdev);
  290. e1000_restore_vlan(adapter);
  291. e1000_configure_tx(adapter);
  292. e1000_setup_rctl(adapter);
  293. e1000_configure_rx(adapter);
  294. for (i = 0; i < adapter->num_queues; i++)
  295. adapter->alloc_rx_buf(adapter, &adapter->rx_ring[i]);
  296. #ifdef CONFIG_PCI_MSI
  297. if(adapter->hw.mac_type > e1000_82547_rev_2) {
  298. adapter->have_msi = TRUE;
  299. if((err = pci_enable_msi(adapter->pdev))) {
  300. DPRINTK(PROBE, ERR,
  301. "Unable to allocate MSI interrupt Error: %d\n", err);
  302. adapter->have_msi = FALSE;
  303. }
  304. }
  305. #endif
  306. if((err = request_irq(adapter->pdev->irq, &e1000_intr,
  307. SA_SHIRQ | SA_SAMPLE_RANDOM,
  308. netdev->name, netdev))) {
  309. DPRINTK(PROBE, ERR,
  310. "Unable to allocate interrupt Error: %d\n", err);
  311. return err;
  312. }
  313. mod_timer(&adapter->watchdog_timer, jiffies);
  314. #ifdef CONFIG_E1000_NAPI
  315. netif_poll_enable(netdev);
  316. #endif
  317. e1000_irq_enable(adapter);
  318. return 0;
  319. }
  320. void
  321. e1000_down(struct e1000_adapter *adapter)
  322. {
  323. struct net_device *netdev = adapter->netdev;
  324. e1000_irq_disable(adapter);
  325. #ifdef CONFIG_E1000_MQ
  326. while (atomic_read(&adapter->rx_sched_call_data.count) != 0);
  327. #endif
  328. free_irq(adapter->pdev->irq, netdev);
  329. #ifdef CONFIG_PCI_MSI
  330. if(adapter->hw.mac_type > e1000_82547_rev_2 &&
  331. adapter->have_msi == TRUE)
  332. pci_disable_msi(adapter->pdev);
  333. #endif
  334. del_timer_sync(&adapter->tx_fifo_stall_timer);
  335. del_timer_sync(&adapter->watchdog_timer);
  336. del_timer_sync(&adapter->phy_info_timer);
  337. #ifdef CONFIG_E1000_NAPI
  338. netif_poll_disable(netdev);
  339. #endif
  340. adapter->link_speed = 0;
  341. adapter->link_duplex = 0;
  342. netif_carrier_off(netdev);
  343. netif_stop_queue(netdev);
  344. e1000_reset(adapter);
  345. e1000_clean_all_tx_rings(adapter);
  346. e1000_clean_all_rx_rings(adapter);
  347. /* If WoL is not enabled
  348. * and management mode is not IAMT
  349. * Power down the PHY so no link is implied when interface is down */
  350. if(!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
  351. adapter->hw.media_type == e1000_media_type_copper &&
  352. !e1000_check_mng_mode(&adapter->hw) &&
  353. !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN)) {
  354. uint16_t mii_reg;
  355. e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
  356. mii_reg |= MII_CR_POWER_DOWN;
  357. e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
  358. mdelay(1);
  359. }
  360. }
  361. void
  362. e1000_reset(struct e1000_adapter *adapter)
  363. {
  364. struct net_device *netdev = adapter->netdev;
  365. uint32_t pba, manc;
  366. uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
  367. uint16_t fc_low_water_mark = E1000_FC_LOW_DIFF;
  368. /* Repartition Pba for greater than 9k mtu
  369. * To take effect CTRL.RST is required.
  370. */
  371. switch (adapter->hw.mac_type) {
  372. case e1000_82547:
  373. case e1000_82547_rev_2:
  374. pba = E1000_PBA_30K;
  375. break;
  376. case e1000_82571:
  377. case e1000_82572:
  378. pba = E1000_PBA_38K;
  379. break;
  380. case e1000_82573:
  381. pba = E1000_PBA_12K;
  382. break;
  383. default:
  384. pba = E1000_PBA_48K;
  385. break;
  386. }
  387. if((adapter->hw.mac_type != e1000_82573) &&
  388. (adapter->rx_buffer_len > E1000_RXBUFFER_8192)) {
  389. pba -= 8; /* allocate more FIFO for Tx */
  390. /* send an XOFF when there is enough space in the
  391. * Rx FIFO to hold one extra full size Rx packet
  392. */
  393. fc_high_water_mark = netdev->mtu + ENET_HEADER_SIZE +
  394. ETHERNET_FCS_SIZE + 1;
  395. fc_low_water_mark = fc_high_water_mark + 8;
  396. }
  397. if(adapter->hw.mac_type == e1000_82547) {
  398. adapter->tx_fifo_head = 0;
  399. adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
  400. adapter->tx_fifo_size =
  401. (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
  402. atomic_set(&adapter->tx_fifo_stall, 0);
  403. }
  404. E1000_WRITE_REG(&adapter->hw, PBA, pba);
  405. /* flow control settings */
  406. adapter->hw.fc_high_water = (pba << E1000_PBA_BYTES_SHIFT) -
  407. fc_high_water_mark;
  408. adapter->hw.fc_low_water = (pba << E1000_PBA_BYTES_SHIFT) -
  409. fc_low_water_mark;
  410. adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
  411. adapter->hw.fc_send_xon = 1;
  412. adapter->hw.fc = adapter->hw.original_fc;
  413. /* Allow time for pending master requests to run */
  414. e1000_reset_hw(&adapter->hw);
  415. if(adapter->hw.mac_type >= e1000_82544)
  416. E1000_WRITE_REG(&adapter->hw, WUC, 0);
  417. if(e1000_init_hw(&adapter->hw))
  418. DPRINTK(PROBE, ERR, "Hardware Error\n");
  419. e1000_update_mng_vlan(adapter);
  420. /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
  421. E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
  422. e1000_reset_adaptive(&adapter->hw);
  423. e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
  424. if (adapter->en_mng_pt) {
  425. manc = E1000_READ_REG(&adapter->hw, MANC);
  426. manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
  427. E1000_WRITE_REG(&adapter->hw, MANC, manc);
  428. }
  429. }
  430. /**
  431. * e1000_probe - Device Initialization Routine
  432. * @pdev: PCI device information struct
  433. * @ent: entry in e1000_pci_tbl
  434. *
  435. * Returns 0 on success, negative on failure
  436. *
  437. * e1000_probe initializes an adapter identified by a pci_dev structure.
  438. * The OS initialization, configuring of the adapter private structure,
  439. * and a hardware reset occur.
  440. **/
  441. static int __devinit
  442. e1000_probe(struct pci_dev *pdev,
  443. const struct pci_device_id *ent)
  444. {
  445. struct net_device *netdev;
  446. struct e1000_adapter *adapter;
  447. unsigned long mmio_start, mmio_len;
  448. uint32_t ctrl_ext;
  449. uint32_t swsm;
  450. static int cards_found = 0;
  451. int i, err, pci_using_dac;
  452. uint16_t eeprom_data;
  453. uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
  454. if((err = pci_enable_device(pdev)))
  455. return err;
  456. if(!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
  457. pci_using_dac = 1;
  458. } else {
  459. if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
  460. E1000_ERR("No usable DMA configuration, aborting\n");
  461. return err;
  462. }
  463. pci_using_dac = 0;
  464. }
  465. if((err = pci_request_regions(pdev, e1000_driver_name)))
  466. return err;
  467. pci_set_master(pdev);
  468. netdev = alloc_etherdev(sizeof(struct e1000_adapter));
  469. if(!netdev) {
  470. err = -ENOMEM;
  471. goto err_alloc_etherdev;
  472. }
  473. SET_MODULE_OWNER(netdev);
  474. SET_NETDEV_DEV(netdev, &pdev->dev);
  475. pci_set_drvdata(pdev, netdev);
  476. adapter = netdev_priv(netdev);
  477. adapter->netdev = netdev;
  478. adapter->pdev = pdev;
  479. adapter->hw.back = adapter;
  480. adapter->msg_enable = (1 << debug) - 1;
  481. mmio_start = pci_resource_start(pdev, BAR_0);
  482. mmio_len = pci_resource_len(pdev, BAR_0);
  483. adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
  484. if(!adapter->hw.hw_addr) {
  485. err = -EIO;
  486. goto err_ioremap;
  487. }
  488. for(i = BAR_1; i <= BAR_5; i++) {
  489. if(pci_resource_len(pdev, i) == 0)
  490. continue;
  491. if(pci_resource_flags(pdev, i) & IORESOURCE_IO) {
  492. adapter->hw.io_base = pci_resource_start(pdev, i);
  493. break;
  494. }
  495. }
  496. netdev->open = &e1000_open;
  497. netdev->stop = &e1000_close;
  498. netdev->hard_start_xmit = &e1000_xmit_frame;
  499. netdev->get_stats = &e1000_get_stats;
  500. netdev->set_multicast_list = &e1000_set_multi;
  501. netdev->set_mac_address = &e1000_set_mac;
  502. netdev->change_mtu = &e1000_change_mtu;
  503. netdev->do_ioctl = &e1000_ioctl;
  504. e1000_set_ethtool_ops(netdev);
  505. netdev->tx_timeout = &e1000_tx_timeout;
  506. netdev->watchdog_timeo = 5 * HZ;
  507. #ifdef CONFIG_E1000_NAPI
  508. netdev->poll = &e1000_clean;
  509. netdev->weight = 64;
  510. #endif
  511. netdev->vlan_rx_register = e1000_vlan_rx_register;
  512. netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
  513. netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
  514. #ifdef CONFIG_NET_POLL_CONTROLLER
  515. netdev->poll_controller = e1000_netpoll;
  516. #endif
  517. strcpy(netdev->name, pci_name(pdev));
  518. netdev->mem_start = mmio_start;
  519. netdev->mem_end = mmio_start + mmio_len;
  520. netdev->base_addr = adapter->hw.io_base;
  521. adapter->bd_number = cards_found;
  522. /* setup the private structure */
  523. if((err = e1000_sw_init(adapter)))
  524. goto err_sw_init;
  525. if((err = e1000_check_phy_reset_block(&adapter->hw)))
  526. DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
  527. if(adapter->hw.mac_type >= e1000_82543) {
  528. netdev->features = NETIF_F_SG |
  529. NETIF_F_HW_CSUM |
  530. NETIF_F_HW_VLAN_TX |
  531. NETIF_F_HW_VLAN_RX |
  532. NETIF_F_HW_VLAN_FILTER;
  533. }
  534. #ifdef NETIF_F_TSO
  535. if((adapter->hw.mac_type >= e1000_82544) &&
  536. (adapter->hw.mac_type != e1000_82547))
  537. netdev->features |= NETIF_F_TSO;
  538. #ifdef NETIF_F_TSO_IPV6
  539. if(adapter->hw.mac_type > e1000_82547_rev_2)
  540. netdev->features |= NETIF_F_TSO_IPV6;
  541. #endif
  542. #endif
  543. if(pci_using_dac)
  544. netdev->features |= NETIF_F_HIGHDMA;
  545. /* hard_start_xmit is safe against parallel locking */
  546. netdev->features |= NETIF_F_LLTX;
  547. adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
  548. /* before reading the EEPROM, reset the controller to
  549. * put the device in a known good starting state */
  550. e1000_reset_hw(&adapter->hw);
  551. /* make sure the EEPROM is good */
  552. if(e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
  553. DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
  554. err = -EIO;
  555. goto err_eeprom;
  556. }
  557. /* copy the MAC address out of the EEPROM */
  558. if(e1000_read_mac_addr(&adapter->hw))
  559. DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
  560. memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
  561. memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
  562. if(!is_valid_ether_addr(netdev->perm_addr)) {
  563. DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
  564. err = -EIO;
  565. goto err_eeprom;
  566. }
  567. e1000_read_part_num(&adapter->hw, &(adapter->part_num));
  568. e1000_get_bus_info(&adapter->hw);
  569. init_timer(&adapter->tx_fifo_stall_timer);
  570. adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
  571. adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
  572. init_timer(&adapter->watchdog_timer);
  573. adapter->watchdog_timer.function = &e1000_watchdog;
  574. adapter->watchdog_timer.data = (unsigned long) adapter;
  575. INIT_WORK(&adapter->watchdog_task,
  576. (void (*)(void *))e1000_watchdog_task, adapter);
  577. init_timer(&adapter->phy_info_timer);
  578. adapter->phy_info_timer.function = &e1000_update_phy_info;
  579. adapter->phy_info_timer.data = (unsigned long) adapter;
  580. INIT_WORK(&adapter->tx_timeout_task,
  581. (void (*)(void *))e1000_tx_timeout_task, netdev);
  582. /* we're going to reset, so assume we have no link for now */
  583. netif_carrier_off(netdev);
  584. netif_stop_queue(netdev);
  585. e1000_check_options(adapter);
  586. /* Initial Wake on LAN setting
  587. * If APM wake is enabled in the EEPROM,
  588. * enable the ACPI Magic Packet filter
  589. */
  590. switch(adapter->hw.mac_type) {
  591. case e1000_82542_rev2_0:
  592. case e1000_82542_rev2_1:
  593. case e1000_82543:
  594. break;
  595. case e1000_82544:
  596. e1000_read_eeprom(&adapter->hw,
  597. EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
  598. eeprom_apme_mask = E1000_EEPROM_82544_APM;
  599. break;
  600. case e1000_82546:
  601. case e1000_82546_rev_3:
  602. if((E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1)
  603. && (adapter->hw.media_type == e1000_media_type_copper)) {
  604. e1000_read_eeprom(&adapter->hw,
  605. EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
  606. break;
  607. }
  608. /* Fall Through */
  609. default:
  610. e1000_read_eeprom(&adapter->hw,
  611. EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
  612. break;
  613. }
  614. if(eeprom_data & eeprom_apme_mask)
  615. adapter->wol |= E1000_WUFC_MAG;
  616. /* reset the hardware with the new settings */
  617. e1000_reset(adapter);
  618. /* Let firmware know the driver has taken over */
  619. switch(adapter->hw.mac_type) {
  620. case e1000_82571:
  621. case e1000_82572:
  622. ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
  623. E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
  624. ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
  625. break;
  626. case e1000_82573:
  627. swsm = E1000_READ_REG(&adapter->hw, SWSM);
  628. E1000_WRITE_REG(&adapter->hw, SWSM,
  629. swsm | E1000_SWSM_DRV_LOAD);
  630. break;
  631. default:
  632. break;
  633. }
  634. strcpy(netdev->name, "eth%d");
  635. if((err = register_netdev(netdev)))
  636. goto err_register;
  637. DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
  638. cards_found++;
  639. return 0;
  640. err_register:
  641. err_sw_init:
  642. err_eeprom:
  643. iounmap(adapter->hw.hw_addr);
  644. err_ioremap:
  645. free_netdev(netdev);
  646. err_alloc_etherdev:
  647. pci_release_regions(pdev);
  648. return err;
  649. }
  650. /**
  651. * e1000_remove - Device Removal Routine
  652. * @pdev: PCI device information struct
  653. *
  654. * e1000_remove is called by the PCI subsystem to alert the driver
  655. * that it should release a PCI device. The could be caused by a
  656. * Hot-Plug event, or because the driver is going to be removed from
  657. * memory.
  658. **/
  659. static void __devexit
  660. e1000_remove(struct pci_dev *pdev)
  661. {
  662. struct net_device *netdev = pci_get_drvdata(pdev);
  663. struct e1000_adapter *adapter = netdev_priv(netdev);
  664. uint32_t ctrl_ext;
  665. uint32_t manc, swsm;
  666. #ifdef CONFIG_E1000_NAPI
  667. int i;
  668. #endif
  669. flush_scheduled_work();
  670. if(adapter->hw.mac_type >= e1000_82540 &&
  671. adapter->hw.media_type == e1000_media_type_copper) {
  672. manc = E1000_READ_REG(&adapter->hw, MANC);
  673. if(manc & E1000_MANC_SMBUS_EN) {
  674. manc |= E1000_MANC_ARP_EN;
  675. E1000_WRITE_REG(&adapter->hw, MANC, manc);
  676. }
  677. }
  678. switch(adapter->hw.mac_type) {
  679. case e1000_82571:
  680. case e1000_82572:
  681. ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
  682. E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
  683. ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
  684. break;
  685. case e1000_82573:
  686. swsm = E1000_READ_REG(&adapter->hw, SWSM);
  687. E1000_WRITE_REG(&adapter->hw, SWSM,
  688. swsm & ~E1000_SWSM_DRV_LOAD);
  689. break;
  690. default:
  691. break;
  692. }
  693. unregister_netdev(netdev);
  694. #ifdef CONFIG_E1000_NAPI
  695. for (i = 0; i < adapter->num_queues; i++)
  696. __dev_put(&adapter->polling_netdev[i]);
  697. #endif
  698. if(!e1000_check_phy_reset_block(&adapter->hw))
  699. e1000_phy_hw_reset(&adapter->hw);
  700. kfree(adapter->tx_ring);
  701. kfree(adapter->rx_ring);
  702. #ifdef CONFIG_E1000_NAPI
  703. kfree(adapter->polling_netdev);
  704. #endif
  705. iounmap(adapter->hw.hw_addr);
  706. pci_release_regions(pdev);
  707. #ifdef CONFIG_E1000_MQ
  708. free_percpu(adapter->cpu_netdev);
  709. free_percpu(adapter->cpu_tx_ring);
  710. #endif
  711. free_netdev(netdev);
  712. pci_disable_device(pdev);
  713. }
  714. /**
  715. * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
  716. * @adapter: board private structure to initialize
  717. *
  718. * e1000_sw_init initializes the Adapter private data structure.
  719. * Fields are initialized based on PCI device information and
  720. * OS network device settings (MTU size).
  721. **/
  722. static int __devinit
  723. e1000_sw_init(struct e1000_adapter *adapter)
  724. {
  725. struct e1000_hw *hw = &adapter->hw;
  726. struct net_device *netdev = adapter->netdev;
  727. struct pci_dev *pdev = adapter->pdev;
  728. #ifdef CONFIG_E1000_NAPI
  729. int i;
  730. #endif
  731. /* PCI config space info */
  732. hw->vendor_id = pdev->vendor;
  733. hw->device_id = pdev->device;
  734. hw->subsystem_vendor_id = pdev->subsystem_vendor;
  735. hw->subsystem_id = pdev->subsystem_device;
  736. pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
  737. pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
  738. adapter->rx_buffer_len = E1000_RXBUFFER_2048;
  739. adapter->rx_ps_bsize0 = E1000_RXBUFFER_256;
  740. hw->max_frame_size = netdev->mtu +
  741. ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
  742. hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
  743. /* identify the MAC */
  744. if(e1000_set_mac_type(hw)) {
  745. DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
  746. return -EIO;
  747. }
  748. /* initialize eeprom parameters */
  749. if(e1000_init_eeprom_params(hw)) {
  750. E1000_ERR("EEPROM initialization failed\n");
  751. return -EIO;
  752. }
  753. switch(hw->mac_type) {
  754. default:
  755. break;
  756. case e1000_82541:
  757. case e1000_82547:
  758. case e1000_82541_rev_2:
  759. case e1000_82547_rev_2:
  760. hw->phy_init_script = 1;
  761. break;
  762. }
  763. e1000_set_media_type(hw);
  764. hw->wait_autoneg_complete = FALSE;
  765. hw->tbi_compatibility_en = TRUE;
  766. hw->adaptive_ifs = TRUE;
  767. /* Copper options */
  768. if(hw->media_type == e1000_media_type_copper) {
  769. hw->mdix = AUTO_ALL_MODES;
  770. hw->disable_polarity_correction = FALSE;
  771. hw->master_slave = E1000_MASTER_SLAVE;
  772. }
  773. #ifdef CONFIG_E1000_MQ
  774. /* Number of supported queues */
  775. switch (hw->mac_type) {
  776. case e1000_82571:
  777. case e1000_82572:
  778. adapter->num_queues = 2;
  779. break;
  780. default:
  781. adapter->num_queues = 1;
  782. break;
  783. }
  784. adapter->num_queues = min(adapter->num_queues, num_online_cpus());
  785. #else
  786. adapter->num_queues = 1;
  787. #endif
  788. if (e1000_alloc_queues(adapter)) {
  789. DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
  790. return -ENOMEM;
  791. }
  792. #ifdef CONFIG_E1000_NAPI
  793. for (i = 0; i < adapter->num_queues; i++) {
  794. adapter->polling_netdev[i].priv = adapter;
  795. adapter->polling_netdev[i].poll = &e1000_clean;
  796. adapter->polling_netdev[i].weight = 64;
  797. dev_hold(&adapter->polling_netdev[i]);
  798. set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
  799. }
  800. #endif
  801. #ifdef CONFIG_E1000_MQ
  802. e1000_setup_queue_mapping(adapter);
  803. #endif
  804. atomic_set(&adapter->irq_sem, 1);
  805. spin_lock_init(&adapter->stats_lock);
  806. return 0;
  807. }
  808. /**
  809. * e1000_alloc_queues - Allocate memory for all rings
  810. * @adapter: board private structure to initialize
  811. *
  812. * We allocate one ring per queue at run-time since we don't know the
  813. * number of queues at compile-time. The polling_netdev array is
  814. * intended for Multiqueue, but should work fine with a single queue.
  815. **/
  816. static int __devinit
  817. e1000_alloc_queues(struct e1000_adapter *adapter)
  818. {
  819. int size;
  820. size = sizeof(struct e1000_tx_ring) * adapter->num_queues;
  821. adapter->tx_ring = kmalloc(size, GFP_KERNEL);
  822. if (!adapter->tx_ring)
  823. return -ENOMEM;
  824. memset(adapter->tx_ring, 0, size);
  825. size = sizeof(struct e1000_rx_ring) * adapter->num_queues;
  826. adapter->rx_ring = kmalloc(size, GFP_KERNEL);
  827. if (!adapter->rx_ring) {
  828. kfree(adapter->tx_ring);
  829. return -ENOMEM;
  830. }
  831. memset(adapter->rx_ring, 0, size);
  832. #ifdef CONFIG_E1000_NAPI
  833. size = sizeof(struct net_device) * adapter->num_queues;
  834. adapter->polling_netdev = kmalloc(size, GFP_KERNEL);
  835. if (!adapter->polling_netdev) {
  836. kfree(adapter->tx_ring);
  837. kfree(adapter->rx_ring);
  838. return -ENOMEM;
  839. }
  840. memset(adapter->polling_netdev, 0, size);
  841. #endif
  842. return E1000_SUCCESS;
  843. }
  844. #ifdef CONFIG_E1000_MQ
  845. static void __devinit
  846. e1000_setup_queue_mapping(struct e1000_adapter *adapter)
  847. {
  848. int i, cpu;
  849. adapter->rx_sched_call_data.func = e1000_rx_schedule;
  850. adapter->rx_sched_call_data.info = adapter->netdev;
  851. cpus_clear(adapter->rx_sched_call_data.cpumask);
  852. adapter->cpu_netdev = alloc_percpu(struct net_device *);
  853. adapter->cpu_tx_ring = alloc_percpu(struct e1000_tx_ring *);
  854. lock_cpu_hotplug();
  855. i = 0;
  856. for_each_online_cpu(cpu) {
  857. *per_cpu_ptr(adapter->cpu_tx_ring, cpu) = &adapter->tx_ring[i % adapter->num_queues];
  858. /* This is incomplete because we'd like to assign separate
  859. * physical cpus to these netdev polling structures and
  860. * avoid saturating a subset of cpus.
  861. */
  862. if (i < adapter->num_queues) {
  863. *per_cpu_ptr(adapter->cpu_netdev, cpu) = &adapter->polling_netdev[i];
  864. adapter->cpu_for_queue[i] = cpu;
  865. } else
  866. *per_cpu_ptr(adapter->cpu_netdev, cpu) = NULL;
  867. i++;
  868. }
  869. unlock_cpu_hotplug();
  870. }
  871. #endif
  872. /**
  873. * e1000_open - Called when a network interface is made active
  874. * @netdev: network interface device structure
  875. *
  876. * Returns 0 on success, negative value on failure
  877. *
  878. * The open entry point is called when a network interface is made
  879. * active by the system (IFF_UP). At this point all resources needed
  880. * for transmit and receive operations are allocated, the interrupt
  881. * handler is registered with the OS, the watchdog timer is started,
  882. * and the stack is notified that the interface is ready.
  883. **/
  884. static int
  885. e1000_open(struct net_device *netdev)
  886. {
  887. struct e1000_adapter *adapter = netdev_priv(netdev);
  888. int err;
  889. /* allocate transmit descriptors */
  890. if ((err = e1000_setup_all_tx_resources(adapter)))
  891. goto err_setup_tx;
  892. /* allocate receive descriptors */
  893. if ((err = e1000_setup_all_rx_resources(adapter)))
  894. goto err_setup_rx;
  895. if((err = e1000_up(adapter)))
  896. goto err_up;
  897. adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
  898. if((adapter->hw.mng_cookie.status &
  899. E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
  900. e1000_update_mng_vlan(adapter);
  901. }
  902. return E1000_SUCCESS;
  903. err_up:
  904. e1000_free_all_rx_resources(adapter);
  905. err_setup_rx:
  906. e1000_free_all_tx_resources(adapter);
  907. err_setup_tx:
  908. e1000_reset(adapter);
  909. return err;
  910. }
  911. /**
  912. * e1000_close - Disables a network interface
  913. * @netdev: network interface device structure
  914. *
  915. * Returns 0, this is not allowed to fail
  916. *
  917. * The close entry point is called when an interface is de-activated
  918. * by the OS. The hardware is still under the drivers control, but
  919. * needs to be disabled. A global MAC reset is issued to stop the
  920. * hardware, and all transmit and receive resources are freed.
  921. **/
  922. static int
  923. e1000_close(struct net_device *netdev)
  924. {
  925. struct e1000_adapter *adapter = netdev_priv(netdev);
  926. e1000_down(adapter);
  927. e1000_free_all_tx_resources(adapter);
  928. e1000_free_all_rx_resources(adapter);
  929. if((adapter->hw.mng_cookie.status &
  930. E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
  931. e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
  932. }
  933. return 0;
  934. }
  935. /**
  936. * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
  937. * @adapter: address of board private structure
  938. * @start: address of beginning of memory
  939. * @len: length of memory
  940. **/
  941. static inline boolean_t
  942. e1000_check_64k_bound(struct e1000_adapter *adapter,
  943. void *start, unsigned long len)
  944. {
  945. unsigned long begin = (unsigned long) start;
  946. unsigned long end = begin + len;
  947. /* First rev 82545 and 82546 need to not allow any memory
  948. * write location to cross 64k boundary due to errata 23 */
  949. if (adapter->hw.mac_type == e1000_82545 ||
  950. adapter->hw.mac_type == e1000_82546) {
  951. return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
  952. }
  953. return TRUE;
  954. }
  955. /**
  956. * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
  957. * @adapter: board private structure
  958. * @txdr: tx descriptor ring (for a specific queue) to setup
  959. *
  960. * Return 0 on success, negative on failure
  961. **/
  962. int
  963. e1000_setup_tx_resources(struct e1000_adapter *adapter,
  964. struct e1000_tx_ring *txdr)
  965. {
  966. struct pci_dev *pdev = adapter->pdev;
  967. int size;
  968. size = sizeof(struct e1000_buffer) * txdr->count;
  969. txdr->buffer_info = vmalloc(size);
  970. if(!txdr->buffer_info) {
  971. DPRINTK(PROBE, ERR,
  972. "Unable to allocate memory for the transmit descriptor ring\n");
  973. return -ENOMEM;
  974. }
  975. memset(txdr->buffer_info, 0, size);
  976. memset(&txdr->previous_buffer_info, 0, sizeof(struct e1000_buffer));
  977. /* round up to nearest 4K */
  978. txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
  979. E1000_ROUNDUP(txdr->size, 4096);
  980. txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
  981. if(!txdr->desc) {
  982. setup_tx_desc_die:
  983. vfree(txdr->buffer_info);
  984. DPRINTK(PROBE, ERR,
  985. "Unable to allocate memory for the transmit descriptor ring\n");
  986. return -ENOMEM;
  987. }
  988. /* Fix for errata 23, can't cross 64kB boundary */
  989. if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
  990. void *olddesc = txdr->desc;
  991. dma_addr_t olddma = txdr->dma;
  992. DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
  993. "at %p\n", txdr->size, txdr->desc);
  994. /* Try again, without freeing the previous */
  995. txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
  996. if(!txdr->desc) {
  997. /* Failed allocation, critical failure */
  998. pci_free_consistent(pdev, txdr->size, olddesc, olddma);
  999. goto setup_tx_desc_die;
  1000. }
  1001. if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
  1002. /* give up */
  1003. pci_free_consistent(pdev, txdr->size, txdr->desc,
  1004. txdr->dma);
  1005. pci_free_consistent(pdev, txdr->size, olddesc, olddma);
  1006. DPRINTK(PROBE, ERR,
  1007. "Unable to allocate aligned memory "
  1008. "for the transmit descriptor ring\n");
  1009. vfree(txdr->buffer_info);
  1010. return -ENOMEM;
  1011. } else {
  1012. /* Free old allocation, new allocation was successful */
  1013. pci_free_consistent(pdev, txdr->size, olddesc, olddma);
  1014. }
  1015. }
  1016. memset(txdr->desc, 0, txdr->size);
  1017. txdr->next_to_use = 0;
  1018. txdr->next_to_clean = 0;
  1019. spin_lock_init(&txdr->tx_lock);
  1020. return 0;
  1021. }
  1022. /**
  1023. * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
  1024. * (Descriptors) for all queues
  1025. * @adapter: board private structure
  1026. *
  1027. * If this function returns with an error, then it's possible one or
  1028. * more of the rings is populated (while the rest are not). It is the
  1029. * callers duty to clean those orphaned rings.
  1030. *
  1031. * Return 0 on success, negative on failure
  1032. **/
  1033. int
  1034. e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
  1035. {
  1036. int i, err = 0;
  1037. for (i = 0; i < adapter->num_queues; i++) {
  1038. err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
  1039. if (err) {
  1040. DPRINTK(PROBE, ERR,
  1041. "Allocation for Tx Queue %u failed\n", i);
  1042. break;
  1043. }
  1044. }
  1045. return err;
  1046. }
  1047. /**
  1048. * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
  1049. * @adapter: board private structure
  1050. *
  1051. * Configure the Tx unit of the MAC after a reset.
  1052. **/
  1053. static void
  1054. e1000_configure_tx(struct e1000_adapter *adapter)
  1055. {
  1056. uint64_t tdba;
  1057. struct e1000_hw *hw = &adapter->hw;
  1058. uint32_t tdlen, tctl, tipg, tarc;
  1059. /* Setup the HW Tx Head and Tail descriptor pointers */
  1060. switch (adapter->num_queues) {
  1061. case 2:
  1062. tdba = adapter->tx_ring[1].dma;
  1063. tdlen = adapter->tx_ring[1].count *
  1064. sizeof(struct e1000_tx_desc);
  1065. E1000_WRITE_REG(hw, TDBAL1, (tdba & 0x00000000ffffffffULL));
  1066. E1000_WRITE_REG(hw, TDBAH1, (tdba >> 32));
  1067. E1000_WRITE_REG(hw, TDLEN1, tdlen);
  1068. E1000_WRITE_REG(hw, TDH1, 0);
  1069. E1000_WRITE_REG(hw, TDT1, 0);
  1070. adapter->tx_ring[1].tdh = E1000_TDH1;
  1071. adapter->tx_ring[1].tdt = E1000_TDT1;
  1072. /* Fall Through */
  1073. case 1:
  1074. default:
  1075. tdba = adapter->tx_ring[0].dma;
  1076. tdlen = adapter->tx_ring[0].count *
  1077. sizeof(struct e1000_tx_desc);
  1078. E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
  1079. E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
  1080. E1000_WRITE_REG(hw, TDLEN, tdlen);
  1081. E1000_WRITE_REG(hw, TDH, 0);
  1082. E1000_WRITE_REG(hw, TDT, 0);
  1083. adapter->tx_ring[0].tdh = E1000_TDH;
  1084. adapter->tx_ring[0].tdt = E1000_TDT;
  1085. break;
  1086. }
  1087. /* Set the default values for the Tx Inter Packet Gap timer */
  1088. switch (hw->mac_type) {
  1089. case e1000_82542_rev2_0:
  1090. case e1000_82542_rev2_1:
  1091. tipg = DEFAULT_82542_TIPG_IPGT;
  1092. tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
  1093. tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
  1094. break;
  1095. default:
  1096. if (hw->media_type == e1000_media_type_fiber ||
  1097. hw->media_type == e1000_media_type_internal_serdes)
  1098. tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
  1099. else
  1100. tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
  1101. tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
  1102. tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
  1103. }
  1104. E1000_WRITE_REG(hw, TIPG, tipg);
  1105. /* Set the Tx Interrupt Delay register */
  1106. E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
  1107. if (hw->mac_type >= e1000_82540)
  1108. E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
  1109. /* Program the Transmit Control Register */
  1110. tctl = E1000_READ_REG(hw, TCTL);
  1111. tctl &= ~E1000_TCTL_CT;
  1112. tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | E1000_TCTL_RTLC |
  1113. (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
  1114. E1000_WRITE_REG(hw, TCTL, tctl);
  1115. if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
  1116. tarc = E1000_READ_REG(hw, TARC0);
  1117. tarc |= ((1 << 25) | (1 << 21));
  1118. E1000_WRITE_REG(hw, TARC0, tarc);
  1119. tarc = E1000_READ_REG(hw, TARC1);
  1120. tarc |= (1 << 25);
  1121. if (tctl & E1000_TCTL_MULR)
  1122. tarc &= ~(1 << 28);
  1123. else
  1124. tarc |= (1 << 28);
  1125. E1000_WRITE_REG(hw, TARC1, tarc);
  1126. }
  1127. e1000_config_collision_dist(hw);
  1128. /* Setup Transmit Descriptor Settings for eop descriptor */
  1129. adapter->txd_cmd = E1000_TXD_CMD_IDE | E1000_TXD_CMD_EOP |
  1130. E1000_TXD_CMD_IFCS;
  1131. if (hw->mac_type < e1000_82543)
  1132. adapter->txd_cmd |= E1000_TXD_CMD_RPS;
  1133. else
  1134. adapter->txd_cmd |= E1000_TXD_CMD_RS;
  1135. /* Cache if we're 82544 running in PCI-X because we'll
  1136. * need this to apply a workaround later in the send path. */
  1137. if (hw->mac_type == e1000_82544 &&
  1138. hw->bus_type == e1000_bus_type_pcix)
  1139. adapter->pcix_82544 = 1;
  1140. }
  1141. /**
  1142. * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
  1143. * @adapter: board private structure
  1144. * @rxdr: rx descriptor ring (for a specific queue) to setup
  1145. *
  1146. * Returns 0 on success, negative on failure
  1147. **/
  1148. int
  1149. e1000_setup_rx_resources(struct e1000_adapter *adapter,
  1150. struct e1000_rx_ring *rxdr)
  1151. {
  1152. struct pci_dev *pdev = adapter->pdev;
  1153. int size, desc_len;
  1154. size = sizeof(struct e1000_buffer) * rxdr->count;
  1155. rxdr->buffer_info = vmalloc(size);
  1156. if (!rxdr->buffer_info) {
  1157. DPRINTK(PROBE, ERR,
  1158. "Unable to allocate memory for the receive descriptor ring\n");
  1159. return -ENOMEM;
  1160. }
  1161. memset(rxdr->buffer_info, 0, size);
  1162. size = sizeof(struct e1000_ps_page) * rxdr->count;
  1163. rxdr->ps_page = kmalloc(size, GFP_KERNEL);
  1164. if(!rxdr->ps_page) {
  1165. vfree(rxdr->buffer_info);
  1166. DPRINTK(PROBE, ERR,
  1167. "Unable to allocate memory for the receive descriptor ring\n");
  1168. return -ENOMEM;
  1169. }
  1170. memset(rxdr->ps_page, 0, size);
  1171. size = sizeof(struct e1000_ps_page_dma) * rxdr->count;
  1172. rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL);
  1173. if(!rxdr->ps_page_dma) {
  1174. vfree(rxdr->buffer_info);
  1175. kfree(rxdr->ps_page);
  1176. DPRINTK(PROBE, ERR,
  1177. "Unable to allocate memory for the receive descriptor ring\n");
  1178. return -ENOMEM;
  1179. }
  1180. memset(rxdr->ps_page_dma, 0, size);
  1181. if(adapter->hw.mac_type <= e1000_82547_rev_2)
  1182. desc_len = sizeof(struct e1000_rx_desc);
  1183. else
  1184. desc_len = sizeof(union e1000_rx_desc_packet_split);
  1185. /* Round up to nearest 4K */
  1186. rxdr->size = rxdr->count * desc_len;
  1187. E1000_ROUNDUP(rxdr->size, 4096);
  1188. rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
  1189. if (!rxdr->desc) {
  1190. DPRINTK(PROBE, ERR,
  1191. "Unable to allocate memory for the receive descriptor ring\n");
  1192. setup_rx_desc_die:
  1193. vfree(rxdr->buffer_info);
  1194. kfree(rxdr->ps_page);
  1195. kfree(rxdr->ps_page_dma);
  1196. return -ENOMEM;
  1197. }
  1198. /* Fix for errata 23, can't cross 64kB boundary */
  1199. if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
  1200. void *olddesc = rxdr->desc;
  1201. dma_addr_t olddma = rxdr->dma;
  1202. DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
  1203. "at %p\n", rxdr->size, rxdr->desc);
  1204. /* Try again, without freeing the previous */
  1205. rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
  1206. /* Failed allocation, critical failure */
  1207. if (!rxdr->desc) {
  1208. pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
  1209. DPRINTK(PROBE, ERR,
  1210. "Unable to allocate memory "
  1211. "for the receive descriptor ring\n");
  1212. goto setup_rx_desc_die;
  1213. }
  1214. if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
  1215. /* give up */
  1216. pci_free_consistent(pdev, rxdr->size, rxdr->desc,
  1217. rxdr->dma);
  1218. pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
  1219. DPRINTK(PROBE, ERR,
  1220. "Unable to allocate aligned memory "
  1221. "for the receive descriptor ring\n");
  1222. goto setup_rx_desc_die;
  1223. } else {
  1224. /* Free old allocation, new allocation was successful */
  1225. pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
  1226. }
  1227. }
  1228. memset(rxdr->desc, 0, rxdr->size);
  1229. rxdr->next_to_clean = 0;
  1230. rxdr->next_to_use = 0;
  1231. return 0;
  1232. }
  1233. /**
  1234. * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
  1235. * (Descriptors) for all queues
  1236. * @adapter: board private structure
  1237. *
  1238. * If this function returns with an error, then it's possible one or
  1239. * more of the rings is populated (while the rest are not). It is the
  1240. * callers duty to clean those orphaned rings.
  1241. *
  1242. * Return 0 on success, negative on failure
  1243. **/
  1244. int
  1245. e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
  1246. {
  1247. int i, err = 0;
  1248. for (i = 0; i < adapter->num_queues; i++) {
  1249. err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
  1250. if (err) {
  1251. DPRINTK(PROBE, ERR,
  1252. "Allocation for Rx Queue %u failed\n", i);
  1253. break;
  1254. }
  1255. }
  1256. return err;
  1257. }
  1258. /**
  1259. * e1000_setup_rctl - configure the receive control registers
  1260. * @adapter: Board private structure
  1261. **/
  1262. #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
  1263. (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
  1264. static void
  1265. e1000_setup_rctl(struct e1000_adapter *adapter)
  1266. {
  1267. uint32_t rctl, rfctl;
  1268. uint32_t psrctl = 0;
  1269. #ifdef CONFIG_E1000_PACKET_SPLIT
  1270. uint32_t pages = 0;
  1271. #endif
  1272. rctl = E1000_READ_REG(&adapter->hw, RCTL);
  1273. rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
  1274. rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
  1275. E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
  1276. (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
  1277. if(adapter->hw.tbi_compatibility_on == 1)
  1278. rctl |= E1000_RCTL_SBP;
  1279. else
  1280. rctl &= ~E1000_RCTL_SBP;
  1281. if (adapter->netdev->mtu <= ETH_DATA_LEN)
  1282. rctl &= ~E1000_RCTL_LPE;
  1283. else
  1284. rctl |= E1000_RCTL_LPE;
  1285. /* Setup buffer sizes */
  1286. if(adapter->hw.mac_type >= e1000_82571) {
  1287. /* We can now specify buffers in 1K increments.
  1288. * BSIZE and BSEX are ignored in this case. */
  1289. rctl |= adapter->rx_buffer_len << 0x11;
  1290. } else {
  1291. rctl &= ~E1000_RCTL_SZ_4096;
  1292. rctl |= E1000_RCTL_BSEX;
  1293. switch (adapter->rx_buffer_len) {
  1294. case E1000_RXBUFFER_2048:
  1295. default:
  1296. rctl |= E1000_RCTL_SZ_2048;
  1297. rctl &= ~E1000_RCTL_BSEX;
  1298. break;
  1299. case E1000_RXBUFFER_4096:
  1300. rctl |= E1000_RCTL_SZ_4096;
  1301. break;
  1302. case E1000_RXBUFFER_8192:
  1303. rctl |= E1000_RCTL_SZ_8192;
  1304. break;
  1305. case E1000_RXBUFFER_16384:
  1306. rctl |= E1000_RCTL_SZ_16384;
  1307. break;
  1308. }
  1309. }
  1310. #ifdef CONFIG_E1000_PACKET_SPLIT
  1311. /* 82571 and greater support packet-split where the protocol
  1312. * header is placed in skb->data and the packet data is
  1313. * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
  1314. * In the case of a non-split, skb->data is linearly filled,
  1315. * followed by the page buffers. Therefore, skb->data is
  1316. * sized to hold the largest protocol header.
  1317. */
  1318. pages = PAGE_USE_COUNT(adapter->netdev->mtu);
  1319. if ((adapter->hw.mac_type > e1000_82547_rev_2) && (pages <= 3) &&
  1320. PAGE_SIZE <= 16384)
  1321. adapter->rx_ps_pages = pages;
  1322. else
  1323. adapter->rx_ps_pages = 0;
  1324. #endif
  1325. if (adapter->rx_ps_pages) {
  1326. /* Configure extra packet-split registers */
  1327. rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
  1328. rfctl |= E1000_RFCTL_EXTEN;
  1329. /* disable IPv6 packet split support */
  1330. rfctl |= E1000_RFCTL_IPV6_DIS;
  1331. E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
  1332. rctl |= E1000_RCTL_DTYP_PS | E1000_RCTL_SECRC;
  1333. psrctl |= adapter->rx_ps_bsize0 >>
  1334. E1000_PSRCTL_BSIZE0_SHIFT;
  1335. switch (adapter->rx_ps_pages) {
  1336. case 3:
  1337. psrctl |= PAGE_SIZE <<
  1338. E1000_PSRCTL_BSIZE3_SHIFT;
  1339. case 2:
  1340. psrctl |= PAGE_SIZE <<
  1341. E1000_PSRCTL_BSIZE2_SHIFT;
  1342. case 1:
  1343. psrctl |= PAGE_SIZE >>
  1344. E1000_PSRCTL_BSIZE1_SHIFT;
  1345. break;
  1346. }
  1347. E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
  1348. }
  1349. E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
  1350. }
  1351. /**
  1352. * e1000_configure_rx - Configure 8254x Receive Unit after Reset
  1353. * @adapter: board private structure
  1354. *
  1355. * Configure the Rx unit of the MAC after a reset.
  1356. **/
  1357. static void
  1358. e1000_configure_rx(struct e1000_adapter *adapter)
  1359. {
  1360. uint64_t rdba;
  1361. struct e1000_hw *hw = &adapter->hw;
  1362. uint32_t rdlen, rctl, rxcsum, ctrl_ext;
  1363. #ifdef CONFIG_E1000_MQ
  1364. uint32_t reta, mrqc;
  1365. int i;
  1366. #endif
  1367. if (adapter->rx_ps_pages) {
  1368. rdlen = adapter->rx_ring[0].count *
  1369. sizeof(union e1000_rx_desc_packet_split);
  1370. adapter->clean_rx = e1000_clean_rx_irq_ps;
  1371. adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
  1372. } else {
  1373. rdlen = adapter->rx_ring[0].count *
  1374. sizeof(struct e1000_rx_desc);
  1375. adapter->clean_rx = e1000_clean_rx_irq;
  1376. adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
  1377. }
  1378. /* disable receives while setting up the descriptors */
  1379. rctl = E1000_READ_REG(hw, RCTL);
  1380. E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
  1381. /* set the Receive Delay Timer Register */
  1382. E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
  1383. if (hw->mac_type >= e1000_82540) {
  1384. E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
  1385. if(adapter->itr > 1)
  1386. E1000_WRITE_REG(hw, ITR,
  1387. 1000000000 / (adapter->itr * 256));
  1388. }
  1389. if (hw->mac_type >= e1000_82571) {
  1390. /* Reset delay timers after every interrupt */
  1391. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1392. ctrl_ext |= E1000_CTRL_EXT_CANC;
  1393. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1394. E1000_WRITE_FLUSH(hw);
  1395. }
  1396. /* Setup the HW Rx Head and Tail Descriptor Pointers and
  1397. * the Base and Length of the Rx Descriptor Ring */
  1398. switch (adapter->num_queues) {
  1399. #ifdef CONFIG_E1000_MQ
  1400. case 2:
  1401. rdba = adapter->rx_ring[1].dma;
  1402. E1000_WRITE_REG(hw, RDBAL1, (rdba & 0x00000000ffffffffULL));
  1403. E1000_WRITE_REG(hw, RDBAH1, (rdba >> 32));
  1404. E1000_WRITE_REG(hw, RDLEN1, rdlen);
  1405. E1000_WRITE_REG(hw, RDH1, 0);
  1406. E1000_WRITE_REG(hw, RDT1, 0);
  1407. adapter->rx_ring[1].rdh = E1000_RDH1;
  1408. adapter->rx_ring[1].rdt = E1000_RDT1;
  1409. /* Fall Through */
  1410. #endif
  1411. case 1:
  1412. default:
  1413. rdba = adapter->rx_ring[0].dma;
  1414. E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
  1415. E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
  1416. E1000_WRITE_REG(hw, RDLEN, rdlen);
  1417. E1000_WRITE_REG(hw, RDH, 0);
  1418. E1000_WRITE_REG(hw, RDT, 0);
  1419. adapter->rx_ring[0].rdh = E1000_RDH;
  1420. adapter->rx_ring[0].rdt = E1000_RDT;
  1421. break;
  1422. }
  1423. #ifdef CONFIG_E1000_MQ
  1424. if (adapter->num_queues > 1) {
  1425. uint32_t random[10];
  1426. get_random_bytes(&random[0], 40);
  1427. if (hw->mac_type <= e1000_82572) {
  1428. E1000_WRITE_REG(hw, RSSIR, 0);
  1429. E1000_WRITE_REG(hw, RSSIM, 0);
  1430. }
  1431. switch (adapter->num_queues) {
  1432. case 2:
  1433. default:
  1434. reta = 0x00800080;
  1435. mrqc = E1000_MRQC_ENABLE_RSS_2Q;
  1436. break;
  1437. }
  1438. /* Fill out redirection table */
  1439. for (i = 0; i < 32; i++)
  1440. E1000_WRITE_REG_ARRAY(hw, RETA, i, reta);
  1441. /* Fill out hash function seeds */
  1442. for (i = 0; i < 10; i++)
  1443. E1000_WRITE_REG_ARRAY(hw, RSSRK, i, random[i]);
  1444. mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
  1445. E1000_MRQC_RSS_FIELD_IPV4_TCP);
  1446. E1000_WRITE_REG(hw, MRQC, mrqc);
  1447. }
  1448. /* Multiqueue and packet checksumming are mutually exclusive. */
  1449. if (hw->mac_type >= e1000_82571) {
  1450. rxcsum = E1000_READ_REG(hw, RXCSUM);
  1451. rxcsum |= E1000_RXCSUM_PCSD;
  1452. E1000_WRITE_REG(hw, RXCSUM, rxcsum);
  1453. }
  1454. #else
  1455. /* Enable 82543 Receive Checksum Offload for TCP and UDP */
  1456. if (hw->mac_type >= e1000_82543) {
  1457. rxcsum = E1000_READ_REG(hw, RXCSUM);
  1458. if(adapter->rx_csum == TRUE) {
  1459. rxcsum |= E1000_RXCSUM_TUOFL;
  1460. /* Enable 82571 IPv4 payload checksum for UDP fragments
  1461. * Must be used in conjunction with packet-split. */
  1462. if ((hw->mac_type >= e1000_82571) &&
  1463. (adapter->rx_ps_pages)) {
  1464. rxcsum |= E1000_RXCSUM_IPPCSE;
  1465. }
  1466. } else {
  1467. rxcsum &= ~E1000_RXCSUM_TUOFL;
  1468. /* don't need to clear IPPCSE as it defaults to 0 */
  1469. }
  1470. E1000_WRITE_REG(hw, RXCSUM, rxcsum);
  1471. }
  1472. #endif /* CONFIG_E1000_MQ */
  1473. if (hw->mac_type == e1000_82573)
  1474. E1000_WRITE_REG(hw, ERT, 0x0100);
  1475. /* Enable Receives */
  1476. E1000_WRITE_REG(hw, RCTL, rctl);
  1477. }
  1478. /**
  1479. * e1000_free_tx_resources - Free Tx Resources per Queue
  1480. * @adapter: board private structure
  1481. * @tx_ring: Tx descriptor ring for a specific queue
  1482. *
  1483. * Free all transmit software resources
  1484. **/
  1485. void
  1486. e1000_free_tx_resources(struct e1000_adapter *adapter,
  1487. struct e1000_tx_ring *tx_ring)
  1488. {
  1489. struct pci_dev *pdev = adapter->pdev;
  1490. e1000_clean_tx_ring(adapter, tx_ring);
  1491. vfree(tx_ring->buffer_info);
  1492. tx_ring->buffer_info = NULL;
  1493. pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
  1494. tx_ring->desc = NULL;
  1495. }
  1496. /**
  1497. * e1000_free_all_tx_resources - Free Tx Resources for All Queues
  1498. * @adapter: board private structure
  1499. *
  1500. * Free all transmit software resources
  1501. **/
  1502. void
  1503. e1000_free_all_tx_resources(struct e1000_adapter *adapter)
  1504. {
  1505. int i;
  1506. for (i = 0; i < adapter->num_queues; i++)
  1507. e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
  1508. }
  1509. static inline void
  1510. e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
  1511. struct e1000_buffer *buffer_info)
  1512. {
  1513. if(buffer_info->dma) {
  1514. pci_unmap_page(adapter->pdev,
  1515. buffer_info->dma,
  1516. buffer_info->length,
  1517. PCI_DMA_TODEVICE);
  1518. buffer_info->dma = 0;
  1519. }
  1520. if(buffer_info->skb) {
  1521. dev_kfree_skb_any(buffer_info->skb);
  1522. buffer_info->skb = NULL;
  1523. }
  1524. }
  1525. /**
  1526. * e1000_clean_tx_ring - Free Tx Buffers
  1527. * @adapter: board private structure
  1528. * @tx_ring: ring to be cleaned
  1529. **/
  1530. static void
  1531. e1000_clean_tx_ring(struct e1000_adapter *adapter,
  1532. struct e1000_tx_ring *tx_ring)
  1533. {
  1534. struct e1000_buffer *buffer_info;
  1535. unsigned long size;
  1536. unsigned int i;
  1537. /* Free all the Tx ring sk_buffs */
  1538. if (likely(tx_ring->previous_buffer_info.skb != NULL)) {
  1539. e1000_unmap_and_free_tx_resource(adapter,
  1540. &tx_ring->previous_buffer_info);
  1541. }
  1542. for(i = 0; i < tx_ring->count; i++) {
  1543. buffer_info = &tx_ring->buffer_info[i];
  1544. e1000_unmap_and_free_tx_resource(adapter, buffer_info);
  1545. }
  1546. size = sizeof(struct e1000_buffer) * tx_ring->count;
  1547. memset(tx_ring->buffer_info, 0, size);
  1548. /* Zero out the descriptor ring */
  1549. memset(tx_ring->desc, 0, tx_ring->size);
  1550. tx_ring->next_to_use = 0;
  1551. tx_ring->next_to_clean = 0;
  1552. writel(0, adapter->hw.hw_addr + tx_ring->tdh);
  1553. writel(0, adapter->hw.hw_addr + tx_ring->tdt);
  1554. }
  1555. /**
  1556. * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
  1557. * @adapter: board private structure
  1558. **/
  1559. static void
  1560. e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
  1561. {
  1562. int i;
  1563. for (i = 0; i < adapter->num_queues; i++)
  1564. e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
  1565. }
  1566. /**
  1567. * e1000_free_rx_resources - Free Rx Resources
  1568. * @adapter: board private structure
  1569. * @rx_ring: ring to clean the resources from
  1570. *
  1571. * Free all receive software resources
  1572. **/
  1573. void
  1574. e1000_free_rx_resources(struct e1000_adapter *adapter,
  1575. struct e1000_rx_ring *rx_ring)
  1576. {
  1577. struct pci_dev *pdev = adapter->pdev;
  1578. e1000_clean_rx_ring(adapter, rx_ring);
  1579. vfree(rx_ring->buffer_info);
  1580. rx_ring->buffer_info = NULL;
  1581. kfree(rx_ring->ps_page);
  1582. rx_ring->ps_page = NULL;
  1583. kfree(rx_ring->ps_page_dma);
  1584. rx_ring->ps_page_dma = NULL;
  1585. pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
  1586. rx_ring->desc = NULL;
  1587. }
  1588. /**
  1589. * e1000_free_all_rx_resources - Free Rx Resources for All Queues
  1590. * @adapter: board private structure
  1591. *
  1592. * Free all receive software resources
  1593. **/
  1594. void
  1595. e1000_free_all_rx_resources(struct e1000_adapter *adapter)
  1596. {
  1597. int i;
  1598. for (i = 0; i < adapter->num_queues; i++)
  1599. e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
  1600. }
  1601. /**
  1602. * e1000_clean_rx_ring - Free Rx Buffers per Queue
  1603. * @adapter: board private structure
  1604. * @rx_ring: ring to free buffers from
  1605. **/
  1606. static void
  1607. e1000_clean_rx_ring(struct e1000_adapter *adapter,
  1608. struct e1000_rx_ring *rx_ring)
  1609. {
  1610. struct e1000_buffer *buffer_info;
  1611. struct e1000_ps_page *ps_page;
  1612. struct e1000_ps_page_dma *ps_page_dma;
  1613. struct pci_dev *pdev = adapter->pdev;
  1614. unsigned long size;
  1615. unsigned int i, j;
  1616. /* Free all the Rx ring sk_buffs */
  1617. for(i = 0; i < rx_ring->count; i++) {
  1618. buffer_info = &rx_ring->buffer_info[i];
  1619. if(buffer_info->skb) {
  1620. ps_page = &rx_ring->ps_page[i];
  1621. ps_page_dma = &rx_ring->ps_page_dma[i];
  1622. pci_unmap_single(pdev,
  1623. buffer_info->dma,
  1624. buffer_info->length,
  1625. PCI_DMA_FROMDEVICE);
  1626. dev_kfree_skb(buffer_info->skb);
  1627. buffer_info->skb = NULL;
  1628. for(j = 0; j < adapter->rx_ps_pages; j++) {
  1629. if(!ps_page->ps_page[j]) break;
  1630. pci_unmap_single(pdev,
  1631. ps_page_dma->ps_page_dma[j],
  1632. PAGE_SIZE, PCI_DMA_FROMDEVICE);
  1633. ps_page_dma->ps_page_dma[j] = 0;
  1634. put_page(ps_page->ps_page[j]);
  1635. ps_page->ps_page[j] = NULL;
  1636. }
  1637. }
  1638. }
  1639. size = sizeof(struct e1000_buffer) * rx_ring->count;
  1640. memset(rx_ring->buffer_info, 0, size);
  1641. size = sizeof(struct e1000_ps_page) * rx_ring->count;
  1642. memset(rx_ring->ps_page, 0, size);
  1643. size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
  1644. memset(rx_ring->ps_page_dma, 0, size);
  1645. /* Zero out the descriptor ring */
  1646. memset(rx_ring->desc, 0, rx_ring->size);
  1647. rx_ring->next_to_clean = 0;
  1648. rx_ring->next_to_use = 0;
  1649. writel(0, adapter->hw.hw_addr + rx_ring->rdh);
  1650. writel(0, adapter->hw.hw_addr + rx_ring->rdt);
  1651. }
  1652. /**
  1653. * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
  1654. * @adapter: board private structure
  1655. **/
  1656. static void
  1657. e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
  1658. {
  1659. int i;
  1660. for (i = 0; i < adapter->num_queues; i++)
  1661. e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
  1662. }
  1663. /* The 82542 2.0 (revision 2) needs to have the receive unit in reset
  1664. * and memory write and invalidate disabled for certain operations
  1665. */
  1666. static void
  1667. e1000_enter_82542_rst(struct e1000_adapter *adapter)
  1668. {
  1669. struct net_device *netdev = adapter->netdev;
  1670. uint32_t rctl;
  1671. e1000_pci_clear_mwi(&adapter->hw);
  1672. rctl = E1000_READ_REG(&adapter->hw, RCTL);
  1673. rctl |= E1000_RCTL_RST;
  1674. E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
  1675. E1000_WRITE_FLUSH(&adapter->hw);
  1676. mdelay(5);
  1677. if(netif_running(netdev))
  1678. e1000_clean_all_rx_rings(adapter);
  1679. }
  1680. static void
  1681. e1000_leave_82542_rst(struct e1000_adapter *adapter)
  1682. {
  1683. struct net_device *netdev = adapter->netdev;
  1684. uint32_t rctl;
  1685. rctl = E1000_READ_REG(&adapter->hw, RCTL);
  1686. rctl &= ~E1000_RCTL_RST;
  1687. E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
  1688. E1000_WRITE_FLUSH(&adapter->hw);
  1689. mdelay(5);
  1690. if(adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
  1691. e1000_pci_set_mwi(&adapter->hw);
  1692. if(netif_running(netdev)) {
  1693. e1000_configure_rx(adapter);
  1694. e1000_alloc_rx_buffers(adapter, &adapter->rx_ring[0]);
  1695. }
  1696. }
  1697. /**
  1698. * e1000_set_mac - Change the Ethernet Address of the NIC
  1699. * @netdev: network interface device structure
  1700. * @p: pointer to an address structure
  1701. *
  1702. * Returns 0 on success, negative on failure
  1703. **/
  1704. static int
  1705. e1000_set_mac(struct net_device *netdev, void *p)
  1706. {
  1707. struct e1000_adapter *adapter = netdev_priv(netdev);
  1708. struct sockaddr *addr = p;
  1709. if(!is_valid_ether_addr(addr->sa_data))
  1710. return -EADDRNOTAVAIL;
  1711. /* 82542 2.0 needs to be in reset to write receive address registers */
  1712. if(adapter->hw.mac_type == e1000_82542_rev2_0)
  1713. e1000_enter_82542_rst(adapter);
  1714. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  1715. memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
  1716. e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
  1717. /* With 82571 controllers, LAA may be overwritten (with the default)
  1718. * due to controller reset from the other port. */
  1719. if (adapter->hw.mac_type == e1000_82571) {
  1720. /* activate the work around */
  1721. adapter->hw.laa_is_present = 1;
  1722. /* Hold a copy of the LAA in RAR[14] This is done so that
  1723. * between the time RAR[0] gets clobbered and the time it
  1724. * gets fixed (in e1000_watchdog), the actual LAA is in one
  1725. * of the RARs and no incoming packets directed to this port
  1726. * are dropped. Eventaully the LAA will be in RAR[0] and
  1727. * RAR[14] */
  1728. e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
  1729. E1000_RAR_ENTRIES - 1);
  1730. }
  1731. if(adapter->hw.mac_type == e1000_82542_rev2_0)
  1732. e1000_leave_82542_rst(adapter);
  1733. return 0;
  1734. }
  1735. /**
  1736. * e1000_set_multi - Multicast and Promiscuous mode set
  1737. * @netdev: network interface device structure
  1738. *
  1739. * The set_multi entry point is called whenever the multicast address
  1740. * list or the network interface flags are updated. This routine is
  1741. * responsible for configuring the hardware for proper multicast,
  1742. * promiscuous mode, and all-multi behavior.
  1743. **/
  1744. static void
  1745. e1000_set_multi(struct net_device *netdev)
  1746. {
  1747. struct e1000_adapter *adapter = netdev_priv(netdev);
  1748. struct e1000_hw *hw = &adapter->hw;
  1749. struct dev_mc_list *mc_ptr;
  1750. uint32_t rctl;
  1751. uint32_t hash_value;
  1752. int i, rar_entries = E1000_RAR_ENTRIES;
  1753. /* reserve RAR[14] for LAA over-write work-around */
  1754. if (adapter->hw.mac_type == e1000_82571)
  1755. rar_entries--;
  1756. /* Check for Promiscuous and All Multicast modes */
  1757. rctl = E1000_READ_REG(hw, RCTL);
  1758. if(netdev->flags & IFF_PROMISC) {
  1759. rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
  1760. } else if(netdev->flags & IFF_ALLMULTI) {
  1761. rctl |= E1000_RCTL_MPE;
  1762. rctl &= ~E1000_RCTL_UPE;
  1763. } else {
  1764. rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
  1765. }
  1766. E1000_WRITE_REG(hw, RCTL, rctl);
  1767. /* 82542 2.0 needs to be in reset to write receive address registers */
  1768. if(hw->mac_type == e1000_82542_rev2_0)
  1769. e1000_enter_82542_rst(adapter);
  1770. /* load the first 14 multicast address into the exact filters 1-14
  1771. * RAR 0 is used for the station MAC adddress
  1772. * if there are not 14 addresses, go ahead and clear the filters
  1773. * -- with 82571 controllers only 0-13 entries are filled here
  1774. */
  1775. mc_ptr = netdev->mc_list;
  1776. for(i = 1; i < rar_entries; i++) {
  1777. if (mc_ptr) {
  1778. e1000_rar_set(hw, mc_ptr->dmi_addr, i);
  1779. mc_ptr = mc_ptr->next;
  1780. } else {
  1781. E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
  1782. E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
  1783. }
  1784. }
  1785. /* clear the old settings from the multicast hash table */
  1786. for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++)
  1787. E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
  1788. /* load any remaining addresses into the hash table */
  1789. for(; mc_ptr; mc_ptr = mc_ptr->next) {
  1790. hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
  1791. e1000_mta_set(hw, hash_value);
  1792. }
  1793. if(hw->mac_type == e1000_82542_rev2_0)
  1794. e1000_leave_82542_rst(adapter);
  1795. }
  1796. /* Need to wait a few seconds after link up to get diagnostic information from
  1797. * the phy */
  1798. static void
  1799. e1000_update_phy_info(unsigned long data)
  1800. {
  1801. struct e1000_adapter *adapter = (struct e1000_adapter *) data;
  1802. e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
  1803. }
  1804. /**
  1805. * e1000_82547_tx_fifo_stall - Timer Call-back
  1806. * @data: pointer to adapter cast into an unsigned long
  1807. **/
  1808. static void
  1809. e1000_82547_tx_fifo_stall(unsigned long data)
  1810. {
  1811. struct e1000_adapter *adapter = (struct e1000_adapter *) data;
  1812. struct net_device *netdev = adapter->netdev;
  1813. uint32_t tctl;
  1814. if(atomic_read(&adapter->tx_fifo_stall)) {
  1815. if((E1000_READ_REG(&adapter->hw, TDT) ==
  1816. E1000_READ_REG(&adapter->hw, TDH)) &&
  1817. (E1000_READ_REG(&adapter->hw, TDFT) ==
  1818. E1000_READ_REG(&adapter->hw, TDFH)) &&
  1819. (E1000_READ_REG(&adapter->hw, TDFTS) ==
  1820. E1000_READ_REG(&adapter->hw, TDFHS))) {
  1821. tctl = E1000_READ_REG(&adapter->hw, TCTL);
  1822. E1000_WRITE_REG(&adapter->hw, TCTL,
  1823. tctl & ~E1000_TCTL_EN);
  1824. E1000_WRITE_REG(&adapter->hw, TDFT,
  1825. adapter->tx_head_addr);
  1826. E1000_WRITE_REG(&adapter->hw, TDFH,
  1827. adapter->tx_head_addr);
  1828. E1000_WRITE_REG(&adapter->hw, TDFTS,
  1829. adapter->tx_head_addr);
  1830. E1000_WRITE_REG(&adapter->hw, TDFHS,
  1831. adapter->tx_head_addr);
  1832. E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
  1833. E1000_WRITE_FLUSH(&adapter->hw);
  1834. adapter->tx_fifo_head = 0;
  1835. atomic_set(&adapter->tx_fifo_stall, 0);
  1836. netif_wake_queue(netdev);
  1837. } else {
  1838. mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
  1839. }
  1840. }
  1841. }
  1842. /**
  1843. * e1000_watchdog - Timer Call-back
  1844. * @data: pointer to adapter cast into an unsigned long
  1845. **/
  1846. static void
  1847. e1000_watchdog(unsigned long data)
  1848. {
  1849. struct e1000_adapter *adapter = (struct e1000_adapter *) data;
  1850. /* Do the rest outside of interrupt context */
  1851. schedule_work(&adapter->watchdog_task);
  1852. }
  1853. static void
  1854. e1000_watchdog_task(struct e1000_adapter *adapter)
  1855. {
  1856. struct net_device *netdev = adapter->netdev;
  1857. struct e1000_tx_ring *txdr = &adapter->tx_ring[0];
  1858. uint32_t link;
  1859. e1000_check_for_link(&adapter->hw);
  1860. if (adapter->hw.mac_type == e1000_82573) {
  1861. e1000_enable_tx_pkt_filtering(&adapter->hw);
  1862. if(adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
  1863. e1000_update_mng_vlan(adapter);
  1864. }
  1865. if((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
  1866. !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
  1867. link = !adapter->hw.serdes_link_down;
  1868. else
  1869. link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
  1870. if(link) {
  1871. if(!netif_carrier_ok(netdev)) {
  1872. e1000_get_speed_and_duplex(&adapter->hw,
  1873. &adapter->link_speed,
  1874. &adapter->link_duplex);
  1875. DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s\n",
  1876. adapter->link_speed,
  1877. adapter->link_duplex == FULL_DUPLEX ?
  1878. "Full Duplex" : "Half Duplex");
  1879. netif_carrier_on(netdev);
  1880. netif_wake_queue(netdev);
  1881. mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
  1882. adapter->smartspeed = 0;
  1883. }
  1884. } else {
  1885. if(netif_carrier_ok(netdev)) {
  1886. adapter->link_speed = 0;
  1887. adapter->link_duplex = 0;
  1888. DPRINTK(LINK, INFO, "NIC Link is Down\n");
  1889. netif_carrier_off(netdev);
  1890. netif_stop_queue(netdev);
  1891. mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
  1892. }
  1893. e1000_smartspeed(adapter);
  1894. }
  1895. e1000_update_stats(adapter);
  1896. adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
  1897. adapter->tpt_old = adapter->stats.tpt;
  1898. adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
  1899. adapter->colc_old = adapter->stats.colc;
  1900. adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
  1901. adapter->gorcl_old = adapter->stats.gorcl;
  1902. adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
  1903. adapter->gotcl_old = adapter->stats.gotcl;
  1904. e1000_update_adaptive(&adapter->hw);
  1905. if (adapter->num_queues == 1 && !netif_carrier_ok(netdev)) {
  1906. if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
  1907. /* We've lost link, so the controller stops DMA,
  1908. * but we've got queued Tx work that's never going
  1909. * to get done, so reset controller to flush Tx.
  1910. * (Do the reset outside of interrupt context). */
  1911. schedule_work(&adapter->tx_timeout_task);
  1912. }
  1913. }
  1914. /* Dynamic mode for Interrupt Throttle Rate (ITR) */
  1915. if(adapter->hw.mac_type >= e1000_82540 && adapter->itr == 1) {
  1916. /* Symmetric Tx/Rx gets a reduced ITR=2000; Total
  1917. * asymmetrical Tx or Rx gets ITR=8000; everyone
  1918. * else is between 2000-8000. */
  1919. uint32_t goc = (adapter->gotcl + adapter->gorcl) / 10000;
  1920. uint32_t dif = (adapter->gotcl > adapter->gorcl ?
  1921. adapter->gotcl - adapter->gorcl :
  1922. adapter->gorcl - adapter->gotcl) / 10000;
  1923. uint32_t itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
  1924. E1000_WRITE_REG(&adapter->hw, ITR, 1000000000 / (itr * 256));
  1925. }
  1926. /* Cause software interrupt to ensure rx ring is cleaned */
  1927. E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
  1928. /* Force detection of hung controller every watchdog period */
  1929. adapter->detect_tx_hung = TRUE;
  1930. /* With 82571 controllers, LAA may be overwritten due to controller
  1931. * reset from the other port. Set the appropriate LAA in RAR[0] */
  1932. if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
  1933. e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
  1934. /* Reset the timer */
  1935. mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
  1936. }
  1937. #define E1000_TX_FLAGS_CSUM 0x00000001
  1938. #define E1000_TX_FLAGS_VLAN 0x00000002
  1939. #define E1000_TX_FLAGS_TSO 0x00000004
  1940. #define E1000_TX_FLAGS_IPV4 0x00000008
  1941. #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
  1942. #define E1000_TX_FLAGS_VLAN_SHIFT 16
  1943. static inline int
  1944. e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
  1945. struct sk_buff *skb)
  1946. {
  1947. #ifdef NETIF_F_TSO
  1948. struct e1000_context_desc *context_desc;
  1949. unsigned int i;
  1950. uint32_t cmd_length = 0;
  1951. uint16_t ipcse = 0, tucse, mss;
  1952. uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
  1953. int err;
  1954. if(skb_shinfo(skb)->tso_size) {
  1955. if (skb_header_cloned(skb)) {
  1956. err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
  1957. if (err)
  1958. return err;
  1959. }
  1960. hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
  1961. mss = skb_shinfo(skb)->tso_size;
  1962. if(skb->protocol == ntohs(ETH_P_IP)) {
  1963. skb->nh.iph->tot_len = 0;
  1964. skb->nh.iph->check = 0;
  1965. skb->h.th->check =
  1966. ~csum_tcpudp_magic(skb->nh.iph->saddr,
  1967. skb->nh.iph->daddr,
  1968. 0,
  1969. IPPROTO_TCP,
  1970. 0);
  1971. cmd_length = E1000_TXD_CMD_IP;
  1972. ipcse = skb->h.raw - skb->data - 1;
  1973. #ifdef NETIF_F_TSO_IPV6
  1974. } else if(skb->protocol == ntohs(ETH_P_IPV6)) {
  1975. skb->nh.ipv6h->payload_len = 0;
  1976. skb->h.th->check =
  1977. ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
  1978. &skb->nh.ipv6h->daddr,
  1979. 0,
  1980. IPPROTO_TCP,
  1981. 0);
  1982. ipcse = 0;
  1983. #endif
  1984. }
  1985. ipcss = skb->nh.raw - skb->data;
  1986. ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
  1987. tucss = skb->h.raw - skb->data;
  1988. tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
  1989. tucse = 0;
  1990. cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
  1991. E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
  1992. i = tx_ring->next_to_use;
  1993. context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
  1994. context_desc->lower_setup.ip_fields.ipcss = ipcss;
  1995. context_desc->lower_setup.ip_fields.ipcso = ipcso;
  1996. context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
  1997. context_desc->upper_setup.tcp_fields.tucss = tucss;
  1998. context_desc->upper_setup.tcp_fields.tucso = tucso;
  1999. context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
  2000. context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
  2001. context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
  2002. context_desc->cmd_and_length = cpu_to_le32(cmd_length);
  2003. if (++i == tx_ring->count) i = 0;
  2004. tx_ring->next_to_use = i;
  2005. return 1;
  2006. }
  2007. #endif
  2008. return 0;
  2009. }
  2010. static inline boolean_t
  2011. e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
  2012. struct sk_buff *skb)
  2013. {
  2014. struct e1000_context_desc *context_desc;
  2015. unsigned int i;
  2016. uint8_t css;
  2017. if(likely(skb->ip_summed == CHECKSUM_HW)) {
  2018. css = skb->h.raw - skb->data;
  2019. i = tx_ring->next_to_use;
  2020. context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
  2021. context_desc->upper_setup.tcp_fields.tucss = css;
  2022. context_desc->upper_setup.tcp_fields.tucso = css + skb->csum;
  2023. context_desc->upper_setup.tcp_fields.tucse = 0;
  2024. context_desc->tcp_seg_setup.data = 0;
  2025. context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
  2026. if (unlikely(++i == tx_ring->count)) i = 0;
  2027. tx_ring->next_to_use = i;
  2028. return TRUE;
  2029. }
  2030. return FALSE;
  2031. }
  2032. #define E1000_MAX_TXD_PWR 12
  2033. #define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
  2034. static inline int
  2035. e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
  2036. struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
  2037. unsigned int nr_frags, unsigned int mss)
  2038. {
  2039. struct e1000_buffer *buffer_info;
  2040. unsigned int len = skb->len;
  2041. unsigned int offset = 0, size, count = 0, i;
  2042. unsigned int f;
  2043. len -= skb->data_len;
  2044. i = tx_ring->next_to_use;
  2045. while(len) {
  2046. buffer_info = &tx_ring->buffer_info[i];
  2047. size = min(len, max_per_txd);
  2048. #ifdef NETIF_F_TSO
  2049. /* Workaround for premature desc write-backs
  2050. * in TSO mode. Append 4-byte sentinel desc */
  2051. if(unlikely(mss && !nr_frags && size == len && size > 8))
  2052. size -= 4;
  2053. #endif
  2054. /* work-around for errata 10 and it applies
  2055. * to all controllers in PCI-X mode
  2056. * The fix is to make sure that the first descriptor of a
  2057. * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
  2058. */
  2059. if(unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
  2060. (size > 2015) && count == 0))
  2061. size = 2015;
  2062. /* Workaround for potential 82544 hang in PCI-X. Avoid
  2063. * terminating buffers within evenly-aligned dwords. */
  2064. if(unlikely(adapter->pcix_82544 &&
  2065. !((unsigned long)(skb->data + offset + size - 1) & 4) &&
  2066. size > 4))
  2067. size -= 4;
  2068. buffer_info->length = size;
  2069. buffer_info->dma =
  2070. pci_map_single(adapter->pdev,
  2071. skb->data + offset,
  2072. size,
  2073. PCI_DMA_TODEVICE);
  2074. buffer_info->time_stamp = jiffies;
  2075. len -= size;
  2076. offset += size;
  2077. count++;
  2078. if(unlikely(++i == tx_ring->count)) i = 0;
  2079. }
  2080. for(f = 0; f < nr_frags; f++) {
  2081. struct skb_frag_struct *frag;
  2082. frag = &skb_shinfo(skb)->frags[f];
  2083. len = frag->size;
  2084. offset = frag->page_offset;
  2085. while(len) {
  2086. buffer_info = &tx_ring->buffer_info[i];
  2087. size = min(len, max_per_txd);
  2088. #ifdef NETIF_F_TSO
  2089. /* Workaround for premature desc write-backs
  2090. * in TSO mode. Append 4-byte sentinel desc */
  2091. if(unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
  2092. size -= 4;
  2093. #endif
  2094. /* Workaround for potential 82544 hang in PCI-X.
  2095. * Avoid terminating buffers within evenly-aligned
  2096. * dwords. */
  2097. if(unlikely(adapter->pcix_82544 &&
  2098. !((unsigned long)(frag->page+offset+size-1) & 4) &&
  2099. size > 4))
  2100. size -= 4;
  2101. buffer_info->length = size;
  2102. buffer_info->dma =
  2103. pci_map_page(adapter->pdev,
  2104. frag->page,
  2105. offset,
  2106. size,
  2107. PCI_DMA_TODEVICE);
  2108. buffer_info->time_stamp = jiffies;
  2109. len -= size;
  2110. offset += size;
  2111. count++;
  2112. if(unlikely(++i == tx_ring->count)) i = 0;
  2113. }
  2114. }
  2115. i = (i == 0) ? tx_ring->count - 1 : i - 1;
  2116. tx_ring->buffer_info[i].skb = skb;
  2117. tx_ring->buffer_info[first].next_to_watch = i;
  2118. return count;
  2119. }
  2120. static inline void
  2121. e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
  2122. int tx_flags, int count)
  2123. {
  2124. struct e1000_tx_desc *tx_desc = NULL;
  2125. struct e1000_buffer *buffer_info;
  2126. uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
  2127. unsigned int i;
  2128. if(likely(tx_flags & E1000_TX_FLAGS_TSO)) {
  2129. txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
  2130. E1000_TXD_CMD_TSE;
  2131. txd_upper |= E1000_TXD_POPTS_TXSM << 8;
  2132. if(likely(tx_flags & E1000_TX_FLAGS_IPV4))
  2133. txd_upper |= E1000_TXD_POPTS_IXSM << 8;
  2134. }
  2135. if(likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
  2136. txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
  2137. txd_upper |= E1000_TXD_POPTS_TXSM << 8;
  2138. }
  2139. if(unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
  2140. txd_lower |= E1000_TXD_CMD_VLE;
  2141. txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
  2142. }
  2143. i = tx_ring->next_to_use;
  2144. while(count--) {
  2145. buffer_info = &tx_ring->buffer_info[i];
  2146. tx_desc = E1000_TX_DESC(*tx_ring, i);
  2147. tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
  2148. tx_desc->lower.data =
  2149. cpu_to_le32(txd_lower | buffer_info->length);
  2150. tx_desc->upper.data = cpu_to_le32(txd_upper);
  2151. if(unlikely(++i == tx_ring->count)) i = 0;
  2152. }
  2153. tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
  2154. /* Force memory writes to complete before letting h/w
  2155. * know there are new descriptors to fetch. (Only
  2156. * applicable for weak-ordered memory model archs,
  2157. * such as IA-64). */
  2158. wmb();
  2159. tx_ring->next_to_use = i;
  2160. writel(i, adapter->hw.hw_addr + tx_ring->tdt);
  2161. }
  2162. /**
  2163. * 82547 workaround to avoid controller hang in half-duplex environment.
  2164. * The workaround is to avoid queuing a large packet that would span
  2165. * the internal Tx FIFO ring boundary by notifying the stack to resend
  2166. * the packet at a later time. This gives the Tx FIFO an opportunity to
  2167. * flush all packets. When that occurs, we reset the Tx FIFO pointers
  2168. * to the beginning of the Tx FIFO.
  2169. **/
  2170. #define E1000_FIFO_HDR 0x10
  2171. #define E1000_82547_PAD_LEN 0x3E0
  2172. static inline int
  2173. e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
  2174. {
  2175. uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
  2176. uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
  2177. E1000_ROUNDUP(skb_fifo_len, E1000_FIFO_HDR);
  2178. if(adapter->link_duplex != HALF_DUPLEX)
  2179. goto no_fifo_stall_required;
  2180. if(atomic_read(&adapter->tx_fifo_stall))
  2181. return 1;
  2182. if(skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
  2183. atomic_set(&adapter->tx_fifo_stall, 1);
  2184. return 1;
  2185. }
  2186. no_fifo_stall_required:
  2187. adapter->tx_fifo_head += skb_fifo_len;
  2188. if(adapter->tx_fifo_head >= adapter->tx_fifo_size)
  2189. adapter->tx_fifo_head -= adapter->tx_fifo_size;
  2190. return 0;
  2191. }
  2192. #define MINIMUM_DHCP_PACKET_SIZE 282
  2193. static inline int
  2194. e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
  2195. {
  2196. struct e1000_hw *hw = &adapter->hw;
  2197. uint16_t length, offset;
  2198. if(vlan_tx_tag_present(skb)) {
  2199. if(!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
  2200. ( adapter->hw.mng_cookie.status &
  2201. E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
  2202. return 0;
  2203. }
  2204. if(htons(ETH_P_IP) == skb->protocol) {
  2205. const struct iphdr *ip = skb->nh.iph;
  2206. if(IPPROTO_UDP == ip->protocol) {
  2207. struct udphdr *udp = (struct udphdr *)(skb->h.uh);
  2208. if(ntohs(udp->dest) == 67) {
  2209. offset = (uint8_t *)udp + 8 - skb->data;
  2210. length = skb->len - offset;
  2211. return e1000_mng_write_dhcp_info(hw,
  2212. (uint8_t *)udp + 8, length);
  2213. }
  2214. }
  2215. } else if((skb->len > MINIMUM_DHCP_PACKET_SIZE) && (!skb->protocol)) {
  2216. struct ethhdr *eth = (struct ethhdr *) skb->data;
  2217. if((htons(ETH_P_IP) == eth->h_proto)) {
  2218. const struct iphdr *ip =
  2219. (struct iphdr *)((uint8_t *)skb->data+14);
  2220. if(IPPROTO_UDP == ip->protocol) {
  2221. struct udphdr *udp =
  2222. (struct udphdr *)((uint8_t *)ip +
  2223. (ip->ihl << 2));
  2224. if(ntohs(udp->dest) == 67) {
  2225. offset = (uint8_t *)udp + 8 - skb->data;
  2226. length = skb->len - offset;
  2227. return e1000_mng_write_dhcp_info(hw,
  2228. (uint8_t *)udp + 8,
  2229. length);
  2230. }
  2231. }
  2232. }
  2233. }
  2234. return 0;
  2235. }
  2236. #define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
  2237. static int
  2238. e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
  2239. {
  2240. struct e1000_adapter *adapter = netdev_priv(netdev);
  2241. struct e1000_tx_ring *tx_ring;
  2242. unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
  2243. unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
  2244. unsigned int tx_flags = 0;
  2245. unsigned int len = skb->len;
  2246. unsigned long flags;
  2247. unsigned int nr_frags = 0;
  2248. unsigned int mss = 0;
  2249. int count = 0;
  2250. int tso;
  2251. unsigned int f;
  2252. len -= skb->data_len;
  2253. #ifdef CONFIG_E1000_MQ
  2254. tx_ring = *per_cpu_ptr(adapter->cpu_tx_ring, smp_processor_id());
  2255. #else
  2256. tx_ring = adapter->tx_ring;
  2257. #endif
  2258. if (unlikely(skb->len <= 0)) {
  2259. dev_kfree_skb_any(skb);
  2260. return NETDEV_TX_OK;
  2261. }
  2262. #ifdef NETIF_F_TSO
  2263. mss = skb_shinfo(skb)->tso_size;
  2264. /* The controller does a simple calculation to
  2265. * make sure there is enough room in the FIFO before
  2266. * initiating the DMA for each buffer. The calc is:
  2267. * 4 = ceil(buffer len/mss). To make sure we don't
  2268. * overrun the FIFO, adjust the max buffer len if mss
  2269. * drops. */
  2270. if(mss) {
  2271. max_per_txd = min(mss << 2, max_per_txd);
  2272. max_txd_pwr = fls(max_per_txd) - 1;
  2273. }
  2274. if((mss) || (skb->ip_summed == CHECKSUM_HW))
  2275. count++;
  2276. count++;
  2277. #else
  2278. if(skb->ip_summed == CHECKSUM_HW)
  2279. count++;
  2280. #endif
  2281. count += TXD_USE_COUNT(len, max_txd_pwr);
  2282. if(adapter->pcix_82544)
  2283. count++;
  2284. /* work-around for errata 10 and it applies to all controllers
  2285. * in PCI-X mode, so add one more descriptor to the count
  2286. */
  2287. if(unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
  2288. (len > 2015)))
  2289. count++;
  2290. nr_frags = skb_shinfo(skb)->nr_frags;
  2291. for(f = 0; f < nr_frags; f++)
  2292. count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
  2293. max_txd_pwr);
  2294. if(adapter->pcix_82544)
  2295. count += nr_frags;
  2296. #ifdef NETIF_F_TSO
  2297. /* TSO Workaround for 82571/2 Controllers -- if skb->data
  2298. * points to just header, pull a few bytes of payload from
  2299. * frags into skb->data */
  2300. if (skb_shinfo(skb)->tso_size) {
  2301. uint8_t hdr_len;
  2302. hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
  2303. if (skb->data_len && (hdr_len < (skb->len - skb->data_len)) &&
  2304. (adapter->hw.mac_type == e1000_82571 ||
  2305. adapter->hw.mac_type == e1000_82572)) {
  2306. unsigned int pull_size;
  2307. pull_size = min((unsigned int)4, skb->data_len);
  2308. if (!__pskb_pull_tail(skb, pull_size)) {
  2309. printk(KERN_ERR "__pskb_pull_tail failed.\n");
  2310. dev_kfree_skb_any(skb);
  2311. return -EFAULT;
  2312. }
  2313. }
  2314. }
  2315. #endif
  2316. if(adapter->hw.tx_pkt_filtering && (adapter->hw.mac_type == e1000_82573) )
  2317. e1000_transfer_dhcp_info(adapter, skb);
  2318. local_irq_save(flags);
  2319. if (!spin_trylock(&tx_ring->tx_lock)) {
  2320. /* Collision - tell upper layer to requeue */
  2321. local_irq_restore(flags);
  2322. return NETDEV_TX_LOCKED;
  2323. }
  2324. /* need: count + 2 desc gap to keep tail from touching
  2325. * head, otherwise try next time */
  2326. if (unlikely(E1000_DESC_UNUSED(tx_ring) < count + 2)) {
  2327. netif_stop_queue(netdev);
  2328. spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
  2329. return NETDEV_TX_BUSY;
  2330. }
  2331. if(unlikely(adapter->hw.mac_type == e1000_82547)) {
  2332. if(unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
  2333. netif_stop_queue(netdev);
  2334. mod_timer(&adapter->tx_fifo_stall_timer, jiffies);
  2335. spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
  2336. return NETDEV_TX_BUSY;
  2337. }
  2338. }
  2339. if(unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
  2340. tx_flags |= E1000_TX_FLAGS_VLAN;
  2341. tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
  2342. }
  2343. first = tx_ring->next_to_use;
  2344. tso = e1000_tso(adapter, tx_ring, skb);
  2345. if (tso < 0) {
  2346. dev_kfree_skb_any(skb);
  2347. spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
  2348. return NETDEV_TX_OK;
  2349. }
  2350. if (likely(tso))
  2351. tx_flags |= E1000_TX_FLAGS_TSO;
  2352. else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
  2353. tx_flags |= E1000_TX_FLAGS_CSUM;
  2354. /* Old method was to assume IPv4 packet by default if TSO was enabled.
  2355. * 82571 hardware supports TSO capabilities for IPv6 as well...
  2356. * no longer assume, we must. */
  2357. if (likely(skb->protocol == ntohs(ETH_P_IP)))
  2358. tx_flags |= E1000_TX_FLAGS_IPV4;
  2359. e1000_tx_queue(adapter, tx_ring, tx_flags,
  2360. e1000_tx_map(adapter, tx_ring, skb, first,
  2361. max_per_txd, nr_frags, mss));
  2362. netdev->trans_start = jiffies;
  2363. /* Make sure there is space in the ring for the next send. */
  2364. if (unlikely(E1000_DESC_UNUSED(tx_ring) < MAX_SKB_FRAGS + 2))
  2365. netif_stop_queue(netdev);
  2366. spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
  2367. return NETDEV_TX_OK;
  2368. }
  2369. /**
  2370. * e1000_tx_timeout - Respond to a Tx Hang
  2371. * @netdev: network interface device structure
  2372. **/
  2373. static void
  2374. e1000_tx_timeout(struct net_device *netdev)
  2375. {
  2376. struct e1000_adapter *adapter = netdev_priv(netdev);
  2377. /* Do the reset outside of interrupt context */
  2378. schedule_work(&adapter->tx_timeout_task);
  2379. }
  2380. static void
  2381. e1000_tx_timeout_task(struct net_device *netdev)
  2382. {
  2383. struct e1000_adapter *adapter = netdev_priv(netdev);
  2384. e1000_down(adapter);
  2385. e1000_up(adapter);
  2386. }
  2387. /**
  2388. * e1000_get_stats - Get System Network Statistics
  2389. * @netdev: network interface device structure
  2390. *
  2391. * Returns the address of the device statistics structure.
  2392. * The statistics are actually updated from the timer callback.
  2393. **/
  2394. static struct net_device_stats *
  2395. e1000_get_stats(struct net_device *netdev)
  2396. {
  2397. struct e1000_adapter *adapter = netdev_priv(netdev);
  2398. e1000_update_stats(adapter);
  2399. return &adapter->net_stats;
  2400. }
  2401. /**
  2402. * e1000_change_mtu - Change the Maximum Transfer Unit
  2403. * @netdev: network interface device structure
  2404. * @new_mtu: new value for maximum frame size
  2405. *
  2406. * Returns 0 on success, negative on failure
  2407. **/
  2408. static int
  2409. e1000_change_mtu(struct net_device *netdev, int new_mtu)
  2410. {
  2411. struct e1000_adapter *adapter = netdev_priv(netdev);
  2412. int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
  2413. if((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
  2414. (max_frame > MAX_JUMBO_FRAME_SIZE)) {
  2415. DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
  2416. return -EINVAL;
  2417. }
  2418. #define MAX_STD_JUMBO_FRAME_SIZE 9234
  2419. /* might want this to be bigger enum check... */
  2420. /* 82571 controllers limit jumbo frame size to 10500 bytes */
  2421. if ((adapter->hw.mac_type == e1000_82571 ||
  2422. adapter->hw.mac_type == e1000_82572) &&
  2423. max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
  2424. DPRINTK(PROBE, ERR, "MTU > 9216 bytes not supported "
  2425. "on 82571 and 82572 controllers.\n");
  2426. return -EINVAL;
  2427. }
  2428. if(adapter->hw.mac_type == e1000_82573 &&
  2429. max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
  2430. DPRINTK(PROBE, ERR, "Jumbo Frames not supported "
  2431. "on 82573\n");
  2432. return -EINVAL;
  2433. }
  2434. if(adapter->hw.mac_type > e1000_82547_rev_2) {
  2435. adapter->rx_buffer_len = max_frame;
  2436. E1000_ROUNDUP(adapter->rx_buffer_len, 1024);
  2437. } else {
  2438. if(unlikely((adapter->hw.mac_type < e1000_82543) &&
  2439. (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE))) {
  2440. DPRINTK(PROBE, ERR, "Jumbo Frames not supported "
  2441. "on 82542\n");
  2442. return -EINVAL;
  2443. } else {
  2444. if(max_frame <= E1000_RXBUFFER_2048) {
  2445. adapter->rx_buffer_len = E1000_RXBUFFER_2048;
  2446. } else if(max_frame <= E1000_RXBUFFER_4096) {
  2447. adapter->rx_buffer_len = E1000_RXBUFFER_4096;
  2448. } else if(max_frame <= E1000_RXBUFFER_8192) {
  2449. adapter->rx_buffer_len = E1000_RXBUFFER_8192;
  2450. } else if(max_frame <= E1000_RXBUFFER_16384) {
  2451. adapter->rx_buffer_len = E1000_RXBUFFER_16384;
  2452. }
  2453. }
  2454. }
  2455. netdev->mtu = new_mtu;
  2456. if(netif_running(netdev)) {
  2457. e1000_down(adapter);
  2458. e1000_up(adapter);
  2459. }
  2460. adapter->hw.max_frame_size = max_frame;
  2461. return 0;
  2462. }
  2463. /**
  2464. * e1000_update_stats - Update the board statistics counters
  2465. * @adapter: board private structure
  2466. **/
  2467. void
  2468. e1000_update_stats(struct e1000_adapter *adapter)
  2469. {
  2470. struct e1000_hw *hw = &adapter->hw;
  2471. unsigned long flags;
  2472. uint16_t phy_tmp;
  2473. #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
  2474. spin_lock_irqsave(&adapter->stats_lock, flags);
  2475. /* these counters are modified from e1000_adjust_tbi_stats,
  2476. * called from the interrupt context, so they must only
  2477. * be written while holding adapter->stats_lock
  2478. */
  2479. adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
  2480. adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
  2481. adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
  2482. adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
  2483. adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
  2484. adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
  2485. adapter->stats.roc += E1000_READ_REG(hw, ROC);
  2486. adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
  2487. adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
  2488. adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
  2489. adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
  2490. adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
  2491. adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
  2492. adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
  2493. adapter->stats.mpc += E1000_READ_REG(hw, MPC);
  2494. adapter->stats.scc += E1000_READ_REG(hw, SCC);
  2495. adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
  2496. adapter->stats.mcc += E1000_READ_REG(hw, MCC);
  2497. adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
  2498. adapter->stats.dc += E1000_READ_REG(hw, DC);
  2499. adapter->stats.sec += E1000_READ_REG(hw, SEC);
  2500. adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
  2501. adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
  2502. adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
  2503. adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
  2504. adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
  2505. adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
  2506. adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
  2507. adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
  2508. adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
  2509. adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
  2510. adapter->stats.ruc += E1000_READ_REG(hw, RUC);
  2511. adapter->stats.rfc += E1000_READ_REG(hw, RFC);
  2512. adapter->stats.rjc += E1000_READ_REG(hw, RJC);
  2513. adapter->stats.torl += E1000_READ_REG(hw, TORL);
  2514. adapter->stats.torh += E1000_READ_REG(hw, TORH);
  2515. adapter->stats.totl += E1000_READ_REG(hw, TOTL);
  2516. adapter->stats.toth += E1000_READ_REG(hw, TOTH);
  2517. adapter->stats.tpr += E1000_READ_REG(hw, TPR);
  2518. adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
  2519. adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
  2520. adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
  2521. adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
  2522. adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
  2523. adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
  2524. adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
  2525. adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
  2526. /* used for adaptive IFS */
  2527. hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
  2528. adapter->stats.tpt += hw->tx_packet_delta;
  2529. hw->collision_delta = E1000_READ_REG(hw, COLC);
  2530. adapter->stats.colc += hw->collision_delta;
  2531. if(hw->mac_type >= e1000_82543) {
  2532. adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
  2533. adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
  2534. adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
  2535. adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
  2536. adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
  2537. adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
  2538. }
  2539. if(hw->mac_type > e1000_82547_rev_2) {
  2540. adapter->stats.iac += E1000_READ_REG(hw, IAC);
  2541. adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
  2542. adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
  2543. adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
  2544. adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
  2545. adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
  2546. adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
  2547. adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
  2548. adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
  2549. }
  2550. /* Fill out the OS statistics structure */
  2551. adapter->net_stats.rx_packets = adapter->stats.gprc;
  2552. adapter->net_stats.tx_packets = adapter->stats.gptc;
  2553. adapter->net_stats.rx_bytes = adapter->stats.gorcl;
  2554. adapter->net_stats.tx_bytes = adapter->stats.gotcl;
  2555. adapter->net_stats.multicast = adapter->stats.mprc;
  2556. adapter->net_stats.collisions = adapter->stats.colc;
  2557. /* Rx Errors */
  2558. adapter->net_stats.rx_errors = adapter->stats.rxerrc +
  2559. adapter->stats.crcerrs + adapter->stats.algnerrc +
  2560. adapter->stats.rlec + adapter->stats.mpc +
  2561. adapter->stats.cexterr;
  2562. adapter->net_stats.rx_length_errors = adapter->stats.rlec;
  2563. adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
  2564. adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
  2565. adapter->net_stats.rx_fifo_errors = adapter->stats.mpc;
  2566. adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
  2567. /* Tx Errors */
  2568. adapter->net_stats.tx_errors = adapter->stats.ecol +
  2569. adapter->stats.latecol;
  2570. adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
  2571. adapter->net_stats.tx_window_errors = adapter->stats.latecol;
  2572. adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
  2573. /* Tx Dropped needs to be maintained elsewhere */
  2574. /* Phy Stats */
  2575. if(hw->media_type == e1000_media_type_copper) {
  2576. if((adapter->link_speed == SPEED_1000) &&
  2577. (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
  2578. phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
  2579. adapter->phy_stats.idle_errors += phy_tmp;
  2580. }
  2581. if((hw->mac_type <= e1000_82546) &&
  2582. (hw->phy_type == e1000_phy_m88) &&
  2583. !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
  2584. adapter->phy_stats.receive_errors += phy_tmp;
  2585. }
  2586. spin_unlock_irqrestore(&adapter->stats_lock, flags);
  2587. }
  2588. #ifdef CONFIG_E1000_MQ
  2589. void
  2590. e1000_rx_schedule(void *data)
  2591. {
  2592. struct net_device *poll_dev, *netdev = data;
  2593. struct e1000_adapter *adapter = netdev->priv;
  2594. int this_cpu = get_cpu();
  2595. poll_dev = *per_cpu_ptr(adapter->cpu_netdev, this_cpu);
  2596. if (poll_dev == NULL) {
  2597. put_cpu();
  2598. return;
  2599. }
  2600. if (likely(netif_rx_schedule_prep(poll_dev)))
  2601. __netif_rx_schedule(poll_dev);
  2602. else
  2603. e1000_irq_enable(adapter);
  2604. put_cpu();
  2605. }
  2606. #endif
  2607. /**
  2608. * e1000_intr - Interrupt Handler
  2609. * @irq: interrupt number
  2610. * @data: pointer to a network interface device structure
  2611. * @pt_regs: CPU registers structure
  2612. **/
  2613. static irqreturn_t
  2614. e1000_intr(int irq, void *data, struct pt_regs *regs)
  2615. {
  2616. struct net_device *netdev = data;
  2617. struct e1000_adapter *adapter = netdev_priv(netdev);
  2618. struct e1000_hw *hw = &adapter->hw;
  2619. uint32_t icr = E1000_READ_REG(hw, ICR);
  2620. #ifdef CONFIG_E1000_MQ
  2621. int i;
  2622. #endif
  2623. if(unlikely(!icr))
  2624. return IRQ_NONE; /* Not our interrupt */
  2625. if(unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
  2626. hw->get_link_status = 1;
  2627. mod_timer(&adapter->watchdog_timer, jiffies);
  2628. }
  2629. #ifdef CONFIG_E1000_NAPI
  2630. atomic_inc(&adapter->irq_sem);
  2631. E1000_WRITE_REG(hw, IMC, ~0);
  2632. E1000_WRITE_FLUSH(hw);
  2633. #ifdef CONFIG_E1000_MQ
  2634. if (atomic_read(&adapter->rx_sched_call_data.count) == 0) {
  2635. cpu_set(adapter->cpu_for_queue[0],
  2636. adapter->rx_sched_call_data.cpumask);
  2637. for (i = 1; i < adapter->num_queues; i++) {
  2638. cpu_set(adapter->cpu_for_queue[i],
  2639. adapter->rx_sched_call_data.cpumask);
  2640. atomic_inc(&adapter->irq_sem);
  2641. }
  2642. atomic_set(&adapter->rx_sched_call_data.count, i);
  2643. smp_call_async_mask(&adapter->rx_sched_call_data);
  2644. } else {
  2645. printk("call_data.count == %u\n", atomic_read(&adapter->rx_sched_call_data.count));
  2646. }
  2647. #else /* if !CONFIG_E1000_MQ */
  2648. if (likely(netif_rx_schedule_prep(&adapter->polling_netdev[0])))
  2649. __netif_rx_schedule(&adapter->polling_netdev[0]);
  2650. else
  2651. e1000_irq_enable(adapter);
  2652. #endif /* CONFIG_E1000_MQ */
  2653. #else /* if !CONFIG_E1000_NAPI */
  2654. /* Writing IMC and IMS is needed for 82547.
  2655. Due to Hub Link bus being occupied, an interrupt
  2656. de-assertion message is not able to be sent.
  2657. When an interrupt assertion message is generated later,
  2658. two messages are re-ordered and sent out.
  2659. That causes APIC to think 82547 is in de-assertion
  2660. state, while 82547 is in assertion state, resulting
  2661. in dead lock. Writing IMC forces 82547 into
  2662. de-assertion state.
  2663. */
  2664. if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2){
  2665. atomic_inc(&adapter->irq_sem);
  2666. E1000_WRITE_REG(hw, IMC, ~0);
  2667. }
  2668. for(i = 0; i < E1000_MAX_INTR; i++)
  2669. if(unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
  2670. !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
  2671. break;
  2672. if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
  2673. e1000_irq_enable(adapter);
  2674. #endif /* CONFIG_E1000_NAPI */
  2675. return IRQ_HANDLED;
  2676. }
  2677. #ifdef CONFIG_E1000_NAPI
  2678. /**
  2679. * e1000_clean - NAPI Rx polling callback
  2680. * @adapter: board private structure
  2681. **/
  2682. static int
  2683. e1000_clean(struct net_device *poll_dev, int *budget)
  2684. {
  2685. struct e1000_adapter *adapter;
  2686. int work_to_do = min(*budget, poll_dev->quota);
  2687. int tx_cleaned, i = 0, work_done = 0;
  2688. /* Must NOT use netdev_priv macro here. */
  2689. adapter = poll_dev->priv;
  2690. /* Keep link state information with original netdev */
  2691. if (!netif_carrier_ok(adapter->netdev))
  2692. goto quit_polling;
  2693. while (poll_dev != &adapter->polling_netdev[i]) {
  2694. i++;
  2695. if (unlikely(i == adapter->num_queues))
  2696. BUG();
  2697. }
  2698. tx_cleaned = e1000_clean_tx_irq(adapter, &adapter->tx_ring[i]);
  2699. adapter->clean_rx(adapter, &adapter->rx_ring[i],
  2700. &work_done, work_to_do);
  2701. *budget -= work_done;
  2702. poll_dev->quota -= work_done;
  2703. /* If no Tx and not enough Rx work done, exit the polling mode */
  2704. if((!tx_cleaned && (work_done == 0)) ||
  2705. !netif_running(adapter->netdev)) {
  2706. quit_polling:
  2707. netif_rx_complete(poll_dev);
  2708. e1000_irq_enable(adapter);
  2709. return 0;
  2710. }
  2711. return 1;
  2712. }
  2713. #endif
  2714. /**
  2715. * e1000_clean_tx_irq - Reclaim resources after transmit completes
  2716. * @adapter: board private structure
  2717. **/
  2718. static boolean_t
  2719. e1000_clean_tx_irq(struct e1000_adapter *adapter,
  2720. struct e1000_tx_ring *tx_ring)
  2721. {
  2722. struct net_device *netdev = adapter->netdev;
  2723. struct e1000_tx_desc *tx_desc, *eop_desc;
  2724. struct e1000_buffer *buffer_info;
  2725. unsigned int i, eop;
  2726. boolean_t cleaned = FALSE;
  2727. i = tx_ring->next_to_clean;
  2728. eop = tx_ring->buffer_info[i].next_to_watch;
  2729. eop_desc = E1000_TX_DESC(*tx_ring, eop);
  2730. while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
  2731. /* Premature writeback of Tx descriptors clear (free buffers
  2732. * and unmap pci_mapping) previous_buffer_info */
  2733. if (likely(tx_ring->previous_buffer_info.skb != NULL)) {
  2734. e1000_unmap_and_free_tx_resource(adapter,
  2735. &tx_ring->previous_buffer_info);
  2736. }
  2737. for(cleaned = FALSE; !cleaned; ) {
  2738. tx_desc = E1000_TX_DESC(*tx_ring, i);
  2739. buffer_info = &tx_ring->buffer_info[i];
  2740. cleaned = (i == eop);
  2741. #ifdef NETIF_F_TSO
  2742. if (!(netdev->features & NETIF_F_TSO)) {
  2743. #endif
  2744. e1000_unmap_and_free_tx_resource(adapter,
  2745. buffer_info);
  2746. #ifdef NETIF_F_TSO
  2747. } else {
  2748. if (cleaned) {
  2749. memcpy(&tx_ring->previous_buffer_info,
  2750. buffer_info,
  2751. sizeof(struct e1000_buffer));
  2752. memset(buffer_info, 0,
  2753. sizeof(struct e1000_buffer));
  2754. } else {
  2755. e1000_unmap_and_free_tx_resource(
  2756. adapter, buffer_info);
  2757. }
  2758. }
  2759. #endif
  2760. tx_desc->buffer_addr = 0;
  2761. tx_desc->lower.data = 0;
  2762. tx_desc->upper.data = 0;
  2763. if(unlikely(++i == tx_ring->count)) i = 0;
  2764. }
  2765. tx_ring->pkt++;
  2766. eop = tx_ring->buffer_info[i].next_to_watch;
  2767. eop_desc = E1000_TX_DESC(*tx_ring, eop);
  2768. }
  2769. tx_ring->next_to_clean = i;
  2770. spin_lock(&tx_ring->tx_lock);
  2771. if(unlikely(cleaned && netif_queue_stopped(netdev) &&
  2772. netif_carrier_ok(netdev)))
  2773. netif_wake_queue(netdev);
  2774. spin_unlock(&tx_ring->tx_lock);
  2775. if (adapter->detect_tx_hung) {
  2776. /* Detect a transmit hang in hardware, this serializes the
  2777. * check with the clearing of time_stamp and movement of i */
  2778. adapter->detect_tx_hung = FALSE;
  2779. if (tx_ring->buffer_info[i].dma &&
  2780. time_after(jiffies, tx_ring->buffer_info[i].time_stamp + HZ)
  2781. && !(E1000_READ_REG(&adapter->hw, STATUS) &
  2782. E1000_STATUS_TXOFF)) {
  2783. /* detected Tx unit hang */
  2784. i = tx_ring->next_to_clean;
  2785. eop = tx_ring->buffer_info[i].next_to_watch;
  2786. eop_desc = E1000_TX_DESC(*tx_ring, eop);
  2787. DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
  2788. " TDH <%x>\n"
  2789. " TDT <%x>\n"
  2790. " next_to_use <%x>\n"
  2791. " next_to_clean <%x>\n"
  2792. "buffer_info[next_to_clean]\n"
  2793. " dma <%llx>\n"
  2794. " time_stamp <%lx>\n"
  2795. " next_to_watch <%x>\n"
  2796. " jiffies <%lx>\n"
  2797. " next_to_watch.status <%x>\n",
  2798. readl(adapter->hw.hw_addr + tx_ring->tdh),
  2799. readl(adapter->hw.hw_addr + tx_ring->tdt),
  2800. tx_ring->next_to_use,
  2801. i,
  2802. (unsigned long long)tx_ring->buffer_info[i].dma,
  2803. tx_ring->buffer_info[i].time_stamp,
  2804. eop,
  2805. jiffies,
  2806. eop_desc->upper.fields.status);
  2807. netif_stop_queue(netdev);
  2808. }
  2809. }
  2810. #ifdef NETIF_F_TSO
  2811. if (unlikely(!(eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
  2812. time_after(jiffies, tx_ring->previous_buffer_info.time_stamp + HZ)))
  2813. e1000_unmap_and_free_tx_resource(
  2814. adapter, &tx_ring->previous_buffer_info);
  2815. #endif
  2816. return cleaned;
  2817. }
  2818. /**
  2819. * e1000_rx_checksum - Receive Checksum Offload for 82543
  2820. * @adapter: board private structure
  2821. * @status_err: receive descriptor status and error fields
  2822. * @csum: receive descriptor csum field
  2823. * @sk_buff: socket buffer with received data
  2824. **/
  2825. static inline void
  2826. e1000_rx_checksum(struct e1000_adapter *adapter,
  2827. uint32_t status_err, uint32_t csum,
  2828. struct sk_buff *skb)
  2829. {
  2830. uint16_t status = (uint16_t)status_err;
  2831. uint8_t errors = (uint8_t)(status_err >> 24);
  2832. skb->ip_summed = CHECKSUM_NONE;
  2833. /* 82543 or newer only */
  2834. if(unlikely(adapter->hw.mac_type < e1000_82543)) return;
  2835. /* Ignore Checksum bit is set */
  2836. if(unlikely(status & E1000_RXD_STAT_IXSM)) return;
  2837. /* TCP/UDP checksum error bit is set */
  2838. if(unlikely(errors & E1000_RXD_ERR_TCPE)) {
  2839. /* let the stack verify checksum errors */
  2840. adapter->hw_csum_err++;
  2841. return;
  2842. }
  2843. /* TCP/UDP Checksum has not been calculated */
  2844. if(adapter->hw.mac_type <= e1000_82547_rev_2) {
  2845. if(!(status & E1000_RXD_STAT_TCPCS))
  2846. return;
  2847. } else {
  2848. if(!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
  2849. return;
  2850. }
  2851. /* It must be a TCP or UDP packet with a valid checksum */
  2852. if (likely(status & E1000_RXD_STAT_TCPCS)) {
  2853. /* TCP checksum is good */
  2854. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2855. } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
  2856. /* IP fragment with UDP payload */
  2857. /* Hardware complements the payload checksum, so we undo it
  2858. * and then put the value in host order for further stack use.
  2859. */
  2860. csum = ntohl(csum ^ 0xFFFF);
  2861. skb->csum = csum;
  2862. skb->ip_summed = CHECKSUM_HW;
  2863. }
  2864. adapter->hw_csum_good++;
  2865. }
  2866. /**
  2867. * e1000_clean_rx_irq - Send received data up the network stack; legacy
  2868. * @adapter: board private structure
  2869. **/
  2870. static boolean_t
  2871. #ifdef CONFIG_E1000_NAPI
  2872. e1000_clean_rx_irq(struct e1000_adapter *adapter,
  2873. struct e1000_rx_ring *rx_ring,
  2874. int *work_done, int work_to_do)
  2875. #else
  2876. e1000_clean_rx_irq(struct e1000_adapter *adapter,
  2877. struct e1000_rx_ring *rx_ring)
  2878. #endif
  2879. {
  2880. struct net_device *netdev = adapter->netdev;
  2881. struct pci_dev *pdev = adapter->pdev;
  2882. struct e1000_rx_desc *rx_desc;
  2883. struct e1000_buffer *buffer_info;
  2884. struct sk_buff *skb;
  2885. unsigned long flags;
  2886. uint32_t length;
  2887. uint8_t last_byte;
  2888. unsigned int i;
  2889. boolean_t cleaned = FALSE;
  2890. i = rx_ring->next_to_clean;
  2891. rx_desc = E1000_RX_DESC(*rx_ring, i);
  2892. while(rx_desc->status & E1000_RXD_STAT_DD) {
  2893. buffer_info = &rx_ring->buffer_info[i];
  2894. #ifdef CONFIG_E1000_NAPI
  2895. if(*work_done >= work_to_do)
  2896. break;
  2897. (*work_done)++;
  2898. #endif
  2899. cleaned = TRUE;
  2900. pci_unmap_single(pdev,
  2901. buffer_info->dma,
  2902. buffer_info->length,
  2903. PCI_DMA_FROMDEVICE);
  2904. skb = buffer_info->skb;
  2905. length = le16_to_cpu(rx_desc->length);
  2906. if(unlikely(!(rx_desc->status & E1000_RXD_STAT_EOP))) {
  2907. /* All receives must fit into a single buffer */
  2908. E1000_DBG("%s: Receive packet consumed multiple"
  2909. " buffers\n", netdev->name);
  2910. dev_kfree_skb_irq(skb);
  2911. goto next_desc;
  2912. }
  2913. if(unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
  2914. last_byte = *(skb->data + length - 1);
  2915. if(TBI_ACCEPT(&adapter->hw, rx_desc->status,
  2916. rx_desc->errors, length, last_byte)) {
  2917. spin_lock_irqsave(&adapter->stats_lock, flags);
  2918. e1000_tbi_adjust_stats(&adapter->hw,
  2919. &adapter->stats,
  2920. length, skb->data);
  2921. spin_unlock_irqrestore(&adapter->stats_lock,
  2922. flags);
  2923. length--;
  2924. } else {
  2925. dev_kfree_skb_irq(skb);
  2926. goto next_desc;
  2927. }
  2928. }
  2929. /* Good Receive */
  2930. skb_put(skb, length - ETHERNET_FCS_SIZE);
  2931. /* Receive Checksum Offload */
  2932. e1000_rx_checksum(adapter,
  2933. (uint32_t)(rx_desc->status) |
  2934. ((uint32_t)(rx_desc->errors) << 24),
  2935. rx_desc->csum, skb);
  2936. skb->protocol = eth_type_trans(skb, netdev);
  2937. #ifdef CONFIG_E1000_NAPI
  2938. if(unlikely(adapter->vlgrp &&
  2939. (rx_desc->status & E1000_RXD_STAT_VP))) {
  2940. vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
  2941. le16_to_cpu(rx_desc->special) &
  2942. E1000_RXD_SPC_VLAN_MASK);
  2943. } else {
  2944. netif_receive_skb(skb);
  2945. }
  2946. #else /* CONFIG_E1000_NAPI */
  2947. if(unlikely(adapter->vlgrp &&
  2948. (rx_desc->status & E1000_RXD_STAT_VP))) {
  2949. vlan_hwaccel_rx(skb, adapter->vlgrp,
  2950. le16_to_cpu(rx_desc->special) &
  2951. E1000_RXD_SPC_VLAN_MASK);
  2952. } else {
  2953. netif_rx(skb);
  2954. }
  2955. #endif /* CONFIG_E1000_NAPI */
  2956. netdev->last_rx = jiffies;
  2957. rx_ring->pkt++;
  2958. next_desc:
  2959. rx_desc->status = 0;
  2960. buffer_info->skb = NULL;
  2961. if(unlikely(++i == rx_ring->count)) i = 0;
  2962. rx_desc = E1000_RX_DESC(*rx_ring, i);
  2963. }
  2964. rx_ring->next_to_clean = i;
  2965. adapter->alloc_rx_buf(adapter, rx_ring);
  2966. return cleaned;
  2967. }
  2968. /**
  2969. * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
  2970. * @adapter: board private structure
  2971. **/
  2972. static boolean_t
  2973. #ifdef CONFIG_E1000_NAPI
  2974. e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
  2975. struct e1000_rx_ring *rx_ring,
  2976. int *work_done, int work_to_do)
  2977. #else
  2978. e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
  2979. struct e1000_rx_ring *rx_ring)
  2980. #endif
  2981. {
  2982. union e1000_rx_desc_packet_split *rx_desc;
  2983. struct net_device *netdev = adapter->netdev;
  2984. struct pci_dev *pdev = adapter->pdev;
  2985. struct e1000_buffer *buffer_info;
  2986. struct e1000_ps_page *ps_page;
  2987. struct e1000_ps_page_dma *ps_page_dma;
  2988. struct sk_buff *skb;
  2989. unsigned int i, j;
  2990. uint32_t length, staterr;
  2991. boolean_t cleaned = FALSE;
  2992. i = rx_ring->next_to_clean;
  2993. rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
  2994. staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
  2995. while(staterr & E1000_RXD_STAT_DD) {
  2996. buffer_info = &rx_ring->buffer_info[i];
  2997. ps_page = &rx_ring->ps_page[i];
  2998. ps_page_dma = &rx_ring->ps_page_dma[i];
  2999. #ifdef CONFIG_E1000_NAPI
  3000. if(unlikely(*work_done >= work_to_do))
  3001. break;
  3002. (*work_done)++;
  3003. #endif
  3004. cleaned = TRUE;
  3005. pci_unmap_single(pdev, buffer_info->dma,
  3006. buffer_info->length,
  3007. PCI_DMA_FROMDEVICE);
  3008. skb = buffer_info->skb;
  3009. if(unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
  3010. E1000_DBG("%s: Packet Split buffers didn't pick up"
  3011. " the full packet\n", netdev->name);
  3012. dev_kfree_skb_irq(skb);
  3013. goto next_desc;
  3014. }
  3015. if(unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
  3016. dev_kfree_skb_irq(skb);
  3017. goto next_desc;
  3018. }
  3019. length = le16_to_cpu(rx_desc->wb.middle.length0);
  3020. if(unlikely(!length)) {
  3021. E1000_DBG("%s: Last part of the packet spanning"
  3022. " multiple descriptors\n", netdev->name);
  3023. dev_kfree_skb_irq(skb);
  3024. goto next_desc;
  3025. }
  3026. /* Good Receive */
  3027. skb_put(skb, length);
  3028. for(j = 0; j < adapter->rx_ps_pages; j++) {
  3029. if(!(length = le16_to_cpu(rx_desc->wb.upper.length[j])))
  3030. break;
  3031. pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
  3032. PAGE_SIZE, PCI_DMA_FROMDEVICE);
  3033. ps_page_dma->ps_page_dma[j] = 0;
  3034. skb_shinfo(skb)->frags[j].page =
  3035. ps_page->ps_page[j];
  3036. ps_page->ps_page[j] = NULL;
  3037. skb_shinfo(skb)->frags[j].page_offset = 0;
  3038. skb_shinfo(skb)->frags[j].size = length;
  3039. skb_shinfo(skb)->nr_frags++;
  3040. skb->len += length;
  3041. skb->data_len += length;
  3042. }
  3043. e1000_rx_checksum(adapter, staterr,
  3044. rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
  3045. skb->protocol = eth_type_trans(skb, netdev);
  3046. if(likely(rx_desc->wb.upper.header_status &
  3047. E1000_RXDPS_HDRSTAT_HDRSP)) {
  3048. adapter->rx_hdr_split++;
  3049. #ifdef HAVE_RX_ZERO_COPY
  3050. skb_shinfo(skb)->zero_copy = TRUE;
  3051. #endif
  3052. }
  3053. #ifdef CONFIG_E1000_NAPI
  3054. if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
  3055. vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
  3056. le16_to_cpu(rx_desc->wb.middle.vlan) &
  3057. E1000_RXD_SPC_VLAN_MASK);
  3058. } else {
  3059. netif_receive_skb(skb);
  3060. }
  3061. #else /* CONFIG_E1000_NAPI */
  3062. if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
  3063. vlan_hwaccel_rx(skb, adapter->vlgrp,
  3064. le16_to_cpu(rx_desc->wb.middle.vlan) &
  3065. E1000_RXD_SPC_VLAN_MASK);
  3066. } else {
  3067. netif_rx(skb);
  3068. }
  3069. #endif /* CONFIG_E1000_NAPI */
  3070. netdev->last_rx = jiffies;
  3071. rx_ring->pkt++;
  3072. next_desc:
  3073. rx_desc->wb.middle.status_error &= ~0xFF;
  3074. buffer_info->skb = NULL;
  3075. if(unlikely(++i == rx_ring->count)) i = 0;
  3076. rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
  3077. staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
  3078. }
  3079. rx_ring->next_to_clean = i;
  3080. adapter->alloc_rx_buf(adapter, rx_ring);
  3081. return cleaned;
  3082. }
  3083. /**
  3084. * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
  3085. * @adapter: address of board private structure
  3086. **/
  3087. static void
  3088. e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
  3089. struct e1000_rx_ring *rx_ring)
  3090. {
  3091. struct net_device *netdev = adapter->netdev;
  3092. struct pci_dev *pdev = adapter->pdev;
  3093. struct e1000_rx_desc *rx_desc;
  3094. struct e1000_buffer *buffer_info;
  3095. struct sk_buff *skb;
  3096. unsigned int i;
  3097. unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
  3098. i = rx_ring->next_to_use;
  3099. buffer_info = &rx_ring->buffer_info[i];
  3100. while(!buffer_info->skb) {
  3101. skb = dev_alloc_skb(bufsz);
  3102. if(unlikely(!skb)) {
  3103. /* Better luck next round */
  3104. break;
  3105. }
  3106. /* Fix for errata 23, can't cross 64kB boundary */
  3107. if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
  3108. struct sk_buff *oldskb = skb;
  3109. DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
  3110. "at %p\n", bufsz, skb->data);
  3111. /* Try again, without freeing the previous */
  3112. skb = dev_alloc_skb(bufsz);
  3113. /* Failed allocation, critical failure */
  3114. if (!skb) {
  3115. dev_kfree_skb(oldskb);
  3116. break;
  3117. }
  3118. if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
  3119. /* give up */
  3120. dev_kfree_skb(skb);
  3121. dev_kfree_skb(oldskb);
  3122. break; /* while !buffer_info->skb */
  3123. } else {
  3124. /* Use new allocation */
  3125. dev_kfree_skb(oldskb);
  3126. }
  3127. }
  3128. /* Make buffer alignment 2 beyond a 16 byte boundary
  3129. * this will result in a 16 byte aligned IP header after
  3130. * the 14 byte MAC header is removed
  3131. */
  3132. skb_reserve(skb, NET_IP_ALIGN);
  3133. skb->dev = netdev;
  3134. buffer_info->skb = skb;
  3135. buffer_info->length = adapter->rx_buffer_len;
  3136. buffer_info->dma = pci_map_single(pdev,
  3137. skb->data,
  3138. adapter->rx_buffer_len,
  3139. PCI_DMA_FROMDEVICE);
  3140. /* Fix for errata 23, can't cross 64kB boundary */
  3141. if (!e1000_check_64k_bound(adapter,
  3142. (void *)(unsigned long)buffer_info->dma,
  3143. adapter->rx_buffer_len)) {
  3144. DPRINTK(RX_ERR, ERR,
  3145. "dma align check failed: %u bytes at %p\n",
  3146. adapter->rx_buffer_len,
  3147. (void *)(unsigned long)buffer_info->dma);
  3148. dev_kfree_skb(skb);
  3149. buffer_info->skb = NULL;
  3150. pci_unmap_single(pdev, buffer_info->dma,
  3151. adapter->rx_buffer_len,
  3152. PCI_DMA_FROMDEVICE);
  3153. break; /* while !buffer_info->skb */
  3154. }
  3155. rx_desc = E1000_RX_DESC(*rx_ring, i);
  3156. rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
  3157. if(unlikely((i & ~(E1000_RX_BUFFER_WRITE - 1)) == i)) {
  3158. /* Force memory writes to complete before letting h/w
  3159. * know there are new descriptors to fetch. (Only
  3160. * applicable for weak-ordered memory model archs,
  3161. * such as IA-64). */
  3162. wmb();
  3163. writel(i, adapter->hw.hw_addr + rx_ring->rdt);
  3164. }
  3165. if(unlikely(++i == rx_ring->count)) i = 0;
  3166. buffer_info = &rx_ring->buffer_info[i];
  3167. }
  3168. rx_ring->next_to_use = i;
  3169. }
  3170. /**
  3171. * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
  3172. * @adapter: address of board private structure
  3173. **/
  3174. static void
  3175. e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
  3176. struct e1000_rx_ring *rx_ring)
  3177. {
  3178. struct net_device *netdev = adapter->netdev;
  3179. struct pci_dev *pdev = adapter->pdev;
  3180. union e1000_rx_desc_packet_split *rx_desc;
  3181. struct e1000_buffer *buffer_info;
  3182. struct e1000_ps_page *ps_page;
  3183. struct e1000_ps_page_dma *ps_page_dma;
  3184. struct sk_buff *skb;
  3185. unsigned int i, j;
  3186. i = rx_ring->next_to_use;
  3187. buffer_info = &rx_ring->buffer_info[i];
  3188. ps_page = &rx_ring->ps_page[i];
  3189. ps_page_dma = &rx_ring->ps_page_dma[i];
  3190. while(!buffer_info->skb) {
  3191. rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
  3192. for(j = 0; j < PS_PAGE_BUFFERS; j++) {
  3193. if (j < adapter->rx_ps_pages) {
  3194. if (likely(!ps_page->ps_page[j])) {
  3195. ps_page->ps_page[j] =
  3196. alloc_page(GFP_ATOMIC);
  3197. if (unlikely(!ps_page->ps_page[j]))
  3198. goto no_buffers;
  3199. ps_page_dma->ps_page_dma[j] =
  3200. pci_map_page(pdev,
  3201. ps_page->ps_page[j],
  3202. 0, PAGE_SIZE,
  3203. PCI_DMA_FROMDEVICE);
  3204. }
  3205. /* Refresh the desc even if buffer_addrs didn't
  3206. * change because each write-back erases
  3207. * this info.
  3208. */
  3209. rx_desc->read.buffer_addr[j+1] =
  3210. cpu_to_le64(ps_page_dma->ps_page_dma[j]);
  3211. } else
  3212. rx_desc->read.buffer_addr[j+1] = ~0;
  3213. }
  3214. skb = dev_alloc_skb(adapter->rx_ps_bsize0 + NET_IP_ALIGN);
  3215. if(unlikely(!skb))
  3216. break;
  3217. /* Make buffer alignment 2 beyond a 16 byte boundary
  3218. * this will result in a 16 byte aligned IP header after
  3219. * the 14 byte MAC header is removed
  3220. */
  3221. skb_reserve(skb, NET_IP_ALIGN);
  3222. skb->dev = netdev;
  3223. buffer_info->skb = skb;
  3224. buffer_info->length = adapter->rx_ps_bsize0;
  3225. buffer_info->dma = pci_map_single(pdev, skb->data,
  3226. adapter->rx_ps_bsize0,
  3227. PCI_DMA_FROMDEVICE);
  3228. rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
  3229. if(unlikely((i & ~(E1000_RX_BUFFER_WRITE - 1)) == i)) {
  3230. /* Force memory writes to complete before letting h/w
  3231. * know there are new descriptors to fetch. (Only
  3232. * applicable for weak-ordered memory model archs,
  3233. * such as IA-64). */
  3234. wmb();
  3235. /* Hardware increments by 16 bytes, but packet split
  3236. * descriptors are 32 bytes...so we increment tail
  3237. * twice as much.
  3238. */
  3239. writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
  3240. }
  3241. if(unlikely(++i == rx_ring->count)) i = 0;
  3242. buffer_info = &rx_ring->buffer_info[i];
  3243. ps_page = &rx_ring->ps_page[i];
  3244. ps_page_dma = &rx_ring->ps_page_dma[i];
  3245. }
  3246. no_buffers:
  3247. rx_ring->next_to_use = i;
  3248. }
  3249. /**
  3250. * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
  3251. * @adapter:
  3252. **/
  3253. static void
  3254. e1000_smartspeed(struct e1000_adapter *adapter)
  3255. {
  3256. uint16_t phy_status;
  3257. uint16_t phy_ctrl;
  3258. if((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
  3259. !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
  3260. return;
  3261. if(adapter->smartspeed == 0) {
  3262. /* If Master/Slave config fault is asserted twice,
  3263. * we assume back-to-back */
  3264. e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
  3265. if(!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
  3266. e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
  3267. if(!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
  3268. e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
  3269. if(phy_ctrl & CR_1000T_MS_ENABLE) {
  3270. phy_ctrl &= ~CR_1000T_MS_ENABLE;
  3271. e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
  3272. phy_ctrl);
  3273. adapter->smartspeed++;
  3274. if(!e1000_phy_setup_autoneg(&adapter->hw) &&
  3275. !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
  3276. &phy_ctrl)) {
  3277. phy_ctrl |= (MII_CR_AUTO_NEG_EN |
  3278. MII_CR_RESTART_AUTO_NEG);
  3279. e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
  3280. phy_ctrl);
  3281. }
  3282. }
  3283. return;
  3284. } else if(adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
  3285. /* If still no link, perhaps using 2/3 pair cable */
  3286. e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
  3287. phy_ctrl |= CR_1000T_MS_ENABLE;
  3288. e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
  3289. if(!e1000_phy_setup_autoneg(&adapter->hw) &&
  3290. !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
  3291. phy_ctrl |= (MII_CR_AUTO_NEG_EN |
  3292. MII_CR_RESTART_AUTO_NEG);
  3293. e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
  3294. }
  3295. }
  3296. /* Restart process after E1000_SMARTSPEED_MAX iterations */
  3297. if(adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
  3298. adapter->smartspeed = 0;
  3299. }
  3300. /**
  3301. * e1000_ioctl -
  3302. * @netdev:
  3303. * @ifreq:
  3304. * @cmd:
  3305. **/
  3306. static int
  3307. e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  3308. {
  3309. switch (cmd) {
  3310. case SIOCGMIIPHY:
  3311. case SIOCGMIIREG:
  3312. case SIOCSMIIREG:
  3313. return e1000_mii_ioctl(netdev, ifr, cmd);
  3314. default:
  3315. return -EOPNOTSUPP;
  3316. }
  3317. }
  3318. /**
  3319. * e1000_mii_ioctl -
  3320. * @netdev:
  3321. * @ifreq:
  3322. * @cmd:
  3323. **/
  3324. static int
  3325. e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  3326. {
  3327. struct e1000_adapter *adapter = netdev_priv(netdev);
  3328. struct mii_ioctl_data *data = if_mii(ifr);
  3329. int retval;
  3330. uint16_t mii_reg;
  3331. uint16_t spddplx;
  3332. unsigned long flags;
  3333. if(adapter->hw.media_type != e1000_media_type_copper)
  3334. return -EOPNOTSUPP;
  3335. switch (cmd) {
  3336. case SIOCGMIIPHY:
  3337. data->phy_id = adapter->hw.phy_addr;
  3338. break;
  3339. case SIOCGMIIREG:
  3340. if(!capable(CAP_NET_ADMIN))
  3341. return -EPERM;
  3342. spin_lock_irqsave(&adapter->stats_lock, flags);
  3343. if(e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
  3344. &data->val_out)) {
  3345. spin_unlock_irqrestore(&adapter->stats_lock, flags);
  3346. return -EIO;
  3347. }
  3348. spin_unlock_irqrestore(&adapter->stats_lock, flags);
  3349. break;
  3350. case SIOCSMIIREG:
  3351. if(!capable(CAP_NET_ADMIN))
  3352. return -EPERM;
  3353. if(data->reg_num & ~(0x1F))
  3354. return -EFAULT;
  3355. mii_reg = data->val_in;
  3356. spin_lock_irqsave(&adapter->stats_lock, flags);
  3357. if(e1000_write_phy_reg(&adapter->hw, data->reg_num,
  3358. mii_reg)) {
  3359. spin_unlock_irqrestore(&adapter->stats_lock, flags);
  3360. return -EIO;
  3361. }
  3362. if(adapter->hw.phy_type == e1000_phy_m88) {
  3363. switch (data->reg_num) {
  3364. case PHY_CTRL:
  3365. if(mii_reg & MII_CR_POWER_DOWN)
  3366. break;
  3367. if(mii_reg & MII_CR_AUTO_NEG_EN) {
  3368. adapter->hw.autoneg = 1;
  3369. adapter->hw.autoneg_advertised = 0x2F;
  3370. } else {
  3371. if (mii_reg & 0x40)
  3372. spddplx = SPEED_1000;
  3373. else if (mii_reg & 0x2000)
  3374. spddplx = SPEED_100;
  3375. else
  3376. spddplx = SPEED_10;
  3377. spddplx += (mii_reg & 0x100)
  3378. ? FULL_DUPLEX :
  3379. HALF_DUPLEX;
  3380. retval = e1000_set_spd_dplx(adapter,
  3381. spddplx);
  3382. if(retval) {
  3383. spin_unlock_irqrestore(
  3384. &adapter->stats_lock,
  3385. flags);
  3386. return retval;
  3387. }
  3388. }
  3389. if(netif_running(adapter->netdev)) {
  3390. e1000_down(adapter);
  3391. e1000_up(adapter);
  3392. } else
  3393. e1000_reset(adapter);
  3394. break;
  3395. case M88E1000_PHY_SPEC_CTRL:
  3396. case M88E1000_EXT_PHY_SPEC_CTRL:
  3397. if(e1000_phy_reset(&adapter->hw)) {
  3398. spin_unlock_irqrestore(
  3399. &adapter->stats_lock, flags);
  3400. return -EIO;
  3401. }
  3402. break;
  3403. }
  3404. } else {
  3405. switch (data->reg_num) {
  3406. case PHY_CTRL:
  3407. if(mii_reg & MII_CR_POWER_DOWN)
  3408. break;
  3409. if(netif_running(adapter->netdev)) {
  3410. e1000_down(adapter);
  3411. e1000_up(adapter);
  3412. } else
  3413. e1000_reset(adapter);
  3414. break;
  3415. }
  3416. }
  3417. spin_unlock_irqrestore(&adapter->stats_lock, flags);
  3418. break;
  3419. default:
  3420. return -EOPNOTSUPP;
  3421. }
  3422. return E1000_SUCCESS;
  3423. }
  3424. void
  3425. e1000_pci_set_mwi(struct e1000_hw *hw)
  3426. {
  3427. struct e1000_adapter *adapter = hw->back;
  3428. int ret_val = pci_set_mwi(adapter->pdev);
  3429. if(ret_val)
  3430. DPRINTK(PROBE, ERR, "Error in setting MWI\n");
  3431. }
  3432. void
  3433. e1000_pci_clear_mwi(struct e1000_hw *hw)
  3434. {
  3435. struct e1000_adapter *adapter = hw->back;
  3436. pci_clear_mwi(adapter->pdev);
  3437. }
  3438. void
  3439. e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
  3440. {
  3441. struct e1000_adapter *adapter = hw->back;
  3442. pci_read_config_word(adapter->pdev, reg, value);
  3443. }
  3444. void
  3445. e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
  3446. {
  3447. struct e1000_adapter *adapter = hw->back;
  3448. pci_write_config_word(adapter->pdev, reg, *value);
  3449. }
  3450. uint32_t
  3451. e1000_io_read(struct e1000_hw *hw, unsigned long port)
  3452. {
  3453. return inl(port);
  3454. }
  3455. void
  3456. e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
  3457. {
  3458. outl(value, port);
  3459. }
  3460. static void
  3461. e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
  3462. {
  3463. struct e1000_adapter *adapter = netdev_priv(netdev);
  3464. uint32_t ctrl, rctl;
  3465. e1000_irq_disable(adapter);
  3466. adapter->vlgrp = grp;
  3467. if(grp) {
  3468. /* enable VLAN tag insert/strip */
  3469. ctrl = E1000_READ_REG(&adapter->hw, CTRL);
  3470. ctrl |= E1000_CTRL_VME;
  3471. E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
  3472. /* enable VLAN receive filtering */
  3473. rctl = E1000_READ_REG(&adapter->hw, RCTL);
  3474. rctl |= E1000_RCTL_VFE;
  3475. rctl &= ~E1000_RCTL_CFIEN;
  3476. E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
  3477. e1000_update_mng_vlan(adapter);
  3478. } else {
  3479. /* disable VLAN tag insert/strip */
  3480. ctrl = E1000_READ_REG(&adapter->hw, CTRL);
  3481. ctrl &= ~E1000_CTRL_VME;
  3482. E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
  3483. /* disable VLAN filtering */
  3484. rctl = E1000_READ_REG(&adapter->hw, RCTL);
  3485. rctl &= ~E1000_RCTL_VFE;
  3486. E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
  3487. if(adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) {
  3488. e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
  3489. adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
  3490. }
  3491. }
  3492. e1000_irq_enable(adapter);
  3493. }
  3494. static void
  3495. e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
  3496. {
  3497. struct e1000_adapter *adapter = netdev_priv(netdev);
  3498. uint32_t vfta, index;
  3499. if((adapter->hw.mng_cookie.status &
  3500. E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
  3501. (vid == adapter->mng_vlan_id))
  3502. return;
  3503. /* add VID to filter table */
  3504. index = (vid >> 5) & 0x7F;
  3505. vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
  3506. vfta |= (1 << (vid & 0x1F));
  3507. e1000_write_vfta(&adapter->hw, index, vfta);
  3508. }
  3509. static void
  3510. e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
  3511. {
  3512. struct e1000_adapter *adapter = netdev_priv(netdev);
  3513. uint32_t vfta, index;
  3514. e1000_irq_disable(adapter);
  3515. if(adapter->vlgrp)
  3516. adapter->vlgrp->vlan_devices[vid] = NULL;
  3517. e1000_irq_enable(adapter);
  3518. if((adapter->hw.mng_cookie.status &
  3519. E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
  3520. (vid == adapter->mng_vlan_id))
  3521. return;
  3522. /* remove VID from filter table */
  3523. index = (vid >> 5) & 0x7F;
  3524. vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
  3525. vfta &= ~(1 << (vid & 0x1F));
  3526. e1000_write_vfta(&adapter->hw, index, vfta);
  3527. }
  3528. static void
  3529. e1000_restore_vlan(struct e1000_adapter *adapter)
  3530. {
  3531. e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
  3532. if(adapter->vlgrp) {
  3533. uint16_t vid;
  3534. for(vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
  3535. if(!adapter->vlgrp->vlan_devices[vid])
  3536. continue;
  3537. e1000_vlan_rx_add_vid(adapter->netdev, vid);
  3538. }
  3539. }
  3540. }
  3541. int
  3542. e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
  3543. {
  3544. adapter->hw.autoneg = 0;
  3545. /* Fiber NICs only allow 1000 gbps Full duplex */
  3546. if((adapter->hw.media_type == e1000_media_type_fiber) &&
  3547. spddplx != (SPEED_1000 + DUPLEX_FULL)) {
  3548. DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
  3549. return -EINVAL;
  3550. }
  3551. switch(spddplx) {
  3552. case SPEED_10 + DUPLEX_HALF:
  3553. adapter->hw.forced_speed_duplex = e1000_10_half;
  3554. break;
  3555. case SPEED_10 + DUPLEX_FULL:
  3556. adapter->hw.forced_speed_duplex = e1000_10_full;
  3557. break;
  3558. case SPEED_100 + DUPLEX_HALF:
  3559. adapter->hw.forced_speed_duplex = e1000_100_half;
  3560. break;
  3561. case SPEED_100 + DUPLEX_FULL:
  3562. adapter->hw.forced_speed_duplex = e1000_100_full;
  3563. break;
  3564. case SPEED_1000 + DUPLEX_FULL:
  3565. adapter->hw.autoneg = 1;
  3566. adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
  3567. break;
  3568. case SPEED_1000 + DUPLEX_HALF: /* not supported */
  3569. default:
  3570. DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
  3571. return -EINVAL;
  3572. }
  3573. return 0;
  3574. }
  3575. static int
  3576. e1000_suspend(struct pci_dev *pdev, pm_message_t state)
  3577. {
  3578. struct net_device *netdev = pci_get_drvdata(pdev);
  3579. struct e1000_adapter *adapter = netdev_priv(netdev);
  3580. uint32_t ctrl, ctrl_ext, rctl, manc, status, swsm;
  3581. uint32_t wufc = adapter->wol;
  3582. netif_device_detach(netdev);
  3583. if(netif_running(netdev))
  3584. e1000_down(adapter);
  3585. status = E1000_READ_REG(&adapter->hw, STATUS);
  3586. if(status & E1000_STATUS_LU)
  3587. wufc &= ~E1000_WUFC_LNKC;
  3588. if(wufc) {
  3589. e1000_setup_rctl(adapter);
  3590. e1000_set_multi(netdev);
  3591. /* turn on all-multi mode if wake on multicast is enabled */
  3592. if(adapter->wol & E1000_WUFC_MC) {
  3593. rctl = E1000_READ_REG(&adapter->hw, RCTL);
  3594. rctl |= E1000_RCTL_MPE;
  3595. E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
  3596. }
  3597. if(adapter->hw.mac_type >= e1000_82540) {
  3598. ctrl = E1000_READ_REG(&adapter->hw, CTRL);
  3599. /* advertise wake from D3Cold */
  3600. #define E1000_CTRL_ADVD3WUC 0x00100000
  3601. /* phy power management enable */
  3602. #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
  3603. ctrl |= E1000_CTRL_ADVD3WUC |
  3604. E1000_CTRL_EN_PHY_PWR_MGMT;
  3605. E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
  3606. }
  3607. if(adapter->hw.media_type == e1000_media_type_fiber ||
  3608. adapter->hw.media_type == e1000_media_type_internal_serdes) {
  3609. /* keep the laser running in D3 */
  3610. ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
  3611. ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
  3612. E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
  3613. }
  3614. /* Allow time for pending master requests to run */
  3615. e1000_disable_pciex_master(&adapter->hw);
  3616. E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
  3617. E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
  3618. pci_enable_wake(pdev, 3, 1);
  3619. pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */
  3620. } else {
  3621. E1000_WRITE_REG(&adapter->hw, WUC, 0);
  3622. E1000_WRITE_REG(&adapter->hw, WUFC, 0);
  3623. pci_enable_wake(pdev, 3, 0);
  3624. pci_enable_wake(pdev, 4, 0); /* 4 == D3 cold */
  3625. }
  3626. pci_save_state(pdev);
  3627. if(adapter->hw.mac_type >= e1000_82540 &&
  3628. adapter->hw.media_type == e1000_media_type_copper) {
  3629. manc = E1000_READ_REG(&adapter->hw, MANC);
  3630. if(manc & E1000_MANC_SMBUS_EN) {
  3631. manc |= E1000_MANC_ARP_EN;
  3632. E1000_WRITE_REG(&adapter->hw, MANC, manc);
  3633. pci_enable_wake(pdev, 3, 1);
  3634. pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */
  3635. }
  3636. }
  3637. switch(adapter->hw.mac_type) {
  3638. case e1000_82571:
  3639. case e1000_82572:
  3640. ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
  3641. E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
  3642. ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
  3643. break;
  3644. case e1000_82573:
  3645. swsm = E1000_READ_REG(&adapter->hw, SWSM);
  3646. E1000_WRITE_REG(&adapter->hw, SWSM,
  3647. swsm & ~E1000_SWSM_DRV_LOAD);
  3648. break;
  3649. default:
  3650. break;
  3651. }
  3652. pci_disable_device(pdev);
  3653. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  3654. return 0;
  3655. }
  3656. #ifdef CONFIG_PM
  3657. static int
  3658. e1000_resume(struct pci_dev *pdev)
  3659. {
  3660. struct net_device *netdev = pci_get_drvdata(pdev);
  3661. struct e1000_adapter *adapter = netdev_priv(netdev);
  3662. uint32_t manc, ret_val, swsm;
  3663. uint32_t ctrl_ext;
  3664. pci_set_power_state(pdev, PCI_D0);
  3665. pci_restore_state(pdev);
  3666. ret_val = pci_enable_device(pdev);
  3667. pci_set_master(pdev);
  3668. pci_enable_wake(pdev, PCI_D3hot, 0);
  3669. pci_enable_wake(pdev, PCI_D3cold, 0);
  3670. e1000_reset(adapter);
  3671. E1000_WRITE_REG(&adapter->hw, WUS, ~0);
  3672. if(netif_running(netdev))
  3673. e1000_up(adapter);
  3674. netif_device_attach(netdev);
  3675. if(adapter->hw.mac_type >= e1000_82540 &&
  3676. adapter->hw.media_type == e1000_media_type_copper) {
  3677. manc = E1000_READ_REG(&adapter->hw, MANC);
  3678. manc &= ~(E1000_MANC_ARP_EN);
  3679. E1000_WRITE_REG(&adapter->hw, MANC, manc);
  3680. }
  3681. switch(adapter->hw.mac_type) {
  3682. case e1000_82571:
  3683. case e1000_82572:
  3684. ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
  3685. E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
  3686. ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
  3687. break;
  3688. case e1000_82573:
  3689. swsm = E1000_READ_REG(&adapter->hw, SWSM);
  3690. E1000_WRITE_REG(&adapter->hw, SWSM,
  3691. swsm | E1000_SWSM_DRV_LOAD);
  3692. break;
  3693. default:
  3694. break;
  3695. }
  3696. return 0;
  3697. }
  3698. #endif
  3699. #ifdef CONFIG_NET_POLL_CONTROLLER
  3700. /*
  3701. * Polling 'interrupt' - used by things like netconsole to send skbs
  3702. * without having to re-enable interrupts. It's not called while
  3703. * the interrupt routine is executing.
  3704. */
  3705. static void
  3706. e1000_netpoll(struct net_device *netdev)
  3707. {
  3708. struct e1000_adapter *adapter = netdev_priv(netdev);
  3709. disable_irq(adapter->pdev->irq);
  3710. e1000_intr(adapter->pdev->irq, netdev, NULL);
  3711. e1000_clean_tx_irq(adapter);
  3712. enable_irq(adapter->pdev->irq);
  3713. }
  3714. #endif
  3715. /* e1000_main.c */