ath79_wdt.c 7.3 KB

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  1. /*
  2. * Atheros AR71XX/AR724X/AR913X built-in hardware watchdog timer.
  3. *
  4. * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  5. * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  6. *
  7. * This driver was based on: drivers/watchdog/ixp4xx_wdt.c
  8. * Author: Deepak Saxena <dsaxena@plexity.net>
  9. * Copyright 2004 (c) MontaVista, Software, Inc.
  10. *
  11. * which again was based on sa1100 driver,
  12. * Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
  13. *
  14. * This program is free software; you can redistribute it and/or modify it
  15. * under the terms of the GNU General Public License version 2 as published
  16. * by the Free Software Foundation.
  17. *
  18. */
  19. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  20. #include <linux/bitops.h>
  21. #include <linux/errno.h>
  22. #include <linux/fs.h>
  23. #include <linux/init.h>
  24. #include <linux/io.h>
  25. #include <linux/kernel.h>
  26. #include <linux/miscdevice.h>
  27. #include <linux/module.h>
  28. #include <linux/moduleparam.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/types.h>
  31. #include <linux/watchdog.h>
  32. #include <linux/clk.h>
  33. #include <linux/err.h>
  34. #include <linux/of.h>
  35. #include <linux/of_platform.h>
  36. #define DRIVER_NAME "ath79-wdt"
  37. #define WDT_TIMEOUT 15 /* seconds */
  38. #define WDOG_REG_CTRL 0x00
  39. #define WDOG_REG_TIMER 0x04
  40. #define WDOG_CTRL_LAST_RESET BIT(31)
  41. #define WDOG_CTRL_ACTION_MASK 3
  42. #define WDOG_CTRL_ACTION_NONE 0 /* no action */
  43. #define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */
  44. #define WDOG_CTRL_ACTION_NMI 2 /* NMI */
  45. #define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
  46. static bool nowayout = WATCHDOG_NOWAYOUT;
  47. module_param(nowayout, bool, 0);
  48. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
  49. "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  50. static int timeout = WDT_TIMEOUT;
  51. module_param(timeout, int, 0);
  52. MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds "
  53. "(default=" __MODULE_STRING(WDT_TIMEOUT) "s)");
  54. static unsigned long wdt_flags;
  55. #define WDT_FLAGS_BUSY 0
  56. #define WDT_FLAGS_EXPECT_CLOSE 1
  57. static struct clk *wdt_clk;
  58. static unsigned long wdt_freq;
  59. static int boot_status;
  60. static int max_timeout;
  61. static void __iomem *wdt_base;
  62. static inline void ath79_wdt_wr(unsigned reg, u32 val)
  63. {
  64. iowrite32(val, wdt_base + reg);
  65. }
  66. static inline u32 ath79_wdt_rr(unsigned reg)
  67. {
  68. return ioread32(wdt_base + reg);
  69. }
  70. static inline void ath79_wdt_keepalive(void)
  71. {
  72. ath79_wdt_wr(WDOG_REG_TIMER, wdt_freq * timeout);
  73. /* flush write */
  74. ath79_wdt_rr(WDOG_REG_TIMER);
  75. }
  76. static inline void ath79_wdt_enable(void)
  77. {
  78. ath79_wdt_keepalive();
  79. ath79_wdt_wr(WDOG_REG_CTRL, WDOG_CTRL_ACTION_FCR);
  80. /* flush write */
  81. ath79_wdt_rr(WDOG_REG_CTRL);
  82. }
  83. static inline void ath79_wdt_disable(void)
  84. {
  85. ath79_wdt_wr(WDOG_REG_CTRL, WDOG_CTRL_ACTION_NONE);
  86. /* flush write */
  87. ath79_wdt_rr(WDOG_REG_CTRL);
  88. }
  89. static int ath79_wdt_set_timeout(int val)
  90. {
  91. if (val < 1 || val > max_timeout)
  92. return -EINVAL;
  93. timeout = val;
  94. ath79_wdt_keepalive();
  95. return 0;
  96. }
  97. static int ath79_wdt_open(struct inode *inode, struct file *file)
  98. {
  99. if (test_and_set_bit(WDT_FLAGS_BUSY, &wdt_flags))
  100. return -EBUSY;
  101. clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags);
  102. ath79_wdt_enable();
  103. return nonseekable_open(inode, file);
  104. }
  105. static int ath79_wdt_release(struct inode *inode, struct file *file)
  106. {
  107. if (test_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags))
  108. ath79_wdt_disable();
  109. else {
  110. pr_crit("device closed unexpectedly, watchdog timer will not stop!\n");
  111. ath79_wdt_keepalive();
  112. }
  113. clear_bit(WDT_FLAGS_BUSY, &wdt_flags);
  114. clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags);
  115. return 0;
  116. }
  117. static ssize_t ath79_wdt_write(struct file *file, const char *data,
  118. size_t len, loff_t *ppos)
  119. {
  120. if (len) {
  121. if (!nowayout) {
  122. size_t i;
  123. clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags);
  124. for (i = 0; i != len; i++) {
  125. char c;
  126. if (get_user(c, data + i))
  127. return -EFAULT;
  128. if (c == 'V')
  129. set_bit(WDT_FLAGS_EXPECT_CLOSE,
  130. &wdt_flags);
  131. }
  132. }
  133. ath79_wdt_keepalive();
  134. }
  135. return len;
  136. }
  137. static const struct watchdog_info ath79_wdt_info = {
  138. .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
  139. WDIOF_MAGICCLOSE | WDIOF_CARDRESET,
  140. .firmware_version = 0,
  141. .identity = "ATH79 watchdog",
  142. };
  143. static long ath79_wdt_ioctl(struct file *file, unsigned int cmd,
  144. unsigned long arg)
  145. {
  146. void __user *argp = (void __user *)arg;
  147. int __user *p = argp;
  148. int err;
  149. int t;
  150. switch (cmd) {
  151. case WDIOC_GETSUPPORT:
  152. err = copy_to_user(argp, &ath79_wdt_info,
  153. sizeof(ath79_wdt_info)) ? -EFAULT : 0;
  154. break;
  155. case WDIOC_GETSTATUS:
  156. err = put_user(0, p);
  157. break;
  158. case WDIOC_GETBOOTSTATUS:
  159. err = put_user(boot_status, p);
  160. break;
  161. case WDIOC_KEEPALIVE:
  162. ath79_wdt_keepalive();
  163. err = 0;
  164. break;
  165. case WDIOC_SETTIMEOUT:
  166. err = get_user(t, p);
  167. if (err)
  168. break;
  169. err = ath79_wdt_set_timeout(t);
  170. if (err)
  171. break;
  172. /* fallthrough */
  173. case WDIOC_GETTIMEOUT:
  174. err = put_user(timeout, p);
  175. break;
  176. default:
  177. err = -ENOTTY;
  178. break;
  179. }
  180. return err;
  181. }
  182. static const struct file_operations ath79_wdt_fops = {
  183. .owner = THIS_MODULE,
  184. .llseek = no_llseek,
  185. .write = ath79_wdt_write,
  186. .unlocked_ioctl = ath79_wdt_ioctl,
  187. .open = ath79_wdt_open,
  188. .release = ath79_wdt_release,
  189. };
  190. static struct miscdevice ath79_wdt_miscdev = {
  191. .minor = WATCHDOG_MINOR,
  192. .name = "watchdog",
  193. .fops = &ath79_wdt_fops,
  194. };
  195. static int ath79_wdt_probe(struct platform_device *pdev)
  196. {
  197. struct resource *res;
  198. u32 ctrl;
  199. int err;
  200. if (wdt_base)
  201. return -EBUSY;
  202. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  203. if (!res) {
  204. dev_err(&pdev->dev, "no memory resource found\n");
  205. return -EINVAL;
  206. }
  207. wdt_base = devm_request_and_ioremap(&pdev->dev, res);
  208. if (!wdt_base) {
  209. dev_err(&pdev->dev, "unable to remap memory region\n");
  210. return -ENOMEM;
  211. }
  212. wdt_clk = devm_clk_get(&pdev->dev, "wdt");
  213. if (IS_ERR(wdt_clk))
  214. return PTR_ERR(wdt_clk);
  215. err = clk_enable(wdt_clk);
  216. if (err)
  217. return err;
  218. wdt_freq = clk_get_rate(wdt_clk);
  219. if (!wdt_freq) {
  220. err = -EINVAL;
  221. goto err_clk_disable;
  222. }
  223. max_timeout = (0xfffffffful / wdt_freq);
  224. if (timeout < 1 || timeout > max_timeout) {
  225. timeout = max_timeout;
  226. dev_info(&pdev->dev,
  227. "timeout value must be 0 < timeout < %d, using %d\n",
  228. max_timeout, timeout);
  229. }
  230. ctrl = ath79_wdt_rr(WDOG_REG_CTRL);
  231. boot_status = (ctrl & WDOG_CTRL_LAST_RESET) ? WDIOF_CARDRESET : 0;
  232. err = misc_register(&ath79_wdt_miscdev);
  233. if (err) {
  234. dev_err(&pdev->dev,
  235. "unable to register misc device, err=%d\n", err);
  236. goto err_clk_disable;
  237. }
  238. return 0;
  239. err_clk_disable:
  240. clk_disable(wdt_clk);
  241. return err;
  242. }
  243. static int ath79_wdt_remove(struct platform_device *pdev)
  244. {
  245. misc_deregister(&ath79_wdt_miscdev);
  246. clk_disable(wdt_clk);
  247. return 0;
  248. }
  249. static void ath97_wdt_shutdown(struct platform_device *pdev)
  250. {
  251. ath79_wdt_disable();
  252. }
  253. #ifdef CONFIG_OF
  254. static const struct of_device_id ath79_wdt_match[] = {
  255. { .compatible = "qca,ar7130-wdt" },
  256. {},
  257. };
  258. MODULE_DEVICE_TABLE(of, ath79_wdt_match);
  259. #endif
  260. static struct platform_driver ath79_wdt_driver = {
  261. .probe = ath79_wdt_probe,
  262. .remove = ath79_wdt_remove,
  263. .shutdown = ath97_wdt_shutdown,
  264. .driver = {
  265. .name = DRIVER_NAME,
  266. .owner = THIS_MODULE,
  267. .of_match_table = of_match_ptr(ath79_wdt_match),
  268. },
  269. };
  270. module_platform_driver(ath79_wdt_driver);
  271. MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X hardware watchdog driver");
  272. MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org");
  273. MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org");
  274. MODULE_LICENSE("GPL v2");
  275. MODULE_ALIAS("platform:" DRIVER_NAME);
  276. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);