sis_main.c 184 KB

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  1. /*
  2. * SiS 300/540/630[S]/730[S],
  3. * SiS 315[E|PRO]/550/[M]65x/[M]66x[F|M|G]X/[M]74x[GX]/330/[M]76x[GX],
  4. * XGI V3XT/V5/V8, Z7
  5. * frame buffer driver for Linux kernels >= 2.4.14 and >=2.6.3
  6. *
  7. * Copyright (C) 2001-2005 Thomas Winischhofer, Vienna, Austria.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the named License,
  12. * or any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
  22. *
  23. * Author: Thomas Winischhofer <thomas@winischhofer.net>
  24. *
  25. * Author of (practically wiped) code base:
  26. * SiS (www.sis.com)
  27. * Copyright (C) 1999 Silicon Integrated Systems, Inc.
  28. *
  29. * See http://www.winischhofer.net/ for more information and updates
  30. *
  31. * Originally based on the VBE 2.0 compliant graphic boards framebuffer driver,
  32. * which is (c) 1998 Gerd Knorr <kraxel@goldbach.in-berlin.de>
  33. *
  34. */
  35. #include <linux/module.h>
  36. #include <linux/moduleparam.h>
  37. #include <linux/kernel.h>
  38. #include <linux/spinlock.h>
  39. #include <linux/errno.h>
  40. #include <linux/string.h>
  41. #include <linux/mm.h>
  42. #include <linux/screen_info.h>
  43. #include <linux/slab.h>
  44. #include <linux/fb.h>
  45. #include <linux/selection.h>
  46. #include <linux/ioport.h>
  47. #include <linux/init.h>
  48. #include <linux/pci.h>
  49. #include <linux/vmalloc.h>
  50. #include <linux/capability.h>
  51. #include <linux/fs.h>
  52. #include <linux/types.h>
  53. #include <linux/uaccess.h>
  54. #include <asm/io.h>
  55. #ifdef CONFIG_MTRR
  56. #include <asm/mtrr.h>
  57. #endif
  58. #include "sis.h"
  59. #include "sis_main.h"
  60. #if !defined(CONFIG_FB_SIS_300) && !defined(CONFIG_FB_SIS_315)
  61. #warning Neither CONFIG_FB_SIS_300 nor CONFIG_FB_SIS_315 is set
  62. #warning sisfb will not work!
  63. #endif
  64. static void sisfb_handle_command(struct sis_video_info *ivideo,
  65. struct sisfb_cmd *sisfb_command);
  66. /* ------------------ Internal helper routines ----------------- */
  67. static void __init
  68. sisfb_setdefaultparms(void)
  69. {
  70. sisfb_off = 0;
  71. sisfb_parm_mem = 0;
  72. sisfb_accel = -1;
  73. sisfb_ypan = -1;
  74. sisfb_max = -1;
  75. sisfb_userom = -1;
  76. sisfb_useoem = -1;
  77. sisfb_mode_idx = -1;
  78. sisfb_parm_rate = -1;
  79. sisfb_crt1off = 0;
  80. sisfb_forcecrt1 = -1;
  81. sisfb_crt2type = -1;
  82. sisfb_crt2flags = 0;
  83. sisfb_pdc = 0xff;
  84. sisfb_pdca = 0xff;
  85. sisfb_scalelcd = -1;
  86. sisfb_specialtiming = CUT_NONE;
  87. sisfb_lvdshl = -1;
  88. sisfb_dstn = 0;
  89. sisfb_fstn = 0;
  90. sisfb_tvplug = -1;
  91. sisfb_tvstd = -1;
  92. sisfb_tvxposoffset = 0;
  93. sisfb_tvyposoffset = 0;
  94. sisfb_nocrt2rate = 0;
  95. #if !defined(__i386__) && !defined(__x86_64__)
  96. sisfb_resetcard = 0;
  97. sisfb_videoram = 0;
  98. #endif
  99. }
  100. /* ------------- Parameter parsing -------------- */
  101. static void sisfb_search_vesamode(unsigned int vesamode, bool quiet)
  102. {
  103. int i = 0, j = 0;
  104. /* We don't know the hardware specs yet and there is no ivideo */
  105. if(vesamode == 0) {
  106. if(!quiet)
  107. printk(KERN_ERR "sisfb: Invalid mode. Using default.\n");
  108. sisfb_mode_idx = DEFAULT_MODE;
  109. return;
  110. }
  111. vesamode &= 0x1dff; /* Clean VESA mode number from other flags */
  112. while(sisbios_mode[i++].mode_no[0] != 0) {
  113. if( (sisbios_mode[i-1].vesa_mode_no_1 == vesamode) ||
  114. (sisbios_mode[i-1].vesa_mode_no_2 == vesamode) ) {
  115. if(sisfb_fstn) {
  116. if(sisbios_mode[i-1].mode_no[1] == 0x50 ||
  117. sisbios_mode[i-1].mode_no[1] == 0x56 ||
  118. sisbios_mode[i-1].mode_no[1] == 0x53)
  119. continue;
  120. } else {
  121. if(sisbios_mode[i-1].mode_no[1] == 0x5a ||
  122. sisbios_mode[i-1].mode_no[1] == 0x5b)
  123. continue;
  124. }
  125. sisfb_mode_idx = i - 1;
  126. j = 1;
  127. break;
  128. }
  129. }
  130. if((!j) && !quiet)
  131. printk(KERN_ERR "sisfb: Invalid VESA mode 0x%x'\n", vesamode);
  132. }
  133. static void sisfb_search_mode(char *name, bool quiet)
  134. {
  135. unsigned int j = 0, xres = 0, yres = 0, depth = 0, rate = 0;
  136. int i = 0;
  137. char strbuf[16], strbuf1[20];
  138. char *nameptr = name;
  139. /* We don't know the hardware specs yet and there is no ivideo */
  140. if(name == NULL) {
  141. if(!quiet)
  142. printk(KERN_ERR "sisfb: Internal error, using default mode.\n");
  143. sisfb_mode_idx = DEFAULT_MODE;
  144. return;
  145. }
  146. if(!strnicmp(name, sisbios_mode[MODE_INDEX_NONE].name, strlen(name))) {
  147. if(!quiet)
  148. printk(KERN_ERR "sisfb: Mode 'none' not supported anymore. Using default.\n");
  149. sisfb_mode_idx = DEFAULT_MODE;
  150. return;
  151. }
  152. if(strlen(name) <= 19) {
  153. strcpy(strbuf1, name);
  154. for(i = 0; i < strlen(strbuf1); i++) {
  155. if(strbuf1[i] < '0' || strbuf1[i] > '9') strbuf1[i] = ' ';
  156. }
  157. /* This does some fuzzy mode naming detection */
  158. if(sscanf(strbuf1, "%u %u %u %u", &xres, &yres, &depth, &rate) == 4) {
  159. if((rate <= 32) || (depth > 32)) {
  160. j = rate; rate = depth; depth = j;
  161. }
  162. sprintf(strbuf, "%ux%ux%u", xres, yres, depth);
  163. nameptr = strbuf;
  164. sisfb_parm_rate = rate;
  165. } else if(sscanf(strbuf1, "%u %u %u", &xres, &yres, &depth) == 3) {
  166. sprintf(strbuf, "%ux%ux%u", xres, yres, depth);
  167. nameptr = strbuf;
  168. } else {
  169. xres = 0;
  170. if((sscanf(strbuf1, "%u %u", &xres, &yres) == 2) && (xres != 0)) {
  171. sprintf(strbuf, "%ux%ux8", xres, yres);
  172. nameptr = strbuf;
  173. } else {
  174. sisfb_search_vesamode(simple_strtoul(name, NULL, 0), quiet);
  175. return;
  176. }
  177. }
  178. }
  179. i = 0; j = 0;
  180. while(sisbios_mode[i].mode_no[0] != 0) {
  181. if(!strnicmp(nameptr, sisbios_mode[i++].name, strlen(nameptr))) {
  182. if(sisfb_fstn) {
  183. if(sisbios_mode[i-1].mode_no[1] == 0x50 ||
  184. sisbios_mode[i-1].mode_no[1] == 0x56 ||
  185. sisbios_mode[i-1].mode_no[1] == 0x53)
  186. continue;
  187. } else {
  188. if(sisbios_mode[i-1].mode_no[1] == 0x5a ||
  189. sisbios_mode[i-1].mode_no[1] == 0x5b)
  190. continue;
  191. }
  192. sisfb_mode_idx = i - 1;
  193. j = 1;
  194. break;
  195. }
  196. }
  197. if((!j) && !quiet)
  198. printk(KERN_ERR "sisfb: Invalid mode '%s'\n", nameptr);
  199. }
  200. #ifndef MODULE
  201. static void sisfb_get_vga_mode_from_kernel(void)
  202. {
  203. #ifdef CONFIG_X86
  204. char mymode[32];
  205. int mydepth = screen_info.lfb_depth;
  206. if(screen_info.orig_video_isVGA != VIDEO_TYPE_VLFB) return;
  207. if( (screen_info.lfb_width >= 320) && (screen_info.lfb_width <= 2048) &&
  208. (screen_info.lfb_height >= 200) && (screen_info.lfb_height <= 1536) &&
  209. (mydepth >= 8) && (mydepth <= 32) ) {
  210. if(mydepth == 24) mydepth = 32;
  211. sprintf(mymode, "%ux%ux%u", screen_info.lfb_width,
  212. screen_info.lfb_height,
  213. mydepth);
  214. printk(KERN_DEBUG
  215. "sisfb: Using vga mode %s pre-set by kernel as default\n",
  216. mymode);
  217. sisfb_search_mode(mymode, true);
  218. }
  219. #endif
  220. return;
  221. }
  222. #endif
  223. static void __init
  224. sisfb_search_crt2type(const char *name)
  225. {
  226. int i = 0;
  227. /* We don't know the hardware specs yet and there is no ivideo */
  228. if(name == NULL) return;
  229. while(sis_crt2type[i].type_no != -1) {
  230. if(!strnicmp(name, sis_crt2type[i].name, strlen(sis_crt2type[i].name))) {
  231. sisfb_crt2type = sis_crt2type[i].type_no;
  232. sisfb_tvplug = sis_crt2type[i].tvplug_no;
  233. sisfb_crt2flags = sis_crt2type[i].flags;
  234. break;
  235. }
  236. i++;
  237. }
  238. sisfb_dstn = (sisfb_crt2flags & FL_550_DSTN) ? 1 : 0;
  239. sisfb_fstn = (sisfb_crt2flags & FL_550_FSTN) ? 1 : 0;
  240. if(sisfb_crt2type < 0)
  241. printk(KERN_ERR "sisfb: Invalid CRT2 type: %s\n", name);
  242. }
  243. static void __init
  244. sisfb_search_tvstd(const char *name)
  245. {
  246. int i = 0;
  247. /* We don't know the hardware specs yet and there is no ivideo */
  248. if(name == NULL)
  249. return;
  250. while(sis_tvtype[i].type_no != -1) {
  251. if(!strnicmp(name, sis_tvtype[i].name, strlen(sis_tvtype[i].name))) {
  252. sisfb_tvstd = sis_tvtype[i].type_no;
  253. break;
  254. }
  255. i++;
  256. }
  257. }
  258. static void __init
  259. sisfb_search_specialtiming(const char *name)
  260. {
  261. int i = 0;
  262. bool found = false;
  263. /* We don't know the hardware specs yet and there is no ivideo */
  264. if(name == NULL)
  265. return;
  266. if(!strnicmp(name, "none", 4)) {
  267. sisfb_specialtiming = CUT_FORCENONE;
  268. printk(KERN_DEBUG "sisfb: Special timing disabled\n");
  269. } else {
  270. while(mycustomttable[i].chipID != 0) {
  271. if(!strnicmp(name,mycustomttable[i].optionName,
  272. strlen(mycustomttable[i].optionName))) {
  273. sisfb_specialtiming = mycustomttable[i].SpecialID;
  274. found = true;
  275. printk(KERN_INFO "sisfb: Special timing for %s %s forced (\"%s\")\n",
  276. mycustomttable[i].vendorName,
  277. mycustomttable[i].cardName,
  278. mycustomttable[i].optionName);
  279. break;
  280. }
  281. i++;
  282. }
  283. if(!found) {
  284. printk(KERN_WARNING "sisfb: Invalid SpecialTiming parameter, valid are:");
  285. printk(KERN_WARNING "\t\"none\" (to disable special timings)\n");
  286. i = 0;
  287. while(mycustomttable[i].chipID != 0) {
  288. printk(KERN_WARNING "\t\"%s\" (for %s %s)\n",
  289. mycustomttable[i].optionName,
  290. mycustomttable[i].vendorName,
  291. mycustomttable[i].cardName);
  292. i++;
  293. }
  294. }
  295. }
  296. }
  297. /* ----------- Various detection routines ----------- */
  298. static void sisfb_detect_custom_timing(struct sis_video_info *ivideo)
  299. {
  300. unsigned char *biosver = NULL;
  301. unsigned char *biosdate = NULL;
  302. bool footprint;
  303. u32 chksum = 0;
  304. int i, j;
  305. if(ivideo->SiS_Pr.UseROM) {
  306. biosver = ivideo->SiS_Pr.VirtualRomBase + 0x06;
  307. biosdate = ivideo->SiS_Pr.VirtualRomBase + 0x2c;
  308. for(i = 0; i < 32768; i++)
  309. chksum += ivideo->SiS_Pr.VirtualRomBase[i];
  310. }
  311. i = 0;
  312. do {
  313. if( (mycustomttable[i].chipID == ivideo->chip) &&
  314. ((!strlen(mycustomttable[i].biosversion)) ||
  315. (ivideo->SiS_Pr.UseROM &&
  316. (!strncmp(mycustomttable[i].biosversion, biosver,
  317. strlen(mycustomttable[i].biosversion))))) &&
  318. ((!strlen(mycustomttable[i].biosdate)) ||
  319. (ivideo->SiS_Pr.UseROM &&
  320. (!strncmp(mycustomttable[i].biosdate, biosdate,
  321. strlen(mycustomttable[i].biosdate))))) &&
  322. ((!mycustomttable[i].bioschksum) ||
  323. (ivideo->SiS_Pr.UseROM &&
  324. (mycustomttable[i].bioschksum == chksum))) &&
  325. (mycustomttable[i].pcisubsysvendor == ivideo->subsysvendor) &&
  326. (mycustomttable[i].pcisubsyscard == ivideo->subsysdevice) ) {
  327. footprint = true;
  328. for(j = 0; j < 5; j++) {
  329. if(mycustomttable[i].biosFootprintAddr[j]) {
  330. if(ivideo->SiS_Pr.UseROM) {
  331. if(ivideo->SiS_Pr.VirtualRomBase[mycustomttable[i].biosFootprintAddr[j]] !=
  332. mycustomttable[i].biosFootprintData[j]) {
  333. footprint = false;
  334. }
  335. } else
  336. footprint = false;
  337. }
  338. }
  339. if(footprint) {
  340. ivideo->SiS_Pr.SiS_CustomT = mycustomttable[i].SpecialID;
  341. printk(KERN_DEBUG "sisfb: Identified [%s %s], special timing applies\n",
  342. mycustomttable[i].vendorName,
  343. mycustomttable[i].cardName);
  344. printk(KERN_DEBUG "sisfb: [specialtiming parameter name: %s]\n",
  345. mycustomttable[i].optionName);
  346. break;
  347. }
  348. }
  349. i++;
  350. } while(mycustomttable[i].chipID);
  351. }
  352. static bool sisfb_interpret_edid(struct sisfb_monitor *monitor, u8 *buffer)
  353. {
  354. int i, j, xres, yres, refresh, index;
  355. u32 emodes;
  356. if(buffer[0] != 0x00 || buffer[1] != 0xff ||
  357. buffer[2] != 0xff || buffer[3] != 0xff ||
  358. buffer[4] != 0xff || buffer[5] != 0xff ||
  359. buffer[6] != 0xff || buffer[7] != 0x00) {
  360. printk(KERN_DEBUG "sisfb: Bad EDID header\n");
  361. return false;
  362. }
  363. if(buffer[0x12] != 0x01) {
  364. printk(KERN_INFO "sisfb: EDID version %d not supported\n",
  365. buffer[0x12]);
  366. return false;
  367. }
  368. monitor->feature = buffer[0x18];
  369. if(!(buffer[0x14] & 0x80)) {
  370. if(!(buffer[0x14] & 0x08)) {
  371. printk(KERN_INFO
  372. "sisfb: WARNING: Monitor does not support separate syncs\n");
  373. }
  374. }
  375. if(buffer[0x13] >= 0x01) {
  376. /* EDID V1 rev 1 and 2: Search for monitor descriptor
  377. * to extract ranges
  378. */
  379. j = 0x36;
  380. for(i=0; i<4; i++) {
  381. if(buffer[j] == 0x00 && buffer[j + 1] == 0x00 &&
  382. buffer[j + 2] == 0x00 && buffer[j + 3] == 0xfd &&
  383. buffer[j + 4] == 0x00) {
  384. monitor->hmin = buffer[j + 7];
  385. monitor->hmax = buffer[j + 8];
  386. monitor->vmin = buffer[j + 5];
  387. monitor->vmax = buffer[j + 6];
  388. monitor->dclockmax = buffer[j + 9] * 10 * 1000;
  389. monitor->datavalid = true;
  390. break;
  391. }
  392. j += 18;
  393. }
  394. }
  395. if(!monitor->datavalid) {
  396. /* Otherwise: Get a range from the list of supported
  397. * Estabished Timings. This is not entirely accurate,
  398. * because fixed frequency monitors are not supported
  399. * that way.
  400. */
  401. monitor->hmin = 65535; monitor->hmax = 0;
  402. monitor->vmin = 65535; monitor->vmax = 0;
  403. monitor->dclockmax = 0;
  404. emodes = buffer[0x23] | (buffer[0x24] << 8) | (buffer[0x25] << 16);
  405. for(i = 0; i < 13; i++) {
  406. if(emodes & sisfb_ddcsmodes[i].mask) {
  407. if(monitor->hmin > sisfb_ddcsmodes[i].h) monitor->hmin = sisfb_ddcsmodes[i].h;
  408. if(monitor->hmax < sisfb_ddcsmodes[i].h) monitor->hmax = sisfb_ddcsmodes[i].h + 1;
  409. if(monitor->vmin > sisfb_ddcsmodes[i].v) monitor->vmin = sisfb_ddcsmodes[i].v;
  410. if(monitor->vmax < sisfb_ddcsmodes[i].v) monitor->vmax = sisfb_ddcsmodes[i].v;
  411. if(monitor->dclockmax < sisfb_ddcsmodes[i].d) monitor->dclockmax = sisfb_ddcsmodes[i].d;
  412. }
  413. }
  414. index = 0x26;
  415. for(i = 0; i < 8; i++) {
  416. xres = (buffer[index] + 31) * 8;
  417. switch(buffer[index + 1] & 0xc0) {
  418. case 0xc0: yres = (xres * 9) / 16; break;
  419. case 0x80: yres = (xres * 4) / 5; break;
  420. case 0x40: yres = (xres * 3) / 4; break;
  421. default: yres = xres; break;
  422. }
  423. refresh = (buffer[index + 1] & 0x3f) + 60;
  424. if((xres >= 640) && (yres >= 480)) {
  425. for(j = 0; j < 8; j++) {
  426. if((xres == sisfb_ddcfmodes[j].x) &&
  427. (yres == sisfb_ddcfmodes[j].y) &&
  428. (refresh == sisfb_ddcfmodes[j].v)) {
  429. if(monitor->hmin > sisfb_ddcfmodes[j].h) monitor->hmin = sisfb_ddcfmodes[j].h;
  430. if(monitor->hmax < sisfb_ddcfmodes[j].h) monitor->hmax = sisfb_ddcfmodes[j].h + 1;
  431. if(monitor->vmin > sisfb_ddcsmodes[j].v) monitor->vmin = sisfb_ddcsmodes[j].v;
  432. if(monitor->vmax < sisfb_ddcsmodes[j].v) monitor->vmax = sisfb_ddcsmodes[j].v;
  433. if(monitor->dclockmax < sisfb_ddcsmodes[j].d) monitor->dclockmax = sisfb_ddcsmodes[j].d;
  434. }
  435. }
  436. }
  437. index += 2;
  438. }
  439. if((monitor->hmin <= monitor->hmax) && (monitor->vmin <= monitor->vmax)) {
  440. monitor->datavalid = true;
  441. }
  442. }
  443. return monitor->datavalid;
  444. }
  445. static void sisfb_handle_ddc(struct sis_video_info *ivideo,
  446. struct sisfb_monitor *monitor, int crtno)
  447. {
  448. unsigned short temp, i, realcrtno = crtno;
  449. unsigned char buffer[256];
  450. monitor->datavalid = false;
  451. if(crtno) {
  452. if(ivideo->vbflags & CRT2_LCD) realcrtno = 1;
  453. else if(ivideo->vbflags & CRT2_VGA) realcrtno = 2;
  454. else return;
  455. }
  456. if((ivideo->sisfb_crt1off) && (!crtno))
  457. return;
  458. temp = SiS_HandleDDC(&ivideo->SiS_Pr, ivideo->vbflags, ivideo->sisvga_engine,
  459. realcrtno, 0, &buffer[0], ivideo->vbflags2);
  460. if((!temp) || (temp == 0xffff)) {
  461. printk(KERN_INFO "sisfb: CRT%d DDC probing failed\n", crtno + 1);
  462. return;
  463. } else {
  464. printk(KERN_INFO "sisfb: CRT%d DDC supported\n", crtno + 1);
  465. printk(KERN_INFO "sisfb: CRT%d DDC level: %s%s%s%s\n",
  466. crtno + 1,
  467. (temp & 0x1a) ? "" : "[none of the supported]",
  468. (temp & 0x02) ? "2 " : "",
  469. (temp & 0x08) ? "D&P" : "",
  470. (temp & 0x10) ? "FPDI-2" : "");
  471. if(temp & 0x02) {
  472. i = 3; /* Number of retrys */
  473. do {
  474. temp = SiS_HandleDDC(&ivideo->SiS_Pr, ivideo->vbflags, ivideo->sisvga_engine,
  475. realcrtno, 1, &buffer[0], ivideo->vbflags2);
  476. } while((temp) && i--);
  477. if(!temp) {
  478. if(sisfb_interpret_edid(monitor, &buffer[0])) {
  479. printk(KERN_INFO "sisfb: Monitor range H %d-%dKHz, V %d-%dHz, Max. dotclock %dMHz\n",
  480. monitor->hmin, monitor->hmax, monitor->vmin, monitor->vmax,
  481. monitor->dclockmax / 1000);
  482. } else {
  483. printk(KERN_INFO "sisfb: CRT%d DDC EDID corrupt\n", crtno + 1);
  484. }
  485. } else {
  486. printk(KERN_INFO "sisfb: CRT%d DDC reading failed\n", crtno + 1);
  487. }
  488. } else {
  489. printk(KERN_INFO "sisfb: VESA D&P and FPDI-2 not supported yet\n");
  490. }
  491. }
  492. }
  493. /* -------------- Mode validation --------------- */
  494. static bool
  495. sisfb_verify_rate(struct sis_video_info *ivideo, struct sisfb_monitor *monitor,
  496. int mode_idx, int rate_idx, int rate)
  497. {
  498. int htotal, vtotal;
  499. unsigned int dclock, hsync;
  500. if(!monitor->datavalid)
  501. return true;
  502. if(mode_idx < 0)
  503. return false;
  504. /* Skip for 320x200, 320x240, 640x400 */
  505. switch(sisbios_mode[mode_idx].mode_no[ivideo->mni]) {
  506. case 0x59:
  507. case 0x41:
  508. case 0x4f:
  509. case 0x50:
  510. case 0x56:
  511. case 0x53:
  512. case 0x2f:
  513. case 0x5d:
  514. case 0x5e:
  515. return true;
  516. #ifdef CONFIG_FB_SIS_315
  517. case 0x5a:
  518. case 0x5b:
  519. if(ivideo->sisvga_engine == SIS_315_VGA) return true;
  520. #endif
  521. }
  522. if(rate < (monitor->vmin - 1))
  523. return false;
  524. if(rate > (monitor->vmax + 1))
  525. return false;
  526. if(sisfb_gettotalfrommode(&ivideo->SiS_Pr,
  527. sisbios_mode[mode_idx].mode_no[ivideo->mni],
  528. &htotal, &vtotal, rate_idx)) {
  529. dclock = (htotal * vtotal * rate) / 1000;
  530. if(dclock > (monitor->dclockmax + 1000))
  531. return false;
  532. hsync = dclock / htotal;
  533. if(hsync < (monitor->hmin - 1))
  534. return false;
  535. if(hsync > (monitor->hmax + 1))
  536. return false;
  537. } else {
  538. return false;
  539. }
  540. return true;
  541. }
  542. static int
  543. sisfb_validate_mode(struct sis_video_info *ivideo, int myindex, u32 vbflags)
  544. {
  545. u16 xres=0, yres, myres;
  546. #ifdef CONFIG_FB_SIS_300
  547. if(ivideo->sisvga_engine == SIS_300_VGA) {
  548. if(!(sisbios_mode[myindex].chipset & MD_SIS300))
  549. return -1 ;
  550. }
  551. #endif
  552. #ifdef CONFIG_FB_SIS_315
  553. if(ivideo->sisvga_engine == SIS_315_VGA) {
  554. if(!(sisbios_mode[myindex].chipset & MD_SIS315))
  555. return -1;
  556. }
  557. #endif
  558. myres = sisbios_mode[myindex].yres;
  559. switch(vbflags & VB_DISPTYPE_DISP2) {
  560. case CRT2_LCD:
  561. xres = ivideo->lcdxres; yres = ivideo->lcdyres;
  562. if((ivideo->SiS_Pr.SiS_CustomT != CUT_PANEL848) &&
  563. (ivideo->SiS_Pr.SiS_CustomT != CUT_PANEL856)) {
  564. if(sisbios_mode[myindex].xres > xres)
  565. return -1;
  566. if(myres > yres)
  567. return -1;
  568. }
  569. if(ivideo->sisfb_fstn) {
  570. if(sisbios_mode[myindex].xres == 320) {
  571. if(myres == 240) {
  572. switch(sisbios_mode[myindex].mode_no[1]) {
  573. case 0x50: myindex = MODE_FSTN_8; break;
  574. case 0x56: myindex = MODE_FSTN_16; break;
  575. case 0x53: return -1;
  576. }
  577. }
  578. }
  579. }
  580. if(SiS_GetModeID_LCD(ivideo->sisvga_engine, vbflags, sisbios_mode[myindex].xres,
  581. sisbios_mode[myindex].yres, 0, ivideo->sisfb_fstn,
  582. ivideo->SiS_Pr.SiS_CustomT, xres, yres, ivideo->vbflags2) < 0x14) {
  583. return -1;
  584. }
  585. break;
  586. case CRT2_TV:
  587. if(SiS_GetModeID_TV(ivideo->sisvga_engine, vbflags, sisbios_mode[myindex].xres,
  588. sisbios_mode[myindex].yres, 0, ivideo->vbflags2) < 0x14) {
  589. return -1;
  590. }
  591. break;
  592. case CRT2_VGA:
  593. if(SiS_GetModeID_VGA2(ivideo->sisvga_engine, vbflags, sisbios_mode[myindex].xres,
  594. sisbios_mode[myindex].yres, 0, ivideo->vbflags2) < 0x14) {
  595. return -1;
  596. }
  597. break;
  598. }
  599. return myindex;
  600. }
  601. static u8
  602. sisfb_search_refresh_rate(struct sis_video_info *ivideo, unsigned int rate, int mode_idx)
  603. {
  604. int i = 0;
  605. u16 xres = sisbios_mode[mode_idx].xres;
  606. u16 yres = sisbios_mode[mode_idx].yres;
  607. ivideo->rate_idx = 0;
  608. while((sisfb_vrate[i].idx != 0) && (sisfb_vrate[i].xres <= xres)) {
  609. if((sisfb_vrate[i].xres == xres) && (sisfb_vrate[i].yres == yres)) {
  610. if(sisfb_vrate[i].refresh == rate) {
  611. ivideo->rate_idx = sisfb_vrate[i].idx;
  612. break;
  613. } else if(sisfb_vrate[i].refresh > rate) {
  614. if((sisfb_vrate[i].refresh - rate) <= 3) {
  615. DPRINTK("sisfb: Adjusting rate from %d up to %d\n",
  616. rate, sisfb_vrate[i].refresh);
  617. ivideo->rate_idx = sisfb_vrate[i].idx;
  618. ivideo->refresh_rate = sisfb_vrate[i].refresh;
  619. } else if((sisfb_vrate[i].idx != 1) &&
  620. ((rate - sisfb_vrate[i-1].refresh) <= 2)) {
  621. DPRINTK("sisfb: Adjusting rate from %d down to %d\n",
  622. rate, sisfb_vrate[i-1].refresh);
  623. ivideo->rate_idx = sisfb_vrate[i-1].idx;
  624. ivideo->refresh_rate = sisfb_vrate[i-1].refresh;
  625. }
  626. break;
  627. } else if((rate - sisfb_vrate[i].refresh) <= 2) {
  628. DPRINTK("sisfb: Adjusting rate from %d down to %d\n",
  629. rate, sisfb_vrate[i].refresh);
  630. ivideo->rate_idx = sisfb_vrate[i].idx;
  631. break;
  632. }
  633. }
  634. i++;
  635. }
  636. if(ivideo->rate_idx > 0) {
  637. return ivideo->rate_idx;
  638. } else {
  639. printk(KERN_INFO "sisfb: Unsupported rate %d for %dx%d\n",
  640. rate, xres, yres);
  641. return 0;
  642. }
  643. }
  644. static bool
  645. sisfb_bridgeisslave(struct sis_video_info *ivideo)
  646. {
  647. unsigned char P1_00;
  648. if(!(ivideo->vbflags2 & VB2_VIDEOBRIDGE))
  649. return false;
  650. P1_00 = SiS_GetReg(SISPART1, 0x00);
  651. if( ((ivideo->sisvga_engine == SIS_300_VGA) && (P1_00 & 0xa0) == 0x20) ||
  652. ((ivideo->sisvga_engine == SIS_315_VGA) && (P1_00 & 0x50) == 0x10) ) {
  653. return true;
  654. } else {
  655. return false;
  656. }
  657. }
  658. static bool
  659. sisfballowretracecrt1(struct sis_video_info *ivideo)
  660. {
  661. u8 temp;
  662. temp = SiS_GetReg(SISCR, 0x17);
  663. if(!(temp & 0x80))
  664. return false;
  665. temp = SiS_GetReg(SISSR, 0x1f);
  666. if(temp & 0xc0)
  667. return false;
  668. return true;
  669. }
  670. static bool
  671. sisfbcheckvretracecrt1(struct sis_video_info *ivideo)
  672. {
  673. if(!sisfballowretracecrt1(ivideo))
  674. return false;
  675. if (SiS_GetRegByte(SISINPSTAT) & 0x08)
  676. return true;
  677. else
  678. return false;
  679. }
  680. static void
  681. sisfbwaitretracecrt1(struct sis_video_info *ivideo)
  682. {
  683. int watchdog;
  684. if(!sisfballowretracecrt1(ivideo))
  685. return;
  686. watchdog = 65536;
  687. while ((!(SiS_GetRegByte(SISINPSTAT) & 0x08)) && --watchdog);
  688. watchdog = 65536;
  689. while ((SiS_GetRegByte(SISINPSTAT) & 0x08) && --watchdog);
  690. }
  691. static bool
  692. sisfbcheckvretracecrt2(struct sis_video_info *ivideo)
  693. {
  694. unsigned char temp, reg;
  695. switch(ivideo->sisvga_engine) {
  696. case SIS_300_VGA: reg = 0x25; break;
  697. case SIS_315_VGA: reg = 0x30; break;
  698. default: return false;
  699. }
  700. temp = SiS_GetReg(SISPART1, reg);
  701. if(temp & 0x02)
  702. return true;
  703. else
  704. return false;
  705. }
  706. static bool
  707. sisfb_CheckVBRetrace(struct sis_video_info *ivideo)
  708. {
  709. if(ivideo->currentvbflags & VB_DISPTYPE_DISP2) {
  710. if(!sisfb_bridgeisslave(ivideo)) {
  711. return sisfbcheckvretracecrt2(ivideo);
  712. }
  713. }
  714. return sisfbcheckvretracecrt1(ivideo);
  715. }
  716. static u32
  717. sisfb_setupvbblankflags(struct sis_video_info *ivideo, u32 *vcount, u32 *hcount)
  718. {
  719. u8 idx, reg1, reg2, reg3, reg4;
  720. u32 ret = 0;
  721. (*vcount) = (*hcount) = 0;
  722. if((ivideo->currentvbflags & VB_DISPTYPE_DISP2) && (!(sisfb_bridgeisslave(ivideo)))) {
  723. ret |= (FB_VBLANK_HAVE_VSYNC |
  724. FB_VBLANK_HAVE_HBLANK |
  725. FB_VBLANK_HAVE_VBLANK |
  726. FB_VBLANK_HAVE_VCOUNT |
  727. FB_VBLANK_HAVE_HCOUNT);
  728. switch(ivideo->sisvga_engine) {
  729. case SIS_300_VGA: idx = 0x25; break;
  730. default:
  731. case SIS_315_VGA: idx = 0x30; break;
  732. }
  733. reg1 = SiS_GetReg(SISPART1, (idx+0)); /* 30 */
  734. reg2 = SiS_GetReg(SISPART1, (idx+1)); /* 31 */
  735. reg3 = SiS_GetReg(SISPART1, (idx+2)); /* 32 */
  736. reg4 = SiS_GetReg(SISPART1, (idx+3)); /* 33 */
  737. if(reg1 & 0x01) ret |= FB_VBLANK_VBLANKING;
  738. if(reg1 & 0x02) ret |= FB_VBLANK_VSYNCING;
  739. if(reg4 & 0x80) ret |= FB_VBLANK_HBLANKING;
  740. (*vcount) = reg3 | ((reg4 & 0x70) << 4);
  741. (*hcount) = reg2 | ((reg4 & 0x0f) << 8);
  742. } else if(sisfballowretracecrt1(ivideo)) {
  743. ret |= (FB_VBLANK_HAVE_VSYNC |
  744. FB_VBLANK_HAVE_VBLANK |
  745. FB_VBLANK_HAVE_VCOUNT |
  746. FB_VBLANK_HAVE_HCOUNT);
  747. reg1 = SiS_GetRegByte(SISINPSTAT);
  748. if(reg1 & 0x08) ret |= FB_VBLANK_VSYNCING;
  749. if(reg1 & 0x01) ret |= FB_VBLANK_VBLANKING;
  750. reg1 = SiS_GetReg(SISCR, 0x20);
  751. reg1 = SiS_GetReg(SISCR, 0x1b);
  752. reg2 = SiS_GetReg(SISCR, 0x1c);
  753. reg3 = SiS_GetReg(SISCR, 0x1d);
  754. (*vcount) = reg2 | ((reg3 & 0x07) << 8);
  755. (*hcount) = (reg1 | ((reg3 & 0x10) << 4)) << 3;
  756. }
  757. return ret;
  758. }
  759. static int
  760. sisfb_myblank(struct sis_video_info *ivideo, int blank)
  761. {
  762. u8 sr01, sr11, sr1f, cr63=0, p2_0, p1_13;
  763. bool backlight = true;
  764. switch(blank) {
  765. case FB_BLANK_UNBLANK: /* on */
  766. sr01 = 0x00;
  767. sr11 = 0x00;
  768. sr1f = 0x00;
  769. cr63 = 0x00;
  770. p2_0 = 0x20;
  771. p1_13 = 0x00;
  772. backlight = true;
  773. break;
  774. case FB_BLANK_NORMAL: /* blank */
  775. sr01 = 0x20;
  776. sr11 = 0x00;
  777. sr1f = 0x00;
  778. cr63 = 0x00;
  779. p2_0 = 0x20;
  780. p1_13 = 0x00;
  781. backlight = true;
  782. break;
  783. case FB_BLANK_VSYNC_SUSPEND: /* no vsync */
  784. sr01 = 0x20;
  785. sr11 = 0x08;
  786. sr1f = 0x80;
  787. cr63 = 0x40;
  788. p2_0 = 0x40;
  789. p1_13 = 0x80;
  790. backlight = false;
  791. break;
  792. case FB_BLANK_HSYNC_SUSPEND: /* no hsync */
  793. sr01 = 0x20;
  794. sr11 = 0x08;
  795. sr1f = 0x40;
  796. cr63 = 0x40;
  797. p2_0 = 0x80;
  798. p1_13 = 0x40;
  799. backlight = false;
  800. break;
  801. case FB_BLANK_POWERDOWN: /* off */
  802. sr01 = 0x20;
  803. sr11 = 0x08;
  804. sr1f = 0xc0;
  805. cr63 = 0x40;
  806. p2_0 = 0xc0;
  807. p1_13 = 0xc0;
  808. backlight = false;
  809. break;
  810. default:
  811. return 1;
  812. }
  813. if(ivideo->currentvbflags & VB_DISPTYPE_CRT1) {
  814. if( (!ivideo->sisfb_thismonitor.datavalid) ||
  815. ((ivideo->sisfb_thismonitor.datavalid) &&
  816. (ivideo->sisfb_thismonitor.feature & 0xe0))) {
  817. if(ivideo->sisvga_engine == SIS_315_VGA) {
  818. SiS_SetRegANDOR(SISCR, ivideo->SiS_Pr.SiS_MyCR63, 0xbf, cr63);
  819. }
  820. if(!(sisfb_bridgeisslave(ivideo))) {
  821. SiS_SetRegANDOR(SISSR, 0x01, ~0x20, sr01);
  822. SiS_SetRegANDOR(SISSR, 0x1f, 0x3f, sr1f);
  823. }
  824. }
  825. }
  826. if(ivideo->currentvbflags & CRT2_LCD) {
  827. if(ivideo->vbflags2 & VB2_SISLVDSBRIDGE) {
  828. if(backlight) {
  829. SiS_SiS30xBLOn(&ivideo->SiS_Pr);
  830. } else {
  831. SiS_SiS30xBLOff(&ivideo->SiS_Pr);
  832. }
  833. } else if(ivideo->sisvga_engine == SIS_315_VGA) {
  834. #ifdef CONFIG_FB_SIS_315
  835. if(ivideo->vbflags2 & VB2_CHRONTEL) {
  836. if(backlight) {
  837. SiS_Chrontel701xBLOn(&ivideo->SiS_Pr);
  838. } else {
  839. SiS_Chrontel701xBLOff(&ivideo->SiS_Pr);
  840. }
  841. }
  842. #endif
  843. }
  844. if(((ivideo->sisvga_engine == SIS_300_VGA) &&
  845. (ivideo->vbflags2 & (VB2_301|VB2_30xBDH|VB2_LVDS))) ||
  846. ((ivideo->sisvga_engine == SIS_315_VGA) &&
  847. ((ivideo->vbflags2 & (VB2_LVDS | VB2_CHRONTEL)) == VB2_LVDS))) {
  848. SiS_SetRegANDOR(SISSR, 0x11, ~0x0c, sr11);
  849. }
  850. if(ivideo->sisvga_engine == SIS_300_VGA) {
  851. if((ivideo->vbflags2 & VB2_30xB) &&
  852. (!(ivideo->vbflags2 & VB2_30xBDH))) {
  853. SiS_SetRegANDOR(SISPART1, 0x13, 0x3f, p1_13);
  854. }
  855. } else if(ivideo->sisvga_engine == SIS_315_VGA) {
  856. if((ivideo->vbflags2 & VB2_30xB) &&
  857. (!(ivideo->vbflags2 & VB2_30xBDH))) {
  858. SiS_SetRegANDOR(SISPART2, 0x00, 0x1f, p2_0);
  859. }
  860. }
  861. } else if(ivideo->currentvbflags & CRT2_VGA) {
  862. if(ivideo->vbflags2 & VB2_30xB) {
  863. SiS_SetRegANDOR(SISPART2, 0x00, 0x1f, p2_0);
  864. }
  865. }
  866. return 0;
  867. }
  868. /* ------------- Callbacks from init.c/init301.c -------------- */
  869. #ifdef CONFIG_FB_SIS_300
  870. unsigned int
  871. sisfb_read_nbridge_pci_dword(struct SiS_Private *SiS_Pr, int reg)
  872. {
  873. struct sis_video_info *ivideo = (struct sis_video_info *)SiS_Pr->ivideo;
  874. u32 val = 0;
  875. pci_read_config_dword(ivideo->nbridge, reg, &val);
  876. return (unsigned int)val;
  877. }
  878. void
  879. sisfb_write_nbridge_pci_dword(struct SiS_Private *SiS_Pr, int reg, unsigned int val)
  880. {
  881. struct sis_video_info *ivideo = (struct sis_video_info *)SiS_Pr->ivideo;
  882. pci_write_config_dword(ivideo->nbridge, reg, (u32)val);
  883. }
  884. unsigned int
  885. sisfb_read_lpc_pci_dword(struct SiS_Private *SiS_Pr, int reg)
  886. {
  887. struct sis_video_info *ivideo = (struct sis_video_info *)SiS_Pr->ivideo;
  888. u32 val = 0;
  889. if(!ivideo->lpcdev) return 0;
  890. pci_read_config_dword(ivideo->lpcdev, reg, &val);
  891. return (unsigned int)val;
  892. }
  893. #endif
  894. #ifdef CONFIG_FB_SIS_315
  895. void
  896. sisfb_write_nbridge_pci_byte(struct SiS_Private *SiS_Pr, int reg, unsigned char val)
  897. {
  898. struct sis_video_info *ivideo = (struct sis_video_info *)SiS_Pr->ivideo;
  899. pci_write_config_byte(ivideo->nbridge, reg, (u8)val);
  900. }
  901. unsigned int
  902. sisfb_read_mio_pci_word(struct SiS_Private *SiS_Pr, int reg)
  903. {
  904. struct sis_video_info *ivideo = (struct sis_video_info *)SiS_Pr->ivideo;
  905. u16 val = 0;
  906. if(!ivideo->lpcdev) return 0;
  907. pci_read_config_word(ivideo->lpcdev, reg, &val);
  908. return (unsigned int)val;
  909. }
  910. #endif
  911. /* ----------- FBDev related routines for all series ----------- */
  912. static int
  913. sisfb_get_cmap_len(const struct fb_var_screeninfo *var)
  914. {
  915. return (var->bits_per_pixel == 8) ? 256 : 16;
  916. }
  917. static void
  918. sisfb_set_vparms(struct sis_video_info *ivideo)
  919. {
  920. switch(ivideo->video_bpp) {
  921. case 8:
  922. ivideo->DstColor = 0x0000;
  923. ivideo->SiS310_AccelDepth = 0x00000000;
  924. ivideo->video_cmap_len = 256;
  925. break;
  926. case 16:
  927. ivideo->DstColor = 0x8000;
  928. ivideo->SiS310_AccelDepth = 0x00010000;
  929. ivideo->video_cmap_len = 16;
  930. break;
  931. case 32:
  932. ivideo->DstColor = 0xC000;
  933. ivideo->SiS310_AccelDepth = 0x00020000;
  934. ivideo->video_cmap_len = 16;
  935. break;
  936. default:
  937. ivideo->video_cmap_len = 16;
  938. printk(KERN_ERR "sisfb: Unsupported depth %d", ivideo->video_bpp);
  939. ivideo->accel = 0;
  940. }
  941. }
  942. static int
  943. sisfb_calc_maxyres(struct sis_video_info *ivideo, struct fb_var_screeninfo *var)
  944. {
  945. int maxyres = ivideo->sisfb_mem / (var->xres_virtual * (var->bits_per_pixel >> 3));
  946. if(maxyres > 32767) maxyres = 32767;
  947. return maxyres;
  948. }
  949. static void
  950. sisfb_calc_pitch(struct sis_video_info *ivideo, struct fb_var_screeninfo *var)
  951. {
  952. ivideo->video_linelength = var->xres_virtual * (var->bits_per_pixel >> 3);
  953. ivideo->scrnpitchCRT1 = ivideo->video_linelength;
  954. if(!(ivideo->currentvbflags & CRT1_LCDA)) {
  955. if((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
  956. ivideo->scrnpitchCRT1 <<= 1;
  957. }
  958. }
  959. }
  960. static void
  961. sisfb_set_pitch(struct sis_video_info *ivideo)
  962. {
  963. bool isslavemode = false;
  964. unsigned short HDisplay1 = ivideo->scrnpitchCRT1 >> 3;
  965. unsigned short HDisplay2 = ivideo->video_linelength >> 3;
  966. if(sisfb_bridgeisslave(ivideo)) isslavemode = true;
  967. /* We need to set pitch for CRT1 if bridge is in slave mode, too */
  968. if((ivideo->currentvbflags & VB_DISPTYPE_DISP1) || (isslavemode)) {
  969. SiS_SetReg(SISCR, 0x13, (HDisplay1 & 0xFF));
  970. SiS_SetRegANDOR(SISSR, 0x0E, 0xF0, (HDisplay1 >> 8));
  971. }
  972. /* We must not set the pitch for CRT2 if bridge is in slave mode */
  973. if((ivideo->currentvbflags & VB_DISPTYPE_DISP2) && (!isslavemode)) {
  974. SiS_SetRegOR(SISPART1, ivideo->CRT2_write_enable, 0x01);
  975. SiS_SetReg(SISPART1, 0x07, (HDisplay2 & 0xFF));
  976. SiS_SetRegANDOR(SISPART1, 0x09, 0xF0, (HDisplay2 >> 8));
  977. }
  978. }
  979. static void
  980. sisfb_bpp_to_var(struct sis_video_info *ivideo, struct fb_var_screeninfo *var)
  981. {
  982. ivideo->video_cmap_len = sisfb_get_cmap_len(var);
  983. switch(var->bits_per_pixel) {
  984. case 8:
  985. var->red.offset = var->green.offset = var->blue.offset = 0;
  986. var->red.length = var->green.length = var->blue.length = 8;
  987. break;
  988. case 16:
  989. var->red.offset = 11;
  990. var->red.length = 5;
  991. var->green.offset = 5;
  992. var->green.length = 6;
  993. var->blue.offset = 0;
  994. var->blue.length = 5;
  995. var->transp.offset = 0;
  996. var->transp.length = 0;
  997. break;
  998. case 32:
  999. var->red.offset = 16;
  1000. var->red.length = 8;
  1001. var->green.offset = 8;
  1002. var->green.length = 8;
  1003. var->blue.offset = 0;
  1004. var->blue.length = 8;
  1005. var->transp.offset = 24;
  1006. var->transp.length = 8;
  1007. break;
  1008. }
  1009. }
  1010. static int
  1011. sisfb_set_mode(struct sis_video_info *ivideo, int clrscrn)
  1012. {
  1013. unsigned short modeno = ivideo->mode_no;
  1014. /* >=2.6.12's fbcon clears the screen anyway */
  1015. modeno |= 0x80;
  1016. SiS_SetReg(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
  1017. sisfb_pre_setmode(ivideo);
  1018. if(!SiSSetMode(&ivideo->SiS_Pr, modeno)) {
  1019. printk(KERN_ERR "sisfb: Setting mode[0x%x] failed\n", ivideo->mode_no);
  1020. return -EINVAL;
  1021. }
  1022. SiS_SetReg(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
  1023. sisfb_post_setmode(ivideo);
  1024. return 0;
  1025. }
  1026. static int
  1027. sisfb_do_set_var(struct fb_var_screeninfo *var, int isactive, struct fb_info *info)
  1028. {
  1029. struct sis_video_info *ivideo = (struct sis_video_info *)info->par;
  1030. unsigned int htotal = 0, vtotal = 0;
  1031. unsigned int drate = 0, hrate = 0;
  1032. int found_mode = 0, ret;
  1033. int old_mode;
  1034. u32 pixclock;
  1035. htotal = var->left_margin + var->xres + var->right_margin + var->hsync_len;
  1036. vtotal = var->upper_margin + var->lower_margin + var->vsync_len;
  1037. pixclock = var->pixclock;
  1038. if((var->vmode & FB_VMODE_MASK) == FB_VMODE_NONINTERLACED) {
  1039. vtotal += var->yres;
  1040. vtotal <<= 1;
  1041. } else if((var->vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
  1042. vtotal += var->yres;
  1043. vtotal <<= 2;
  1044. } else if((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
  1045. vtotal += var->yres;
  1046. vtotal <<= 1;
  1047. } else vtotal += var->yres;
  1048. if(!(htotal) || !(vtotal)) {
  1049. DPRINTK("sisfb: Invalid 'var' information\n");
  1050. return -EINVAL;
  1051. }
  1052. if(pixclock && htotal && vtotal) {
  1053. drate = 1000000000 / pixclock;
  1054. hrate = (drate * 1000) / htotal;
  1055. ivideo->refresh_rate = (unsigned int) (hrate * 2 / vtotal);
  1056. } else {
  1057. ivideo->refresh_rate = 60;
  1058. }
  1059. old_mode = ivideo->sisfb_mode_idx;
  1060. ivideo->sisfb_mode_idx = 0;
  1061. while( (sisbios_mode[ivideo->sisfb_mode_idx].mode_no[0] != 0) &&
  1062. (sisbios_mode[ivideo->sisfb_mode_idx].xres <= var->xres) ) {
  1063. if( (sisbios_mode[ivideo->sisfb_mode_idx].xres == var->xres) &&
  1064. (sisbios_mode[ivideo->sisfb_mode_idx].yres == var->yres) &&
  1065. (sisbios_mode[ivideo->sisfb_mode_idx].bpp == var->bits_per_pixel)) {
  1066. ivideo->mode_no = sisbios_mode[ivideo->sisfb_mode_idx].mode_no[ivideo->mni];
  1067. found_mode = 1;
  1068. break;
  1069. }
  1070. ivideo->sisfb_mode_idx++;
  1071. }
  1072. if(found_mode) {
  1073. ivideo->sisfb_mode_idx = sisfb_validate_mode(ivideo,
  1074. ivideo->sisfb_mode_idx, ivideo->currentvbflags);
  1075. } else {
  1076. ivideo->sisfb_mode_idx = -1;
  1077. }
  1078. if(ivideo->sisfb_mode_idx < 0) {
  1079. printk(KERN_ERR "sisfb: Mode %dx%dx%d not supported\n", var->xres,
  1080. var->yres, var->bits_per_pixel);
  1081. ivideo->sisfb_mode_idx = old_mode;
  1082. return -EINVAL;
  1083. }
  1084. ivideo->mode_no = sisbios_mode[ivideo->sisfb_mode_idx].mode_no[ivideo->mni];
  1085. if(sisfb_search_refresh_rate(ivideo, ivideo->refresh_rate, ivideo->sisfb_mode_idx) == 0) {
  1086. ivideo->rate_idx = sisbios_mode[ivideo->sisfb_mode_idx].rate_idx;
  1087. ivideo->refresh_rate = 60;
  1088. }
  1089. if(isactive) {
  1090. /* If acceleration to be used? Need to know
  1091. * before pre/post_set_mode()
  1092. */
  1093. ivideo->accel = 0;
  1094. #if defined(FBINFO_HWACCEL_DISABLED) && defined(FBINFO_HWACCEL_XPAN)
  1095. #ifdef STUPID_ACCELF_TEXT_SHIT
  1096. if(var->accel_flags & FB_ACCELF_TEXT) {
  1097. info->flags &= ~FBINFO_HWACCEL_DISABLED;
  1098. } else {
  1099. info->flags |= FBINFO_HWACCEL_DISABLED;
  1100. }
  1101. #endif
  1102. if(!(info->flags & FBINFO_HWACCEL_DISABLED)) ivideo->accel = -1;
  1103. #else
  1104. if(var->accel_flags & FB_ACCELF_TEXT) ivideo->accel = -1;
  1105. #endif
  1106. if((ret = sisfb_set_mode(ivideo, 1))) {
  1107. return ret;
  1108. }
  1109. ivideo->video_bpp = sisbios_mode[ivideo->sisfb_mode_idx].bpp;
  1110. ivideo->video_width = sisbios_mode[ivideo->sisfb_mode_idx].xres;
  1111. ivideo->video_height = sisbios_mode[ivideo->sisfb_mode_idx].yres;
  1112. sisfb_calc_pitch(ivideo, var);
  1113. sisfb_set_pitch(ivideo);
  1114. sisfb_set_vparms(ivideo);
  1115. ivideo->current_width = ivideo->video_width;
  1116. ivideo->current_height = ivideo->video_height;
  1117. ivideo->current_bpp = ivideo->video_bpp;
  1118. ivideo->current_htotal = htotal;
  1119. ivideo->current_vtotal = vtotal;
  1120. ivideo->current_linelength = ivideo->video_linelength;
  1121. ivideo->current_pixclock = var->pixclock;
  1122. ivideo->current_refresh_rate = ivideo->refresh_rate;
  1123. ivideo->sisfb_lastrates[ivideo->mode_no] = ivideo->refresh_rate;
  1124. }
  1125. return 0;
  1126. }
  1127. static void
  1128. sisfb_set_base_CRT1(struct sis_video_info *ivideo, unsigned int base)
  1129. {
  1130. SiS_SetReg(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
  1131. SiS_SetReg(SISCR, 0x0D, base & 0xFF);
  1132. SiS_SetReg(SISCR, 0x0C, (base >> 8) & 0xFF);
  1133. SiS_SetReg(SISSR, 0x0D, (base >> 16) & 0xFF);
  1134. if(ivideo->sisvga_engine == SIS_315_VGA) {
  1135. SiS_SetRegANDOR(SISSR, 0x37, 0xFE, (base >> 24) & 0x01);
  1136. }
  1137. }
  1138. static void
  1139. sisfb_set_base_CRT2(struct sis_video_info *ivideo, unsigned int base)
  1140. {
  1141. if(ivideo->currentvbflags & VB_DISPTYPE_DISP2) {
  1142. SiS_SetRegOR(SISPART1, ivideo->CRT2_write_enable, 0x01);
  1143. SiS_SetReg(SISPART1, 0x06, (base & 0xFF));
  1144. SiS_SetReg(SISPART1, 0x05, ((base >> 8) & 0xFF));
  1145. SiS_SetReg(SISPART1, 0x04, ((base >> 16) & 0xFF));
  1146. if(ivideo->sisvga_engine == SIS_315_VGA) {
  1147. SiS_SetRegANDOR(SISPART1, 0x02, 0x7F, ((base >> 24) & 0x01) << 7);
  1148. }
  1149. }
  1150. }
  1151. static int
  1152. sisfb_pan_var(struct sis_video_info *ivideo, struct fb_info *info,
  1153. struct fb_var_screeninfo *var)
  1154. {
  1155. ivideo->current_base = var->yoffset * info->var.xres_virtual
  1156. + var->xoffset;
  1157. /* calculate base bpp dep. */
  1158. switch (info->var.bits_per_pixel) {
  1159. case 32:
  1160. break;
  1161. case 16:
  1162. ivideo->current_base >>= 1;
  1163. break;
  1164. case 8:
  1165. default:
  1166. ivideo->current_base >>= 2;
  1167. break;
  1168. }
  1169. ivideo->current_base += (ivideo->video_offset >> 2);
  1170. sisfb_set_base_CRT1(ivideo, ivideo->current_base);
  1171. sisfb_set_base_CRT2(ivideo, ivideo->current_base);
  1172. return 0;
  1173. }
  1174. static int
  1175. sisfb_open(struct fb_info *info, int user)
  1176. {
  1177. return 0;
  1178. }
  1179. static int
  1180. sisfb_release(struct fb_info *info, int user)
  1181. {
  1182. return 0;
  1183. }
  1184. static int
  1185. sisfb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
  1186. unsigned transp, struct fb_info *info)
  1187. {
  1188. struct sis_video_info *ivideo = (struct sis_video_info *)info->par;
  1189. if(regno >= sisfb_get_cmap_len(&info->var))
  1190. return 1;
  1191. switch(info->var.bits_per_pixel) {
  1192. case 8:
  1193. SiS_SetRegByte(SISDACA, regno);
  1194. SiS_SetRegByte(SISDACD, (red >> 10));
  1195. SiS_SetRegByte(SISDACD, (green >> 10));
  1196. SiS_SetRegByte(SISDACD, (blue >> 10));
  1197. if(ivideo->currentvbflags & VB_DISPTYPE_DISP2) {
  1198. SiS_SetRegByte(SISDAC2A, regno);
  1199. SiS_SetRegByte(SISDAC2D, (red >> 8));
  1200. SiS_SetRegByte(SISDAC2D, (green >> 8));
  1201. SiS_SetRegByte(SISDAC2D, (blue >> 8));
  1202. }
  1203. break;
  1204. case 16:
  1205. if (regno >= 16)
  1206. break;
  1207. ((u32 *)(info->pseudo_palette))[regno] =
  1208. (red & 0xf800) |
  1209. ((green & 0xfc00) >> 5) |
  1210. ((blue & 0xf800) >> 11);
  1211. break;
  1212. case 32:
  1213. if (regno >= 16)
  1214. break;
  1215. red >>= 8;
  1216. green >>= 8;
  1217. blue >>= 8;
  1218. ((u32 *)(info->pseudo_palette))[regno] =
  1219. (red << 16) | (green << 8) | (blue);
  1220. break;
  1221. }
  1222. return 0;
  1223. }
  1224. static int
  1225. sisfb_set_par(struct fb_info *info)
  1226. {
  1227. int err;
  1228. if((err = sisfb_do_set_var(&info->var, 1, info)))
  1229. return err;
  1230. sisfb_get_fix(&info->fix, -1, info);
  1231. return 0;
  1232. }
  1233. static int
  1234. sisfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  1235. {
  1236. struct sis_video_info *ivideo = (struct sis_video_info *)info->par;
  1237. unsigned int htotal = 0, vtotal = 0, myrateindex = 0;
  1238. unsigned int drate = 0, hrate = 0, maxyres;
  1239. int found_mode = 0;
  1240. int refresh_rate, search_idx, tidx;
  1241. bool recalc_clock = false;
  1242. u32 pixclock;
  1243. htotal = var->left_margin + var->xres + var->right_margin + var->hsync_len;
  1244. vtotal = var->upper_margin + var->lower_margin + var->vsync_len;
  1245. pixclock = var->pixclock;
  1246. if((var->vmode & FB_VMODE_MASK) == FB_VMODE_NONINTERLACED) {
  1247. vtotal += var->yres;
  1248. vtotal <<= 1;
  1249. } else if((var->vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
  1250. vtotal += var->yres;
  1251. vtotal <<= 2;
  1252. } else if((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
  1253. vtotal += var->yres;
  1254. vtotal <<= 1;
  1255. } else
  1256. vtotal += var->yres;
  1257. if(!(htotal) || !(vtotal)) {
  1258. SISFAIL("sisfb: no valid timing data");
  1259. }
  1260. search_idx = 0;
  1261. while( (sisbios_mode[search_idx].mode_no[0] != 0) &&
  1262. (sisbios_mode[search_idx].xres <= var->xres) ) {
  1263. if( (sisbios_mode[search_idx].xres == var->xres) &&
  1264. (sisbios_mode[search_idx].yres == var->yres) &&
  1265. (sisbios_mode[search_idx].bpp == var->bits_per_pixel)) {
  1266. if((tidx = sisfb_validate_mode(ivideo, search_idx,
  1267. ivideo->currentvbflags)) > 0) {
  1268. found_mode = 1;
  1269. search_idx = tidx;
  1270. break;
  1271. }
  1272. }
  1273. search_idx++;
  1274. }
  1275. if(!found_mode) {
  1276. search_idx = 0;
  1277. while(sisbios_mode[search_idx].mode_no[0] != 0) {
  1278. if( (var->xres <= sisbios_mode[search_idx].xres) &&
  1279. (var->yres <= sisbios_mode[search_idx].yres) &&
  1280. (var->bits_per_pixel == sisbios_mode[search_idx].bpp) ) {
  1281. if((tidx = sisfb_validate_mode(ivideo,search_idx,
  1282. ivideo->currentvbflags)) > 0) {
  1283. found_mode = 1;
  1284. search_idx = tidx;
  1285. break;
  1286. }
  1287. }
  1288. search_idx++;
  1289. }
  1290. if(found_mode) {
  1291. printk(KERN_DEBUG
  1292. "sisfb: Adapted from %dx%dx%d to %dx%dx%d\n",
  1293. var->xres, var->yres, var->bits_per_pixel,
  1294. sisbios_mode[search_idx].xres,
  1295. sisbios_mode[search_idx].yres,
  1296. var->bits_per_pixel);
  1297. var->xres = sisbios_mode[search_idx].xres;
  1298. var->yres = sisbios_mode[search_idx].yres;
  1299. } else {
  1300. printk(KERN_ERR
  1301. "sisfb: Failed to find supported mode near %dx%dx%d\n",
  1302. var->xres, var->yres, var->bits_per_pixel);
  1303. return -EINVAL;
  1304. }
  1305. }
  1306. if( ((ivideo->vbflags2 & VB2_LVDS) ||
  1307. ((ivideo->vbflags2 & VB2_30xBDH) && (ivideo->currentvbflags & CRT2_LCD))) &&
  1308. (var->bits_per_pixel == 8) ) {
  1309. /* Slave modes on LVDS and 301B-DH */
  1310. refresh_rate = 60;
  1311. recalc_clock = true;
  1312. } else if( (ivideo->current_htotal == htotal) &&
  1313. (ivideo->current_vtotal == vtotal) &&
  1314. (ivideo->current_pixclock == pixclock) ) {
  1315. /* x=x & y=y & c=c -> assume depth change */
  1316. drate = 1000000000 / pixclock;
  1317. hrate = (drate * 1000) / htotal;
  1318. refresh_rate = (unsigned int) (hrate * 2 / vtotal);
  1319. } else if( ( (ivideo->current_htotal != htotal) ||
  1320. (ivideo->current_vtotal != vtotal) ) &&
  1321. (ivideo->current_pixclock == var->pixclock) ) {
  1322. /* x!=x | y!=y & c=c -> invalid pixclock */
  1323. if(ivideo->sisfb_lastrates[sisbios_mode[search_idx].mode_no[ivideo->mni]]) {
  1324. refresh_rate =
  1325. ivideo->sisfb_lastrates[sisbios_mode[search_idx].mode_no[ivideo->mni]];
  1326. } else if(ivideo->sisfb_parm_rate != -1) {
  1327. /* Sic, sisfb_parm_rate - want to know originally desired rate here */
  1328. refresh_rate = ivideo->sisfb_parm_rate;
  1329. } else {
  1330. refresh_rate = 60;
  1331. }
  1332. recalc_clock = true;
  1333. } else if((pixclock) && (htotal) && (vtotal)) {
  1334. drate = 1000000000 / pixclock;
  1335. hrate = (drate * 1000) / htotal;
  1336. refresh_rate = (unsigned int) (hrate * 2 / vtotal);
  1337. } else if(ivideo->current_refresh_rate) {
  1338. refresh_rate = ivideo->current_refresh_rate;
  1339. recalc_clock = true;
  1340. } else {
  1341. refresh_rate = 60;
  1342. recalc_clock = true;
  1343. }
  1344. myrateindex = sisfb_search_refresh_rate(ivideo, refresh_rate, search_idx);
  1345. /* Eventually recalculate timing and clock */
  1346. if(recalc_clock) {
  1347. if(!myrateindex) myrateindex = sisbios_mode[search_idx].rate_idx;
  1348. var->pixclock = (u32) (1000000000 / sisfb_mode_rate_to_dclock(&ivideo->SiS_Pr,
  1349. sisbios_mode[search_idx].mode_no[ivideo->mni],
  1350. myrateindex));
  1351. sisfb_mode_rate_to_ddata(&ivideo->SiS_Pr,
  1352. sisbios_mode[search_idx].mode_no[ivideo->mni],
  1353. myrateindex, var);
  1354. if((var->vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
  1355. var->pixclock <<= 1;
  1356. }
  1357. }
  1358. if(ivideo->sisfb_thismonitor.datavalid) {
  1359. if(!sisfb_verify_rate(ivideo, &ivideo->sisfb_thismonitor, search_idx,
  1360. myrateindex, refresh_rate)) {
  1361. printk(KERN_INFO
  1362. "sisfb: WARNING: Refresh rate exceeds monitor specs!\n");
  1363. }
  1364. }
  1365. /* Adapt RGB settings */
  1366. sisfb_bpp_to_var(ivideo, var);
  1367. /* Sanity check for offsets */
  1368. if(var->xoffset < 0) var->xoffset = 0;
  1369. if(var->yoffset < 0) var->yoffset = 0;
  1370. if(var->xres > var->xres_virtual)
  1371. var->xres_virtual = var->xres;
  1372. if(ivideo->sisfb_ypan) {
  1373. maxyres = sisfb_calc_maxyres(ivideo, var);
  1374. if(ivideo->sisfb_max) {
  1375. var->yres_virtual = maxyres;
  1376. } else {
  1377. if(var->yres_virtual > maxyres) {
  1378. var->yres_virtual = maxyres;
  1379. }
  1380. }
  1381. if(var->yres_virtual <= var->yres) {
  1382. var->yres_virtual = var->yres;
  1383. }
  1384. } else {
  1385. if(var->yres != var->yres_virtual) {
  1386. var->yres_virtual = var->yres;
  1387. }
  1388. var->xoffset = 0;
  1389. var->yoffset = 0;
  1390. }
  1391. /* Truncate offsets to maximum if too high */
  1392. if(var->xoffset > var->xres_virtual - var->xres) {
  1393. var->xoffset = var->xres_virtual - var->xres - 1;
  1394. }
  1395. if(var->yoffset > var->yres_virtual - var->yres) {
  1396. var->yoffset = var->yres_virtual - var->yres - 1;
  1397. }
  1398. /* Set everything else to 0 */
  1399. var->red.msb_right =
  1400. var->green.msb_right =
  1401. var->blue.msb_right =
  1402. var->transp.offset =
  1403. var->transp.length =
  1404. var->transp.msb_right = 0;
  1405. return 0;
  1406. }
  1407. static int
  1408. sisfb_pan_display(struct fb_var_screeninfo *var, struct fb_info* info)
  1409. {
  1410. struct sis_video_info *ivideo = (struct sis_video_info *)info->par;
  1411. int err;
  1412. if (var->vmode & FB_VMODE_YWRAP)
  1413. return -EINVAL;
  1414. if (var->xoffset + info->var.xres > info->var.xres_virtual ||
  1415. var->yoffset + info->var.yres > info->var.yres_virtual)
  1416. return -EINVAL;
  1417. err = sisfb_pan_var(ivideo, info, var);
  1418. if (err < 0)
  1419. return err;
  1420. info->var.xoffset = var->xoffset;
  1421. info->var.yoffset = var->yoffset;
  1422. return 0;
  1423. }
  1424. static int
  1425. sisfb_blank(int blank, struct fb_info *info)
  1426. {
  1427. struct sis_video_info *ivideo = (struct sis_video_info *)info->par;
  1428. return sisfb_myblank(ivideo, blank);
  1429. }
  1430. /* ----------- FBDev related routines for all series ---------- */
  1431. static int sisfb_ioctl(struct fb_info *info, unsigned int cmd,
  1432. unsigned long arg)
  1433. {
  1434. struct sis_video_info *ivideo = (struct sis_video_info *)info->par;
  1435. struct sis_memreq sismemreq;
  1436. struct fb_vblank sisvbblank;
  1437. u32 gpu32 = 0;
  1438. #ifndef __user
  1439. #define __user
  1440. #endif
  1441. u32 __user *argp = (u32 __user *)arg;
  1442. switch(cmd) {
  1443. case FBIO_ALLOC:
  1444. if(!capable(CAP_SYS_RAWIO))
  1445. return -EPERM;
  1446. if(copy_from_user(&sismemreq, (void __user *)arg, sizeof(sismemreq)))
  1447. return -EFAULT;
  1448. sis_malloc(&sismemreq);
  1449. if(copy_to_user((void __user *)arg, &sismemreq, sizeof(sismemreq))) {
  1450. sis_free((u32)sismemreq.offset);
  1451. return -EFAULT;
  1452. }
  1453. break;
  1454. case FBIO_FREE:
  1455. if(!capable(CAP_SYS_RAWIO))
  1456. return -EPERM;
  1457. if(get_user(gpu32, argp))
  1458. return -EFAULT;
  1459. sis_free(gpu32);
  1460. break;
  1461. case FBIOGET_VBLANK:
  1462. memset(&sisvbblank, 0, sizeof(struct fb_vblank));
  1463. sisvbblank.count = 0;
  1464. sisvbblank.flags = sisfb_setupvbblankflags(ivideo, &sisvbblank.vcount, &sisvbblank.hcount);
  1465. if(copy_to_user((void __user *)arg, &sisvbblank, sizeof(sisvbblank)))
  1466. return -EFAULT;
  1467. break;
  1468. case SISFB_GET_INFO_SIZE:
  1469. return put_user(sizeof(struct sisfb_info), argp);
  1470. case SISFB_GET_INFO_OLD:
  1471. if(ivideo->warncount++ < 10)
  1472. printk(KERN_INFO
  1473. "sisfb: Deprecated ioctl call received - update your application!\n");
  1474. case SISFB_GET_INFO: /* For communication with X driver */
  1475. ivideo->sisfb_infoblock.sisfb_id = SISFB_ID;
  1476. ivideo->sisfb_infoblock.sisfb_version = VER_MAJOR;
  1477. ivideo->sisfb_infoblock.sisfb_revision = VER_MINOR;
  1478. ivideo->sisfb_infoblock.sisfb_patchlevel = VER_LEVEL;
  1479. ivideo->sisfb_infoblock.chip_id = ivideo->chip_id;
  1480. ivideo->sisfb_infoblock.sisfb_pci_vendor = ivideo->chip_vendor;
  1481. ivideo->sisfb_infoblock.memory = ivideo->video_size / 1024;
  1482. ivideo->sisfb_infoblock.heapstart = ivideo->heapstart / 1024;
  1483. if(ivideo->modechanged) {
  1484. ivideo->sisfb_infoblock.fbvidmode = ivideo->mode_no;
  1485. } else {
  1486. ivideo->sisfb_infoblock.fbvidmode = ivideo->modeprechange;
  1487. }
  1488. ivideo->sisfb_infoblock.sisfb_caps = ivideo->caps;
  1489. ivideo->sisfb_infoblock.sisfb_tqlen = ivideo->cmdQueueSize / 1024;
  1490. ivideo->sisfb_infoblock.sisfb_pcibus = ivideo->pcibus;
  1491. ivideo->sisfb_infoblock.sisfb_pcislot = ivideo->pcislot;
  1492. ivideo->sisfb_infoblock.sisfb_pcifunc = ivideo->pcifunc;
  1493. ivideo->sisfb_infoblock.sisfb_lcdpdc = ivideo->detectedpdc;
  1494. ivideo->sisfb_infoblock.sisfb_lcdpdca = ivideo->detectedpdca;
  1495. ivideo->sisfb_infoblock.sisfb_lcda = ivideo->detectedlcda;
  1496. ivideo->sisfb_infoblock.sisfb_vbflags = ivideo->vbflags;
  1497. ivideo->sisfb_infoblock.sisfb_currentvbflags = ivideo->currentvbflags;
  1498. ivideo->sisfb_infoblock.sisfb_scalelcd = ivideo->SiS_Pr.UsePanelScaler;
  1499. ivideo->sisfb_infoblock.sisfb_specialtiming = ivideo->SiS_Pr.SiS_CustomT;
  1500. ivideo->sisfb_infoblock.sisfb_haveemi = ivideo->SiS_Pr.HaveEMI ? 1 : 0;
  1501. ivideo->sisfb_infoblock.sisfb_haveemilcd = ivideo->SiS_Pr.HaveEMILCD ? 1 : 0;
  1502. ivideo->sisfb_infoblock.sisfb_emi30 = ivideo->SiS_Pr.EMI_30;
  1503. ivideo->sisfb_infoblock.sisfb_emi31 = ivideo->SiS_Pr.EMI_31;
  1504. ivideo->sisfb_infoblock.sisfb_emi32 = ivideo->SiS_Pr.EMI_32;
  1505. ivideo->sisfb_infoblock.sisfb_emi33 = ivideo->SiS_Pr.EMI_33;
  1506. ivideo->sisfb_infoblock.sisfb_tvxpos = (u16)(ivideo->tvxpos + 32);
  1507. ivideo->sisfb_infoblock.sisfb_tvypos = (u16)(ivideo->tvypos + 32);
  1508. ivideo->sisfb_infoblock.sisfb_heapsize = ivideo->sisfb_heap_size / 1024;
  1509. ivideo->sisfb_infoblock.sisfb_videooffset = ivideo->video_offset;
  1510. ivideo->sisfb_infoblock.sisfb_curfstn = ivideo->curFSTN;
  1511. ivideo->sisfb_infoblock.sisfb_curdstn = ivideo->curDSTN;
  1512. ivideo->sisfb_infoblock.sisfb_vbflags2 = ivideo->vbflags2;
  1513. ivideo->sisfb_infoblock.sisfb_can_post = ivideo->sisfb_can_post ? 1 : 0;
  1514. ivideo->sisfb_infoblock.sisfb_card_posted = ivideo->sisfb_card_posted ? 1 : 0;
  1515. ivideo->sisfb_infoblock.sisfb_was_boot_device = ivideo->sisfb_was_boot_device ? 1 : 0;
  1516. if(copy_to_user((void __user *)arg, &ivideo->sisfb_infoblock,
  1517. sizeof(ivideo->sisfb_infoblock)))
  1518. return -EFAULT;
  1519. break;
  1520. case SISFB_GET_VBRSTATUS_OLD:
  1521. if(ivideo->warncount++ < 10)
  1522. printk(KERN_INFO
  1523. "sisfb: Deprecated ioctl call received - update your application!\n");
  1524. case SISFB_GET_VBRSTATUS:
  1525. if(sisfb_CheckVBRetrace(ivideo))
  1526. return put_user((u32)1, argp);
  1527. else
  1528. return put_user((u32)0, argp);
  1529. case SISFB_GET_AUTOMAXIMIZE_OLD:
  1530. if(ivideo->warncount++ < 10)
  1531. printk(KERN_INFO
  1532. "sisfb: Deprecated ioctl call received - update your application!\n");
  1533. case SISFB_GET_AUTOMAXIMIZE:
  1534. if(ivideo->sisfb_max)
  1535. return put_user((u32)1, argp);
  1536. else
  1537. return put_user((u32)0, argp);
  1538. case SISFB_SET_AUTOMAXIMIZE_OLD:
  1539. if(ivideo->warncount++ < 10)
  1540. printk(KERN_INFO
  1541. "sisfb: Deprecated ioctl call received - update your application!\n");
  1542. case SISFB_SET_AUTOMAXIMIZE:
  1543. if(get_user(gpu32, argp))
  1544. return -EFAULT;
  1545. ivideo->sisfb_max = (gpu32) ? 1 : 0;
  1546. break;
  1547. case SISFB_SET_TVPOSOFFSET:
  1548. if(get_user(gpu32, argp))
  1549. return -EFAULT;
  1550. sisfb_set_TVxposoffset(ivideo, ((int)(gpu32 >> 16)) - 32);
  1551. sisfb_set_TVyposoffset(ivideo, ((int)(gpu32 & 0xffff)) - 32);
  1552. break;
  1553. case SISFB_GET_TVPOSOFFSET:
  1554. return put_user((u32)(((ivideo->tvxpos+32)<<16)|((ivideo->tvypos+32)&0xffff)),
  1555. argp);
  1556. case SISFB_COMMAND:
  1557. if(copy_from_user(&ivideo->sisfb_command, (void __user *)arg,
  1558. sizeof(struct sisfb_cmd)))
  1559. return -EFAULT;
  1560. sisfb_handle_command(ivideo, &ivideo->sisfb_command);
  1561. if(copy_to_user((void __user *)arg, &ivideo->sisfb_command,
  1562. sizeof(struct sisfb_cmd)))
  1563. return -EFAULT;
  1564. break;
  1565. case SISFB_SET_LOCK:
  1566. if(get_user(gpu32, argp))
  1567. return -EFAULT;
  1568. ivideo->sisfblocked = (gpu32) ? 1 : 0;
  1569. break;
  1570. default:
  1571. #ifdef SIS_NEW_CONFIG_COMPAT
  1572. return -ENOIOCTLCMD;
  1573. #else
  1574. return -EINVAL;
  1575. #endif
  1576. }
  1577. return 0;
  1578. }
  1579. static int
  1580. sisfb_get_fix(struct fb_fix_screeninfo *fix, int con, struct fb_info *info)
  1581. {
  1582. struct sis_video_info *ivideo = (struct sis_video_info *)info->par;
  1583. memset(fix, 0, sizeof(struct fb_fix_screeninfo));
  1584. strlcpy(fix->id, ivideo->myid, sizeof(fix->id));
  1585. mutex_lock(&info->mm_lock);
  1586. fix->smem_start = ivideo->video_base + ivideo->video_offset;
  1587. fix->smem_len = ivideo->sisfb_mem;
  1588. mutex_unlock(&info->mm_lock);
  1589. fix->type = FB_TYPE_PACKED_PIXELS;
  1590. fix->type_aux = 0;
  1591. fix->visual = (ivideo->video_bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
  1592. fix->xpanstep = 1;
  1593. fix->ypanstep = (ivideo->sisfb_ypan) ? 1 : 0;
  1594. fix->ywrapstep = 0;
  1595. fix->line_length = ivideo->video_linelength;
  1596. fix->mmio_start = ivideo->mmio_base;
  1597. fix->mmio_len = ivideo->mmio_size;
  1598. if(ivideo->sisvga_engine == SIS_300_VGA) {
  1599. fix->accel = FB_ACCEL_SIS_GLAMOUR;
  1600. } else if((ivideo->chip == SIS_330) ||
  1601. (ivideo->chip == SIS_760) ||
  1602. (ivideo->chip == SIS_761)) {
  1603. fix->accel = FB_ACCEL_SIS_XABRE;
  1604. } else if(ivideo->chip == XGI_20) {
  1605. fix->accel = FB_ACCEL_XGI_VOLARI_Z;
  1606. } else if(ivideo->chip >= XGI_40) {
  1607. fix->accel = FB_ACCEL_XGI_VOLARI_V;
  1608. } else {
  1609. fix->accel = FB_ACCEL_SIS_GLAMOUR_2;
  1610. }
  1611. return 0;
  1612. }
  1613. /* ---------------- fb_ops structures ----------------- */
  1614. static struct fb_ops sisfb_ops = {
  1615. .owner = THIS_MODULE,
  1616. .fb_open = sisfb_open,
  1617. .fb_release = sisfb_release,
  1618. .fb_check_var = sisfb_check_var,
  1619. .fb_set_par = sisfb_set_par,
  1620. .fb_setcolreg = sisfb_setcolreg,
  1621. .fb_pan_display = sisfb_pan_display,
  1622. .fb_blank = sisfb_blank,
  1623. .fb_fillrect = fbcon_sis_fillrect,
  1624. .fb_copyarea = fbcon_sis_copyarea,
  1625. .fb_imageblit = cfb_imageblit,
  1626. .fb_sync = fbcon_sis_sync,
  1627. #ifdef SIS_NEW_CONFIG_COMPAT
  1628. .fb_compat_ioctl= sisfb_ioctl,
  1629. #endif
  1630. .fb_ioctl = sisfb_ioctl
  1631. };
  1632. /* ---------------- Chip generation dependent routines ---------------- */
  1633. static struct pci_dev *sisfb_get_northbridge(int basechipid)
  1634. {
  1635. struct pci_dev *pdev = NULL;
  1636. int nbridgenum, nbridgeidx, i;
  1637. static const unsigned short nbridgeids[] = {
  1638. PCI_DEVICE_ID_SI_540, /* for SiS 540 VGA */
  1639. PCI_DEVICE_ID_SI_630, /* for SiS 630/730 VGA */
  1640. PCI_DEVICE_ID_SI_730,
  1641. PCI_DEVICE_ID_SI_550, /* for SiS 550 VGA */
  1642. PCI_DEVICE_ID_SI_650, /* for SiS 650/651/740 VGA */
  1643. PCI_DEVICE_ID_SI_651,
  1644. PCI_DEVICE_ID_SI_740,
  1645. PCI_DEVICE_ID_SI_661, /* for SiS 661/741/660/760/761 VGA */
  1646. PCI_DEVICE_ID_SI_741,
  1647. PCI_DEVICE_ID_SI_660,
  1648. PCI_DEVICE_ID_SI_760,
  1649. PCI_DEVICE_ID_SI_761
  1650. };
  1651. switch(basechipid) {
  1652. #ifdef CONFIG_FB_SIS_300
  1653. case SIS_540: nbridgeidx = 0; nbridgenum = 1; break;
  1654. case SIS_630: nbridgeidx = 1; nbridgenum = 2; break;
  1655. #endif
  1656. #ifdef CONFIG_FB_SIS_315
  1657. case SIS_550: nbridgeidx = 3; nbridgenum = 1; break;
  1658. case SIS_650: nbridgeidx = 4; nbridgenum = 3; break;
  1659. case SIS_660: nbridgeidx = 7; nbridgenum = 5; break;
  1660. #endif
  1661. default: return NULL;
  1662. }
  1663. for(i = 0; i < nbridgenum; i++) {
  1664. if((pdev = pci_get_device(PCI_VENDOR_ID_SI,
  1665. nbridgeids[nbridgeidx+i], NULL)))
  1666. break;
  1667. }
  1668. return pdev;
  1669. }
  1670. static int sisfb_get_dram_size(struct sis_video_info *ivideo)
  1671. {
  1672. #if defined(CONFIG_FB_SIS_300) || defined(CONFIG_FB_SIS_315)
  1673. u8 reg;
  1674. #endif
  1675. ivideo->video_size = 0;
  1676. ivideo->UMAsize = ivideo->LFBsize = 0;
  1677. switch(ivideo->chip) {
  1678. #ifdef CONFIG_FB_SIS_300
  1679. case SIS_300:
  1680. reg = SiS_GetReg(SISSR, 0x14);
  1681. ivideo->video_size = ((reg & 0x3F) + 1) << 20;
  1682. break;
  1683. case SIS_540:
  1684. case SIS_630:
  1685. case SIS_730:
  1686. if(!ivideo->nbridge)
  1687. return -1;
  1688. pci_read_config_byte(ivideo->nbridge, 0x63, &reg);
  1689. ivideo->video_size = 1 << (((reg & 0x70) >> 4) + 21);
  1690. break;
  1691. #endif
  1692. #ifdef CONFIG_FB_SIS_315
  1693. case SIS_315H:
  1694. case SIS_315PRO:
  1695. case SIS_315:
  1696. reg = SiS_GetReg(SISSR, 0x14);
  1697. ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20;
  1698. switch((reg >> 2) & 0x03) {
  1699. case 0x01:
  1700. case 0x03:
  1701. ivideo->video_size <<= 1;
  1702. break;
  1703. case 0x02:
  1704. ivideo->video_size += (ivideo->video_size/2);
  1705. }
  1706. break;
  1707. case SIS_330:
  1708. reg = SiS_GetReg(SISSR, 0x14);
  1709. ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20;
  1710. if(reg & 0x0c) ivideo->video_size <<= 1;
  1711. break;
  1712. case SIS_550:
  1713. case SIS_650:
  1714. case SIS_740:
  1715. reg = SiS_GetReg(SISSR, 0x14);
  1716. ivideo->video_size = (((reg & 0x3f) + 1) << 2) << 20;
  1717. break;
  1718. case SIS_661:
  1719. case SIS_741:
  1720. reg = SiS_GetReg(SISCR, 0x79);
  1721. ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20;
  1722. break;
  1723. case SIS_660:
  1724. case SIS_760:
  1725. case SIS_761:
  1726. reg = SiS_GetReg(SISCR, 0x79);
  1727. reg = (reg & 0xf0) >> 4;
  1728. if(reg) {
  1729. ivideo->video_size = (1 << reg) << 20;
  1730. ivideo->UMAsize = ivideo->video_size;
  1731. }
  1732. reg = SiS_GetReg(SISCR, 0x78);
  1733. reg &= 0x30;
  1734. if(reg) {
  1735. if(reg == 0x10) {
  1736. ivideo->LFBsize = (32 << 20);
  1737. } else {
  1738. ivideo->LFBsize = (64 << 20);
  1739. }
  1740. ivideo->video_size += ivideo->LFBsize;
  1741. }
  1742. break;
  1743. case SIS_340:
  1744. case XGI_20:
  1745. case XGI_40:
  1746. reg = SiS_GetReg(SISSR, 0x14);
  1747. ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20;
  1748. if(ivideo->chip != XGI_20) {
  1749. reg = (reg & 0x0c) >> 2;
  1750. if(ivideo->revision_id == 2) {
  1751. if(reg & 0x01) reg = 0x02;
  1752. else reg = 0x00;
  1753. }
  1754. if(reg == 0x02) ivideo->video_size <<= 1;
  1755. else if(reg == 0x03) ivideo->video_size <<= 2;
  1756. }
  1757. break;
  1758. #endif
  1759. default:
  1760. return -1;
  1761. }
  1762. return 0;
  1763. }
  1764. /* -------------- video bridge device detection --------------- */
  1765. static void sisfb_detect_VB_connect(struct sis_video_info *ivideo)
  1766. {
  1767. u8 cr32, temp;
  1768. /* No CRT2 on XGI Z7 */
  1769. if(ivideo->chip == XGI_20) {
  1770. ivideo->sisfb_crt1off = 0;
  1771. return;
  1772. }
  1773. #ifdef CONFIG_FB_SIS_300
  1774. if(ivideo->sisvga_engine == SIS_300_VGA) {
  1775. temp = SiS_GetReg(SISSR, 0x17);
  1776. if((temp & 0x0F) && (ivideo->chip != SIS_300)) {
  1777. /* PAL/NTSC is stored on SR16 on such machines */
  1778. if(!(ivideo->vbflags & (TV_PAL | TV_NTSC | TV_PALM | TV_PALN))) {
  1779. temp = SiS_GetReg(SISSR, 0x16);
  1780. if(temp & 0x20)
  1781. ivideo->vbflags |= TV_PAL;
  1782. else
  1783. ivideo->vbflags |= TV_NTSC;
  1784. }
  1785. }
  1786. }
  1787. #endif
  1788. cr32 = SiS_GetReg(SISCR, 0x32);
  1789. if(cr32 & SIS_CRT1) {
  1790. ivideo->sisfb_crt1off = 0;
  1791. } else {
  1792. ivideo->sisfb_crt1off = (cr32 & 0xDF) ? 1 : 0;
  1793. }
  1794. ivideo->vbflags &= ~(CRT2_TV | CRT2_LCD | CRT2_VGA);
  1795. if(cr32 & SIS_VB_TV) ivideo->vbflags |= CRT2_TV;
  1796. if(cr32 & SIS_VB_LCD) ivideo->vbflags |= CRT2_LCD;
  1797. if(cr32 & SIS_VB_CRT2) ivideo->vbflags |= CRT2_VGA;
  1798. /* Check given parms for hardware compatibility.
  1799. * (Cannot do this in the search_xx routines since we don't
  1800. * know what hardware we are running on then)
  1801. */
  1802. if(ivideo->chip != SIS_550) {
  1803. ivideo->sisfb_dstn = ivideo->sisfb_fstn = 0;
  1804. }
  1805. if(ivideo->sisfb_tvplug != -1) {
  1806. if( (ivideo->sisvga_engine != SIS_315_VGA) ||
  1807. (!(ivideo->vbflags2 & VB2_SISYPBPRBRIDGE)) ) {
  1808. if(ivideo->sisfb_tvplug & TV_YPBPR) {
  1809. ivideo->sisfb_tvplug = -1;
  1810. printk(KERN_ERR "sisfb: YPbPr not supported\n");
  1811. }
  1812. }
  1813. }
  1814. if(ivideo->sisfb_tvplug != -1) {
  1815. if( (ivideo->sisvga_engine != SIS_315_VGA) ||
  1816. (!(ivideo->vbflags2 & VB2_SISHIVISIONBRIDGE)) ) {
  1817. if(ivideo->sisfb_tvplug & TV_HIVISION) {
  1818. ivideo->sisfb_tvplug = -1;
  1819. printk(KERN_ERR "sisfb: HiVision not supported\n");
  1820. }
  1821. }
  1822. }
  1823. if(ivideo->sisfb_tvstd != -1) {
  1824. if( (!(ivideo->vbflags2 & VB2_SISBRIDGE)) &&
  1825. (!((ivideo->sisvga_engine == SIS_315_VGA) &&
  1826. (ivideo->vbflags2 & VB2_CHRONTEL))) ) {
  1827. if(ivideo->sisfb_tvstd & (TV_PALM | TV_PALN | TV_NTSCJ)) {
  1828. ivideo->sisfb_tvstd = -1;
  1829. printk(KERN_ERR "sisfb: PALM/PALN/NTSCJ not supported\n");
  1830. }
  1831. }
  1832. }
  1833. /* Detect/set TV plug & type */
  1834. if(ivideo->sisfb_tvplug != -1) {
  1835. ivideo->vbflags |= ivideo->sisfb_tvplug;
  1836. } else {
  1837. if(cr32 & SIS_VB_YPBPR) ivideo->vbflags |= (TV_YPBPR|TV_YPBPR525I); /* default: 480i */
  1838. else if(cr32 & SIS_VB_HIVISION) ivideo->vbflags |= TV_HIVISION;
  1839. else if(cr32 & SIS_VB_SCART) ivideo->vbflags |= TV_SCART;
  1840. else {
  1841. if(cr32 & SIS_VB_SVIDEO) ivideo->vbflags |= TV_SVIDEO;
  1842. if(cr32 & SIS_VB_COMPOSITE) ivideo->vbflags |= TV_AVIDEO;
  1843. }
  1844. }
  1845. if(!(ivideo->vbflags & (TV_YPBPR | TV_HIVISION))) {
  1846. if(ivideo->sisfb_tvstd != -1) {
  1847. ivideo->vbflags &= ~(TV_NTSC | TV_PAL | TV_PALM | TV_PALN | TV_NTSCJ);
  1848. ivideo->vbflags |= ivideo->sisfb_tvstd;
  1849. }
  1850. if(ivideo->vbflags & TV_SCART) {
  1851. ivideo->vbflags &= ~(TV_NTSC | TV_PALM | TV_PALN | TV_NTSCJ);
  1852. ivideo->vbflags |= TV_PAL;
  1853. }
  1854. if(!(ivideo->vbflags & (TV_PAL | TV_NTSC | TV_PALM | TV_PALN | TV_NTSCJ))) {
  1855. if(ivideo->sisvga_engine == SIS_300_VGA) {
  1856. temp = SiS_GetReg(SISSR, 0x38);
  1857. if(temp & 0x01) ivideo->vbflags |= TV_PAL;
  1858. else ivideo->vbflags |= TV_NTSC;
  1859. } else if((ivideo->chip <= SIS_315PRO) || (ivideo->chip >= SIS_330)) {
  1860. temp = SiS_GetReg(SISSR, 0x38);
  1861. if(temp & 0x01) ivideo->vbflags |= TV_PAL;
  1862. else ivideo->vbflags |= TV_NTSC;
  1863. } else {
  1864. temp = SiS_GetReg(SISCR, 0x79);
  1865. if(temp & 0x20) ivideo->vbflags |= TV_PAL;
  1866. else ivideo->vbflags |= TV_NTSC;
  1867. }
  1868. }
  1869. }
  1870. /* Copy forceCRT1 option to CRT1off if option is given */
  1871. if(ivideo->sisfb_forcecrt1 != -1) {
  1872. ivideo->sisfb_crt1off = (ivideo->sisfb_forcecrt1) ? 0 : 1;
  1873. }
  1874. }
  1875. /* ------------------ Sensing routines ------------------ */
  1876. static bool sisfb_test_DDC1(struct sis_video_info *ivideo)
  1877. {
  1878. unsigned short old;
  1879. int count = 48;
  1880. old = SiS_ReadDDC1Bit(&ivideo->SiS_Pr);
  1881. do {
  1882. if(old != SiS_ReadDDC1Bit(&ivideo->SiS_Pr)) break;
  1883. } while(count--);
  1884. return (count != -1);
  1885. }
  1886. static void sisfb_sense_crt1(struct sis_video_info *ivideo)
  1887. {
  1888. bool mustwait = false;
  1889. u8 sr1F, cr17;
  1890. #ifdef CONFIG_FB_SIS_315
  1891. u8 cr63=0;
  1892. #endif
  1893. u16 temp = 0xffff;
  1894. int i;
  1895. sr1F = SiS_GetReg(SISSR, 0x1F);
  1896. SiS_SetRegOR(SISSR, 0x1F, 0x04);
  1897. SiS_SetRegAND(SISSR, 0x1F, 0x3F);
  1898. if(sr1F & 0xc0) mustwait = true;
  1899. #ifdef CONFIG_FB_SIS_315
  1900. if(ivideo->sisvga_engine == SIS_315_VGA) {
  1901. cr63 = SiS_GetReg(SISCR, ivideo->SiS_Pr.SiS_MyCR63);
  1902. cr63 &= 0x40;
  1903. SiS_SetRegAND(SISCR, ivideo->SiS_Pr.SiS_MyCR63, 0xBF);
  1904. }
  1905. #endif
  1906. cr17 = SiS_GetReg(SISCR, 0x17);
  1907. cr17 &= 0x80;
  1908. if(!cr17) {
  1909. SiS_SetRegOR(SISCR, 0x17, 0x80);
  1910. mustwait = true;
  1911. SiS_SetReg(SISSR, 0x00, 0x01);
  1912. SiS_SetReg(SISSR, 0x00, 0x03);
  1913. }
  1914. if(mustwait) {
  1915. for(i=0; i < 10; i++) sisfbwaitretracecrt1(ivideo);
  1916. }
  1917. #ifdef CONFIG_FB_SIS_315
  1918. if(ivideo->chip >= SIS_330) {
  1919. SiS_SetRegAND(SISCR, 0x32, ~0x20);
  1920. if(ivideo->chip >= SIS_340) {
  1921. SiS_SetReg(SISCR, 0x57, 0x4a);
  1922. } else {
  1923. SiS_SetReg(SISCR, 0x57, 0x5f);
  1924. }
  1925. SiS_SetRegOR(SISCR, 0x53, 0x02);
  1926. while ((SiS_GetRegByte(SISINPSTAT)) & 0x01) break;
  1927. while (!((SiS_GetRegByte(SISINPSTAT)) & 0x01)) break;
  1928. if ((SiS_GetRegByte(SISMISCW)) & 0x10) temp = 1;
  1929. SiS_SetRegAND(SISCR, 0x53, 0xfd);
  1930. SiS_SetRegAND(SISCR, 0x57, 0x00);
  1931. }
  1932. #endif
  1933. if(temp == 0xffff) {
  1934. i = 3;
  1935. do {
  1936. temp = SiS_HandleDDC(&ivideo->SiS_Pr, ivideo->vbflags,
  1937. ivideo->sisvga_engine, 0, 0, NULL, ivideo->vbflags2);
  1938. } while(((temp == 0) || (temp == 0xffff)) && i--);
  1939. if((temp == 0) || (temp == 0xffff)) {
  1940. if(sisfb_test_DDC1(ivideo)) temp = 1;
  1941. }
  1942. }
  1943. if((temp) && (temp != 0xffff)) {
  1944. SiS_SetRegOR(SISCR, 0x32, 0x20);
  1945. }
  1946. #ifdef CONFIG_FB_SIS_315
  1947. if(ivideo->sisvga_engine == SIS_315_VGA) {
  1948. SiS_SetRegANDOR(SISCR, ivideo->SiS_Pr.SiS_MyCR63, 0xBF, cr63);
  1949. }
  1950. #endif
  1951. SiS_SetRegANDOR(SISCR, 0x17, 0x7F, cr17);
  1952. SiS_SetReg(SISSR, 0x1F, sr1F);
  1953. }
  1954. /* Determine and detect attached devices on SiS30x */
  1955. static void SiS_SenseLCD(struct sis_video_info *ivideo)
  1956. {
  1957. unsigned char buffer[256];
  1958. unsigned short temp, realcrtno, i;
  1959. u8 reg, cr37 = 0, paneltype = 0;
  1960. u16 xres, yres;
  1961. ivideo->SiS_Pr.PanelSelfDetected = false;
  1962. /* LCD detection only for TMDS bridges */
  1963. if(!(ivideo->vbflags2 & VB2_SISTMDSBRIDGE))
  1964. return;
  1965. if(ivideo->vbflags2 & VB2_30xBDH)
  1966. return;
  1967. /* If LCD already set up by BIOS, skip it */
  1968. reg = SiS_GetReg(SISCR, 0x32);
  1969. if(reg & 0x08)
  1970. return;
  1971. realcrtno = 1;
  1972. if(ivideo->SiS_Pr.DDCPortMixup)
  1973. realcrtno = 0;
  1974. /* Check DDC capabilities */
  1975. temp = SiS_HandleDDC(&ivideo->SiS_Pr, ivideo->vbflags, ivideo->sisvga_engine,
  1976. realcrtno, 0, &buffer[0], ivideo->vbflags2);
  1977. if((!temp) || (temp == 0xffff) || (!(temp & 0x02)))
  1978. return;
  1979. /* Read DDC data */
  1980. i = 3; /* Number of retrys */
  1981. do {
  1982. temp = SiS_HandleDDC(&ivideo->SiS_Pr, ivideo->vbflags,
  1983. ivideo->sisvga_engine, realcrtno, 1,
  1984. &buffer[0], ivideo->vbflags2);
  1985. } while((temp) && i--);
  1986. if(temp)
  1987. return;
  1988. /* No digital device */
  1989. if(!(buffer[0x14] & 0x80))
  1990. return;
  1991. /* First detailed timing preferred timing? */
  1992. if(!(buffer[0x18] & 0x02))
  1993. return;
  1994. xres = buffer[0x38] | ((buffer[0x3a] & 0xf0) << 4);
  1995. yres = buffer[0x3b] | ((buffer[0x3d] & 0xf0) << 4);
  1996. switch(xres) {
  1997. case 1024:
  1998. if(yres == 768)
  1999. paneltype = 0x02;
  2000. break;
  2001. case 1280:
  2002. if(yres == 1024)
  2003. paneltype = 0x03;
  2004. break;
  2005. case 1600:
  2006. if((yres == 1200) && (ivideo->vbflags2 & VB2_30xC))
  2007. paneltype = 0x0b;
  2008. break;
  2009. }
  2010. if(!paneltype)
  2011. return;
  2012. if(buffer[0x23])
  2013. cr37 |= 0x10;
  2014. if((buffer[0x47] & 0x18) == 0x18)
  2015. cr37 |= ((((buffer[0x47] & 0x06) ^ 0x06) << 5) | 0x20);
  2016. else
  2017. cr37 |= 0xc0;
  2018. SiS_SetReg(SISCR, 0x36, paneltype);
  2019. cr37 &= 0xf1;
  2020. SiS_SetRegANDOR(SISCR, 0x37, 0x0c, cr37);
  2021. SiS_SetRegOR(SISCR, 0x32, 0x08);
  2022. ivideo->SiS_Pr.PanelSelfDetected = true;
  2023. }
  2024. static int SISDoSense(struct sis_video_info *ivideo, u16 type, u16 test)
  2025. {
  2026. int temp, mytest, result, i, j;
  2027. for(j = 0; j < 10; j++) {
  2028. result = 0;
  2029. for(i = 0; i < 3; i++) {
  2030. mytest = test;
  2031. SiS_SetReg(SISPART4, 0x11, (type & 0x00ff));
  2032. temp = (type >> 8) | (mytest & 0x00ff);
  2033. SiS_SetRegANDOR(SISPART4, 0x10, 0xe0, temp);
  2034. SiS_DDC2Delay(&ivideo->SiS_Pr, 0x1500);
  2035. mytest >>= 8;
  2036. mytest &= 0x7f;
  2037. temp = SiS_GetReg(SISPART4, 0x03);
  2038. temp ^= 0x0e;
  2039. temp &= mytest;
  2040. if(temp == mytest) result++;
  2041. #if 1
  2042. SiS_SetReg(SISPART4, 0x11, 0x00);
  2043. SiS_SetRegAND(SISPART4, 0x10, 0xe0);
  2044. SiS_DDC2Delay(&ivideo->SiS_Pr, 0x1000);
  2045. #endif
  2046. }
  2047. if((result == 0) || (result >= 2)) break;
  2048. }
  2049. return result;
  2050. }
  2051. static void SiS_Sense30x(struct sis_video_info *ivideo)
  2052. {
  2053. u8 backupP4_0d,backupP2_00,backupP2_4d,backupSR_1e,biosflag=0;
  2054. u16 svhs=0, svhs_c=0;
  2055. u16 cvbs=0, cvbs_c=0;
  2056. u16 vga2=0, vga2_c=0;
  2057. int myflag, result;
  2058. char stdstr[] = "sisfb: Detected";
  2059. char tvstr[] = "TV connected to";
  2060. if(ivideo->vbflags2 & VB2_301) {
  2061. svhs = 0x00b9; cvbs = 0x00b3; vga2 = 0x00d1;
  2062. myflag = SiS_GetReg(SISPART4, 0x01);
  2063. if(myflag & 0x04) {
  2064. svhs = 0x00dd; cvbs = 0x00ee; vga2 = 0x00fd;
  2065. }
  2066. } else if(ivideo->vbflags2 & (VB2_301B | VB2_302B)) {
  2067. svhs = 0x016b; cvbs = 0x0174; vga2 = 0x0190;
  2068. } else if(ivideo->vbflags2 & (VB2_301LV | VB2_302LV)) {
  2069. svhs = 0x0200; cvbs = 0x0100;
  2070. } else if(ivideo->vbflags2 & (VB2_301C | VB2_302ELV | VB2_307T | VB2_307LV)) {
  2071. svhs = 0x016b; cvbs = 0x0110; vga2 = 0x0190;
  2072. } else
  2073. return;
  2074. vga2_c = 0x0e08; svhs_c = 0x0404; cvbs_c = 0x0804;
  2075. if(ivideo->vbflags & (VB2_301LV|VB2_302LV|VB2_302ELV|VB2_307LV)) {
  2076. svhs_c = 0x0408; cvbs_c = 0x0808;
  2077. }
  2078. biosflag = 2;
  2079. if(ivideo->haveXGIROM) {
  2080. biosflag = ivideo->bios_abase[0x58] & 0x03;
  2081. } else if(ivideo->newrom) {
  2082. if(ivideo->bios_abase[0x5d] & 0x04) biosflag |= 0x01;
  2083. } else if(ivideo->sisvga_engine == SIS_300_VGA) {
  2084. if(ivideo->bios_abase) {
  2085. biosflag = ivideo->bios_abase[0xfe] & 0x03;
  2086. }
  2087. }
  2088. if(ivideo->chip == SIS_300) {
  2089. myflag = SiS_GetReg(SISSR, 0x3b);
  2090. if(!(myflag & 0x01)) vga2 = vga2_c = 0;
  2091. }
  2092. if(!(ivideo->vbflags2 & VB2_SISVGA2BRIDGE)) {
  2093. vga2 = vga2_c = 0;
  2094. }
  2095. backupSR_1e = SiS_GetReg(SISSR, 0x1e);
  2096. SiS_SetRegOR(SISSR, 0x1e, 0x20);
  2097. backupP4_0d = SiS_GetReg(SISPART4, 0x0d);
  2098. if(ivideo->vbflags2 & VB2_30xC) {
  2099. SiS_SetRegANDOR(SISPART4, 0x0d, ~0x07, 0x01);
  2100. } else {
  2101. SiS_SetRegOR(SISPART4, 0x0d, 0x04);
  2102. }
  2103. SiS_DDC2Delay(&ivideo->SiS_Pr, 0x2000);
  2104. backupP2_00 = SiS_GetReg(SISPART2, 0x00);
  2105. SiS_SetReg(SISPART2, 0x00, ((backupP2_00 | 0x1c) & 0xfc));
  2106. backupP2_4d = SiS_GetReg(SISPART2, 0x4d);
  2107. if(ivideo->vbflags2 & VB2_SISYPBPRBRIDGE) {
  2108. SiS_SetReg(SISPART2, 0x4d, (backupP2_4d & ~0x10));
  2109. }
  2110. if(!(ivideo->vbflags2 & VB2_30xCLV)) {
  2111. SISDoSense(ivideo, 0, 0);
  2112. }
  2113. SiS_SetRegAND(SISCR, 0x32, ~0x14);
  2114. if(vga2_c || vga2) {
  2115. if(SISDoSense(ivideo, vga2, vga2_c)) {
  2116. if(biosflag & 0x01) {
  2117. printk(KERN_INFO "%s %s SCART output\n", stdstr, tvstr);
  2118. SiS_SetRegOR(SISCR, 0x32, 0x04);
  2119. } else {
  2120. printk(KERN_INFO "%s secondary VGA connection\n", stdstr);
  2121. SiS_SetRegOR(SISCR, 0x32, 0x10);
  2122. }
  2123. }
  2124. }
  2125. SiS_SetRegAND(SISCR, 0x32, 0x3f);
  2126. if(ivideo->vbflags2 & VB2_30xCLV) {
  2127. SiS_SetRegOR(SISPART4, 0x0d, 0x04);
  2128. }
  2129. if((ivideo->sisvga_engine == SIS_315_VGA) && (ivideo->vbflags2 & VB2_SISYPBPRBRIDGE)) {
  2130. SiS_SetReg(SISPART2, 0x4d, (backupP2_4d | 0x10));
  2131. SiS_DDC2Delay(&ivideo->SiS_Pr, 0x2000);
  2132. if((result = SISDoSense(ivideo, svhs, 0x0604))) {
  2133. if((result = SISDoSense(ivideo, cvbs, 0x0804))) {
  2134. printk(KERN_INFO "%s %s YPbPr component output\n", stdstr, tvstr);
  2135. SiS_SetRegOR(SISCR, 0x32, 0x80);
  2136. }
  2137. }
  2138. SiS_SetReg(SISPART2, 0x4d, backupP2_4d);
  2139. }
  2140. SiS_SetRegAND(SISCR, 0x32, ~0x03);
  2141. if(!(ivideo->vbflags & TV_YPBPR)) {
  2142. if((result = SISDoSense(ivideo, svhs, svhs_c))) {
  2143. printk(KERN_INFO "%s %s SVIDEO output\n", stdstr, tvstr);
  2144. SiS_SetRegOR(SISCR, 0x32, 0x02);
  2145. }
  2146. if((biosflag & 0x02) || (!result)) {
  2147. if(SISDoSense(ivideo, cvbs, cvbs_c)) {
  2148. printk(KERN_INFO "%s %s COMPOSITE output\n", stdstr, tvstr);
  2149. SiS_SetRegOR(SISCR, 0x32, 0x01);
  2150. }
  2151. }
  2152. }
  2153. SISDoSense(ivideo, 0, 0);
  2154. SiS_SetReg(SISPART2, 0x00, backupP2_00);
  2155. SiS_SetReg(SISPART4, 0x0d, backupP4_0d);
  2156. SiS_SetReg(SISSR, 0x1e, backupSR_1e);
  2157. if(ivideo->vbflags2 & VB2_30xCLV) {
  2158. biosflag = SiS_GetReg(SISPART2, 0x00);
  2159. if(biosflag & 0x20) {
  2160. for(myflag = 2; myflag > 0; myflag--) {
  2161. biosflag ^= 0x20;
  2162. SiS_SetReg(SISPART2, 0x00, biosflag);
  2163. }
  2164. }
  2165. }
  2166. SiS_SetReg(SISPART2, 0x00, backupP2_00);
  2167. }
  2168. /* Determine and detect attached TV's on Chrontel */
  2169. static void SiS_SenseCh(struct sis_video_info *ivideo)
  2170. {
  2171. #if defined(CONFIG_FB_SIS_300) || defined(CONFIG_FB_SIS_315)
  2172. u8 temp1, temp2;
  2173. char stdstr[] = "sisfb: Chrontel: Detected TV connected to";
  2174. #endif
  2175. #ifdef CONFIG_FB_SIS_300
  2176. unsigned char test[3];
  2177. int i;
  2178. #endif
  2179. if(ivideo->chip < SIS_315H) {
  2180. #ifdef CONFIG_FB_SIS_300
  2181. ivideo->SiS_Pr.SiS_IF_DEF_CH70xx = 1; /* Chrontel 700x */
  2182. SiS_SetChrontelGPIO(&ivideo->SiS_Pr, 0x9c); /* Set general purpose IO for Chrontel communication */
  2183. SiS_DDC2Delay(&ivideo->SiS_Pr, 1000);
  2184. temp1 = SiS_GetCH700x(&ivideo->SiS_Pr, 0x25);
  2185. /* See Chrontel TB31 for explanation */
  2186. temp2 = SiS_GetCH700x(&ivideo->SiS_Pr, 0x0e);
  2187. if(((temp2 & 0x07) == 0x01) || (temp2 & 0x04)) {
  2188. SiS_SetCH700x(&ivideo->SiS_Pr, 0x0e, 0x0b);
  2189. SiS_DDC2Delay(&ivideo->SiS_Pr, 300);
  2190. }
  2191. temp2 = SiS_GetCH700x(&ivideo->SiS_Pr, 0x25);
  2192. if(temp2 != temp1) temp1 = temp2;
  2193. if((temp1 >= 0x22) && (temp1 <= 0x50)) {
  2194. /* Read power status */
  2195. temp1 = SiS_GetCH700x(&ivideo->SiS_Pr, 0x0e);
  2196. if((temp1 & 0x03) != 0x03) {
  2197. /* Power all outputs */
  2198. SiS_SetCH700x(&ivideo->SiS_Pr, 0x0e,0x0b);
  2199. SiS_DDC2Delay(&ivideo->SiS_Pr, 300);
  2200. }
  2201. /* Sense connected TV devices */
  2202. for(i = 0; i < 3; i++) {
  2203. SiS_SetCH700x(&ivideo->SiS_Pr, 0x10, 0x01);
  2204. SiS_DDC2Delay(&ivideo->SiS_Pr, 0x96);
  2205. SiS_SetCH700x(&ivideo->SiS_Pr, 0x10, 0x00);
  2206. SiS_DDC2Delay(&ivideo->SiS_Pr, 0x96);
  2207. temp1 = SiS_GetCH700x(&ivideo->SiS_Pr, 0x10);
  2208. if(!(temp1 & 0x08)) test[i] = 0x02;
  2209. else if(!(temp1 & 0x02)) test[i] = 0x01;
  2210. else test[i] = 0;
  2211. SiS_DDC2Delay(&ivideo->SiS_Pr, 0x96);
  2212. }
  2213. if(test[0] == test[1]) temp1 = test[0];
  2214. else if(test[0] == test[2]) temp1 = test[0];
  2215. else if(test[1] == test[2]) temp1 = test[1];
  2216. else {
  2217. printk(KERN_INFO
  2218. "sisfb: TV detection unreliable - test results varied\n");
  2219. temp1 = test[2];
  2220. }
  2221. if(temp1 == 0x02) {
  2222. printk(KERN_INFO "%s SVIDEO output\n", stdstr);
  2223. ivideo->vbflags |= TV_SVIDEO;
  2224. SiS_SetRegOR(SISCR, 0x32, 0x02);
  2225. SiS_SetRegAND(SISCR, 0x32, ~0x05);
  2226. } else if (temp1 == 0x01) {
  2227. printk(KERN_INFO "%s CVBS output\n", stdstr);
  2228. ivideo->vbflags |= TV_AVIDEO;
  2229. SiS_SetRegOR(SISCR, 0x32, 0x01);
  2230. SiS_SetRegAND(SISCR, 0x32, ~0x06);
  2231. } else {
  2232. SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x0e, 0x01, 0xF8);
  2233. SiS_SetRegAND(SISCR, 0x32, ~0x07);
  2234. }
  2235. } else if(temp1 == 0) {
  2236. SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x0e, 0x01, 0xF8);
  2237. SiS_SetRegAND(SISCR, 0x32, ~0x07);
  2238. }
  2239. /* Set general purpose IO for Chrontel communication */
  2240. SiS_SetChrontelGPIO(&ivideo->SiS_Pr, 0x00);
  2241. #endif
  2242. } else {
  2243. #ifdef CONFIG_FB_SIS_315
  2244. ivideo->SiS_Pr.SiS_IF_DEF_CH70xx = 2; /* Chrontel 7019 */
  2245. temp1 = SiS_GetCH701x(&ivideo->SiS_Pr, 0x49);
  2246. SiS_SetCH701x(&ivideo->SiS_Pr, 0x49, 0x20);
  2247. SiS_DDC2Delay(&ivideo->SiS_Pr, 0x96);
  2248. temp2 = SiS_GetCH701x(&ivideo->SiS_Pr, 0x20);
  2249. temp2 |= 0x01;
  2250. SiS_SetCH701x(&ivideo->SiS_Pr, 0x20, temp2);
  2251. SiS_DDC2Delay(&ivideo->SiS_Pr, 0x96);
  2252. temp2 ^= 0x01;
  2253. SiS_SetCH701x(&ivideo->SiS_Pr, 0x20, temp2);
  2254. SiS_DDC2Delay(&ivideo->SiS_Pr, 0x96);
  2255. temp2 = SiS_GetCH701x(&ivideo->SiS_Pr, 0x20);
  2256. SiS_SetCH701x(&ivideo->SiS_Pr, 0x49, temp1);
  2257. temp1 = 0;
  2258. if(temp2 & 0x02) temp1 |= 0x01;
  2259. if(temp2 & 0x10) temp1 |= 0x01;
  2260. if(temp2 & 0x04) temp1 |= 0x02;
  2261. if( (temp1 & 0x01) && (temp1 & 0x02) ) temp1 = 0x04;
  2262. switch(temp1) {
  2263. case 0x01:
  2264. printk(KERN_INFO "%s CVBS output\n", stdstr);
  2265. ivideo->vbflags |= TV_AVIDEO;
  2266. SiS_SetRegOR(SISCR, 0x32, 0x01);
  2267. SiS_SetRegAND(SISCR, 0x32, ~0x06);
  2268. break;
  2269. case 0x02:
  2270. printk(KERN_INFO "%s SVIDEO output\n", stdstr);
  2271. ivideo->vbflags |= TV_SVIDEO;
  2272. SiS_SetRegOR(SISCR, 0x32, 0x02);
  2273. SiS_SetRegAND(SISCR, 0x32, ~0x05);
  2274. break;
  2275. case 0x04:
  2276. printk(KERN_INFO "%s SCART output\n", stdstr);
  2277. SiS_SetRegOR(SISCR, 0x32, 0x04);
  2278. SiS_SetRegAND(SISCR, 0x32, ~0x03);
  2279. break;
  2280. default:
  2281. SiS_SetRegAND(SISCR, 0x32, ~0x07);
  2282. }
  2283. #endif
  2284. }
  2285. }
  2286. static void sisfb_get_VB_type(struct sis_video_info *ivideo)
  2287. {
  2288. char stdstr[] = "sisfb: Detected";
  2289. char bridgestr[] = "video bridge";
  2290. u8 vb_chipid;
  2291. u8 reg;
  2292. /* No CRT2 on XGI Z7 */
  2293. if(ivideo->chip == XGI_20)
  2294. return;
  2295. vb_chipid = SiS_GetReg(SISPART4, 0x00);
  2296. switch(vb_chipid) {
  2297. case 0x01:
  2298. reg = SiS_GetReg(SISPART4, 0x01);
  2299. if(reg < 0xb0) {
  2300. ivideo->vbflags |= VB_301; /* Deprecated */
  2301. ivideo->vbflags2 |= VB2_301;
  2302. printk(KERN_INFO "%s SiS301 %s\n", stdstr, bridgestr);
  2303. } else if(reg < 0xc0) {
  2304. ivideo->vbflags |= VB_301B; /* Deprecated */
  2305. ivideo->vbflags2 |= VB2_301B;
  2306. reg = SiS_GetReg(SISPART4, 0x23);
  2307. if(!(reg & 0x02)) {
  2308. ivideo->vbflags |= VB_30xBDH; /* Deprecated */
  2309. ivideo->vbflags2 |= VB2_30xBDH;
  2310. printk(KERN_INFO "%s SiS301B-DH %s\n", stdstr, bridgestr);
  2311. } else {
  2312. printk(KERN_INFO "%s SiS301B %s\n", stdstr, bridgestr);
  2313. }
  2314. } else if(reg < 0xd0) {
  2315. ivideo->vbflags |= VB_301C; /* Deprecated */
  2316. ivideo->vbflags2 |= VB2_301C;
  2317. printk(KERN_INFO "%s SiS301C %s\n", stdstr, bridgestr);
  2318. } else if(reg < 0xe0) {
  2319. ivideo->vbflags |= VB_301LV; /* Deprecated */
  2320. ivideo->vbflags2 |= VB2_301LV;
  2321. printk(KERN_INFO "%s SiS301LV %s\n", stdstr, bridgestr);
  2322. } else if(reg <= 0xe1) {
  2323. reg = SiS_GetReg(SISPART4, 0x39);
  2324. if(reg == 0xff) {
  2325. ivideo->vbflags |= VB_302LV; /* Deprecated */
  2326. ivideo->vbflags2 |= VB2_302LV;
  2327. printk(KERN_INFO "%s SiS302LV %s\n", stdstr, bridgestr);
  2328. } else {
  2329. ivideo->vbflags |= VB_301C; /* Deprecated */
  2330. ivideo->vbflags2 |= VB2_301C;
  2331. printk(KERN_INFO "%s SiS301C(P4) %s\n", stdstr, bridgestr);
  2332. #if 0
  2333. ivideo->vbflags |= VB_302ELV; /* Deprecated */
  2334. ivideo->vbflags2 |= VB2_302ELV;
  2335. printk(KERN_INFO "%s SiS302ELV %s\n", stdstr, bridgestr);
  2336. #endif
  2337. }
  2338. }
  2339. break;
  2340. case 0x02:
  2341. ivideo->vbflags |= VB_302B; /* Deprecated */
  2342. ivideo->vbflags2 |= VB2_302B;
  2343. printk(KERN_INFO "%s SiS302B %s\n", stdstr, bridgestr);
  2344. break;
  2345. }
  2346. if((!(ivideo->vbflags2 & VB2_VIDEOBRIDGE)) && (ivideo->chip != SIS_300)) {
  2347. reg = SiS_GetReg(SISCR, 0x37);
  2348. reg &= SIS_EXTERNAL_CHIP_MASK;
  2349. reg >>= 1;
  2350. if(ivideo->sisvga_engine == SIS_300_VGA) {
  2351. #ifdef CONFIG_FB_SIS_300
  2352. switch(reg) {
  2353. case SIS_EXTERNAL_CHIP_LVDS:
  2354. ivideo->vbflags |= VB_LVDS; /* Deprecated */
  2355. ivideo->vbflags2 |= VB2_LVDS;
  2356. break;
  2357. case SIS_EXTERNAL_CHIP_TRUMPION:
  2358. ivideo->vbflags |= (VB_LVDS | VB_TRUMPION); /* Deprecated */
  2359. ivideo->vbflags2 |= (VB2_LVDS | VB2_TRUMPION);
  2360. break;
  2361. case SIS_EXTERNAL_CHIP_CHRONTEL:
  2362. ivideo->vbflags |= VB_CHRONTEL; /* Deprecated */
  2363. ivideo->vbflags2 |= VB2_CHRONTEL;
  2364. break;
  2365. case SIS_EXTERNAL_CHIP_LVDS_CHRONTEL:
  2366. ivideo->vbflags |= (VB_LVDS | VB_CHRONTEL); /* Deprecated */
  2367. ivideo->vbflags2 |= (VB2_LVDS | VB2_CHRONTEL);
  2368. break;
  2369. }
  2370. if(ivideo->vbflags2 & VB2_CHRONTEL) ivideo->chronteltype = 1;
  2371. #endif
  2372. } else if(ivideo->chip < SIS_661) {
  2373. #ifdef CONFIG_FB_SIS_315
  2374. switch (reg) {
  2375. case SIS310_EXTERNAL_CHIP_LVDS:
  2376. ivideo->vbflags |= VB_LVDS; /* Deprecated */
  2377. ivideo->vbflags2 |= VB2_LVDS;
  2378. break;
  2379. case SIS310_EXTERNAL_CHIP_LVDS_CHRONTEL:
  2380. ivideo->vbflags |= (VB_LVDS | VB_CHRONTEL); /* Deprecated */
  2381. ivideo->vbflags2 |= (VB2_LVDS | VB2_CHRONTEL);
  2382. break;
  2383. }
  2384. if(ivideo->vbflags2 & VB2_CHRONTEL) ivideo->chronteltype = 2;
  2385. #endif
  2386. } else if(ivideo->chip >= SIS_661) {
  2387. #ifdef CONFIG_FB_SIS_315
  2388. reg = SiS_GetReg(SISCR, 0x38);
  2389. reg >>= 5;
  2390. switch(reg) {
  2391. case 0x02:
  2392. ivideo->vbflags |= VB_LVDS; /* Deprecated */
  2393. ivideo->vbflags2 |= VB2_LVDS;
  2394. break;
  2395. case 0x03:
  2396. ivideo->vbflags |= (VB_LVDS | VB_CHRONTEL); /* Deprecated */
  2397. ivideo->vbflags2 |= (VB2_LVDS | VB2_CHRONTEL);
  2398. break;
  2399. case 0x04:
  2400. ivideo->vbflags |= (VB_LVDS | VB_CONEXANT); /* Deprecated */
  2401. ivideo->vbflags2 |= (VB2_LVDS | VB2_CONEXANT);
  2402. break;
  2403. }
  2404. if(ivideo->vbflags2 & VB2_CHRONTEL) ivideo->chronteltype = 2;
  2405. #endif
  2406. }
  2407. if(ivideo->vbflags2 & VB2_LVDS) {
  2408. printk(KERN_INFO "%s LVDS transmitter\n", stdstr);
  2409. }
  2410. if((ivideo->sisvga_engine == SIS_300_VGA) && (ivideo->vbflags2 & VB2_TRUMPION)) {
  2411. printk(KERN_INFO "%s Trumpion Zurac LCD scaler\n", stdstr);
  2412. }
  2413. if(ivideo->vbflags2 & VB2_CHRONTEL) {
  2414. printk(KERN_INFO "%s Chrontel TV encoder\n", stdstr);
  2415. }
  2416. if((ivideo->chip >= SIS_661) && (ivideo->vbflags2 & VB2_CONEXANT)) {
  2417. printk(KERN_INFO "%s Conexant external device\n", stdstr);
  2418. }
  2419. }
  2420. if(ivideo->vbflags2 & VB2_SISBRIDGE) {
  2421. SiS_SenseLCD(ivideo);
  2422. SiS_Sense30x(ivideo);
  2423. } else if(ivideo->vbflags2 & VB2_CHRONTEL) {
  2424. SiS_SenseCh(ivideo);
  2425. }
  2426. }
  2427. /* ---------- Engine initialization routines ------------ */
  2428. static void
  2429. sisfb_engine_init(struct sis_video_info *ivideo)
  2430. {
  2431. /* Initialize command queue (we use MMIO only) */
  2432. /* BEFORE THIS IS CALLED, THE ENGINES *MUST* BE SYNC'ED */
  2433. ivideo->caps &= ~(TURBO_QUEUE_CAP |
  2434. MMIO_CMD_QUEUE_CAP |
  2435. VM_CMD_QUEUE_CAP |
  2436. AGP_CMD_QUEUE_CAP);
  2437. #ifdef CONFIG_FB_SIS_300
  2438. if(ivideo->sisvga_engine == SIS_300_VGA) {
  2439. u32 tqueue_pos;
  2440. u8 tq_state;
  2441. tqueue_pos = (ivideo->video_size - ivideo->cmdQueueSize) / (64 * 1024);
  2442. tq_state = SiS_GetReg(SISSR, IND_SIS_TURBOQUEUE_SET);
  2443. tq_state |= 0xf0;
  2444. tq_state &= 0xfc;
  2445. tq_state |= (u8)(tqueue_pos >> 8);
  2446. SiS_SetReg(SISSR, IND_SIS_TURBOQUEUE_SET, tq_state);
  2447. SiS_SetReg(SISSR, IND_SIS_TURBOQUEUE_ADR, (u8)(tqueue_pos & 0xff));
  2448. ivideo->caps |= TURBO_QUEUE_CAP;
  2449. }
  2450. #endif
  2451. #ifdef CONFIG_FB_SIS_315
  2452. if(ivideo->sisvga_engine == SIS_315_VGA) {
  2453. u32 tempq = 0, templ;
  2454. u8 temp;
  2455. if(ivideo->chip == XGI_20) {
  2456. switch(ivideo->cmdQueueSize) {
  2457. case (64 * 1024):
  2458. temp = SIS_CMD_QUEUE_SIZE_Z7_64k;
  2459. break;
  2460. case (128 * 1024):
  2461. default:
  2462. temp = SIS_CMD_QUEUE_SIZE_Z7_128k;
  2463. }
  2464. } else {
  2465. switch(ivideo->cmdQueueSize) {
  2466. case (4 * 1024 * 1024):
  2467. temp = SIS_CMD_QUEUE_SIZE_4M;
  2468. break;
  2469. case (2 * 1024 * 1024):
  2470. temp = SIS_CMD_QUEUE_SIZE_2M;
  2471. break;
  2472. case (1 * 1024 * 1024):
  2473. temp = SIS_CMD_QUEUE_SIZE_1M;
  2474. break;
  2475. default:
  2476. case (512 * 1024):
  2477. temp = SIS_CMD_QUEUE_SIZE_512k;
  2478. }
  2479. }
  2480. SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_THRESHOLD, COMMAND_QUEUE_THRESHOLD);
  2481. SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, SIS_CMD_QUEUE_RESET);
  2482. if((ivideo->chip >= XGI_40) && ivideo->modechanged) {
  2483. /* Must disable dual pipe on XGI_40. Can't do
  2484. * this in MMIO mode, because it requires
  2485. * setting/clearing a bit in the MMIO fire trigger
  2486. * register.
  2487. */
  2488. if(!((templ = MMIO_IN32(ivideo->mmio_vbase, 0x8240)) & (1 << 10))) {
  2489. MMIO_OUT32(ivideo->mmio_vbase, Q_WRITE_PTR, 0);
  2490. SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, (temp | SIS_VRAM_CMDQUEUE_ENABLE));
  2491. tempq = MMIO_IN32(ivideo->mmio_vbase, Q_READ_PTR);
  2492. MMIO_OUT32(ivideo->mmio_vbase, Q_WRITE_PTR, tempq);
  2493. tempq = (u32)(ivideo->video_size - ivideo->cmdQueueSize);
  2494. MMIO_OUT32(ivideo->mmio_vbase, Q_BASE_ADDR, tempq);
  2495. writel(0x16800000 + 0x8240, ivideo->video_vbase + tempq);
  2496. writel(templ | (1 << 10), ivideo->video_vbase + tempq + 4);
  2497. writel(0x168F0000, ivideo->video_vbase + tempq + 8);
  2498. writel(0x168F0000, ivideo->video_vbase + tempq + 12);
  2499. MMIO_OUT32(ivideo->mmio_vbase, Q_WRITE_PTR, (tempq + 16));
  2500. sisfb_syncaccel(ivideo);
  2501. SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, SIS_CMD_QUEUE_RESET);
  2502. }
  2503. }
  2504. tempq = MMIO_IN32(ivideo->mmio_vbase, MMIO_QUEUE_READPORT);
  2505. MMIO_OUT32(ivideo->mmio_vbase, MMIO_QUEUE_WRITEPORT, tempq);
  2506. temp |= (SIS_MMIO_CMD_ENABLE | SIS_CMD_AUTO_CORR);
  2507. SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, temp);
  2508. tempq = (u32)(ivideo->video_size - ivideo->cmdQueueSize);
  2509. MMIO_OUT32(ivideo->mmio_vbase, MMIO_QUEUE_PHYBASE, tempq);
  2510. ivideo->caps |= MMIO_CMD_QUEUE_CAP;
  2511. }
  2512. #endif
  2513. ivideo->engineok = 1;
  2514. }
  2515. static void sisfb_detect_lcd_type(struct sis_video_info *ivideo)
  2516. {
  2517. u8 reg;
  2518. int i;
  2519. reg = SiS_GetReg(SISCR, 0x36);
  2520. reg &= 0x0f;
  2521. if(ivideo->sisvga_engine == SIS_300_VGA) {
  2522. ivideo->CRT2LCDType = sis300paneltype[reg];
  2523. } else if(ivideo->chip >= SIS_661) {
  2524. ivideo->CRT2LCDType = sis661paneltype[reg];
  2525. } else {
  2526. ivideo->CRT2LCDType = sis310paneltype[reg];
  2527. if((ivideo->chip == SIS_550) && (sisfb_fstn)) {
  2528. if((ivideo->CRT2LCDType != LCD_320x240_2) &&
  2529. (ivideo->CRT2LCDType != LCD_320x240_3)) {
  2530. ivideo->CRT2LCDType = LCD_320x240;
  2531. }
  2532. }
  2533. }
  2534. if(ivideo->CRT2LCDType == LCD_UNKNOWN) {
  2535. /* For broken BIOSes: Assume 1024x768, RGB18 */
  2536. ivideo->CRT2LCDType = LCD_1024x768;
  2537. SiS_SetRegANDOR(SISCR, 0x36, 0xf0, 0x02);
  2538. SiS_SetRegANDOR(SISCR, 0x37, 0xee, 0x01);
  2539. printk(KERN_DEBUG "sisfb: Invalid panel ID (%02x), assuming 1024x768, RGB18\n", reg);
  2540. }
  2541. for(i = 0; i < SIS_LCD_NUMBER; i++) {
  2542. if(ivideo->CRT2LCDType == sis_lcd_data[i].lcdtype) {
  2543. ivideo->lcdxres = sis_lcd_data[i].xres;
  2544. ivideo->lcdyres = sis_lcd_data[i].yres;
  2545. ivideo->lcddefmodeidx = sis_lcd_data[i].default_mode_idx;
  2546. break;
  2547. }
  2548. }
  2549. #ifdef CONFIG_FB_SIS_300
  2550. if(ivideo->SiS_Pr.SiS_CustomT == CUT_BARCO1366) {
  2551. ivideo->lcdxres = 1360; ivideo->lcdyres = 1024;
  2552. ivideo->lcddefmodeidx = DEFAULT_MODE_1360;
  2553. } else if(ivideo->SiS_Pr.SiS_CustomT == CUT_PANEL848) {
  2554. ivideo->lcdxres = 848; ivideo->lcdyres = 480;
  2555. ivideo->lcddefmodeidx = DEFAULT_MODE_848;
  2556. } else if(ivideo->SiS_Pr.SiS_CustomT == CUT_PANEL856) {
  2557. ivideo->lcdxres = 856; ivideo->lcdyres = 480;
  2558. ivideo->lcddefmodeidx = DEFAULT_MODE_856;
  2559. }
  2560. #endif
  2561. printk(KERN_DEBUG "sisfb: Detected %dx%d flat panel\n",
  2562. ivideo->lcdxres, ivideo->lcdyres);
  2563. }
  2564. static void sisfb_save_pdc_emi(struct sis_video_info *ivideo)
  2565. {
  2566. #ifdef CONFIG_FB_SIS_300
  2567. /* Save the current PanelDelayCompensation if the LCD is currently used */
  2568. if(ivideo->sisvga_engine == SIS_300_VGA) {
  2569. if(ivideo->vbflags2 & (VB2_LVDS | VB2_30xBDH)) {
  2570. int tmp;
  2571. tmp = SiS_GetReg(SISCR, 0x30);
  2572. if(tmp & 0x20) {
  2573. /* Currently on LCD? If yes, read current pdc */
  2574. ivideo->detectedpdc = SiS_GetReg(SISPART1, 0x13);
  2575. ivideo->detectedpdc &= 0x3c;
  2576. if(ivideo->SiS_Pr.PDC == -1) {
  2577. /* Let option override detection */
  2578. ivideo->SiS_Pr.PDC = ivideo->detectedpdc;
  2579. }
  2580. printk(KERN_INFO "sisfb: Detected LCD PDC 0x%02x\n",
  2581. ivideo->detectedpdc);
  2582. }
  2583. if((ivideo->SiS_Pr.PDC != -1) &&
  2584. (ivideo->SiS_Pr.PDC != ivideo->detectedpdc)) {
  2585. printk(KERN_INFO "sisfb: Using LCD PDC 0x%02x\n",
  2586. ivideo->SiS_Pr.PDC);
  2587. }
  2588. }
  2589. }
  2590. #endif
  2591. #ifdef CONFIG_FB_SIS_315
  2592. if(ivideo->sisvga_engine == SIS_315_VGA) {
  2593. /* Try to find about LCDA */
  2594. if(ivideo->vbflags2 & VB2_SISLCDABRIDGE) {
  2595. int tmp;
  2596. tmp = SiS_GetReg(SISPART1, 0x13);
  2597. if(tmp & 0x04) {
  2598. ivideo->SiS_Pr.SiS_UseLCDA = true;
  2599. ivideo->detectedlcda = 0x03;
  2600. }
  2601. }
  2602. /* Save PDC */
  2603. if(ivideo->vbflags2 & VB2_SISLVDSBRIDGE) {
  2604. int tmp;
  2605. tmp = SiS_GetReg(SISCR, 0x30);
  2606. if((tmp & 0x20) || (ivideo->detectedlcda != 0xff)) {
  2607. /* Currently on LCD? If yes, read current pdc */
  2608. u8 pdc;
  2609. pdc = SiS_GetReg(SISPART1, 0x2D);
  2610. ivideo->detectedpdc = (pdc & 0x0f) << 1;
  2611. ivideo->detectedpdca = (pdc & 0xf0) >> 3;
  2612. pdc = SiS_GetReg(SISPART1, 0x35);
  2613. ivideo->detectedpdc |= ((pdc >> 7) & 0x01);
  2614. pdc = SiS_GetReg(SISPART1, 0x20);
  2615. ivideo->detectedpdca |= ((pdc >> 6) & 0x01);
  2616. if(ivideo->newrom) {
  2617. /* New ROM invalidates other PDC resp. */
  2618. if(ivideo->detectedlcda != 0xff) {
  2619. ivideo->detectedpdc = 0xff;
  2620. } else {
  2621. ivideo->detectedpdca = 0xff;
  2622. }
  2623. }
  2624. if(ivideo->SiS_Pr.PDC == -1) {
  2625. if(ivideo->detectedpdc != 0xff) {
  2626. ivideo->SiS_Pr.PDC = ivideo->detectedpdc;
  2627. }
  2628. }
  2629. if(ivideo->SiS_Pr.PDCA == -1) {
  2630. if(ivideo->detectedpdca != 0xff) {
  2631. ivideo->SiS_Pr.PDCA = ivideo->detectedpdca;
  2632. }
  2633. }
  2634. if(ivideo->detectedpdc != 0xff) {
  2635. printk(KERN_INFO
  2636. "sisfb: Detected LCD PDC 0x%02x (for LCD=CRT2)\n",
  2637. ivideo->detectedpdc);
  2638. }
  2639. if(ivideo->detectedpdca != 0xff) {
  2640. printk(KERN_INFO
  2641. "sisfb: Detected LCD PDC1 0x%02x (for LCD=CRT1)\n",
  2642. ivideo->detectedpdca);
  2643. }
  2644. }
  2645. /* Save EMI */
  2646. if(ivideo->vbflags2 & VB2_SISEMIBRIDGE) {
  2647. ivideo->SiS_Pr.EMI_30 = SiS_GetReg(SISPART4, 0x30);
  2648. ivideo->SiS_Pr.EMI_31 = SiS_GetReg(SISPART4, 0x31);
  2649. ivideo->SiS_Pr.EMI_32 = SiS_GetReg(SISPART4, 0x32);
  2650. ivideo->SiS_Pr.EMI_33 = SiS_GetReg(SISPART4, 0x33);
  2651. ivideo->SiS_Pr.HaveEMI = true;
  2652. if((tmp & 0x20) || (ivideo->detectedlcda != 0xff)) {
  2653. ivideo->SiS_Pr.HaveEMILCD = true;
  2654. }
  2655. }
  2656. }
  2657. /* Let user override detected PDCs (all bridges) */
  2658. if(ivideo->vbflags2 & VB2_30xBLV) {
  2659. if((ivideo->SiS_Pr.PDC != -1) &&
  2660. (ivideo->SiS_Pr.PDC != ivideo->detectedpdc)) {
  2661. printk(KERN_INFO "sisfb: Using LCD PDC 0x%02x (for LCD=CRT2)\n",
  2662. ivideo->SiS_Pr.PDC);
  2663. }
  2664. if((ivideo->SiS_Pr.PDCA != -1) &&
  2665. (ivideo->SiS_Pr.PDCA != ivideo->detectedpdca)) {
  2666. printk(KERN_INFO "sisfb: Using LCD PDC1 0x%02x (for LCD=CRT1)\n",
  2667. ivideo->SiS_Pr.PDCA);
  2668. }
  2669. }
  2670. }
  2671. #endif
  2672. }
  2673. /* -------------------- Memory manager routines ---------------------- */
  2674. static u32 sisfb_getheapstart(struct sis_video_info *ivideo)
  2675. {
  2676. u32 ret = ivideo->sisfb_parm_mem * 1024;
  2677. u32 maxoffs = ivideo->video_size - ivideo->hwcursor_size - ivideo->cmdQueueSize;
  2678. u32 def;
  2679. /* Calculate heap start = end of memory for console
  2680. *
  2681. * CCCCCCCCDDDDDDDDDDDDDDDDDDDDDDDDDDDDHHHHQQQQQQQQQQ
  2682. * C = console, D = heap, H = HWCursor, Q = cmd-queue
  2683. *
  2684. * On 76x in UMA+LFB mode, the layout is as follows:
  2685. * DDDDDDDDDDDCCCCCCCCCCCCCCCCCCCCCCCCHHHHQQQQQQQQQQQ
  2686. * where the heap is the entire UMA area, eventually
  2687. * into the LFB area if the given mem parameter is
  2688. * higher than the size of the UMA memory.
  2689. *
  2690. * Basically given by "mem" parameter
  2691. *
  2692. * maximum = videosize - cmd_queue - hwcursor
  2693. * (results in a heap of size 0)
  2694. * default = SiS 300: depends on videosize
  2695. * SiS 315/330/340/XGI: 32k below max
  2696. */
  2697. if(ivideo->sisvga_engine == SIS_300_VGA) {
  2698. if(ivideo->video_size > 0x1000000) {
  2699. def = 0xc00000;
  2700. } else if(ivideo->video_size > 0x800000) {
  2701. def = 0x800000;
  2702. } else {
  2703. def = 0x400000;
  2704. }
  2705. } else if(ivideo->UMAsize && ivideo->LFBsize) {
  2706. ret = def = 0;
  2707. } else {
  2708. def = maxoffs - 0x8000;
  2709. }
  2710. /* Use default for secondary card for now (FIXME) */
  2711. if((!ret) || (ret > maxoffs) || (ivideo->cardnumber != 0))
  2712. ret = def;
  2713. return ret;
  2714. }
  2715. static u32 sisfb_getheapsize(struct sis_video_info *ivideo)
  2716. {
  2717. u32 max = ivideo->video_size - ivideo->hwcursor_size - ivideo->cmdQueueSize;
  2718. u32 ret = 0;
  2719. if(ivideo->UMAsize && ivideo->LFBsize) {
  2720. if( (!ivideo->sisfb_parm_mem) ||
  2721. ((ivideo->sisfb_parm_mem * 1024) > max) ||
  2722. ((max - (ivideo->sisfb_parm_mem * 1024)) < ivideo->UMAsize) ) {
  2723. ret = ivideo->UMAsize;
  2724. max -= ivideo->UMAsize;
  2725. } else {
  2726. ret = max - (ivideo->sisfb_parm_mem * 1024);
  2727. max = ivideo->sisfb_parm_mem * 1024;
  2728. }
  2729. ivideo->video_offset = ret;
  2730. ivideo->sisfb_mem = max;
  2731. } else {
  2732. ret = max - ivideo->heapstart;
  2733. ivideo->sisfb_mem = ivideo->heapstart;
  2734. }
  2735. return ret;
  2736. }
  2737. static int sisfb_heap_init(struct sis_video_info *ivideo)
  2738. {
  2739. struct SIS_OH *poh;
  2740. ivideo->video_offset = 0;
  2741. if(ivideo->sisfb_parm_mem) {
  2742. if( (ivideo->sisfb_parm_mem < (2 * 1024 * 1024)) ||
  2743. (ivideo->sisfb_parm_mem > ivideo->video_size) ) {
  2744. ivideo->sisfb_parm_mem = 0;
  2745. }
  2746. }
  2747. ivideo->heapstart = sisfb_getheapstart(ivideo);
  2748. ivideo->sisfb_heap_size = sisfb_getheapsize(ivideo);
  2749. ivideo->sisfb_heap_start = ivideo->video_vbase + ivideo->heapstart;
  2750. ivideo->sisfb_heap_end = ivideo->sisfb_heap_start + ivideo->sisfb_heap_size;
  2751. printk(KERN_INFO "sisfb: Memory heap starting at %dK, size %dK\n",
  2752. (int)(ivideo->heapstart / 1024), (int)(ivideo->sisfb_heap_size / 1024));
  2753. ivideo->sisfb_heap.vinfo = ivideo;
  2754. ivideo->sisfb_heap.poha_chain = NULL;
  2755. ivideo->sisfb_heap.poh_freelist = NULL;
  2756. poh = sisfb_poh_new_node(&ivideo->sisfb_heap);
  2757. if(poh == NULL)
  2758. return 1;
  2759. poh->poh_next = &ivideo->sisfb_heap.oh_free;
  2760. poh->poh_prev = &ivideo->sisfb_heap.oh_free;
  2761. poh->size = ivideo->sisfb_heap_size;
  2762. poh->offset = ivideo->heapstart;
  2763. ivideo->sisfb_heap.oh_free.poh_next = poh;
  2764. ivideo->sisfb_heap.oh_free.poh_prev = poh;
  2765. ivideo->sisfb_heap.oh_free.size = 0;
  2766. ivideo->sisfb_heap.max_freesize = poh->size;
  2767. ivideo->sisfb_heap.oh_used.poh_next = &ivideo->sisfb_heap.oh_used;
  2768. ivideo->sisfb_heap.oh_used.poh_prev = &ivideo->sisfb_heap.oh_used;
  2769. ivideo->sisfb_heap.oh_used.size = SENTINEL;
  2770. if(ivideo->cardnumber == 0) {
  2771. /* For the first card, make this heap the "global" one
  2772. * for old DRM (which could handle only one card)
  2773. */
  2774. sisfb_heap = &ivideo->sisfb_heap;
  2775. }
  2776. return 0;
  2777. }
  2778. static struct SIS_OH *
  2779. sisfb_poh_new_node(struct SIS_HEAP *memheap)
  2780. {
  2781. struct SIS_OHALLOC *poha;
  2782. struct SIS_OH *poh;
  2783. unsigned long cOhs;
  2784. int i;
  2785. if(memheap->poh_freelist == NULL) {
  2786. poha = kmalloc(SIS_OH_ALLOC_SIZE, GFP_KERNEL);
  2787. if(!poha)
  2788. return NULL;
  2789. poha->poha_next = memheap->poha_chain;
  2790. memheap->poha_chain = poha;
  2791. cOhs = (SIS_OH_ALLOC_SIZE - sizeof(struct SIS_OHALLOC)) / sizeof(struct SIS_OH) + 1;
  2792. poh = &poha->aoh[0];
  2793. for(i = cOhs - 1; i != 0; i--) {
  2794. poh->poh_next = poh + 1;
  2795. poh = poh + 1;
  2796. }
  2797. poh->poh_next = NULL;
  2798. memheap->poh_freelist = &poha->aoh[0];
  2799. }
  2800. poh = memheap->poh_freelist;
  2801. memheap->poh_freelist = poh->poh_next;
  2802. return poh;
  2803. }
  2804. static struct SIS_OH *
  2805. sisfb_poh_allocate(struct SIS_HEAP *memheap, u32 size)
  2806. {
  2807. struct SIS_OH *pohThis;
  2808. struct SIS_OH *pohRoot;
  2809. int bAllocated = 0;
  2810. if(size > memheap->max_freesize) {
  2811. DPRINTK("sisfb: Can't allocate %dk video memory\n",
  2812. (unsigned int) size / 1024);
  2813. return NULL;
  2814. }
  2815. pohThis = memheap->oh_free.poh_next;
  2816. while(pohThis != &memheap->oh_free) {
  2817. if(size <= pohThis->size) {
  2818. bAllocated = 1;
  2819. break;
  2820. }
  2821. pohThis = pohThis->poh_next;
  2822. }
  2823. if(!bAllocated) {
  2824. DPRINTK("sisfb: Can't allocate %dk video memory\n",
  2825. (unsigned int) size / 1024);
  2826. return NULL;
  2827. }
  2828. if(size == pohThis->size) {
  2829. pohRoot = pohThis;
  2830. sisfb_delete_node(pohThis);
  2831. } else {
  2832. pohRoot = sisfb_poh_new_node(memheap);
  2833. if(pohRoot == NULL)
  2834. return NULL;
  2835. pohRoot->offset = pohThis->offset;
  2836. pohRoot->size = size;
  2837. pohThis->offset += size;
  2838. pohThis->size -= size;
  2839. }
  2840. memheap->max_freesize -= size;
  2841. pohThis = &memheap->oh_used;
  2842. sisfb_insert_node(pohThis, pohRoot);
  2843. return pohRoot;
  2844. }
  2845. static void
  2846. sisfb_delete_node(struct SIS_OH *poh)
  2847. {
  2848. poh->poh_prev->poh_next = poh->poh_next;
  2849. poh->poh_next->poh_prev = poh->poh_prev;
  2850. }
  2851. static void
  2852. sisfb_insert_node(struct SIS_OH *pohList, struct SIS_OH *poh)
  2853. {
  2854. struct SIS_OH *pohTemp = pohList->poh_next;
  2855. pohList->poh_next = poh;
  2856. pohTemp->poh_prev = poh;
  2857. poh->poh_prev = pohList;
  2858. poh->poh_next = pohTemp;
  2859. }
  2860. static struct SIS_OH *
  2861. sisfb_poh_free(struct SIS_HEAP *memheap, u32 base)
  2862. {
  2863. struct SIS_OH *pohThis;
  2864. struct SIS_OH *poh_freed;
  2865. struct SIS_OH *poh_prev;
  2866. struct SIS_OH *poh_next;
  2867. u32 ulUpper;
  2868. u32 ulLower;
  2869. int foundNode = 0;
  2870. poh_freed = memheap->oh_used.poh_next;
  2871. while(poh_freed != &memheap->oh_used) {
  2872. if(poh_freed->offset == base) {
  2873. foundNode = 1;
  2874. break;
  2875. }
  2876. poh_freed = poh_freed->poh_next;
  2877. }
  2878. if(!foundNode)
  2879. return NULL;
  2880. memheap->max_freesize += poh_freed->size;
  2881. poh_prev = poh_next = NULL;
  2882. ulUpper = poh_freed->offset + poh_freed->size;
  2883. ulLower = poh_freed->offset;
  2884. pohThis = memheap->oh_free.poh_next;
  2885. while(pohThis != &memheap->oh_free) {
  2886. if(pohThis->offset == ulUpper) {
  2887. poh_next = pohThis;
  2888. } else if((pohThis->offset + pohThis->size) == ulLower) {
  2889. poh_prev = pohThis;
  2890. }
  2891. pohThis = pohThis->poh_next;
  2892. }
  2893. sisfb_delete_node(poh_freed);
  2894. if(poh_prev && poh_next) {
  2895. poh_prev->size += (poh_freed->size + poh_next->size);
  2896. sisfb_delete_node(poh_next);
  2897. sisfb_free_node(memheap, poh_freed);
  2898. sisfb_free_node(memheap, poh_next);
  2899. return poh_prev;
  2900. }
  2901. if(poh_prev) {
  2902. poh_prev->size += poh_freed->size;
  2903. sisfb_free_node(memheap, poh_freed);
  2904. return poh_prev;
  2905. }
  2906. if(poh_next) {
  2907. poh_next->size += poh_freed->size;
  2908. poh_next->offset = poh_freed->offset;
  2909. sisfb_free_node(memheap, poh_freed);
  2910. return poh_next;
  2911. }
  2912. sisfb_insert_node(&memheap->oh_free, poh_freed);
  2913. return poh_freed;
  2914. }
  2915. static void
  2916. sisfb_free_node(struct SIS_HEAP *memheap, struct SIS_OH *poh)
  2917. {
  2918. if(poh == NULL)
  2919. return;
  2920. poh->poh_next = memheap->poh_freelist;
  2921. memheap->poh_freelist = poh;
  2922. }
  2923. static void
  2924. sis_int_malloc(struct sis_video_info *ivideo, struct sis_memreq *req)
  2925. {
  2926. struct SIS_OH *poh = NULL;
  2927. if((ivideo) && (ivideo->sisfb_id == SISFB_ID) && (!ivideo->havenoheap))
  2928. poh = sisfb_poh_allocate(&ivideo->sisfb_heap, (u32)req->size);
  2929. if(poh == NULL) {
  2930. req->offset = req->size = 0;
  2931. DPRINTK("sisfb: Video RAM allocation failed\n");
  2932. } else {
  2933. req->offset = poh->offset;
  2934. req->size = poh->size;
  2935. DPRINTK("sisfb: Video RAM allocation succeeded: 0x%lx\n",
  2936. (poh->offset + ivideo->video_vbase));
  2937. }
  2938. }
  2939. void
  2940. sis_malloc(struct sis_memreq *req)
  2941. {
  2942. struct sis_video_info *ivideo = sisfb_heap->vinfo;
  2943. if(&ivideo->sisfb_heap == sisfb_heap)
  2944. sis_int_malloc(ivideo, req);
  2945. else
  2946. req->offset = req->size = 0;
  2947. }
  2948. void
  2949. sis_malloc_new(struct pci_dev *pdev, struct sis_memreq *req)
  2950. {
  2951. struct sis_video_info *ivideo = pci_get_drvdata(pdev);
  2952. sis_int_malloc(ivideo, req);
  2953. }
  2954. /* sis_free: u32 because "base" is offset inside video ram, can never be >4GB */
  2955. static void
  2956. sis_int_free(struct sis_video_info *ivideo, u32 base)
  2957. {
  2958. struct SIS_OH *poh;
  2959. if((!ivideo) || (ivideo->sisfb_id != SISFB_ID) || (ivideo->havenoheap))
  2960. return;
  2961. poh = sisfb_poh_free(&ivideo->sisfb_heap, base);
  2962. if(poh == NULL) {
  2963. DPRINTK("sisfb: sisfb_poh_free() failed at base 0x%x\n",
  2964. (unsigned int) base);
  2965. }
  2966. }
  2967. void
  2968. sis_free(u32 base)
  2969. {
  2970. struct sis_video_info *ivideo = sisfb_heap->vinfo;
  2971. sis_int_free(ivideo, base);
  2972. }
  2973. void
  2974. sis_free_new(struct pci_dev *pdev, u32 base)
  2975. {
  2976. struct sis_video_info *ivideo = pci_get_drvdata(pdev);
  2977. sis_int_free(ivideo, base);
  2978. }
  2979. /* --------------------- SetMode routines ------------------------- */
  2980. static void
  2981. sisfb_check_engine_and_sync(struct sis_video_info *ivideo)
  2982. {
  2983. u8 cr30, cr31;
  2984. /* Check if MMIO and engines are enabled,
  2985. * and sync in case they are. Can't use
  2986. * ivideo->accel here, as this might have
  2987. * been changed before this is called.
  2988. */
  2989. cr30 = SiS_GetReg(SISSR, IND_SIS_PCI_ADDRESS_SET);
  2990. cr31 = SiS_GetReg(SISSR, IND_SIS_MODULE_ENABLE);
  2991. /* MMIO and 2D/3D engine enabled? */
  2992. if((cr30 & SIS_MEM_MAP_IO_ENABLE) && (cr31 & 0x42)) {
  2993. #ifdef CONFIG_FB_SIS_300
  2994. if(ivideo->sisvga_engine == SIS_300_VGA) {
  2995. /* Don't care about TurboQueue. It's
  2996. * enough to know that the engines
  2997. * are enabled
  2998. */
  2999. sisfb_syncaccel(ivideo);
  3000. }
  3001. #endif
  3002. #ifdef CONFIG_FB_SIS_315
  3003. if(ivideo->sisvga_engine == SIS_315_VGA) {
  3004. /* Check that any queue mode is
  3005. * enabled, and that the queue
  3006. * is not in the state of "reset"
  3007. */
  3008. cr30 = SiS_GetReg(SISSR, 0x26);
  3009. if((cr30 & 0xe0) && (!(cr30 & 0x01))) {
  3010. sisfb_syncaccel(ivideo);
  3011. }
  3012. }
  3013. #endif
  3014. }
  3015. }
  3016. static void
  3017. sisfb_pre_setmode(struct sis_video_info *ivideo)
  3018. {
  3019. u8 cr30 = 0, cr31 = 0, cr33 = 0, cr35 = 0, cr38 = 0;
  3020. int tvregnum = 0;
  3021. ivideo->currentvbflags &= (VB_VIDEOBRIDGE | VB_DISPTYPE_DISP2);
  3022. SiS_SetReg(SISSR, 0x05, 0x86);
  3023. cr31 = SiS_GetReg(SISCR, 0x31);
  3024. cr31 &= ~0x60;
  3025. cr31 |= 0x04;
  3026. cr33 = ivideo->rate_idx & 0x0F;
  3027. #ifdef CONFIG_FB_SIS_315
  3028. if(ivideo->sisvga_engine == SIS_315_VGA) {
  3029. if(ivideo->chip >= SIS_661) {
  3030. cr38 = SiS_GetReg(SISCR, 0x38);
  3031. cr38 &= ~0x07; /* Clear LCDA/DualEdge and YPbPr bits */
  3032. } else {
  3033. tvregnum = 0x38;
  3034. cr38 = SiS_GetReg(SISCR, tvregnum);
  3035. cr38 &= ~0x3b; /* Clear LCDA/DualEdge and YPbPr bits */
  3036. }
  3037. }
  3038. #endif
  3039. #ifdef CONFIG_FB_SIS_300
  3040. if(ivideo->sisvga_engine == SIS_300_VGA) {
  3041. tvregnum = 0x35;
  3042. cr38 = SiS_GetReg(SISCR, tvregnum);
  3043. }
  3044. #endif
  3045. SiS_SetEnableDstn(&ivideo->SiS_Pr, false);
  3046. SiS_SetEnableFstn(&ivideo->SiS_Pr, false);
  3047. ivideo->curFSTN = ivideo->curDSTN = 0;
  3048. switch(ivideo->currentvbflags & VB_DISPTYPE_DISP2) {
  3049. case CRT2_TV:
  3050. cr38 &= ~0xc0; /* Clear PAL-M / PAL-N bits */
  3051. if((ivideo->vbflags & TV_YPBPR) && (ivideo->vbflags2 & VB2_SISYPBPRBRIDGE)) {
  3052. #ifdef CONFIG_FB_SIS_315
  3053. if(ivideo->chip >= SIS_661) {
  3054. cr38 |= 0x04;
  3055. if(ivideo->vbflags & TV_YPBPR525P) cr35 |= 0x20;
  3056. else if(ivideo->vbflags & TV_YPBPR750P) cr35 |= 0x40;
  3057. else if(ivideo->vbflags & TV_YPBPR1080I) cr35 |= 0x60;
  3058. cr30 |= SIS_SIMULTANEOUS_VIEW_ENABLE;
  3059. cr35 &= ~0x01;
  3060. ivideo->currentvbflags |= (TV_YPBPR | (ivideo->vbflags & TV_YPBPRALL));
  3061. } else if(ivideo->sisvga_engine == SIS_315_VGA) {
  3062. cr30 |= (0x80 | SIS_SIMULTANEOUS_VIEW_ENABLE);
  3063. cr38 |= 0x08;
  3064. if(ivideo->vbflags & TV_YPBPR525P) cr38 |= 0x10;
  3065. else if(ivideo->vbflags & TV_YPBPR750P) cr38 |= 0x20;
  3066. else if(ivideo->vbflags & TV_YPBPR1080I) cr38 |= 0x30;
  3067. cr31 &= ~0x01;
  3068. ivideo->currentvbflags |= (TV_YPBPR | (ivideo->vbflags & TV_YPBPRALL));
  3069. }
  3070. #endif
  3071. } else if((ivideo->vbflags & TV_HIVISION) &&
  3072. (ivideo->vbflags2 & VB2_SISHIVISIONBRIDGE)) {
  3073. if(ivideo->chip >= SIS_661) {
  3074. cr38 |= 0x04;
  3075. cr35 |= 0x60;
  3076. } else {
  3077. cr30 |= 0x80;
  3078. }
  3079. cr30 |= SIS_SIMULTANEOUS_VIEW_ENABLE;
  3080. cr31 |= 0x01;
  3081. cr35 |= 0x01;
  3082. ivideo->currentvbflags |= TV_HIVISION;
  3083. } else if(ivideo->vbflags & TV_SCART) {
  3084. cr30 = (SIS_VB_OUTPUT_SCART | SIS_SIMULTANEOUS_VIEW_ENABLE);
  3085. cr31 |= 0x01;
  3086. cr35 |= 0x01;
  3087. ivideo->currentvbflags |= TV_SCART;
  3088. } else {
  3089. if(ivideo->vbflags & TV_SVIDEO) {
  3090. cr30 = (SIS_VB_OUTPUT_SVIDEO | SIS_SIMULTANEOUS_VIEW_ENABLE);
  3091. ivideo->currentvbflags |= TV_SVIDEO;
  3092. }
  3093. if(ivideo->vbflags & TV_AVIDEO) {
  3094. cr30 = (SIS_VB_OUTPUT_COMPOSITE | SIS_SIMULTANEOUS_VIEW_ENABLE);
  3095. ivideo->currentvbflags |= TV_AVIDEO;
  3096. }
  3097. }
  3098. cr31 |= SIS_DRIVER_MODE;
  3099. if(ivideo->vbflags & (TV_AVIDEO | TV_SVIDEO)) {
  3100. if(ivideo->vbflags & TV_PAL) {
  3101. cr31 |= 0x01; cr35 |= 0x01;
  3102. ivideo->currentvbflags |= TV_PAL;
  3103. if(ivideo->vbflags & TV_PALM) {
  3104. cr38 |= 0x40; cr35 |= 0x04;
  3105. ivideo->currentvbflags |= TV_PALM;
  3106. } else if(ivideo->vbflags & TV_PALN) {
  3107. cr38 |= 0x80; cr35 |= 0x08;
  3108. ivideo->currentvbflags |= TV_PALN;
  3109. }
  3110. } else {
  3111. cr31 &= ~0x01; cr35 &= ~0x01;
  3112. ivideo->currentvbflags |= TV_NTSC;
  3113. if(ivideo->vbflags & TV_NTSCJ) {
  3114. cr38 |= 0x40; cr35 |= 0x02;
  3115. ivideo->currentvbflags |= TV_NTSCJ;
  3116. }
  3117. }
  3118. }
  3119. break;
  3120. case CRT2_LCD:
  3121. cr30 = (SIS_VB_OUTPUT_LCD | SIS_SIMULTANEOUS_VIEW_ENABLE);
  3122. cr31 |= SIS_DRIVER_MODE;
  3123. SiS_SetEnableDstn(&ivideo->SiS_Pr, ivideo->sisfb_dstn);
  3124. SiS_SetEnableFstn(&ivideo->SiS_Pr, ivideo->sisfb_fstn);
  3125. ivideo->curFSTN = ivideo->sisfb_fstn;
  3126. ivideo->curDSTN = ivideo->sisfb_dstn;
  3127. break;
  3128. case CRT2_VGA:
  3129. cr30 = (SIS_VB_OUTPUT_CRT2 | SIS_SIMULTANEOUS_VIEW_ENABLE);
  3130. cr31 |= SIS_DRIVER_MODE;
  3131. if(ivideo->sisfb_nocrt2rate) {
  3132. cr33 |= (sisbios_mode[ivideo->sisfb_mode_idx].rate_idx << 4);
  3133. } else {
  3134. cr33 |= ((ivideo->rate_idx & 0x0F) << 4);
  3135. }
  3136. break;
  3137. default: /* disable CRT2 */
  3138. cr30 = 0x00;
  3139. cr31 |= (SIS_DRIVER_MODE | SIS_VB_OUTPUT_DISABLE);
  3140. }
  3141. SiS_SetReg(SISCR, 0x30, cr30);
  3142. SiS_SetReg(SISCR, 0x33, cr33);
  3143. if(ivideo->chip >= SIS_661) {
  3144. #ifdef CONFIG_FB_SIS_315
  3145. cr31 &= ~0x01; /* Clear PAL flag (now in CR35) */
  3146. SiS_SetRegANDOR(SISCR, 0x35, ~0x10, cr35); /* Leave overscan bit alone */
  3147. cr38 &= 0x07; /* Use only LCDA and HiVision/YPbPr bits */
  3148. SiS_SetRegANDOR(SISCR, 0x38, 0xf8, cr38);
  3149. #endif
  3150. } else if(ivideo->chip != SIS_300) {
  3151. SiS_SetReg(SISCR, tvregnum, cr38);
  3152. }
  3153. SiS_SetReg(SISCR, 0x31, cr31);
  3154. ivideo->SiS_Pr.SiS_UseOEM = ivideo->sisfb_useoem;
  3155. sisfb_check_engine_and_sync(ivideo);
  3156. }
  3157. /* Fix SR11 for 661 and later */
  3158. #ifdef CONFIG_FB_SIS_315
  3159. static void
  3160. sisfb_fixup_SR11(struct sis_video_info *ivideo)
  3161. {
  3162. u8 tmpreg;
  3163. if(ivideo->chip >= SIS_661) {
  3164. tmpreg = SiS_GetReg(SISSR, 0x11);
  3165. if(tmpreg & 0x20) {
  3166. tmpreg = SiS_GetReg(SISSR, 0x3e);
  3167. tmpreg = (tmpreg + 1) & 0xff;
  3168. SiS_SetReg(SISSR, 0x3e, tmpreg);
  3169. tmpreg = SiS_GetReg(SISSR, 0x11);
  3170. }
  3171. if(tmpreg & 0xf0) {
  3172. SiS_SetRegAND(SISSR, 0x11, 0x0f);
  3173. }
  3174. }
  3175. }
  3176. #endif
  3177. static void
  3178. sisfb_set_TVxposoffset(struct sis_video_info *ivideo, int val)
  3179. {
  3180. if(val > 32) val = 32;
  3181. if(val < -32) val = -32;
  3182. ivideo->tvxpos = val;
  3183. if(ivideo->sisfblocked) return;
  3184. if(!ivideo->modechanged) return;
  3185. if(ivideo->currentvbflags & CRT2_TV) {
  3186. if(ivideo->vbflags2 & VB2_CHRONTEL) {
  3187. int x = ivideo->tvx;
  3188. switch(ivideo->chronteltype) {
  3189. case 1:
  3190. x += val;
  3191. if(x < 0) x = 0;
  3192. SiS_SetReg(SISSR, 0x05, 0x86);
  3193. SiS_SetCH700x(&ivideo->SiS_Pr, 0x0a, (x & 0xff));
  3194. SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x08, ((x & 0x0100) >> 7), 0xFD);
  3195. break;
  3196. case 2:
  3197. /* Not supported by hardware */
  3198. break;
  3199. }
  3200. } else if(ivideo->vbflags2 & VB2_SISBRIDGE) {
  3201. u8 p2_1f,p2_20,p2_2b,p2_42,p2_43;
  3202. unsigned short temp;
  3203. p2_1f = ivideo->p2_1f;
  3204. p2_20 = ivideo->p2_20;
  3205. p2_2b = ivideo->p2_2b;
  3206. p2_42 = ivideo->p2_42;
  3207. p2_43 = ivideo->p2_43;
  3208. temp = p2_1f | ((p2_20 & 0xf0) << 4);
  3209. temp += (val * 2);
  3210. p2_1f = temp & 0xff;
  3211. p2_20 = (temp & 0xf00) >> 4;
  3212. p2_2b = ((p2_2b & 0x0f) + (val * 2)) & 0x0f;
  3213. temp = p2_43 | ((p2_42 & 0xf0) << 4);
  3214. temp += (val * 2);
  3215. p2_43 = temp & 0xff;
  3216. p2_42 = (temp & 0xf00) >> 4;
  3217. SiS_SetReg(SISPART2, 0x1f, p2_1f);
  3218. SiS_SetRegANDOR(SISPART2, 0x20, 0x0F, p2_20);
  3219. SiS_SetRegANDOR(SISPART2, 0x2b, 0xF0, p2_2b);
  3220. SiS_SetRegANDOR(SISPART2, 0x42, 0x0F, p2_42);
  3221. SiS_SetReg(SISPART2, 0x43, p2_43);
  3222. }
  3223. }
  3224. }
  3225. static void
  3226. sisfb_set_TVyposoffset(struct sis_video_info *ivideo, int val)
  3227. {
  3228. if(val > 32) val = 32;
  3229. if(val < -32) val = -32;
  3230. ivideo->tvypos = val;
  3231. if(ivideo->sisfblocked) return;
  3232. if(!ivideo->modechanged) return;
  3233. if(ivideo->currentvbflags & CRT2_TV) {
  3234. if(ivideo->vbflags2 & VB2_CHRONTEL) {
  3235. int y = ivideo->tvy;
  3236. switch(ivideo->chronteltype) {
  3237. case 1:
  3238. y -= val;
  3239. if(y < 0) y = 0;
  3240. SiS_SetReg(SISSR, 0x05, 0x86);
  3241. SiS_SetCH700x(&ivideo->SiS_Pr, 0x0b, (y & 0xff));
  3242. SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x08, ((y & 0x0100) >> 8), 0xFE);
  3243. break;
  3244. case 2:
  3245. /* Not supported by hardware */
  3246. break;
  3247. }
  3248. } else if(ivideo->vbflags2 & VB2_SISBRIDGE) {
  3249. char p2_01, p2_02;
  3250. val /= 2;
  3251. p2_01 = ivideo->p2_01;
  3252. p2_02 = ivideo->p2_02;
  3253. p2_01 += val;
  3254. p2_02 += val;
  3255. if(!(ivideo->currentvbflags & (TV_HIVISION | TV_YPBPR))) {
  3256. while((p2_01 <= 0) || (p2_02 <= 0)) {
  3257. p2_01 += 2;
  3258. p2_02 += 2;
  3259. }
  3260. }
  3261. SiS_SetReg(SISPART2, 0x01, p2_01);
  3262. SiS_SetReg(SISPART2, 0x02, p2_02);
  3263. }
  3264. }
  3265. }
  3266. static void
  3267. sisfb_post_setmode(struct sis_video_info *ivideo)
  3268. {
  3269. bool crt1isoff = false;
  3270. bool doit = true;
  3271. #if defined(CONFIG_FB_SIS_300) || defined(CONFIG_FB_SIS_315)
  3272. u8 reg;
  3273. #endif
  3274. #ifdef CONFIG_FB_SIS_315
  3275. u8 reg1;
  3276. #endif
  3277. SiS_SetReg(SISSR, 0x05, 0x86);
  3278. #ifdef CONFIG_FB_SIS_315
  3279. sisfb_fixup_SR11(ivideo);
  3280. #endif
  3281. /* Now we actually HAVE changed the display mode */
  3282. ivideo->modechanged = 1;
  3283. /* We can't switch off CRT1 if bridge is in slave mode */
  3284. if(ivideo->vbflags2 & VB2_VIDEOBRIDGE) {
  3285. if(sisfb_bridgeisslave(ivideo)) doit = false;
  3286. } else
  3287. ivideo->sisfb_crt1off = 0;
  3288. #ifdef CONFIG_FB_SIS_300
  3289. if(ivideo->sisvga_engine == SIS_300_VGA) {
  3290. if((ivideo->sisfb_crt1off) && (doit)) {
  3291. crt1isoff = true;
  3292. reg = 0x00;
  3293. } else {
  3294. crt1isoff = false;
  3295. reg = 0x80;
  3296. }
  3297. SiS_SetRegANDOR(SISCR, 0x17, 0x7f, reg);
  3298. }
  3299. #endif
  3300. #ifdef CONFIG_FB_SIS_315
  3301. if(ivideo->sisvga_engine == SIS_315_VGA) {
  3302. if((ivideo->sisfb_crt1off) && (doit)) {
  3303. crt1isoff = true;
  3304. reg = 0x40;
  3305. reg1 = 0xc0;
  3306. } else {
  3307. crt1isoff = false;
  3308. reg = 0x00;
  3309. reg1 = 0x00;
  3310. }
  3311. SiS_SetRegANDOR(SISCR, ivideo->SiS_Pr.SiS_MyCR63, ~0x40, reg);
  3312. SiS_SetRegANDOR(SISSR, 0x1f, 0x3f, reg1);
  3313. }
  3314. #endif
  3315. if(crt1isoff) {
  3316. ivideo->currentvbflags &= ~VB_DISPTYPE_CRT1;
  3317. ivideo->currentvbflags |= VB_SINGLE_MODE;
  3318. } else {
  3319. ivideo->currentvbflags |= VB_DISPTYPE_CRT1;
  3320. if(ivideo->currentvbflags & VB_DISPTYPE_CRT2) {
  3321. ivideo->currentvbflags |= VB_MIRROR_MODE;
  3322. } else {
  3323. ivideo->currentvbflags |= VB_SINGLE_MODE;
  3324. }
  3325. }
  3326. SiS_SetRegAND(SISSR, IND_SIS_RAMDAC_CONTROL, ~0x04);
  3327. if(ivideo->currentvbflags & CRT2_TV) {
  3328. if(ivideo->vbflags2 & VB2_SISBRIDGE) {
  3329. ivideo->p2_1f = SiS_GetReg(SISPART2, 0x1f);
  3330. ivideo->p2_20 = SiS_GetReg(SISPART2, 0x20);
  3331. ivideo->p2_2b = SiS_GetReg(SISPART2, 0x2b);
  3332. ivideo->p2_42 = SiS_GetReg(SISPART2, 0x42);
  3333. ivideo->p2_43 = SiS_GetReg(SISPART2, 0x43);
  3334. ivideo->p2_01 = SiS_GetReg(SISPART2, 0x01);
  3335. ivideo->p2_02 = SiS_GetReg(SISPART2, 0x02);
  3336. } else if(ivideo->vbflags2 & VB2_CHRONTEL) {
  3337. if(ivideo->chronteltype == 1) {
  3338. ivideo->tvx = SiS_GetCH700x(&ivideo->SiS_Pr, 0x0a);
  3339. ivideo->tvx |= (((SiS_GetCH700x(&ivideo->SiS_Pr, 0x08) & 0x02) >> 1) << 8);
  3340. ivideo->tvy = SiS_GetCH700x(&ivideo->SiS_Pr, 0x0b);
  3341. ivideo->tvy |= ((SiS_GetCH700x(&ivideo->SiS_Pr, 0x08) & 0x01) << 8);
  3342. }
  3343. }
  3344. }
  3345. if(ivideo->tvxpos) {
  3346. sisfb_set_TVxposoffset(ivideo, ivideo->tvxpos);
  3347. }
  3348. if(ivideo->tvypos) {
  3349. sisfb_set_TVyposoffset(ivideo, ivideo->tvypos);
  3350. }
  3351. /* Eventually sync engines */
  3352. sisfb_check_engine_and_sync(ivideo);
  3353. /* (Re-)Initialize chip engines */
  3354. if(ivideo->accel) {
  3355. sisfb_engine_init(ivideo);
  3356. } else {
  3357. ivideo->engineok = 0;
  3358. }
  3359. }
  3360. static int
  3361. sisfb_reset_mode(struct sis_video_info *ivideo)
  3362. {
  3363. if(sisfb_set_mode(ivideo, 0))
  3364. return 1;
  3365. sisfb_set_pitch(ivideo);
  3366. sisfb_set_base_CRT1(ivideo, ivideo->current_base);
  3367. sisfb_set_base_CRT2(ivideo, ivideo->current_base);
  3368. return 0;
  3369. }
  3370. static void
  3371. sisfb_handle_command(struct sis_video_info *ivideo, struct sisfb_cmd *sisfb_command)
  3372. {
  3373. int mycrt1off;
  3374. switch(sisfb_command->sisfb_cmd) {
  3375. case SISFB_CMD_GETVBFLAGS:
  3376. if(!ivideo->modechanged) {
  3377. sisfb_command->sisfb_result[0] = SISFB_CMD_ERR_EARLY;
  3378. } else {
  3379. sisfb_command->sisfb_result[0] = SISFB_CMD_ERR_OK;
  3380. sisfb_command->sisfb_result[1] = ivideo->currentvbflags;
  3381. sisfb_command->sisfb_result[2] = ivideo->vbflags2;
  3382. }
  3383. break;
  3384. case SISFB_CMD_SWITCHCRT1:
  3385. /* arg[0]: 0 = off, 1 = on, 99 = query */
  3386. if(!ivideo->modechanged) {
  3387. sisfb_command->sisfb_result[0] = SISFB_CMD_ERR_EARLY;
  3388. } else if(sisfb_command->sisfb_arg[0] == 99) {
  3389. /* Query */
  3390. sisfb_command->sisfb_result[1] = ivideo->sisfb_crt1off ? 0 : 1;
  3391. sisfb_command->sisfb_result[0] = SISFB_CMD_ERR_OK;
  3392. } else if(ivideo->sisfblocked) {
  3393. sisfb_command->sisfb_result[0] = SISFB_CMD_ERR_LOCKED;
  3394. } else if((!(ivideo->currentvbflags & CRT2_ENABLE)) &&
  3395. (sisfb_command->sisfb_arg[0] == 0)) {
  3396. sisfb_command->sisfb_result[0] = SISFB_CMD_ERR_NOCRT2;
  3397. } else {
  3398. sisfb_command->sisfb_result[0] = SISFB_CMD_ERR_OK;
  3399. mycrt1off = sisfb_command->sisfb_arg[0] ? 0 : 1;
  3400. if( ((ivideo->currentvbflags & VB_DISPTYPE_CRT1) && mycrt1off) ||
  3401. ((!(ivideo->currentvbflags & VB_DISPTYPE_CRT1)) && !mycrt1off) ) {
  3402. ivideo->sisfb_crt1off = mycrt1off;
  3403. if(sisfb_reset_mode(ivideo)) {
  3404. sisfb_command->sisfb_result[0] = SISFB_CMD_ERR_OTHER;
  3405. }
  3406. }
  3407. sisfb_command->sisfb_result[1] = ivideo->sisfb_crt1off ? 0 : 1;
  3408. }
  3409. break;
  3410. /* more to come */
  3411. default:
  3412. sisfb_command->sisfb_result[0] = SISFB_CMD_ERR_UNKNOWN;
  3413. printk(KERN_ERR "sisfb: Unknown command 0x%x\n",
  3414. sisfb_command->sisfb_cmd);
  3415. }
  3416. }
  3417. #ifndef MODULE
  3418. static int __init sisfb_setup(char *options)
  3419. {
  3420. char *this_opt;
  3421. sisfb_setdefaultparms();
  3422. if(!options || !(*options))
  3423. return 0;
  3424. while((this_opt = strsep(&options, ",")) != NULL) {
  3425. if(!(*this_opt)) continue;
  3426. if(!strnicmp(this_opt, "off", 3)) {
  3427. sisfb_off = 1;
  3428. } else if(!strnicmp(this_opt, "forcecrt2type:", 14)) {
  3429. /* Need to check crt2 type first for fstn/dstn */
  3430. sisfb_search_crt2type(this_opt + 14);
  3431. } else if(!strnicmp(this_opt, "tvmode:",7)) {
  3432. sisfb_search_tvstd(this_opt + 7);
  3433. } else if(!strnicmp(this_opt, "tvstandard:",11)) {
  3434. sisfb_search_tvstd(this_opt + 11);
  3435. } else if(!strnicmp(this_opt, "mode:", 5)) {
  3436. sisfb_search_mode(this_opt + 5, false);
  3437. } else if(!strnicmp(this_opt, "vesa:", 5)) {
  3438. sisfb_search_vesamode(simple_strtoul(this_opt + 5, NULL, 0), false);
  3439. } else if(!strnicmp(this_opt, "rate:", 5)) {
  3440. sisfb_parm_rate = simple_strtoul(this_opt + 5, NULL, 0);
  3441. } else if(!strnicmp(this_opt, "forcecrt1:", 10)) {
  3442. sisfb_forcecrt1 = (int)simple_strtoul(this_opt + 10, NULL, 0);
  3443. } else if(!strnicmp(this_opt, "mem:",4)) {
  3444. sisfb_parm_mem = simple_strtoul(this_opt + 4, NULL, 0);
  3445. } else if(!strnicmp(this_opt, "pdc:", 4)) {
  3446. sisfb_pdc = simple_strtoul(this_opt + 4, NULL, 0);
  3447. } else if(!strnicmp(this_opt, "pdc1:", 5)) {
  3448. sisfb_pdca = simple_strtoul(this_opt + 5, NULL, 0);
  3449. } else if(!strnicmp(this_opt, "noaccel", 7)) {
  3450. sisfb_accel = 0;
  3451. } else if(!strnicmp(this_opt, "accel", 5)) {
  3452. sisfb_accel = -1;
  3453. } else if(!strnicmp(this_opt, "noypan", 6)) {
  3454. sisfb_ypan = 0;
  3455. } else if(!strnicmp(this_opt, "ypan", 4)) {
  3456. sisfb_ypan = -1;
  3457. } else if(!strnicmp(this_opt, "nomax", 5)) {
  3458. sisfb_max = 0;
  3459. } else if(!strnicmp(this_opt, "max", 3)) {
  3460. sisfb_max = -1;
  3461. } else if(!strnicmp(this_opt, "userom:", 7)) {
  3462. sisfb_userom = (int)simple_strtoul(this_opt + 7, NULL, 0);
  3463. } else if(!strnicmp(this_opt, "useoem:", 7)) {
  3464. sisfb_useoem = (int)simple_strtoul(this_opt + 7, NULL, 0);
  3465. } else if(!strnicmp(this_opt, "nocrt2rate", 10)) {
  3466. sisfb_nocrt2rate = 1;
  3467. } else if(!strnicmp(this_opt, "scalelcd:", 9)) {
  3468. unsigned long temp = 2;
  3469. temp = simple_strtoul(this_opt + 9, NULL, 0);
  3470. if((temp == 0) || (temp == 1)) {
  3471. sisfb_scalelcd = temp ^ 1;
  3472. }
  3473. } else if(!strnicmp(this_opt, "tvxposoffset:", 13)) {
  3474. int temp = 0;
  3475. temp = (int)simple_strtol(this_opt + 13, NULL, 0);
  3476. if((temp >= -32) && (temp <= 32)) {
  3477. sisfb_tvxposoffset = temp;
  3478. }
  3479. } else if(!strnicmp(this_opt, "tvyposoffset:", 13)) {
  3480. int temp = 0;
  3481. temp = (int)simple_strtol(this_opt + 13, NULL, 0);
  3482. if((temp >= -32) && (temp <= 32)) {
  3483. sisfb_tvyposoffset = temp;
  3484. }
  3485. } else if(!strnicmp(this_opt, "specialtiming:", 14)) {
  3486. sisfb_search_specialtiming(this_opt + 14);
  3487. } else if(!strnicmp(this_opt, "lvdshl:", 7)) {
  3488. int temp = 4;
  3489. temp = simple_strtoul(this_opt + 7, NULL, 0);
  3490. if((temp >= 0) && (temp <= 3)) {
  3491. sisfb_lvdshl = temp;
  3492. }
  3493. } else if(this_opt[0] >= '0' && this_opt[0] <= '9') {
  3494. sisfb_search_mode(this_opt, true);
  3495. #if !defined(__i386__) && !defined(__x86_64__)
  3496. } else if(!strnicmp(this_opt, "resetcard", 9)) {
  3497. sisfb_resetcard = 1;
  3498. } else if(!strnicmp(this_opt, "videoram:", 9)) {
  3499. sisfb_videoram = simple_strtoul(this_opt + 9, NULL, 0);
  3500. #endif
  3501. } else {
  3502. printk(KERN_INFO "sisfb: Invalid option %s\n", this_opt);
  3503. }
  3504. }
  3505. return 0;
  3506. }
  3507. #endif
  3508. static int sisfb_check_rom(void __iomem *rom_base,
  3509. struct sis_video_info *ivideo)
  3510. {
  3511. void __iomem *rom;
  3512. int romptr;
  3513. if((readb(rom_base) != 0x55) || (readb(rom_base + 1) != 0xaa))
  3514. return 0;
  3515. romptr = (readb(rom_base + 0x18) | (readb(rom_base + 0x19) << 8));
  3516. if(romptr > (0x10000 - 8))
  3517. return 0;
  3518. rom = rom_base + romptr;
  3519. if((readb(rom) != 'P') || (readb(rom + 1) != 'C') ||
  3520. (readb(rom + 2) != 'I') || (readb(rom + 3) != 'R'))
  3521. return 0;
  3522. if((readb(rom + 4) | (readb(rom + 5) << 8)) != ivideo->chip_vendor)
  3523. return 0;
  3524. if((readb(rom + 6) | (readb(rom + 7) << 8)) != ivideo->chip_id)
  3525. return 0;
  3526. return 1;
  3527. }
  3528. static unsigned char *sisfb_find_rom(struct pci_dev *pdev)
  3529. {
  3530. struct sis_video_info *ivideo = pci_get_drvdata(pdev);
  3531. void __iomem *rom_base;
  3532. unsigned char *myrombase = NULL;
  3533. size_t romsize;
  3534. /* First, try the official pci ROM functions (except
  3535. * on integrated chipsets which have no ROM).
  3536. */
  3537. if(!ivideo->nbridge) {
  3538. if((rom_base = pci_map_rom(pdev, &romsize))) {
  3539. if(sisfb_check_rom(rom_base, ivideo)) {
  3540. if((myrombase = vmalloc(65536))) {
  3541. memcpy_fromio(myrombase, rom_base,
  3542. (romsize > 65536) ? 65536 : romsize);
  3543. }
  3544. }
  3545. pci_unmap_rom(pdev, rom_base);
  3546. }
  3547. }
  3548. if(myrombase) return myrombase;
  3549. /* Otherwise do it the conventional way. */
  3550. #if defined(__i386__) || defined(__x86_64__)
  3551. {
  3552. u32 temp;
  3553. for (temp = 0x000c0000; temp < 0x000f0000; temp += 0x00001000) {
  3554. rom_base = ioremap(temp, 65536);
  3555. if (!rom_base)
  3556. continue;
  3557. if (!sisfb_check_rom(rom_base, ivideo)) {
  3558. iounmap(rom_base);
  3559. continue;
  3560. }
  3561. if ((myrombase = vmalloc(65536)))
  3562. memcpy_fromio(myrombase, rom_base, 65536);
  3563. iounmap(rom_base);
  3564. break;
  3565. }
  3566. }
  3567. #endif
  3568. return myrombase;
  3569. }
  3570. static void sisfb_post_map_vram(struct sis_video_info *ivideo,
  3571. unsigned int *mapsize, unsigned int min)
  3572. {
  3573. if (*mapsize < (min << 20))
  3574. return;
  3575. ivideo->video_vbase = ioremap(ivideo->video_base, (*mapsize));
  3576. if(!ivideo->video_vbase) {
  3577. printk(KERN_ERR
  3578. "sisfb: Unable to map maximum video RAM for size detection\n");
  3579. (*mapsize) >>= 1;
  3580. while((!(ivideo->video_vbase = ioremap(ivideo->video_base, (*mapsize))))) {
  3581. (*mapsize) >>= 1;
  3582. if((*mapsize) < (min << 20))
  3583. break;
  3584. }
  3585. if(ivideo->video_vbase) {
  3586. printk(KERN_ERR
  3587. "sisfb: Video RAM size detection limited to %dMB\n",
  3588. (int)((*mapsize) >> 20));
  3589. }
  3590. }
  3591. }
  3592. #ifdef CONFIG_FB_SIS_300
  3593. static int sisfb_post_300_buswidth(struct sis_video_info *ivideo)
  3594. {
  3595. void __iomem *FBAddress = ivideo->video_vbase;
  3596. unsigned short temp;
  3597. unsigned char reg;
  3598. int i, j;
  3599. SiS_SetRegAND(SISSR, 0x15, 0xFB);
  3600. SiS_SetRegOR(SISSR, 0x15, 0x04);
  3601. SiS_SetReg(SISSR, 0x13, 0x00);
  3602. SiS_SetReg(SISSR, 0x14, 0xBF);
  3603. for(i = 0; i < 2; i++) {
  3604. temp = 0x1234;
  3605. for(j = 0; j < 4; j++) {
  3606. writew(temp, FBAddress);
  3607. if(readw(FBAddress) == temp)
  3608. break;
  3609. SiS_SetRegOR(SISSR, 0x3c, 0x01);
  3610. reg = SiS_GetReg(SISSR, 0x05);
  3611. reg = SiS_GetReg(SISSR, 0x05);
  3612. SiS_SetRegAND(SISSR, 0x3c, 0xfe);
  3613. reg = SiS_GetReg(SISSR, 0x05);
  3614. reg = SiS_GetReg(SISSR, 0x05);
  3615. temp++;
  3616. }
  3617. }
  3618. writel(0x01234567L, FBAddress);
  3619. writel(0x456789ABL, (FBAddress + 4));
  3620. writel(0x89ABCDEFL, (FBAddress + 8));
  3621. writel(0xCDEF0123L, (FBAddress + 12));
  3622. reg = SiS_GetReg(SISSR, 0x3b);
  3623. if(reg & 0x01) {
  3624. if(readl((FBAddress + 12)) == 0xCDEF0123L)
  3625. return 4; /* Channel A 128bit */
  3626. }
  3627. if(readl((FBAddress + 4)) == 0x456789ABL)
  3628. return 2; /* Channel B 64bit */
  3629. return 1; /* 32bit */
  3630. }
  3631. static const unsigned short SiS_DRAMType[17][5] = {
  3632. {0x0C,0x0A,0x02,0x40,0x39},
  3633. {0x0D,0x0A,0x01,0x40,0x48},
  3634. {0x0C,0x09,0x02,0x20,0x35},
  3635. {0x0D,0x09,0x01,0x20,0x44},
  3636. {0x0C,0x08,0x02,0x10,0x31},
  3637. {0x0D,0x08,0x01,0x10,0x40},
  3638. {0x0C,0x0A,0x01,0x20,0x34},
  3639. {0x0C,0x09,0x01,0x08,0x32},
  3640. {0x0B,0x08,0x02,0x08,0x21},
  3641. {0x0C,0x08,0x01,0x08,0x30},
  3642. {0x0A,0x08,0x02,0x04,0x11},
  3643. {0x0B,0x0A,0x01,0x10,0x28},
  3644. {0x09,0x08,0x02,0x02,0x01},
  3645. {0x0B,0x09,0x01,0x08,0x24},
  3646. {0x0B,0x08,0x01,0x04,0x20},
  3647. {0x0A,0x08,0x01,0x02,0x10},
  3648. {0x09,0x08,0x01,0x01,0x00}
  3649. };
  3650. static int sisfb_post_300_rwtest(struct sis_video_info *ivideo, int iteration,
  3651. int buswidth, int PseudoRankCapacity,
  3652. int PseudoAdrPinCount, unsigned int mapsize)
  3653. {
  3654. void __iomem *FBAddr = ivideo->video_vbase;
  3655. unsigned short sr14;
  3656. unsigned int k, RankCapacity, PageCapacity, BankNumHigh, BankNumMid;
  3657. unsigned int PhysicalAdrOtherPage, PhysicalAdrHigh, PhysicalAdrHalfPage;
  3658. for(k = 0; k < ARRAY_SIZE(SiS_DRAMType); k++) {
  3659. RankCapacity = buswidth * SiS_DRAMType[k][3];
  3660. if(RankCapacity != PseudoRankCapacity)
  3661. continue;
  3662. if((SiS_DRAMType[k][2] + SiS_DRAMType[k][0]) > PseudoAdrPinCount)
  3663. continue;
  3664. BankNumHigh = RankCapacity * 16 * iteration - 1;
  3665. if(iteration == 3) { /* Rank No */
  3666. BankNumMid = RankCapacity * 16 - 1;
  3667. } else {
  3668. BankNumMid = RankCapacity * 16 * iteration / 2 - 1;
  3669. }
  3670. PageCapacity = (1 << SiS_DRAMType[k][1]) * buswidth * 4;
  3671. PhysicalAdrHigh = BankNumHigh;
  3672. PhysicalAdrHalfPage = (PageCapacity / 2 + PhysicalAdrHigh) % PageCapacity;
  3673. PhysicalAdrOtherPage = PageCapacity * SiS_DRAMType[k][2] + PhysicalAdrHigh;
  3674. SiS_SetRegAND(SISSR, 0x15, 0xFB); /* Test */
  3675. SiS_SetRegOR(SISSR, 0x15, 0x04); /* Test */
  3676. sr14 = (SiS_DRAMType[k][3] * buswidth) - 1;
  3677. if(buswidth == 4) sr14 |= 0x80;
  3678. else if(buswidth == 2) sr14 |= 0x40;
  3679. SiS_SetReg(SISSR, 0x13, SiS_DRAMType[k][4]);
  3680. SiS_SetReg(SISSR, 0x14, sr14);
  3681. BankNumHigh <<= 16;
  3682. BankNumMid <<= 16;
  3683. if((BankNumHigh + PhysicalAdrHigh >= mapsize) ||
  3684. (BankNumMid + PhysicalAdrHigh >= mapsize) ||
  3685. (BankNumHigh + PhysicalAdrHalfPage >= mapsize) ||
  3686. (BankNumHigh + PhysicalAdrOtherPage >= mapsize))
  3687. continue;
  3688. /* Write data */
  3689. writew(((unsigned short)PhysicalAdrHigh),
  3690. (FBAddr + BankNumHigh + PhysicalAdrHigh));
  3691. writew(((unsigned short)BankNumMid),
  3692. (FBAddr + BankNumMid + PhysicalAdrHigh));
  3693. writew(((unsigned short)PhysicalAdrHalfPage),
  3694. (FBAddr + BankNumHigh + PhysicalAdrHalfPage));
  3695. writew(((unsigned short)PhysicalAdrOtherPage),
  3696. (FBAddr + BankNumHigh + PhysicalAdrOtherPage));
  3697. /* Read data */
  3698. if(readw(FBAddr + BankNumHigh + PhysicalAdrHigh) == PhysicalAdrHigh)
  3699. return 1;
  3700. }
  3701. return 0;
  3702. }
  3703. static void sisfb_post_300_ramsize(struct pci_dev *pdev, unsigned int mapsize)
  3704. {
  3705. struct sis_video_info *ivideo = pci_get_drvdata(pdev);
  3706. int i, j, buswidth;
  3707. int PseudoRankCapacity, PseudoAdrPinCount;
  3708. buswidth = sisfb_post_300_buswidth(ivideo);
  3709. for(i = 6; i >= 0; i--) {
  3710. PseudoRankCapacity = 1 << i;
  3711. for(j = 4; j >= 1; j--) {
  3712. PseudoAdrPinCount = 15 - j;
  3713. if((PseudoRankCapacity * j) <= 64) {
  3714. if(sisfb_post_300_rwtest(ivideo,
  3715. j,
  3716. buswidth,
  3717. PseudoRankCapacity,
  3718. PseudoAdrPinCount,
  3719. mapsize))
  3720. return;
  3721. }
  3722. }
  3723. }
  3724. }
  3725. static void sisfb_post_sis300(struct pci_dev *pdev)
  3726. {
  3727. struct sis_video_info *ivideo = pci_get_drvdata(pdev);
  3728. unsigned char *bios = ivideo->SiS_Pr.VirtualRomBase;
  3729. u8 reg, v1, v2, v3, v4, v5, v6, v7, v8;
  3730. u16 index, rindex, memtype = 0;
  3731. unsigned int mapsize;
  3732. if(!ivideo->SiS_Pr.UseROM)
  3733. bios = NULL;
  3734. SiS_SetReg(SISSR, 0x05, 0x86);
  3735. if(bios) {
  3736. if(bios[0x52] & 0x80) {
  3737. memtype = bios[0x52];
  3738. } else {
  3739. memtype = SiS_GetReg(SISSR, 0x3a);
  3740. }
  3741. memtype &= 0x07;
  3742. }
  3743. v3 = 0x80; v6 = 0x80;
  3744. if(ivideo->revision_id <= 0x13) {
  3745. v1 = 0x44; v2 = 0x42;
  3746. v4 = 0x44; v5 = 0x42;
  3747. } else {
  3748. v1 = 0x68; v2 = 0x43; /* Assume 125Mhz MCLK */
  3749. v4 = 0x68; v5 = 0x43; /* Assume 125Mhz ECLK */
  3750. if(bios) {
  3751. index = memtype * 5;
  3752. rindex = index + 0x54;
  3753. v1 = bios[rindex++];
  3754. v2 = bios[rindex++];
  3755. v3 = bios[rindex++];
  3756. rindex = index + 0x7c;
  3757. v4 = bios[rindex++];
  3758. v5 = bios[rindex++];
  3759. v6 = bios[rindex++];
  3760. }
  3761. }
  3762. SiS_SetReg(SISSR, 0x28, v1);
  3763. SiS_SetReg(SISSR, 0x29, v2);
  3764. SiS_SetReg(SISSR, 0x2a, v3);
  3765. SiS_SetReg(SISSR, 0x2e, v4);
  3766. SiS_SetReg(SISSR, 0x2f, v5);
  3767. SiS_SetReg(SISSR, 0x30, v6);
  3768. v1 = 0x10;
  3769. if(bios)
  3770. v1 = bios[0xa4];
  3771. SiS_SetReg(SISSR, 0x07, v1); /* DAC speed */
  3772. SiS_SetReg(SISSR, 0x11, 0x0f); /* DDC, power save */
  3773. v1 = 0x01; v2 = 0x43; v3 = 0x1e; v4 = 0x2a;
  3774. v5 = 0x06; v6 = 0x00; v7 = 0x00; v8 = 0x00;
  3775. if(bios) {
  3776. memtype += 0xa5;
  3777. v1 = bios[memtype];
  3778. v2 = bios[memtype + 8];
  3779. v3 = bios[memtype + 16];
  3780. v4 = bios[memtype + 24];
  3781. v5 = bios[memtype + 32];
  3782. v6 = bios[memtype + 40];
  3783. v7 = bios[memtype + 48];
  3784. v8 = bios[memtype + 56];
  3785. }
  3786. if(ivideo->revision_id >= 0x80)
  3787. v3 &= 0xfd;
  3788. SiS_SetReg(SISSR, 0x15, v1); /* Ram type (assuming 0, BIOS 0xa5 step 8) */
  3789. SiS_SetReg(SISSR, 0x16, v2);
  3790. SiS_SetReg(SISSR, 0x17, v3);
  3791. SiS_SetReg(SISSR, 0x18, v4);
  3792. SiS_SetReg(SISSR, 0x19, v5);
  3793. SiS_SetReg(SISSR, 0x1a, v6);
  3794. SiS_SetReg(SISSR, 0x1b, v7);
  3795. SiS_SetReg(SISSR, 0x1c, v8); /* ---- */
  3796. SiS_SetRegAND(SISSR, 0x15, 0xfb);
  3797. SiS_SetRegOR(SISSR, 0x15, 0x04);
  3798. if(bios) {
  3799. if(bios[0x53] & 0x02) {
  3800. SiS_SetRegOR(SISSR, 0x19, 0x20);
  3801. }
  3802. }
  3803. v1 = 0x04; /* DAC pedestal (BIOS 0xe5) */
  3804. if(ivideo->revision_id >= 0x80)
  3805. v1 |= 0x01;
  3806. SiS_SetReg(SISSR, 0x1f, v1);
  3807. SiS_SetReg(SISSR, 0x20, 0xa4); /* linear & relocated io & disable a0000 */
  3808. v1 = 0xf6; v2 = 0x0d; v3 = 0x00;
  3809. if(bios) {
  3810. v1 = bios[0xe8];
  3811. v2 = bios[0xe9];
  3812. v3 = bios[0xea];
  3813. }
  3814. SiS_SetReg(SISSR, 0x23, v1);
  3815. SiS_SetReg(SISSR, 0x24, v2);
  3816. SiS_SetReg(SISSR, 0x25, v3);
  3817. SiS_SetReg(SISSR, 0x21, 0x84);
  3818. SiS_SetReg(SISSR, 0x22, 0x00);
  3819. SiS_SetReg(SISCR, 0x37, 0x00);
  3820. SiS_SetRegOR(SISPART1, 0x24, 0x01); /* unlock crt2 */
  3821. SiS_SetReg(SISPART1, 0x00, 0x00);
  3822. v1 = 0x40; v2 = 0x11;
  3823. if(bios) {
  3824. v1 = bios[0xec];
  3825. v2 = bios[0xeb];
  3826. }
  3827. SiS_SetReg(SISPART1, 0x02, v1);
  3828. if(ivideo->revision_id >= 0x80)
  3829. v2 &= ~0x01;
  3830. reg = SiS_GetReg(SISPART4, 0x00);
  3831. if((reg == 1) || (reg == 2)) {
  3832. SiS_SetReg(SISCR, 0x37, 0x02);
  3833. SiS_SetReg(SISPART2, 0x00, 0x1c);
  3834. v4 = 0x00; v5 = 0x00; v6 = 0x10;
  3835. if(ivideo->SiS_Pr.UseROM) {
  3836. v4 = bios[0xf5];
  3837. v5 = bios[0xf6];
  3838. v6 = bios[0xf7];
  3839. }
  3840. SiS_SetReg(SISPART4, 0x0d, v4);
  3841. SiS_SetReg(SISPART4, 0x0e, v5);
  3842. SiS_SetReg(SISPART4, 0x10, v6);
  3843. SiS_SetReg(SISPART4, 0x0f, 0x3f);
  3844. reg = SiS_GetReg(SISPART4, 0x01);
  3845. if(reg >= 0xb0) {
  3846. reg = SiS_GetReg(SISPART4, 0x23);
  3847. reg &= 0x20;
  3848. reg <<= 1;
  3849. SiS_SetReg(SISPART4, 0x23, reg);
  3850. }
  3851. } else {
  3852. v2 &= ~0x10;
  3853. }
  3854. SiS_SetReg(SISSR, 0x32, v2);
  3855. SiS_SetRegAND(SISPART1, 0x24, 0xfe); /* Lock CRT2 */
  3856. reg = SiS_GetReg(SISSR, 0x16);
  3857. reg &= 0xc3;
  3858. SiS_SetReg(SISCR, 0x35, reg);
  3859. SiS_SetReg(SISCR, 0x83, 0x00);
  3860. #if !defined(__i386__) && !defined(__x86_64__)
  3861. if(sisfb_videoram) {
  3862. SiS_SetReg(SISSR, 0x13, 0x28); /* ? */
  3863. reg = ((sisfb_videoram >> 10) - 1) | 0x40;
  3864. SiS_SetReg(SISSR, 0x14, reg);
  3865. } else {
  3866. #endif
  3867. /* Need to map max FB size for finding out about RAM size */
  3868. mapsize = ivideo->video_size;
  3869. sisfb_post_map_vram(ivideo, &mapsize, 4);
  3870. if(ivideo->video_vbase) {
  3871. sisfb_post_300_ramsize(pdev, mapsize);
  3872. iounmap(ivideo->video_vbase);
  3873. } else {
  3874. printk(KERN_DEBUG
  3875. "sisfb: Failed to map memory for size detection, assuming 8MB\n");
  3876. SiS_SetReg(SISSR, 0x13, 0x28); /* ? */
  3877. SiS_SetReg(SISSR, 0x14, 0x47); /* 8MB, 64bit default */
  3878. }
  3879. #if !defined(__i386__) && !defined(__x86_64__)
  3880. }
  3881. #endif
  3882. if(bios) {
  3883. v1 = bios[0xe6];
  3884. v2 = bios[0xe7];
  3885. } else {
  3886. reg = SiS_GetReg(SISSR, 0x3a);
  3887. if((reg & 0x30) == 0x30) {
  3888. v1 = 0x04; /* PCI */
  3889. v2 = 0x92;
  3890. } else {
  3891. v1 = 0x14; /* AGP */
  3892. v2 = 0xb2;
  3893. }
  3894. }
  3895. SiS_SetReg(SISSR, 0x21, v1);
  3896. SiS_SetReg(SISSR, 0x22, v2);
  3897. /* Sense CRT1 */
  3898. sisfb_sense_crt1(ivideo);
  3899. /* Set default mode, don't clear screen */
  3900. ivideo->SiS_Pr.SiS_UseOEM = false;
  3901. SiS_SetEnableDstn(&ivideo->SiS_Pr, false);
  3902. SiS_SetEnableFstn(&ivideo->SiS_Pr, false);
  3903. ivideo->curFSTN = ivideo->curDSTN = 0;
  3904. ivideo->SiS_Pr.VideoMemorySize = 8 << 20;
  3905. SiSSetMode(&ivideo->SiS_Pr, 0x2e | 0x80);
  3906. SiS_SetReg(SISSR, 0x05, 0x86);
  3907. /* Display off */
  3908. SiS_SetRegOR(SISSR, 0x01, 0x20);
  3909. /* Save mode number in CR34 */
  3910. SiS_SetReg(SISCR, 0x34, 0x2e);
  3911. /* Let everyone know what the current mode is */
  3912. ivideo->modeprechange = 0x2e;
  3913. }
  3914. #endif
  3915. #ifdef CONFIG_FB_SIS_315
  3916. #if 0
  3917. static void sisfb_post_sis315330(struct pci_dev *pdev)
  3918. {
  3919. /* TODO */
  3920. }
  3921. #endif
  3922. static inline int sisfb_xgi_is21(struct sis_video_info *ivideo)
  3923. {
  3924. return ivideo->chip_real_id == XGI_21;
  3925. }
  3926. static void sisfb_post_xgi_delay(struct sis_video_info *ivideo, int delay)
  3927. {
  3928. unsigned int i;
  3929. u8 reg;
  3930. for(i = 0; i <= (delay * 10 * 36); i++) {
  3931. reg = SiS_GetReg(SISSR, 0x05);
  3932. reg++;
  3933. }
  3934. }
  3935. static int sisfb_find_host_bridge(struct sis_video_info *ivideo,
  3936. struct pci_dev *mypdev,
  3937. unsigned short pcivendor)
  3938. {
  3939. struct pci_dev *pdev = NULL;
  3940. unsigned short temp;
  3941. int ret = 0;
  3942. while((pdev = pci_get_class(PCI_CLASS_BRIDGE_HOST, pdev))) {
  3943. temp = pdev->vendor;
  3944. if(temp == pcivendor) {
  3945. ret = 1;
  3946. pci_dev_put(pdev);
  3947. break;
  3948. }
  3949. }
  3950. return ret;
  3951. }
  3952. static int sisfb_post_xgi_rwtest(struct sis_video_info *ivideo, int starta,
  3953. unsigned int enda, unsigned int mapsize)
  3954. {
  3955. unsigned int pos;
  3956. int i;
  3957. writel(0, ivideo->video_vbase);
  3958. for(i = starta; i <= enda; i++) {
  3959. pos = 1 << i;
  3960. if(pos < mapsize)
  3961. writel(pos, ivideo->video_vbase + pos);
  3962. }
  3963. sisfb_post_xgi_delay(ivideo, 150);
  3964. if(readl(ivideo->video_vbase) != 0)
  3965. return 0;
  3966. for(i = starta; i <= enda; i++) {
  3967. pos = 1 << i;
  3968. if(pos < mapsize) {
  3969. if(readl(ivideo->video_vbase + pos) != pos)
  3970. return 0;
  3971. } else
  3972. return 0;
  3973. }
  3974. return 1;
  3975. }
  3976. static int sisfb_post_xgi_ramsize(struct sis_video_info *ivideo)
  3977. {
  3978. unsigned int buswidth, ranksize, channelab, mapsize;
  3979. int i, j, k, l, status;
  3980. u8 reg, sr14;
  3981. static const u8 dramsr13[12 * 5] = {
  3982. 0x02, 0x0e, 0x0b, 0x80, 0x5d,
  3983. 0x02, 0x0e, 0x0a, 0x40, 0x59,
  3984. 0x02, 0x0d, 0x0b, 0x40, 0x4d,
  3985. 0x02, 0x0e, 0x09, 0x20, 0x55,
  3986. 0x02, 0x0d, 0x0a, 0x20, 0x49,
  3987. 0x02, 0x0c, 0x0b, 0x20, 0x3d,
  3988. 0x02, 0x0e, 0x08, 0x10, 0x51,
  3989. 0x02, 0x0d, 0x09, 0x10, 0x45,
  3990. 0x02, 0x0c, 0x0a, 0x10, 0x39,
  3991. 0x02, 0x0d, 0x08, 0x08, 0x41,
  3992. 0x02, 0x0c, 0x09, 0x08, 0x35,
  3993. 0x02, 0x0c, 0x08, 0x04, 0x31
  3994. };
  3995. static const u8 dramsr13_4[4 * 5] = {
  3996. 0x02, 0x0d, 0x09, 0x40, 0x45,
  3997. 0x02, 0x0c, 0x09, 0x20, 0x35,
  3998. 0x02, 0x0c, 0x08, 0x10, 0x31,
  3999. 0x02, 0x0b, 0x08, 0x08, 0x21
  4000. };
  4001. /* Enable linear mode, disable 0xa0000 address decoding */
  4002. /* We disable a0000 address decoding, because
  4003. * - if running on x86, if the card is disabled, it means
  4004. * that another card is in the system. We don't want
  4005. * to interphere with that primary card's textmode.
  4006. * - if running on non-x86, there usually is no VGA window
  4007. * at a0000.
  4008. */
  4009. SiS_SetRegOR(SISSR, 0x20, (0x80 | 0x04));
  4010. /* Need to map max FB size for finding out about RAM size */
  4011. mapsize = ivideo->video_size;
  4012. sisfb_post_map_vram(ivideo, &mapsize, 32);
  4013. if(!ivideo->video_vbase) {
  4014. printk(KERN_ERR "sisfb: Unable to detect RAM size. Setting default.\n");
  4015. SiS_SetReg(SISSR, 0x13, 0x35);
  4016. SiS_SetReg(SISSR, 0x14, 0x41);
  4017. /* TODO */
  4018. return -ENOMEM;
  4019. }
  4020. /* Non-interleaving */
  4021. SiS_SetReg(SISSR, 0x15, 0x00);
  4022. /* No tiling */
  4023. SiS_SetReg(SISSR, 0x1c, 0x00);
  4024. if(ivideo->chip == XGI_20) {
  4025. channelab = 1;
  4026. reg = SiS_GetReg(SISCR, 0x97);
  4027. if(!(reg & 0x01)) { /* Single 32/16 */
  4028. buswidth = 32;
  4029. SiS_SetReg(SISSR, 0x13, 0xb1);
  4030. SiS_SetReg(SISSR, 0x14, 0x52);
  4031. sisfb_post_xgi_delay(ivideo, 1);
  4032. sr14 = 0x02;
  4033. if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
  4034. goto bail_out;
  4035. SiS_SetReg(SISSR, 0x13, 0x31);
  4036. SiS_SetReg(SISSR, 0x14, 0x42);
  4037. sisfb_post_xgi_delay(ivideo, 1);
  4038. if(sisfb_post_xgi_rwtest(ivideo, 23, 23, mapsize))
  4039. goto bail_out;
  4040. buswidth = 16;
  4041. SiS_SetReg(SISSR, 0x13, 0xb1);
  4042. SiS_SetReg(SISSR, 0x14, 0x41);
  4043. sisfb_post_xgi_delay(ivideo, 1);
  4044. sr14 = 0x01;
  4045. if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
  4046. goto bail_out;
  4047. else
  4048. SiS_SetReg(SISSR, 0x13, 0x31);
  4049. } else { /* Dual 16/8 */
  4050. buswidth = 16;
  4051. SiS_SetReg(SISSR, 0x13, 0xb1);
  4052. SiS_SetReg(SISSR, 0x14, 0x41);
  4053. sisfb_post_xgi_delay(ivideo, 1);
  4054. sr14 = 0x01;
  4055. if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
  4056. goto bail_out;
  4057. SiS_SetReg(SISSR, 0x13, 0x31);
  4058. SiS_SetReg(SISSR, 0x14, 0x31);
  4059. sisfb_post_xgi_delay(ivideo, 1);
  4060. if(sisfb_post_xgi_rwtest(ivideo, 22, 22, mapsize))
  4061. goto bail_out;
  4062. buswidth = 8;
  4063. SiS_SetReg(SISSR, 0x13, 0xb1);
  4064. SiS_SetReg(SISSR, 0x14, 0x30);
  4065. sisfb_post_xgi_delay(ivideo, 1);
  4066. sr14 = 0x00;
  4067. if(sisfb_post_xgi_rwtest(ivideo, 21, 22, mapsize))
  4068. goto bail_out;
  4069. else
  4070. SiS_SetReg(SISSR, 0x13, 0x31);
  4071. }
  4072. } else { /* XGI_40 */
  4073. reg = SiS_GetReg(SISCR, 0x97);
  4074. if(!(reg & 0x10)) {
  4075. reg = SiS_GetReg(SISSR, 0x39);
  4076. reg >>= 1;
  4077. }
  4078. if(reg & 0x01) { /* DDRII */
  4079. buswidth = 32;
  4080. if(ivideo->revision_id == 2) {
  4081. channelab = 2;
  4082. SiS_SetReg(SISSR, 0x13, 0xa1);
  4083. SiS_SetReg(SISSR, 0x14, 0x44);
  4084. sr14 = 0x04;
  4085. sisfb_post_xgi_delay(ivideo, 1);
  4086. if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
  4087. goto bail_out;
  4088. SiS_SetReg(SISSR, 0x13, 0x21);
  4089. SiS_SetReg(SISSR, 0x14, 0x34);
  4090. if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
  4091. goto bail_out;
  4092. channelab = 1;
  4093. SiS_SetReg(SISSR, 0x13, 0xa1);
  4094. SiS_SetReg(SISSR, 0x14, 0x40);
  4095. sr14 = 0x00;
  4096. if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
  4097. goto bail_out;
  4098. SiS_SetReg(SISSR, 0x13, 0x21);
  4099. SiS_SetReg(SISSR, 0x14, 0x30);
  4100. } else {
  4101. channelab = 3;
  4102. SiS_SetReg(SISSR, 0x13, 0xa1);
  4103. SiS_SetReg(SISSR, 0x14, 0x4c);
  4104. sr14 = 0x0c;
  4105. sisfb_post_xgi_delay(ivideo, 1);
  4106. if(sisfb_post_xgi_rwtest(ivideo, 23, 25, mapsize))
  4107. goto bail_out;
  4108. channelab = 2;
  4109. SiS_SetReg(SISSR, 0x14, 0x48);
  4110. sisfb_post_xgi_delay(ivideo, 1);
  4111. sr14 = 0x08;
  4112. if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
  4113. goto bail_out;
  4114. SiS_SetReg(SISSR, 0x13, 0x21);
  4115. SiS_SetReg(SISSR, 0x14, 0x3c);
  4116. sr14 = 0x0c;
  4117. if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize)) {
  4118. channelab = 3;
  4119. } else {
  4120. channelab = 2;
  4121. SiS_SetReg(SISSR, 0x14, 0x38);
  4122. sr14 = 0x08;
  4123. }
  4124. }
  4125. sisfb_post_xgi_delay(ivideo, 1);
  4126. } else { /* DDR */
  4127. buswidth = 64;
  4128. if(ivideo->revision_id == 2) {
  4129. channelab = 1;
  4130. SiS_SetReg(SISSR, 0x13, 0xa1);
  4131. SiS_SetReg(SISSR, 0x14, 0x52);
  4132. sisfb_post_xgi_delay(ivideo, 1);
  4133. sr14 = 0x02;
  4134. if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
  4135. goto bail_out;
  4136. SiS_SetReg(SISSR, 0x13, 0x21);
  4137. SiS_SetReg(SISSR, 0x14, 0x42);
  4138. } else {
  4139. channelab = 2;
  4140. SiS_SetReg(SISSR, 0x13, 0xa1);
  4141. SiS_SetReg(SISSR, 0x14, 0x5a);
  4142. sisfb_post_xgi_delay(ivideo, 1);
  4143. sr14 = 0x0a;
  4144. if(sisfb_post_xgi_rwtest(ivideo, 24, 25, mapsize))
  4145. goto bail_out;
  4146. SiS_SetReg(SISSR, 0x13, 0x21);
  4147. SiS_SetReg(SISSR, 0x14, 0x4a);
  4148. }
  4149. sisfb_post_xgi_delay(ivideo, 1);
  4150. }
  4151. }
  4152. bail_out:
  4153. SiS_SetRegANDOR(SISSR, 0x14, 0xf0, sr14);
  4154. sisfb_post_xgi_delay(ivideo, 1);
  4155. j = (ivideo->chip == XGI_20) ? 5 : 9;
  4156. k = (ivideo->chip == XGI_20) ? 12 : 4;
  4157. status = -EIO;
  4158. for(i = 0; i < k; i++) {
  4159. reg = (ivideo->chip == XGI_20) ?
  4160. dramsr13[(i * 5) + 4] : dramsr13_4[(i * 5) + 4];
  4161. SiS_SetRegANDOR(SISSR, 0x13, 0x80, reg);
  4162. sisfb_post_xgi_delay(ivideo, 50);
  4163. ranksize = (ivideo->chip == XGI_20) ?
  4164. dramsr13[(i * 5) + 3] : dramsr13_4[(i * 5) + 3];
  4165. reg = SiS_GetReg(SISSR, 0x13);
  4166. if(reg & 0x80) ranksize <<= 1;
  4167. if(ivideo->chip == XGI_20) {
  4168. if(buswidth == 16) ranksize <<= 1;
  4169. else if(buswidth == 32) ranksize <<= 2;
  4170. } else {
  4171. if(buswidth == 64) ranksize <<= 1;
  4172. }
  4173. reg = 0;
  4174. l = channelab;
  4175. if(l == 3) l = 4;
  4176. if((ranksize * l) <= 256) {
  4177. while((ranksize >>= 1)) reg += 0x10;
  4178. }
  4179. if(!reg) continue;
  4180. SiS_SetRegANDOR(SISSR, 0x14, 0x0f, (reg & 0xf0));
  4181. sisfb_post_xgi_delay(ivideo, 1);
  4182. if (sisfb_post_xgi_rwtest(ivideo, j, ((reg >> 4) + channelab - 2 + 20), mapsize)) {
  4183. status = 0;
  4184. break;
  4185. }
  4186. }
  4187. iounmap(ivideo->video_vbase);
  4188. return status;
  4189. }
  4190. static void sisfb_post_xgi_setclocks(struct sis_video_info *ivideo, u8 regb)
  4191. {
  4192. u8 v1, v2, v3;
  4193. int index;
  4194. static const u8 cs90[8 * 3] = {
  4195. 0x16, 0x01, 0x01,
  4196. 0x3e, 0x03, 0x01,
  4197. 0x7c, 0x08, 0x01,
  4198. 0x79, 0x06, 0x01,
  4199. 0x29, 0x01, 0x81,
  4200. 0x5c, 0x23, 0x01,
  4201. 0x5c, 0x23, 0x01,
  4202. 0x5c, 0x23, 0x01
  4203. };
  4204. static const u8 csb8[8 * 3] = {
  4205. 0x5c, 0x23, 0x01,
  4206. 0x29, 0x01, 0x01,
  4207. 0x7c, 0x08, 0x01,
  4208. 0x79, 0x06, 0x01,
  4209. 0x29, 0x01, 0x81,
  4210. 0x5c, 0x23, 0x01,
  4211. 0x5c, 0x23, 0x01,
  4212. 0x5c, 0x23, 0x01
  4213. };
  4214. regb = 0; /* ! */
  4215. index = regb * 3;
  4216. v1 = cs90[index]; v2 = cs90[index + 1]; v3 = cs90[index + 2];
  4217. if(ivideo->haveXGIROM) {
  4218. v1 = ivideo->bios_abase[0x90 + index];
  4219. v2 = ivideo->bios_abase[0x90 + index + 1];
  4220. v3 = ivideo->bios_abase[0x90 + index + 2];
  4221. }
  4222. SiS_SetReg(SISSR, 0x28, v1);
  4223. SiS_SetReg(SISSR, 0x29, v2);
  4224. SiS_SetReg(SISSR, 0x2a, v3);
  4225. sisfb_post_xgi_delay(ivideo, 0x43);
  4226. sisfb_post_xgi_delay(ivideo, 0x43);
  4227. sisfb_post_xgi_delay(ivideo, 0x43);
  4228. index = regb * 3;
  4229. v1 = csb8[index]; v2 = csb8[index + 1]; v3 = csb8[index + 2];
  4230. if(ivideo->haveXGIROM) {
  4231. v1 = ivideo->bios_abase[0xb8 + index];
  4232. v2 = ivideo->bios_abase[0xb8 + index + 1];
  4233. v3 = ivideo->bios_abase[0xb8 + index + 2];
  4234. }
  4235. SiS_SetReg(SISSR, 0x2e, v1);
  4236. SiS_SetReg(SISSR, 0x2f, v2);
  4237. SiS_SetReg(SISSR, 0x30, v3);
  4238. sisfb_post_xgi_delay(ivideo, 0x43);
  4239. sisfb_post_xgi_delay(ivideo, 0x43);
  4240. sisfb_post_xgi_delay(ivideo, 0x43);
  4241. }
  4242. static void sisfb_post_xgi_ddr2_mrs_default(struct sis_video_info *ivideo,
  4243. u8 regb)
  4244. {
  4245. unsigned char *bios = ivideo->bios_abase;
  4246. u8 v1;
  4247. SiS_SetReg(SISSR, 0x28, 0x64);
  4248. SiS_SetReg(SISSR, 0x29, 0x63);
  4249. sisfb_post_xgi_delay(ivideo, 15);
  4250. SiS_SetReg(SISSR, 0x18, 0x00);
  4251. SiS_SetReg(SISSR, 0x19, 0x20);
  4252. SiS_SetReg(SISSR, 0x16, 0x00);
  4253. SiS_SetReg(SISSR, 0x16, 0x80);
  4254. SiS_SetReg(SISSR, 0x18, 0xc5);
  4255. SiS_SetReg(SISSR, 0x19, 0x23);
  4256. SiS_SetReg(SISSR, 0x16, 0x00);
  4257. SiS_SetReg(SISSR, 0x16, 0x80);
  4258. sisfb_post_xgi_delay(ivideo, 1);
  4259. SiS_SetReg(SISCR, 0x97, 0x11);
  4260. sisfb_post_xgi_setclocks(ivideo, regb);
  4261. sisfb_post_xgi_delay(ivideo, 0x46);
  4262. SiS_SetReg(SISSR, 0x18, 0xc5);
  4263. SiS_SetReg(SISSR, 0x19, 0x23);
  4264. SiS_SetReg(SISSR, 0x16, 0x00);
  4265. SiS_SetReg(SISSR, 0x16, 0x80);
  4266. sisfb_post_xgi_delay(ivideo, 1);
  4267. SiS_SetReg(SISSR, 0x1b, 0x04);
  4268. sisfb_post_xgi_delay(ivideo, 1);
  4269. SiS_SetReg(SISSR, 0x1b, 0x00);
  4270. sisfb_post_xgi_delay(ivideo, 1);
  4271. v1 = 0x31;
  4272. if (ivideo->haveXGIROM) {
  4273. v1 = bios[0xf0];
  4274. }
  4275. SiS_SetReg(SISSR, 0x18, v1);
  4276. SiS_SetReg(SISSR, 0x19, 0x06);
  4277. SiS_SetReg(SISSR, 0x16, 0x04);
  4278. SiS_SetReg(SISSR, 0x16, 0x84);
  4279. sisfb_post_xgi_delay(ivideo, 1);
  4280. }
  4281. static void sisfb_post_xgi_ddr2_mrs_xg21(struct sis_video_info *ivideo)
  4282. {
  4283. sisfb_post_xgi_setclocks(ivideo, 1);
  4284. SiS_SetReg(SISCR, 0x97, 0x11);
  4285. sisfb_post_xgi_delay(ivideo, 0x46);
  4286. SiS_SetReg(SISSR, 0x18, 0x00); /* EMRS2 */
  4287. SiS_SetReg(SISSR, 0x19, 0x80);
  4288. SiS_SetReg(SISSR, 0x16, 0x05);
  4289. SiS_SetReg(SISSR, 0x16, 0x85);
  4290. SiS_SetReg(SISSR, 0x18, 0x00); /* EMRS3 */
  4291. SiS_SetReg(SISSR, 0x19, 0xc0);
  4292. SiS_SetReg(SISSR, 0x16, 0x05);
  4293. SiS_SetReg(SISSR, 0x16, 0x85);
  4294. SiS_SetReg(SISSR, 0x18, 0x00); /* EMRS1 */
  4295. SiS_SetReg(SISSR, 0x19, 0x40);
  4296. SiS_SetReg(SISSR, 0x16, 0x05);
  4297. SiS_SetReg(SISSR, 0x16, 0x85);
  4298. SiS_SetReg(SISSR, 0x18, 0x42); /* MRS1 */
  4299. SiS_SetReg(SISSR, 0x19, 0x02);
  4300. SiS_SetReg(SISSR, 0x16, 0x05);
  4301. SiS_SetReg(SISSR, 0x16, 0x85);
  4302. sisfb_post_xgi_delay(ivideo, 1);
  4303. SiS_SetReg(SISSR, 0x1b, 0x04);
  4304. sisfb_post_xgi_delay(ivideo, 1);
  4305. SiS_SetReg(SISSR, 0x1b, 0x00);
  4306. sisfb_post_xgi_delay(ivideo, 1);
  4307. SiS_SetReg(SISSR, 0x18, 0x42); /* MRS1 */
  4308. SiS_SetReg(SISSR, 0x19, 0x00);
  4309. SiS_SetReg(SISSR, 0x16, 0x05);
  4310. SiS_SetReg(SISSR, 0x16, 0x85);
  4311. sisfb_post_xgi_delay(ivideo, 1);
  4312. }
  4313. static void sisfb_post_xgi_ddr2(struct sis_video_info *ivideo, u8 regb)
  4314. {
  4315. unsigned char *bios = ivideo->bios_abase;
  4316. static const u8 cs158[8] = {
  4317. 0x88, 0xaa, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00
  4318. };
  4319. static const u8 cs160[8] = {
  4320. 0x44, 0x77, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00
  4321. };
  4322. static const u8 cs168[8] = {
  4323. 0x48, 0x78, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00
  4324. };
  4325. u8 reg;
  4326. u8 v1;
  4327. u8 v2;
  4328. u8 v3;
  4329. SiS_SetReg(SISCR, 0xb0, 0x80); /* DDR2 dual frequency mode */
  4330. SiS_SetReg(SISCR, 0x82, 0x77);
  4331. SiS_SetReg(SISCR, 0x86, 0x00);
  4332. reg = SiS_GetReg(SISCR, 0x86);
  4333. SiS_SetReg(SISCR, 0x86, 0x88);
  4334. reg = SiS_GetReg(SISCR, 0x86);
  4335. v1 = cs168[regb]; v2 = cs160[regb]; v3 = cs158[regb];
  4336. if (ivideo->haveXGIROM) {
  4337. v1 = bios[regb + 0x168];
  4338. v2 = bios[regb + 0x160];
  4339. v3 = bios[regb + 0x158];
  4340. }
  4341. SiS_SetReg(SISCR, 0x86, v1);
  4342. SiS_SetReg(SISCR, 0x82, 0x77);
  4343. SiS_SetReg(SISCR, 0x85, 0x00);
  4344. reg = SiS_GetReg(SISCR, 0x85);
  4345. SiS_SetReg(SISCR, 0x85, 0x88);
  4346. reg = SiS_GetReg(SISCR, 0x85);
  4347. SiS_SetReg(SISCR, 0x85, v2);
  4348. SiS_SetReg(SISCR, 0x82, v3);
  4349. SiS_SetReg(SISCR, 0x98, 0x01);
  4350. SiS_SetReg(SISCR, 0x9a, 0x02);
  4351. if (sisfb_xgi_is21(ivideo))
  4352. sisfb_post_xgi_ddr2_mrs_xg21(ivideo);
  4353. else
  4354. sisfb_post_xgi_ddr2_mrs_default(ivideo, regb);
  4355. }
  4356. static u8 sisfb_post_xgi_ramtype(struct sis_video_info *ivideo)
  4357. {
  4358. unsigned char *bios = ivideo->bios_abase;
  4359. u8 ramtype;
  4360. u8 reg;
  4361. u8 v1;
  4362. ramtype = 0x00; v1 = 0x10;
  4363. if (ivideo->haveXGIROM) {
  4364. ramtype = bios[0x62];
  4365. v1 = bios[0x1d2];
  4366. }
  4367. if (!(ramtype & 0x80)) {
  4368. if (sisfb_xgi_is21(ivideo)) {
  4369. SiS_SetRegAND(SISCR, 0xb4, 0xfd); /* GPIO control */
  4370. SiS_SetRegOR(SISCR, 0x4a, 0x80); /* GPIOH EN */
  4371. reg = SiS_GetReg(SISCR, 0x48);
  4372. SiS_SetRegOR(SISCR, 0xb4, 0x02);
  4373. ramtype = reg & 0x01; /* GPIOH */
  4374. } else if (ivideo->chip == XGI_20) {
  4375. SiS_SetReg(SISCR, 0x97, v1);
  4376. reg = SiS_GetReg(SISCR, 0x97);
  4377. if (reg & 0x10) {
  4378. ramtype = (reg & 0x01) << 1;
  4379. }
  4380. } else {
  4381. reg = SiS_GetReg(SISSR, 0x39);
  4382. ramtype = reg & 0x02;
  4383. if (!(ramtype)) {
  4384. reg = SiS_GetReg(SISSR, 0x3a);
  4385. ramtype = (reg >> 1) & 0x01;
  4386. }
  4387. }
  4388. }
  4389. ramtype &= 0x07;
  4390. return ramtype;
  4391. }
  4392. static int sisfb_post_xgi(struct pci_dev *pdev)
  4393. {
  4394. struct sis_video_info *ivideo = pci_get_drvdata(pdev);
  4395. unsigned char *bios = ivideo->bios_abase;
  4396. struct pci_dev *mypdev = NULL;
  4397. const u8 *ptr, *ptr2;
  4398. u8 v1, v2, v3, v4, v5, reg, ramtype;
  4399. u32 rega, regb, regd;
  4400. int i, j, k, index;
  4401. static const u8 cs78[3] = { 0xf6, 0x0d, 0x00 };
  4402. static const u8 cs76[2] = { 0xa3, 0xfb };
  4403. static const u8 cs7b[3] = { 0xc0, 0x11, 0x00 };
  4404. static const u8 cs158[8] = {
  4405. 0x88, 0xaa, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00
  4406. };
  4407. static const u8 cs160[8] = {
  4408. 0x44, 0x77, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00
  4409. };
  4410. static const u8 cs168[8] = {
  4411. 0x48, 0x78, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00
  4412. };
  4413. static const u8 cs128[3 * 8] = {
  4414. 0x90, 0x28, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00,
  4415. 0x77, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
  4416. 0x77, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00
  4417. };
  4418. static const u8 cs148[2 * 8] = {
  4419. 0x55, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00,
  4420. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  4421. };
  4422. static const u8 cs31a[8 * 4] = {
  4423. 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
  4424. 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00,
  4425. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  4426. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  4427. };
  4428. static const u8 cs33a[8 * 4] = {
  4429. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  4430. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  4431. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  4432. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  4433. };
  4434. static const u8 cs45a[8 * 2] = {
  4435. 0x00, 0x00, 0xa0, 0x00, 0xa0, 0x00, 0x00, 0x00,
  4436. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  4437. };
  4438. static const u8 cs170[7 * 8] = {
  4439. 0x54, 0x32, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
  4440. 0x54, 0x43, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
  4441. 0x0a, 0x05, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
  4442. 0x44, 0x34, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
  4443. 0x10, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00,
  4444. 0x11, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00,
  4445. 0x05, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00
  4446. };
  4447. static const u8 cs1a8[3 * 8] = {
  4448. 0xf0, 0xf0, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00,
  4449. 0x05, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
  4450. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  4451. };
  4452. static const u8 cs100[2 * 8] = {
  4453. 0xc4, 0x04, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00,
  4454. 0xc4, 0x04, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00
  4455. };
  4456. /* VGA enable */
  4457. reg = SiS_GetRegByte(SISVGAENABLE) | 0x01;
  4458. SiS_SetRegByte(SISVGAENABLE, reg);
  4459. /* Misc */
  4460. reg = SiS_GetRegByte(SISMISCR) | 0x01;
  4461. SiS_SetRegByte(SISMISCW, reg);
  4462. /* Unlock SR */
  4463. SiS_SetReg(SISSR, 0x05, 0x86);
  4464. reg = SiS_GetReg(SISSR, 0x05);
  4465. if(reg != 0xa1)
  4466. return 0;
  4467. /* Clear some regs */
  4468. for(i = 0; i < 0x22; i++) {
  4469. if(0x06 + i == 0x20) continue;
  4470. SiS_SetReg(SISSR, 0x06 + i, 0x00);
  4471. }
  4472. for(i = 0; i < 0x0b; i++) {
  4473. SiS_SetReg(SISSR, 0x31 + i, 0x00);
  4474. }
  4475. for(i = 0; i < 0x10; i++) {
  4476. SiS_SetReg(SISCR, 0x30 + i, 0x00);
  4477. }
  4478. ptr = cs78;
  4479. if(ivideo->haveXGIROM) {
  4480. ptr = (const u8 *)&bios[0x78];
  4481. }
  4482. for(i = 0; i < 3; i++) {
  4483. SiS_SetReg(SISSR, 0x23 + i, ptr[i]);
  4484. }
  4485. ptr = cs76;
  4486. if(ivideo->haveXGIROM) {
  4487. ptr = (const u8 *)&bios[0x76];
  4488. }
  4489. for(i = 0; i < 2; i++) {
  4490. SiS_SetReg(SISSR, 0x21 + i, ptr[i]);
  4491. }
  4492. v1 = 0x18; v2 = 0x00;
  4493. if(ivideo->haveXGIROM) {
  4494. v1 = bios[0x74];
  4495. v2 = bios[0x75];
  4496. }
  4497. SiS_SetReg(SISSR, 0x07, v1);
  4498. SiS_SetReg(SISSR, 0x11, 0x0f);
  4499. SiS_SetReg(SISSR, 0x1f, v2);
  4500. /* PCI linear mode, RelIO enabled, A0000 decoding disabled */
  4501. SiS_SetReg(SISSR, 0x20, 0x80 | 0x20 | 0x04);
  4502. SiS_SetReg(SISSR, 0x27, 0x74);
  4503. ptr = cs7b;
  4504. if(ivideo->haveXGIROM) {
  4505. ptr = (const u8 *)&bios[0x7b];
  4506. }
  4507. for(i = 0; i < 3; i++) {
  4508. SiS_SetReg(SISSR, 0x31 + i, ptr[i]);
  4509. }
  4510. if(ivideo->chip == XGI_40) {
  4511. if(ivideo->revision_id == 2) {
  4512. SiS_SetRegANDOR(SISSR, 0x3b, 0x3f, 0xc0);
  4513. }
  4514. SiS_SetReg(SISCR, 0x7d, 0xfe);
  4515. SiS_SetReg(SISCR, 0x7e, 0x0f);
  4516. }
  4517. if(ivideo->revision_id == 0) { /* 40 *and* 20? */
  4518. SiS_SetRegAND(SISCR, 0x58, 0xd7);
  4519. reg = SiS_GetReg(SISCR, 0xcb);
  4520. if(reg & 0x20) {
  4521. SiS_SetRegANDOR(SISCR, 0x58, 0xd7, (reg & 0x10) ? 0x08 : 0x20); /* =0x28 Z7 ? */
  4522. }
  4523. }
  4524. reg = (ivideo->chip == XGI_40) ? 0x20 : 0x00;
  4525. SiS_SetRegANDOR(SISCR, 0x38, 0x1f, reg);
  4526. if(ivideo->chip == XGI_20) {
  4527. SiS_SetReg(SISSR, 0x36, 0x70);
  4528. } else {
  4529. SiS_SetReg(SISVID, 0x00, 0x86);
  4530. SiS_SetReg(SISVID, 0x32, 0x00);
  4531. SiS_SetReg(SISVID, 0x30, 0x00);
  4532. SiS_SetReg(SISVID, 0x32, 0x01);
  4533. SiS_SetReg(SISVID, 0x30, 0x00);
  4534. SiS_SetRegAND(SISVID, 0x2f, 0xdf);
  4535. SiS_SetRegAND(SISCAP, 0x00, 0x3f);
  4536. SiS_SetReg(SISPART1, 0x2f, 0x01);
  4537. SiS_SetReg(SISPART1, 0x00, 0x00);
  4538. SiS_SetReg(SISPART1, 0x02, bios[0x7e]);
  4539. SiS_SetReg(SISPART1, 0x2e, 0x08);
  4540. SiS_SetRegAND(SISPART1, 0x35, 0x7f);
  4541. SiS_SetRegAND(SISPART1, 0x50, 0xfe);
  4542. reg = SiS_GetReg(SISPART4, 0x00);
  4543. if(reg == 1 || reg == 2) {
  4544. SiS_SetReg(SISPART2, 0x00, 0x1c);
  4545. SiS_SetReg(SISPART4, 0x0d, bios[0x7f]);
  4546. SiS_SetReg(SISPART4, 0x0e, bios[0x80]);
  4547. SiS_SetReg(SISPART4, 0x10, bios[0x81]);
  4548. SiS_SetRegAND(SISPART4, 0x0f, 0x3f);
  4549. reg = SiS_GetReg(SISPART4, 0x01);
  4550. if((reg & 0xf0) >= 0xb0) {
  4551. reg = SiS_GetReg(SISPART4, 0x23);
  4552. if(reg & 0x20) reg |= 0x40;
  4553. SiS_SetReg(SISPART4, 0x23, reg);
  4554. reg = (reg & 0x20) ? 0x02 : 0x00;
  4555. SiS_SetRegANDOR(SISPART1, 0x1e, 0xfd, reg);
  4556. }
  4557. }
  4558. v1 = bios[0x77];
  4559. reg = SiS_GetReg(SISSR, 0x3b);
  4560. if(reg & 0x02) {
  4561. reg = SiS_GetReg(SISSR, 0x3a);
  4562. v2 = (reg & 0x30) >> 3;
  4563. if(!(v2 & 0x04)) v2 ^= 0x02;
  4564. reg = SiS_GetReg(SISSR, 0x39);
  4565. if(reg & 0x80) v2 |= 0x80;
  4566. v2 |= 0x01;
  4567. if((mypdev = pci_get_device(PCI_VENDOR_ID_SI, 0x0730, NULL))) {
  4568. pci_dev_put(mypdev);
  4569. if(((v2 & 0x06) == 2) || ((v2 & 0x06) == 4))
  4570. v2 &= 0xf9;
  4571. v2 |= 0x08;
  4572. v1 &= 0xfe;
  4573. } else {
  4574. mypdev = pci_get_device(PCI_VENDOR_ID_SI, 0x0735, NULL);
  4575. if(!mypdev)
  4576. mypdev = pci_get_device(PCI_VENDOR_ID_SI, 0x0645, NULL);
  4577. if(!mypdev)
  4578. mypdev = pci_get_device(PCI_VENDOR_ID_SI, 0x0650, NULL);
  4579. if(mypdev) {
  4580. pci_read_config_dword(mypdev, 0x94, &regd);
  4581. regd &= 0xfffffeff;
  4582. pci_write_config_dword(mypdev, 0x94, regd);
  4583. v1 &= 0xfe;
  4584. pci_dev_put(mypdev);
  4585. } else if(sisfb_find_host_bridge(ivideo, pdev, PCI_VENDOR_ID_SI)) {
  4586. v1 &= 0xfe;
  4587. } else if(sisfb_find_host_bridge(ivideo, pdev, 0x1106) ||
  4588. sisfb_find_host_bridge(ivideo, pdev, 0x1022) ||
  4589. sisfb_find_host_bridge(ivideo, pdev, 0x700e) ||
  4590. sisfb_find_host_bridge(ivideo, pdev, 0x10de)) {
  4591. if((v2 & 0x06) == 4)
  4592. v2 ^= 0x06;
  4593. v2 |= 0x08;
  4594. }
  4595. }
  4596. SiS_SetRegANDOR(SISCR, 0x5f, 0xf0, v2);
  4597. }
  4598. SiS_SetReg(SISSR, 0x22, v1);
  4599. if(ivideo->revision_id == 2) {
  4600. v1 = SiS_GetReg(SISSR, 0x3b);
  4601. v2 = SiS_GetReg(SISSR, 0x3a);
  4602. regd = bios[0x90 + 3] | (bios[0x90 + 4] << 8);
  4603. if( (!(v1 & 0x02)) && (v2 & 0x30) && (regd < 0xcf) )
  4604. SiS_SetRegANDOR(SISCR, 0x5f, 0xf1, 0x01);
  4605. if((mypdev = pci_get_device(0x10de, 0x01e0, NULL))) {
  4606. /* TODO: set CR5f &0xf1 | 0x01 for version 6570
  4607. * of nforce 2 ROM
  4608. */
  4609. if(0)
  4610. SiS_SetRegANDOR(SISCR, 0x5f, 0xf1, 0x01);
  4611. pci_dev_put(mypdev);
  4612. }
  4613. }
  4614. v1 = 0x30;
  4615. reg = SiS_GetReg(SISSR, 0x3b);
  4616. v2 = SiS_GetReg(SISCR, 0x5f);
  4617. if((!(reg & 0x02)) && (v2 & 0x0e))
  4618. v1 |= 0x08;
  4619. SiS_SetReg(SISSR, 0x27, v1);
  4620. if(bios[0x64] & 0x01) {
  4621. SiS_SetRegANDOR(SISCR, 0x5f, 0xf0, bios[0x64]);
  4622. }
  4623. v1 = bios[0x4f7];
  4624. pci_read_config_dword(pdev, 0x50, &regd);
  4625. regd = (regd >> 20) & 0x0f;
  4626. if(regd == 1) {
  4627. v1 &= 0xfc;
  4628. SiS_SetRegOR(SISCR, 0x5f, 0x08);
  4629. }
  4630. SiS_SetReg(SISCR, 0x48, v1);
  4631. SiS_SetRegANDOR(SISCR, 0x47, 0x04, bios[0x4f6] & 0xfb);
  4632. SiS_SetRegANDOR(SISCR, 0x49, 0xf0, bios[0x4f8] & 0x0f);
  4633. SiS_SetRegANDOR(SISCR, 0x4a, 0x60, bios[0x4f9] & 0x9f);
  4634. SiS_SetRegANDOR(SISCR, 0x4b, 0x08, bios[0x4fa] & 0xf7);
  4635. SiS_SetRegANDOR(SISCR, 0x4c, 0x80, bios[0x4fb] & 0x7f);
  4636. SiS_SetReg(SISCR, 0x70, bios[0x4fc]);
  4637. SiS_SetRegANDOR(SISCR, 0x71, 0xf0, bios[0x4fd] & 0x0f);
  4638. SiS_SetReg(SISCR, 0x74, 0xd0);
  4639. SiS_SetRegANDOR(SISCR, 0x74, 0xcf, bios[0x4fe] & 0x30);
  4640. SiS_SetRegANDOR(SISCR, 0x75, 0xe0, bios[0x4ff] & 0x1f);
  4641. SiS_SetRegANDOR(SISCR, 0x76, 0xe0, bios[0x500] & 0x1f);
  4642. v1 = bios[0x501];
  4643. if((mypdev = pci_get_device(0x8086, 0x2530, NULL))) {
  4644. v1 = 0xf0;
  4645. pci_dev_put(mypdev);
  4646. }
  4647. SiS_SetReg(SISCR, 0x77, v1);
  4648. }
  4649. /* RAM type:
  4650. *
  4651. * 0 == DDR1, 1 == DDR2, 2..7 == reserved?
  4652. *
  4653. * The code seems to written so that regb should equal ramtype,
  4654. * however, so far it has been hardcoded to 0. Enable other values only
  4655. * on XGI Z9, as it passes the POST, and add a warning for others.
  4656. */
  4657. ramtype = sisfb_post_xgi_ramtype(ivideo);
  4658. if (!sisfb_xgi_is21(ivideo) && ramtype) {
  4659. dev_warn(&pdev->dev,
  4660. "RAM type something else than expected: %d\n",
  4661. ramtype);
  4662. regb = 0;
  4663. } else {
  4664. regb = ramtype;
  4665. }
  4666. v1 = 0xff;
  4667. if(ivideo->haveXGIROM) {
  4668. v1 = bios[0x140 + regb];
  4669. }
  4670. SiS_SetReg(SISCR, 0x6d, v1);
  4671. ptr = cs128;
  4672. if(ivideo->haveXGIROM) {
  4673. ptr = (const u8 *)&bios[0x128];
  4674. }
  4675. for(i = 0, j = 0; i < 3; i++, j += 8) {
  4676. SiS_SetReg(SISCR, 0x68 + i, ptr[j + regb]);
  4677. }
  4678. ptr = cs31a;
  4679. ptr2 = cs33a;
  4680. if(ivideo->haveXGIROM) {
  4681. index = (ivideo->chip == XGI_20) ? 0x31a : 0x3a6;
  4682. ptr = (const u8 *)&bios[index];
  4683. ptr2 = (const u8 *)&bios[index + 0x20];
  4684. }
  4685. for(i = 0; i < 2; i++) {
  4686. if(i == 0) {
  4687. regd = le32_to_cpu(((u32 *)ptr)[regb]);
  4688. rega = 0x6b;
  4689. } else {
  4690. regd = le32_to_cpu(((u32 *)ptr2)[regb]);
  4691. rega = 0x6e;
  4692. }
  4693. reg = 0x00;
  4694. for(j = 0; j < 16; j++) {
  4695. reg &= 0xf3;
  4696. if(regd & 0x01) reg |= 0x04;
  4697. if(regd & 0x02) reg |= 0x08;
  4698. regd >>= 2;
  4699. SiS_SetReg(SISCR, rega, reg);
  4700. reg = SiS_GetReg(SISCR, rega);
  4701. reg = SiS_GetReg(SISCR, rega);
  4702. reg += 0x10;
  4703. }
  4704. }
  4705. SiS_SetRegAND(SISCR, 0x6e, 0xfc);
  4706. ptr = NULL;
  4707. if(ivideo->haveXGIROM) {
  4708. index = (ivideo->chip == XGI_20) ? 0x35a : 0x3e6;
  4709. ptr = (const u8 *)&bios[index];
  4710. }
  4711. for(i = 0; i < 4; i++) {
  4712. SiS_SetRegANDOR(SISCR, 0x6e, 0xfc, i);
  4713. reg = 0x00;
  4714. for(j = 0; j < 2; j++) {
  4715. regd = 0;
  4716. if(ptr) {
  4717. regd = le32_to_cpu(((u32 *)ptr)[regb * 8]);
  4718. ptr += 4;
  4719. }
  4720. /* reg = 0x00; */
  4721. for(k = 0; k < 16; k++) {
  4722. reg &= 0xfc;
  4723. if(regd & 0x01) reg |= 0x01;
  4724. if(regd & 0x02) reg |= 0x02;
  4725. regd >>= 2;
  4726. SiS_SetReg(SISCR, 0x6f, reg);
  4727. reg = SiS_GetReg(SISCR, 0x6f);
  4728. reg = SiS_GetReg(SISCR, 0x6f);
  4729. reg += 0x08;
  4730. }
  4731. }
  4732. }
  4733. ptr = cs148;
  4734. if(ivideo->haveXGIROM) {
  4735. ptr = (const u8 *)&bios[0x148];
  4736. }
  4737. for(i = 0, j = 0; i < 2; i++, j += 8) {
  4738. SiS_SetReg(SISCR, 0x80 + i, ptr[j + regb]);
  4739. }
  4740. SiS_SetRegAND(SISCR, 0x89, 0x8f);
  4741. ptr = cs45a;
  4742. if(ivideo->haveXGIROM) {
  4743. index = (ivideo->chip == XGI_20) ? 0x45a : 0x4e6;
  4744. ptr = (const u8 *)&bios[index];
  4745. }
  4746. regd = le16_to_cpu(((const u16 *)ptr)[regb]);
  4747. reg = 0x80;
  4748. for(i = 0; i < 5; i++) {
  4749. reg &= 0xfc;
  4750. if(regd & 0x01) reg |= 0x01;
  4751. if(regd & 0x02) reg |= 0x02;
  4752. regd >>= 2;
  4753. SiS_SetReg(SISCR, 0x89, reg);
  4754. reg = SiS_GetReg(SISCR, 0x89);
  4755. reg = SiS_GetReg(SISCR, 0x89);
  4756. reg += 0x10;
  4757. }
  4758. v1 = 0xb5; v2 = 0x20; v3 = 0xf0; v4 = 0x13;
  4759. if(ivideo->haveXGIROM) {
  4760. v1 = bios[0x118 + regb];
  4761. v2 = bios[0xf8 + regb];
  4762. v3 = bios[0x120 + regb];
  4763. v4 = bios[0x1ca];
  4764. }
  4765. SiS_SetReg(SISCR, 0x45, v1 & 0x0f);
  4766. SiS_SetReg(SISCR, 0x99, (v1 >> 4) & 0x07);
  4767. SiS_SetRegOR(SISCR, 0x40, v1 & 0x80);
  4768. SiS_SetReg(SISCR, 0x41, v2);
  4769. ptr = cs170;
  4770. if(ivideo->haveXGIROM) {
  4771. ptr = (const u8 *)&bios[0x170];
  4772. }
  4773. for(i = 0, j = 0; i < 7; i++, j += 8) {
  4774. SiS_SetReg(SISCR, 0x90 + i, ptr[j + regb]);
  4775. }
  4776. SiS_SetReg(SISCR, 0x59, v3);
  4777. ptr = cs1a8;
  4778. if(ivideo->haveXGIROM) {
  4779. ptr = (const u8 *)&bios[0x1a8];
  4780. }
  4781. for(i = 0, j = 0; i < 3; i++, j += 8) {
  4782. SiS_SetReg(SISCR, 0xc3 + i, ptr[j + regb]);
  4783. }
  4784. ptr = cs100;
  4785. if(ivideo->haveXGIROM) {
  4786. ptr = (const u8 *)&bios[0x100];
  4787. }
  4788. for(i = 0, j = 0; i < 2; i++, j += 8) {
  4789. SiS_SetReg(SISCR, 0x8a + i, ptr[j + regb]);
  4790. }
  4791. SiS_SetReg(SISCR, 0xcf, v4);
  4792. SiS_SetReg(SISCR, 0x83, 0x09);
  4793. SiS_SetReg(SISCR, 0x87, 0x00);
  4794. if(ivideo->chip == XGI_40) {
  4795. if( (ivideo->revision_id == 1) ||
  4796. (ivideo->revision_id == 2) ) {
  4797. SiS_SetReg(SISCR, 0x8c, 0x87);
  4798. }
  4799. }
  4800. if (regb == 1)
  4801. SiS_SetReg(SISSR, 0x17, 0x80); /* DDR2 */
  4802. else
  4803. SiS_SetReg(SISSR, 0x17, 0x00); /* DDR1 */
  4804. SiS_SetReg(SISSR, 0x1a, 0x87);
  4805. if(ivideo->chip == XGI_20) {
  4806. SiS_SetReg(SISSR, 0x15, 0x00);
  4807. SiS_SetReg(SISSR, 0x1c, 0x00);
  4808. }
  4809. switch(ramtype) {
  4810. case 0:
  4811. sisfb_post_xgi_setclocks(ivideo, regb);
  4812. if((ivideo->chip == XGI_20) ||
  4813. (ivideo->revision_id == 1) ||
  4814. (ivideo->revision_id == 2)) {
  4815. v1 = cs158[regb]; v2 = cs160[regb]; v3 = cs168[regb];
  4816. if(ivideo->haveXGIROM) {
  4817. v1 = bios[regb + 0x158];
  4818. v2 = bios[regb + 0x160];
  4819. v3 = bios[regb + 0x168];
  4820. }
  4821. SiS_SetReg(SISCR, 0x82, v1);
  4822. SiS_SetReg(SISCR, 0x85, v2);
  4823. SiS_SetReg(SISCR, 0x86, v3);
  4824. } else {
  4825. SiS_SetReg(SISCR, 0x82, 0x88);
  4826. SiS_SetReg(SISCR, 0x86, 0x00);
  4827. reg = SiS_GetReg(SISCR, 0x86);
  4828. SiS_SetReg(SISCR, 0x86, 0x88);
  4829. reg = SiS_GetReg(SISCR, 0x86);
  4830. SiS_SetReg(SISCR, 0x86, bios[regb + 0x168]);
  4831. SiS_SetReg(SISCR, 0x82, 0x77);
  4832. SiS_SetReg(SISCR, 0x85, 0x00);
  4833. reg = SiS_GetReg(SISCR, 0x85);
  4834. SiS_SetReg(SISCR, 0x85, 0x88);
  4835. reg = SiS_GetReg(SISCR, 0x85);
  4836. SiS_SetReg(SISCR, 0x85, bios[regb + 0x160]);
  4837. SiS_SetReg(SISCR, 0x82, bios[regb + 0x158]);
  4838. }
  4839. if(ivideo->chip == XGI_40) {
  4840. SiS_SetReg(SISCR, 0x97, 0x00);
  4841. }
  4842. SiS_SetReg(SISCR, 0x98, 0x01);
  4843. SiS_SetReg(SISCR, 0x9a, 0x02);
  4844. SiS_SetReg(SISSR, 0x18, 0x01);
  4845. if((ivideo->chip == XGI_20) ||
  4846. (ivideo->revision_id == 2)) {
  4847. SiS_SetReg(SISSR, 0x19, 0x40);
  4848. } else {
  4849. SiS_SetReg(SISSR, 0x19, 0x20);
  4850. }
  4851. SiS_SetReg(SISSR, 0x16, 0x00);
  4852. SiS_SetReg(SISSR, 0x16, 0x80);
  4853. if((ivideo->chip == XGI_20) || (bios[0x1cb] != 0x0c)) {
  4854. sisfb_post_xgi_delay(ivideo, 0x43);
  4855. sisfb_post_xgi_delay(ivideo, 0x43);
  4856. sisfb_post_xgi_delay(ivideo, 0x43);
  4857. SiS_SetReg(SISSR, 0x18, 0x00);
  4858. if((ivideo->chip == XGI_20) ||
  4859. (ivideo->revision_id == 2)) {
  4860. SiS_SetReg(SISSR, 0x19, 0x40);
  4861. } else {
  4862. SiS_SetReg(SISSR, 0x19, 0x20);
  4863. }
  4864. } else if((ivideo->chip == XGI_40) && (bios[0x1cb] == 0x0c)) {
  4865. /* SiS_SetReg(SISSR, 0x16, 0x0c); */ /* ? */
  4866. }
  4867. SiS_SetReg(SISSR, 0x16, 0x00);
  4868. SiS_SetReg(SISSR, 0x16, 0x80);
  4869. sisfb_post_xgi_delay(ivideo, 4);
  4870. v1 = 0x31; v2 = 0x03; v3 = 0x83; v4 = 0x03; v5 = 0x83;
  4871. if(ivideo->haveXGIROM) {
  4872. v1 = bios[0xf0];
  4873. index = (ivideo->chip == XGI_20) ? 0x4b2 : 0x53e;
  4874. v2 = bios[index];
  4875. v3 = bios[index + 1];
  4876. v4 = bios[index + 2];
  4877. v5 = bios[index + 3];
  4878. }
  4879. SiS_SetReg(SISSR, 0x18, v1);
  4880. SiS_SetReg(SISSR, 0x19, ((ivideo->chip == XGI_20) ? 0x02 : 0x01));
  4881. SiS_SetReg(SISSR, 0x16, v2);
  4882. SiS_SetReg(SISSR, 0x16, v3);
  4883. sisfb_post_xgi_delay(ivideo, 0x43);
  4884. SiS_SetReg(SISSR, 0x1b, 0x03);
  4885. sisfb_post_xgi_delay(ivideo, 0x22);
  4886. SiS_SetReg(SISSR, 0x18, v1);
  4887. SiS_SetReg(SISSR, 0x19, 0x00);
  4888. SiS_SetReg(SISSR, 0x16, v4);
  4889. SiS_SetReg(SISSR, 0x16, v5);
  4890. SiS_SetReg(SISSR, 0x1b, 0x00);
  4891. break;
  4892. case 1:
  4893. sisfb_post_xgi_ddr2(ivideo, regb);
  4894. break;
  4895. default:
  4896. sisfb_post_xgi_setclocks(ivideo, regb);
  4897. if((ivideo->chip == XGI_40) &&
  4898. ((ivideo->revision_id == 1) ||
  4899. (ivideo->revision_id == 2))) {
  4900. SiS_SetReg(SISCR, 0x82, bios[regb + 0x158]);
  4901. SiS_SetReg(SISCR, 0x85, bios[regb + 0x160]);
  4902. SiS_SetReg(SISCR, 0x86, bios[regb + 0x168]);
  4903. } else {
  4904. SiS_SetReg(SISCR, 0x82, 0x88);
  4905. SiS_SetReg(SISCR, 0x86, 0x00);
  4906. reg = SiS_GetReg(SISCR, 0x86);
  4907. SiS_SetReg(SISCR, 0x86, 0x88);
  4908. SiS_SetReg(SISCR, 0x82, 0x77);
  4909. SiS_SetReg(SISCR, 0x85, 0x00);
  4910. reg = SiS_GetReg(SISCR, 0x85);
  4911. SiS_SetReg(SISCR, 0x85, 0x88);
  4912. reg = SiS_GetReg(SISCR, 0x85);
  4913. v1 = cs160[regb]; v2 = cs158[regb];
  4914. if(ivideo->haveXGIROM) {
  4915. v1 = bios[regb + 0x160];
  4916. v2 = bios[regb + 0x158];
  4917. }
  4918. SiS_SetReg(SISCR, 0x85, v1);
  4919. SiS_SetReg(SISCR, 0x82, v2);
  4920. }
  4921. if(ivideo->chip == XGI_40) {
  4922. SiS_SetReg(SISCR, 0x97, 0x11);
  4923. }
  4924. if((ivideo->chip == XGI_40) && (ivideo->revision_id == 2)) {
  4925. SiS_SetReg(SISCR, 0x98, 0x01);
  4926. } else {
  4927. SiS_SetReg(SISCR, 0x98, 0x03);
  4928. }
  4929. SiS_SetReg(SISCR, 0x9a, 0x02);
  4930. if(ivideo->chip == XGI_40) {
  4931. SiS_SetReg(SISSR, 0x18, 0x01);
  4932. } else {
  4933. SiS_SetReg(SISSR, 0x18, 0x00);
  4934. }
  4935. SiS_SetReg(SISSR, 0x19, 0x40);
  4936. SiS_SetReg(SISSR, 0x16, 0x00);
  4937. SiS_SetReg(SISSR, 0x16, 0x80);
  4938. if((ivideo->chip == XGI_40) && (bios[0x1cb] != 0x0c)) {
  4939. sisfb_post_xgi_delay(ivideo, 0x43);
  4940. sisfb_post_xgi_delay(ivideo, 0x43);
  4941. sisfb_post_xgi_delay(ivideo, 0x43);
  4942. SiS_SetReg(SISSR, 0x18, 0x00);
  4943. SiS_SetReg(SISSR, 0x19, 0x40);
  4944. SiS_SetReg(SISSR, 0x16, 0x00);
  4945. SiS_SetReg(SISSR, 0x16, 0x80);
  4946. }
  4947. sisfb_post_xgi_delay(ivideo, 4);
  4948. v1 = 0x31;
  4949. if(ivideo->haveXGIROM) {
  4950. v1 = bios[0xf0];
  4951. }
  4952. SiS_SetReg(SISSR, 0x18, v1);
  4953. SiS_SetReg(SISSR, 0x19, 0x01);
  4954. if(ivideo->chip == XGI_40) {
  4955. SiS_SetReg(SISSR, 0x16, bios[0x53e]);
  4956. SiS_SetReg(SISSR, 0x16, bios[0x53f]);
  4957. } else {
  4958. SiS_SetReg(SISSR, 0x16, 0x05);
  4959. SiS_SetReg(SISSR, 0x16, 0x85);
  4960. }
  4961. sisfb_post_xgi_delay(ivideo, 0x43);
  4962. if(ivideo->chip == XGI_40) {
  4963. SiS_SetReg(SISSR, 0x1b, 0x01);
  4964. } else {
  4965. SiS_SetReg(SISSR, 0x1b, 0x03);
  4966. }
  4967. sisfb_post_xgi_delay(ivideo, 0x22);
  4968. SiS_SetReg(SISSR, 0x18, v1);
  4969. SiS_SetReg(SISSR, 0x19, 0x00);
  4970. if(ivideo->chip == XGI_40) {
  4971. SiS_SetReg(SISSR, 0x16, bios[0x540]);
  4972. SiS_SetReg(SISSR, 0x16, bios[0x541]);
  4973. } else {
  4974. SiS_SetReg(SISSR, 0x16, 0x05);
  4975. SiS_SetReg(SISSR, 0x16, 0x85);
  4976. }
  4977. SiS_SetReg(SISSR, 0x1b, 0x00);
  4978. }
  4979. regb = 0; /* ! */
  4980. v1 = 0x03;
  4981. if(ivideo->haveXGIROM) {
  4982. v1 = bios[0x110 + regb];
  4983. }
  4984. SiS_SetReg(SISSR, 0x1b, v1);
  4985. /* RAM size */
  4986. v1 = 0x00; v2 = 0x00;
  4987. if(ivideo->haveXGIROM) {
  4988. v1 = bios[0x62];
  4989. v2 = bios[0x63];
  4990. }
  4991. regb = 0; /* ! */
  4992. regd = 1 << regb;
  4993. if((v1 & 0x40) && (v2 & regd) && ivideo->haveXGIROM) {
  4994. SiS_SetReg(SISSR, 0x13, bios[regb + 0xe0]);
  4995. SiS_SetReg(SISSR, 0x14, bios[regb + 0xe0 + 8]);
  4996. } else {
  4997. int err;
  4998. /* Set default mode, don't clear screen */
  4999. ivideo->SiS_Pr.SiS_UseOEM = false;
  5000. SiS_SetEnableDstn(&ivideo->SiS_Pr, false);
  5001. SiS_SetEnableFstn(&ivideo->SiS_Pr, false);
  5002. ivideo->curFSTN = ivideo->curDSTN = 0;
  5003. ivideo->SiS_Pr.VideoMemorySize = 8 << 20;
  5004. SiSSetMode(&ivideo->SiS_Pr, 0x2e | 0x80);
  5005. SiS_SetReg(SISSR, 0x05, 0x86);
  5006. /* Disable read-cache */
  5007. SiS_SetRegAND(SISSR, 0x21, 0xdf);
  5008. err = sisfb_post_xgi_ramsize(ivideo);
  5009. /* Enable read-cache */
  5010. SiS_SetRegOR(SISSR, 0x21, 0x20);
  5011. if (err) {
  5012. dev_err(&pdev->dev,
  5013. "%s: RAM size detection failed: %d\n",
  5014. __func__, err);
  5015. return 0;
  5016. }
  5017. }
  5018. #if 0
  5019. printk(KERN_DEBUG "-----------------\n");
  5020. for(i = 0; i < 0xff; i++) {
  5021. reg = SiS_GetReg(SISCR, i);
  5022. printk(KERN_DEBUG "CR%02x(%x) = 0x%02x\n", i, SISCR, reg);
  5023. }
  5024. for(i = 0; i < 0x40; i++) {
  5025. reg = SiS_GetReg(SISSR, i);
  5026. printk(KERN_DEBUG "SR%02x(%x) = 0x%02x\n", i, SISSR, reg);
  5027. }
  5028. printk(KERN_DEBUG "-----------------\n");
  5029. #endif
  5030. /* Sense CRT1 */
  5031. if(ivideo->chip == XGI_20) {
  5032. SiS_SetRegOR(SISCR, 0x32, 0x20);
  5033. } else {
  5034. reg = SiS_GetReg(SISPART4, 0x00);
  5035. if((reg == 1) || (reg == 2)) {
  5036. sisfb_sense_crt1(ivideo);
  5037. } else {
  5038. SiS_SetRegOR(SISCR, 0x32, 0x20);
  5039. }
  5040. }
  5041. /* Set default mode, don't clear screen */
  5042. ivideo->SiS_Pr.SiS_UseOEM = false;
  5043. SiS_SetEnableDstn(&ivideo->SiS_Pr, false);
  5044. SiS_SetEnableFstn(&ivideo->SiS_Pr, false);
  5045. ivideo->curFSTN = ivideo->curDSTN = 0;
  5046. SiSSetMode(&ivideo->SiS_Pr, 0x2e | 0x80);
  5047. SiS_SetReg(SISSR, 0x05, 0x86);
  5048. /* Display off */
  5049. SiS_SetRegOR(SISSR, 0x01, 0x20);
  5050. /* Save mode number in CR34 */
  5051. SiS_SetReg(SISCR, 0x34, 0x2e);
  5052. /* Let everyone know what the current mode is */
  5053. ivideo->modeprechange = 0x2e;
  5054. if(ivideo->chip == XGI_40) {
  5055. reg = SiS_GetReg(SISCR, 0xca);
  5056. v1 = SiS_GetReg(SISCR, 0xcc);
  5057. if((reg & 0x10) && (!(v1 & 0x04))) {
  5058. printk(KERN_ERR
  5059. "sisfb: Please connect power to the card.\n");
  5060. return 0;
  5061. }
  5062. }
  5063. return 1;
  5064. }
  5065. #endif
  5066. static int sisfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  5067. {
  5068. struct sisfb_chip_info *chipinfo = &sisfb_chip_info[ent->driver_data];
  5069. struct sis_video_info *ivideo = NULL;
  5070. struct fb_info *sis_fb_info = NULL;
  5071. u16 reg16;
  5072. u8 reg;
  5073. int i, ret;
  5074. if(sisfb_off)
  5075. return -ENXIO;
  5076. sis_fb_info = framebuffer_alloc(sizeof(*ivideo), &pdev->dev);
  5077. if(!sis_fb_info)
  5078. return -ENOMEM;
  5079. ivideo = (struct sis_video_info *)sis_fb_info->par;
  5080. ivideo->memyselfandi = sis_fb_info;
  5081. ivideo->sisfb_id = SISFB_ID;
  5082. if(card_list == NULL) {
  5083. ivideo->cardnumber = 0;
  5084. } else {
  5085. struct sis_video_info *countvideo = card_list;
  5086. ivideo->cardnumber = 1;
  5087. while((countvideo = countvideo->next) != NULL)
  5088. ivideo->cardnumber++;
  5089. }
  5090. strncpy(ivideo->myid, chipinfo->chip_name, 30);
  5091. ivideo->warncount = 0;
  5092. ivideo->chip_id = pdev->device;
  5093. ivideo->chip_vendor = pdev->vendor;
  5094. ivideo->revision_id = pdev->revision;
  5095. ivideo->SiS_Pr.ChipRevision = ivideo->revision_id;
  5096. pci_read_config_word(pdev, PCI_COMMAND, &reg16);
  5097. ivideo->sisvga_enabled = reg16 & 0x01;
  5098. ivideo->pcibus = pdev->bus->number;
  5099. ivideo->pcislot = PCI_SLOT(pdev->devfn);
  5100. ivideo->pcifunc = PCI_FUNC(pdev->devfn);
  5101. ivideo->subsysvendor = pdev->subsystem_vendor;
  5102. ivideo->subsysdevice = pdev->subsystem_device;
  5103. #ifndef MODULE
  5104. if(sisfb_mode_idx == -1) {
  5105. sisfb_get_vga_mode_from_kernel();
  5106. }
  5107. #endif
  5108. ivideo->chip = chipinfo->chip;
  5109. ivideo->chip_real_id = chipinfo->chip;
  5110. ivideo->sisvga_engine = chipinfo->vgaengine;
  5111. ivideo->hwcursor_size = chipinfo->hwcursor_size;
  5112. ivideo->CRT2_write_enable = chipinfo->CRT2_write_enable;
  5113. ivideo->mni = chipinfo->mni;
  5114. ivideo->detectedpdc = 0xff;
  5115. ivideo->detectedpdca = 0xff;
  5116. ivideo->detectedlcda = 0xff;
  5117. ivideo->sisfb_thismonitor.datavalid = false;
  5118. ivideo->current_base = 0;
  5119. ivideo->engineok = 0;
  5120. ivideo->sisfb_was_boot_device = 0;
  5121. if(pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW) {
  5122. if(ivideo->sisvga_enabled)
  5123. ivideo->sisfb_was_boot_device = 1;
  5124. else {
  5125. printk(KERN_DEBUG "sisfb: PCI device is disabled, "
  5126. "but marked as boot video device ???\n");
  5127. printk(KERN_DEBUG "sisfb: I will not accept this "
  5128. "as the primary VGA device\n");
  5129. }
  5130. }
  5131. ivideo->sisfb_parm_mem = sisfb_parm_mem;
  5132. ivideo->sisfb_accel = sisfb_accel;
  5133. ivideo->sisfb_ypan = sisfb_ypan;
  5134. ivideo->sisfb_max = sisfb_max;
  5135. ivideo->sisfb_userom = sisfb_userom;
  5136. ivideo->sisfb_useoem = sisfb_useoem;
  5137. ivideo->sisfb_mode_idx = sisfb_mode_idx;
  5138. ivideo->sisfb_parm_rate = sisfb_parm_rate;
  5139. ivideo->sisfb_crt1off = sisfb_crt1off;
  5140. ivideo->sisfb_forcecrt1 = sisfb_forcecrt1;
  5141. ivideo->sisfb_crt2type = sisfb_crt2type;
  5142. ivideo->sisfb_crt2flags = sisfb_crt2flags;
  5143. /* pdc(a), scalelcd, special timing, lvdshl handled below */
  5144. ivideo->sisfb_dstn = sisfb_dstn;
  5145. ivideo->sisfb_fstn = sisfb_fstn;
  5146. ivideo->sisfb_tvplug = sisfb_tvplug;
  5147. ivideo->sisfb_tvstd = sisfb_tvstd;
  5148. ivideo->tvxpos = sisfb_tvxposoffset;
  5149. ivideo->tvypos = sisfb_tvyposoffset;
  5150. ivideo->sisfb_nocrt2rate = sisfb_nocrt2rate;
  5151. ivideo->refresh_rate = 0;
  5152. if(ivideo->sisfb_parm_rate != -1) {
  5153. ivideo->refresh_rate = ivideo->sisfb_parm_rate;
  5154. }
  5155. ivideo->SiS_Pr.UsePanelScaler = sisfb_scalelcd;
  5156. ivideo->SiS_Pr.CenterScreen = -1;
  5157. ivideo->SiS_Pr.SiS_CustomT = sisfb_specialtiming;
  5158. ivideo->SiS_Pr.LVDSHL = sisfb_lvdshl;
  5159. ivideo->SiS_Pr.SiS_Backup70xx = 0xff;
  5160. ivideo->SiS_Pr.SiS_CHOverScan = -1;
  5161. ivideo->SiS_Pr.SiS_ChSW = false;
  5162. ivideo->SiS_Pr.SiS_UseLCDA = false;
  5163. ivideo->SiS_Pr.HaveEMI = false;
  5164. ivideo->SiS_Pr.HaveEMILCD = false;
  5165. ivideo->SiS_Pr.OverruleEMI = false;
  5166. ivideo->SiS_Pr.SiS_SensibleSR11 = false;
  5167. ivideo->SiS_Pr.SiS_MyCR63 = 0x63;
  5168. ivideo->SiS_Pr.PDC = -1;
  5169. ivideo->SiS_Pr.PDCA = -1;
  5170. ivideo->SiS_Pr.DDCPortMixup = false;
  5171. #ifdef CONFIG_FB_SIS_315
  5172. if(ivideo->chip >= SIS_330) {
  5173. ivideo->SiS_Pr.SiS_MyCR63 = 0x53;
  5174. if(ivideo->chip >= SIS_661) {
  5175. ivideo->SiS_Pr.SiS_SensibleSR11 = true;
  5176. }
  5177. }
  5178. #endif
  5179. memcpy(&ivideo->default_var, &my_default_var, sizeof(my_default_var));
  5180. pci_set_drvdata(pdev, ivideo);
  5181. /* Patch special cases */
  5182. if((ivideo->nbridge = sisfb_get_northbridge(ivideo->chip))) {
  5183. switch(ivideo->nbridge->device) {
  5184. #ifdef CONFIG_FB_SIS_300
  5185. case PCI_DEVICE_ID_SI_730:
  5186. ivideo->chip = SIS_730;
  5187. strcpy(ivideo->myid, "SiS 730");
  5188. break;
  5189. #endif
  5190. #ifdef CONFIG_FB_SIS_315
  5191. case PCI_DEVICE_ID_SI_651:
  5192. /* ivideo->chip is ok */
  5193. strcpy(ivideo->myid, "SiS 651");
  5194. break;
  5195. case PCI_DEVICE_ID_SI_740:
  5196. ivideo->chip = SIS_740;
  5197. strcpy(ivideo->myid, "SiS 740");
  5198. break;
  5199. case PCI_DEVICE_ID_SI_661:
  5200. ivideo->chip = SIS_661;
  5201. strcpy(ivideo->myid, "SiS 661");
  5202. break;
  5203. case PCI_DEVICE_ID_SI_741:
  5204. ivideo->chip = SIS_741;
  5205. strcpy(ivideo->myid, "SiS 741");
  5206. break;
  5207. case PCI_DEVICE_ID_SI_760:
  5208. ivideo->chip = SIS_760;
  5209. strcpy(ivideo->myid, "SiS 760");
  5210. break;
  5211. case PCI_DEVICE_ID_SI_761:
  5212. ivideo->chip = SIS_761;
  5213. strcpy(ivideo->myid, "SiS 761");
  5214. break;
  5215. #endif
  5216. default:
  5217. break;
  5218. }
  5219. }
  5220. ivideo->SiS_Pr.ChipType = ivideo->chip;
  5221. ivideo->SiS_Pr.ivideo = (void *)ivideo;
  5222. #ifdef CONFIG_FB_SIS_315
  5223. if((ivideo->SiS_Pr.ChipType == SIS_315PRO) ||
  5224. (ivideo->SiS_Pr.ChipType == SIS_315)) {
  5225. ivideo->SiS_Pr.ChipType = SIS_315H;
  5226. }
  5227. #endif
  5228. if(!ivideo->sisvga_enabled) {
  5229. if(pci_enable_device(pdev)) {
  5230. if(ivideo->nbridge) pci_dev_put(ivideo->nbridge);
  5231. pci_set_drvdata(pdev, NULL);
  5232. framebuffer_release(sis_fb_info);
  5233. return -EIO;
  5234. }
  5235. }
  5236. ivideo->video_base = pci_resource_start(pdev, 0);
  5237. ivideo->video_size = pci_resource_len(pdev, 0);
  5238. ivideo->mmio_base = pci_resource_start(pdev, 1);
  5239. ivideo->mmio_size = pci_resource_len(pdev, 1);
  5240. ivideo->SiS_Pr.RelIO = pci_resource_start(pdev, 2) + 0x30;
  5241. ivideo->SiS_Pr.IOAddress = ivideo->vga_base = ivideo->SiS_Pr.RelIO;
  5242. SiSRegInit(&ivideo->SiS_Pr, ivideo->SiS_Pr.IOAddress);
  5243. #ifdef CONFIG_FB_SIS_300
  5244. /* Find PCI systems for Chrontel/GPIO communication setup */
  5245. if(ivideo->chip == SIS_630) {
  5246. i = 0;
  5247. do {
  5248. if(mychswtable[i].subsysVendor == ivideo->subsysvendor &&
  5249. mychswtable[i].subsysCard == ivideo->subsysdevice) {
  5250. ivideo->SiS_Pr.SiS_ChSW = true;
  5251. printk(KERN_DEBUG "sisfb: Identified [%s %s] "
  5252. "requiring Chrontel/GPIO setup\n",
  5253. mychswtable[i].vendorName,
  5254. mychswtable[i].cardName);
  5255. ivideo->lpcdev = pci_get_device(PCI_VENDOR_ID_SI, 0x0008, NULL);
  5256. break;
  5257. }
  5258. i++;
  5259. } while(mychswtable[i].subsysVendor != 0);
  5260. }
  5261. #endif
  5262. #ifdef CONFIG_FB_SIS_315
  5263. if((ivideo->chip == SIS_760) && (ivideo->nbridge)) {
  5264. ivideo->lpcdev = pci_get_slot(ivideo->nbridge->bus, (2 << 3));
  5265. }
  5266. #endif
  5267. SiS_SetReg(SISSR, 0x05, 0x86);
  5268. if( (!ivideo->sisvga_enabled)
  5269. #if !defined(__i386__) && !defined(__x86_64__)
  5270. || (sisfb_resetcard)
  5271. #endif
  5272. ) {
  5273. for(i = 0x30; i <= 0x3f; i++) {
  5274. SiS_SetReg(SISCR, i, 0x00);
  5275. }
  5276. }
  5277. /* Find out about current video mode */
  5278. ivideo->modeprechange = 0x03;
  5279. reg = SiS_GetReg(SISCR, 0x34);
  5280. if(reg & 0x7f) {
  5281. ivideo->modeprechange = reg & 0x7f;
  5282. } else if(ivideo->sisvga_enabled) {
  5283. #if defined(__i386__) || defined(__x86_64__)
  5284. unsigned char __iomem *tt = ioremap(0x400, 0x100);
  5285. if(tt) {
  5286. ivideo->modeprechange = readb(tt + 0x49);
  5287. iounmap(tt);
  5288. }
  5289. #endif
  5290. }
  5291. /* Search and copy ROM image */
  5292. ivideo->bios_abase = NULL;
  5293. ivideo->SiS_Pr.VirtualRomBase = NULL;
  5294. ivideo->SiS_Pr.UseROM = false;
  5295. ivideo->haveXGIROM = ivideo->SiS_Pr.SiS_XGIROM = false;
  5296. if(ivideo->sisfb_userom) {
  5297. ivideo->SiS_Pr.VirtualRomBase = sisfb_find_rom(pdev);
  5298. ivideo->bios_abase = ivideo->SiS_Pr.VirtualRomBase;
  5299. ivideo->SiS_Pr.UseROM = (bool)(ivideo->SiS_Pr.VirtualRomBase);
  5300. printk(KERN_INFO "sisfb: Video ROM %sfound\n",
  5301. ivideo->SiS_Pr.UseROM ? "" : "not ");
  5302. if((ivideo->SiS_Pr.UseROM) && (ivideo->chip >= XGI_20)) {
  5303. ivideo->SiS_Pr.UseROM = false;
  5304. ivideo->haveXGIROM = ivideo->SiS_Pr.SiS_XGIROM = true;
  5305. if( (ivideo->revision_id == 2) &&
  5306. (!(ivideo->bios_abase[0x1d1] & 0x01)) ) {
  5307. ivideo->SiS_Pr.DDCPortMixup = true;
  5308. }
  5309. }
  5310. } else {
  5311. printk(KERN_INFO "sisfb: Video ROM usage disabled\n");
  5312. }
  5313. /* Find systems for special custom timing */
  5314. if(ivideo->SiS_Pr.SiS_CustomT == CUT_NONE) {
  5315. sisfb_detect_custom_timing(ivideo);
  5316. }
  5317. #ifdef CONFIG_FB_SIS_315
  5318. if (ivideo->chip == XGI_20) {
  5319. /* Check if our Z7 chip is actually Z9 */
  5320. SiS_SetRegOR(SISCR, 0x4a, 0x40); /* GPIOG EN */
  5321. reg = SiS_GetReg(SISCR, 0x48);
  5322. if (reg & 0x02) { /* GPIOG */
  5323. ivideo->chip_real_id = XGI_21;
  5324. dev_info(&pdev->dev, "Z9 detected\n");
  5325. }
  5326. }
  5327. #endif
  5328. /* POST card in case this has not been done by the BIOS */
  5329. if( (!ivideo->sisvga_enabled)
  5330. #if !defined(__i386__) && !defined(__x86_64__)
  5331. || (sisfb_resetcard)
  5332. #endif
  5333. ) {
  5334. #ifdef CONFIG_FB_SIS_300
  5335. if(ivideo->sisvga_engine == SIS_300_VGA) {
  5336. if(ivideo->chip == SIS_300) {
  5337. sisfb_post_sis300(pdev);
  5338. ivideo->sisfb_can_post = 1;
  5339. }
  5340. }
  5341. #endif
  5342. #ifdef CONFIG_FB_SIS_315
  5343. if(ivideo->sisvga_engine == SIS_315_VGA) {
  5344. int result = 1;
  5345. /* if((ivideo->chip == SIS_315H) ||
  5346. (ivideo->chip == SIS_315) ||
  5347. (ivideo->chip == SIS_315PRO) ||
  5348. (ivideo->chip == SIS_330)) {
  5349. sisfb_post_sis315330(pdev);
  5350. } else */ if(ivideo->chip == XGI_20) {
  5351. result = sisfb_post_xgi(pdev);
  5352. ivideo->sisfb_can_post = 1;
  5353. } else if((ivideo->chip == XGI_40) && ivideo->haveXGIROM) {
  5354. result = sisfb_post_xgi(pdev);
  5355. ivideo->sisfb_can_post = 1;
  5356. } else {
  5357. printk(KERN_INFO "sisfb: Card is not "
  5358. "POSTed and sisfb can't do this either.\n");
  5359. }
  5360. if(!result) {
  5361. printk(KERN_ERR "sisfb: Failed to POST card\n");
  5362. ret = -ENODEV;
  5363. goto error_3;
  5364. }
  5365. }
  5366. #endif
  5367. }
  5368. ivideo->sisfb_card_posted = 1;
  5369. /* Find out about RAM size */
  5370. if(sisfb_get_dram_size(ivideo)) {
  5371. printk(KERN_INFO "sisfb: Fatal error: Unable to determine VRAM size.\n");
  5372. ret = -ENODEV;
  5373. goto error_3;
  5374. }
  5375. /* Enable PCI addressing and MMIO */
  5376. if((ivideo->sisfb_mode_idx < 0) ||
  5377. ((sisbios_mode[ivideo->sisfb_mode_idx].mode_no[ivideo->mni]) != 0xFF)) {
  5378. /* Enable PCI_LINEAR_ADDRESSING and MMIO_ENABLE */
  5379. SiS_SetRegOR(SISSR, IND_SIS_PCI_ADDRESS_SET, (SIS_PCI_ADDR_ENABLE | SIS_MEM_MAP_IO_ENABLE));
  5380. /* Enable 2D accelerator engine */
  5381. SiS_SetRegOR(SISSR, IND_SIS_MODULE_ENABLE, SIS_ENABLE_2D);
  5382. }
  5383. if(sisfb_pdc != 0xff) {
  5384. if(ivideo->sisvga_engine == SIS_300_VGA)
  5385. sisfb_pdc &= 0x3c;
  5386. else
  5387. sisfb_pdc &= 0x1f;
  5388. ivideo->SiS_Pr.PDC = sisfb_pdc;
  5389. }
  5390. #ifdef CONFIG_FB_SIS_315
  5391. if(ivideo->sisvga_engine == SIS_315_VGA) {
  5392. if(sisfb_pdca != 0xff)
  5393. ivideo->SiS_Pr.PDCA = sisfb_pdca & 0x1f;
  5394. }
  5395. #endif
  5396. if(!request_mem_region(ivideo->video_base, ivideo->video_size, "sisfb FB")) {
  5397. printk(KERN_ERR "sisfb: Fatal error: Unable to reserve %dMB framebuffer memory\n",
  5398. (int)(ivideo->video_size >> 20));
  5399. printk(KERN_ERR "sisfb: Is there another framebuffer driver active?\n");
  5400. ret = -ENODEV;
  5401. goto error_3;
  5402. }
  5403. if(!request_mem_region(ivideo->mmio_base, ivideo->mmio_size, "sisfb MMIO")) {
  5404. printk(KERN_ERR "sisfb: Fatal error: Unable to reserve MMIO region\n");
  5405. ret = -ENODEV;
  5406. goto error_2;
  5407. }
  5408. ivideo->video_vbase = ioremap(ivideo->video_base, ivideo->video_size);
  5409. ivideo->SiS_Pr.VideoMemoryAddress = ivideo->video_vbase;
  5410. if(!ivideo->video_vbase) {
  5411. printk(KERN_ERR "sisfb: Fatal error: Unable to map framebuffer memory\n");
  5412. ret = -ENODEV;
  5413. goto error_1;
  5414. }
  5415. ivideo->mmio_vbase = ioremap(ivideo->mmio_base, ivideo->mmio_size);
  5416. if(!ivideo->mmio_vbase) {
  5417. printk(KERN_ERR "sisfb: Fatal error: Unable to map MMIO region\n");
  5418. ret = -ENODEV;
  5419. error_0: iounmap(ivideo->video_vbase);
  5420. error_1: release_mem_region(ivideo->video_base, ivideo->video_size);
  5421. error_2: release_mem_region(ivideo->mmio_base, ivideo->mmio_size);
  5422. error_3: vfree(ivideo->bios_abase);
  5423. if(ivideo->lpcdev)
  5424. pci_dev_put(ivideo->lpcdev);
  5425. if(ivideo->nbridge)
  5426. pci_dev_put(ivideo->nbridge);
  5427. pci_set_drvdata(pdev, NULL);
  5428. if(!ivideo->sisvga_enabled)
  5429. pci_disable_device(pdev);
  5430. framebuffer_release(sis_fb_info);
  5431. return ret;
  5432. }
  5433. printk(KERN_INFO "sisfb: Video RAM at 0x%lx, mapped to 0x%lx, size %ldk\n",
  5434. ivideo->video_base, (unsigned long)ivideo->video_vbase, ivideo->video_size / 1024);
  5435. if(ivideo->video_offset) {
  5436. printk(KERN_INFO "sisfb: Viewport offset %ldk\n",
  5437. ivideo->video_offset / 1024);
  5438. }
  5439. printk(KERN_INFO "sisfb: MMIO at 0x%lx, mapped to 0x%lx, size %ldk\n",
  5440. ivideo->mmio_base, (unsigned long)ivideo->mmio_vbase, ivideo->mmio_size / 1024);
  5441. /* Determine the size of the command queue */
  5442. if(ivideo->sisvga_engine == SIS_300_VGA) {
  5443. ivideo->cmdQueueSize = TURBO_QUEUE_AREA_SIZE;
  5444. } else {
  5445. if(ivideo->chip == XGI_20) {
  5446. ivideo->cmdQueueSize = COMMAND_QUEUE_AREA_SIZE_Z7;
  5447. } else {
  5448. ivideo->cmdQueueSize = COMMAND_QUEUE_AREA_SIZE;
  5449. }
  5450. }
  5451. /* Engines are no longer initialized here; this is
  5452. * now done after the first mode-switch (if the
  5453. * submitted var has its acceleration flags set).
  5454. */
  5455. /* Calculate the base of the (unused) hw cursor */
  5456. ivideo->hwcursor_vbase = ivideo->video_vbase
  5457. + ivideo->video_size
  5458. - ivideo->cmdQueueSize
  5459. - ivideo->hwcursor_size;
  5460. ivideo->caps |= HW_CURSOR_CAP;
  5461. /* Initialize offscreen memory manager */
  5462. if((ivideo->havenoheap = sisfb_heap_init(ivideo))) {
  5463. printk(KERN_WARNING "sisfb: Failed to initialize offscreen memory heap\n");
  5464. }
  5465. /* Used for clearing the screen only, therefore respect our mem limit */
  5466. ivideo->SiS_Pr.VideoMemoryAddress += ivideo->video_offset;
  5467. ivideo->SiS_Pr.VideoMemorySize = ivideo->sisfb_mem;
  5468. ivideo->mtrr = -1;
  5469. ivideo->vbflags = 0;
  5470. ivideo->lcddefmodeidx = DEFAULT_LCDMODE;
  5471. ivideo->tvdefmodeidx = DEFAULT_TVMODE;
  5472. ivideo->defmodeidx = DEFAULT_MODE;
  5473. ivideo->newrom = 0;
  5474. if(ivideo->chip < XGI_20) {
  5475. if(ivideo->bios_abase) {
  5476. ivideo->newrom = SiSDetermineROMLayout661(&ivideo->SiS_Pr);
  5477. }
  5478. }
  5479. if((ivideo->sisfb_mode_idx < 0) ||
  5480. ((sisbios_mode[ivideo->sisfb_mode_idx].mode_no[ivideo->mni]) != 0xFF)) {
  5481. sisfb_sense_crt1(ivideo);
  5482. sisfb_get_VB_type(ivideo);
  5483. if(ivideo->vbflags2 & VB2_VIDEOBRIDGE) {
  5484. sisfb_detect_VB_connect(ivideo);
  5485. }
  5486. ivideo->currentvbflags = ivideo->vbflags & (VB_VIDEOBRIDGE | TV_STANDARD);
  5487. /* Decide on which CRT2 device to use */
  5488. if(ivideo->vbflags2 & VB2_VIDEOBRIDGE) {
  5489. if(ivideo->sisfb_crt2type != -1) {
  5490. if((ivideo->sisfb_crt2type == CRT2_LCD) &&
  5491. (ivideo->vbflags & CRT2_LCD)) {
  5492. ivideo->currentvbflags |= CRT2_LCD;
  5493. } else if(ivideo->sisfb_crt2type != CRT2_LCD) {
  5494. ivideo->currentvbflags |= ivideo->sisfb_crt2type;
  5495. }
  5496. } else {
  5497. /* Chrontel 700x TV detection often unreliable, therefore
  5498. * use a different default order on such machines
  5499. */
  5500. if((ivideo->sisvga_engine == SIS_300_VGA) &&
  5501. (ivideo->vbflags2 & VB2_CHRONTEL)) {
  5502. if(ivideo->vbflags & CRT2_LCD)
  5503. ivideo->currentvbflags |= CRT2_LCD;
  5504. else if(ivideo->vbflags & CRT2_TV)
  5505. ivideo->currentvbflags |= CRT2_TV;
  5506. else if(ivideo->vbflags & CRT2_VGA)
  5507. ivideo->currentvbflags |= CRT2_VGA;
  5508. } else {
  5509. if(ivideo->vbflags & CRT2_TV)
  5510. ivideo->currentvbflags |= CRT2_TV;
  5511. else if(ivideo->vbflags & CRT2_LCD)
  5512. ivideo->currentvbflags |= CRT2_LCD;
  5513. else if(ivideo->vbflags & CRT2_VGA)
  5514. ivideo->currentvbflags |= CRT2_VGA;
  5515. }
  5516. }
  5517. }
  5518. if(ivideo->vbflags & CRT2_LCD) {
  5519. sisfb_detect_lcd_type(ivideo);
  5520. }
  5521. sisfb_save_pdc_emi(ivideo);
  5522. if(!ivideo->sisfb_crt1off) {
  5523. sisfb_handle_ddc(ivideo, &ivideo->sisfb_thismonitor, 0);
  5524. } else {
  5525. if((ivideo->vbflags2 & VB2_SISTMDSBRIDGE) &&
  5526. (ivideo->vbflags & (CRT2_VGA | CRT2_LCD))) {
  5527. sisfb_handle_ddc(ivideo, &ivideo->sisfb_thismonitor, 1);
  5528. }
  5529. }
  5530. if(ivideo->sisfb_mode_idx >= 0) {
  5531. int bu = ivideo->sisfb_mode_idx;
  5532. ivideo->sisfb_mode_idx = sisfb_validate_mode(ivideo,
  5533. ivideo->sisfb_mode_idx, ivideo->currentvbflags);
  5534. if(bu != ivideo->sisfb_mode_idx) {
  5535. printk(KERN_ERR "Mode %dx%dx%d failed validation\n",
  5536. sisbios_mode[bu].xres,
  5537. sisbios_mode[bu].yres,
  5538. sisbios_mode[bu].bpp);
  5539. }
  5540. }
  5541. if(ivideo->sisfb_mode_idx < 0) {
  5542. switch(ivideo->currentvbflags & VB_DISPTYPE_DISP2) {
  5543. case CRT2_LCD:
  5544. ivideo->sisfb_mode_idx = ivideo->lcddefmodeidx;
  5545. break;
  5546. case CRT2_TV:
  5547. ivideo->sisfb_mode_idx = ivideo->tvdefmodeidx;
  5548. break;
  5549. default:
  5550. ivideo->sisfb_mode_idx = ivideo->defmodeidx;
  5551. break;
  5552. }
  5553. }
  5554. ivideo->mode_no = sisbios_mode[ivideo->sisfb_mode_idx].mode_no[ivideo->mni];
  5555. if(ivideo->refresh_rate != 0) {
  5556. sisfb_search_refresh_rate(ivideo, ivideo->refresh_rate,
  5557. ivideo->sisfb_mode_idx);
  5558. }
  5559. if(ivideo->rate_idx == 0) {
  5560. ivideo->rate_idx = sisbios_mode[ivideo->sisfb_mode_idx].rate_idx;
  5561. ivideo->refresh_rate = 60;
  5562. }
  5563. if(ivideo->sisfb_thismonitor.datavalid) {
  5564. if(!sisfb_verify_rate(ivideo, &ivideo->sisfb_thismonitor,
  5565. ivideo->sisfb_mode_idx,
  5566. ivideo->rate_idx,
  5567. ivideo->refresh_rate)) {
  5568. printk(KERN_INFO "sisfb: WARNING: Refresh rate "
  5569. "exceeds monitor specs!\n");
  5570. }
  5571. }
  5572. ivideo->video_bpp = sisbios_mode[ivideo->sisfb_mode_idx].bpp;
  5573. ivideo->video_width = sisbios_mode[ivideo->sisfb_mode_idx].xres;
  5574. ivideo->video_height = sisbios_mode[ivideo->sisfb_mode_idx].yres;
  5575. sisfb_set_vparms(ivideo);
  5576. printk(KERN_INFO "sisfb: Default mode is %dx%dx%d (%dHz)\n",
  5577. ivideo->video_width, ivideo->video_height, ivideo->video_bpp,
  5578. ivideo->refresh_rate);
  5579. /* Set up the default var according to chosen default display mode */
  5580. ivideo->default_var.xres = ivideo->default_var.xres_virtual = ivideo->video_width;
  5581. ivideo->default_var.yres = ivideo->default_var.yres_virtual = ivideo->video_height;
  5582. ivideo->default_var.bits_per_pixel = ivideo->video_bpp;
  5583. sisfb_bpp_to_var(ivideo, &ivideo->default_var);
  5584. ivideo->default_var.pixclock = (u32) (1000000000 /
  5585. sisfb_mode_rate_to_dclock(&ivideo->SiS_Pr, ivideo->mode_no, ivideo->rate_idx));
  5586. if(sisfb_mode_rate_to_ddata(&ivideo->SiS_Pr, ivideo->mode_no,
  5587. ivideo->rate_idx, &ivideo->default_var)) {
  5588. if((ivideo->default_var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
  5589. ivideo->default_var.pixclock <<= 1;
  5590. }
  5591. }
  5592. if(ivideo->sisfb_ypan) {
  5593. /* Maximize regardless of sisfb_max at startup */
  5594. ivideo->default_var.yres_virtual =
  5595. sisfb_calc_maxyres(ivideo, &ivideo->default_var);
  5596. if(ivideo->default_var.yres_virtual < ivideo->default_var.yres) {
  5597. ivideo->default_var.yres_virtual = ivideo->default_var.yres;
  5598. }
  5599. }
  5600. sisfb_calc_pitch(ivideo, &ivideo->default_var);
  5601. ivideo->accel = 0;
  5602. if(ivideo->sisfb_accel) {
  5603. ivideo->accel = -1;
  5604. #ifdef STUPID_ACCELF_TEXT_SHIT
  5605. ivideo->default_var.accel_flags |= FB_ACCELF_TEXT;
  5606. #endif
  5607. }
  5608. sisfb_initaccel(ivideo);
  5609. #if defined(FBINFO_HWACCEL_DISABLED) && defined(FBINFO_HWACCEL_XPAN)
  5610. sis_fb_info->flags = FBINFO_DEFAULT |
  5611. FBINFO_HWACCEL_YPAN |
  5612. FBINFO_HWACCEL_XPAN |
  5613. FBINFO_HWACCEL_COPYAREA |
  5614. FBINFO_HWACCEL_FILLRECT |
  5615. ((ivideo->accel) ? 0 : FBINFO_HWACCEL_DISABLED);
  5616. #else
  5617. sis_fb_info->flags = FBINFO_FLAG_DEFAULT;
  5618. #endif
  5619. sis_fb_info->var = ivideo->default_var;
  5620. sis_fb_info->fix = ivideo->sisfb_fix;
  5621. sis_fb_info->screen_base = ivideo->video_vbase + ivideo->video_offset;
  5622. sis_fb_info->fbops = &sisfb_ops;
  5623. sis_fb_info->pseudo_palette = ivideo->pseudo_palette;
  5624. fb_alloc_cmap(&sis_fb_info->cmap, 256 , 0);
  5625. printk(KERN_DEBUG "sisfb: Initial vbflags 0x%x\n", (int)ivideo->vbflags);
  5626. #ifdef CONFIG_MTRR
  5627. ivideo->mtrr = mtrr_add(ivideo->video_base, ivideo->video_size,
  5628. MTRR_TYPE_WRCOMB, 1);
  5629. if(ivideo->mtrr < 0) {
  5630. printk(KERN_DEBUG "sisfb: Failed to add MTRRs\n");
  5631. }
  5632. #endif
  5633. if(register_framebuffer(sis_fb_info) < 0) {
  5634. printk(KERN_ERR "sisfb: Fatal error: Failed to register framebuffer\n");
  5635. ret = -EINVAL;
  5636. iounmap(ivideo->mmio_vbase);
  5637. goto error_0;
  5638. }
  5639. ivideo->registered = 1;
  5640. /* Enlist us */
  5641. ivideo->next = card_list;
  5642. card_list = ivideo;
  5643. printk(KERN_INFO "sisfb: 2D acceleration is %s, y-panning %s\n",
  5644. ivideo->sisfb_accel ? "enabled" : "disabled",
  5645. ivideo->sisfb_ypan ?
  5646. (ivideo->sisfb_max ? "enabled (auto-max)" :
  5647. "enabled (no auto-max)") :
  5648. "disabled");
  5649. printk(KERN_INFO "fb%d: %s frame buffer device version %d.%d.%d\n",
  5650. sis_fb_info->node, ivideo->myid, VER_MAJOR, VER_MINOR, VER_LEVEL);
  5651. printk(KERN_INFO "sisfb: Copyright (C) 2001-2005 Thomas Winischhofer\n");
  5652. } /* if mode = "none" */
  5653. return 0;
  5654. }
  5655. /*****************************************************/
  5656. /* PCI DEVICE HANDLING */
  5657. /*****************************************************/
  5658. static void sisfb_remove(struct pci_dev *pdev)
  5659. {
  5660. struct sis_video_info *ivideo = pci_get_drvdata(pdev);
  5661. struct fb_info *sis_fb_info = ivideo->memyselfandi;
  5662. int registered = ivideo->registered;
  5663. int modechanged = ivideo->modechanged;
  5664. /* Unmap */
  5665. iounmap(ivideo->mmio_vbase);
  5666. iounmap(ivideo->video_vbase);
  5667. /* Release mem regions */
  5668. release_mem_region(ivideo->video_base, ivideo->video_size);
  5669. release_mem_region(ivideo->mmio_base, ivideo->mmio_size);
  5670. vfree(ivideo->bios_abase);
  5671. if(ivideo->lpcdev)
  5672. pci_dev_put(ivideo->lpcdev);
  5673. if(ivideo->nbridge)
  5674. pci_dev_put(ivideo->nbridge);
  5675. #ifdef CONFIG_MTRR
  5676. /* Release MTRR region */
  5677. if(ivideo->mtrr >= 0)
  5678. mtrr_del(ivideo->mtrr, ivideo->video_base, ivideo->video_size);
  5679. #endif
  5680. pci_set_drvdata(pdev, NULL);
  5681. /* If device was disabled when starting, disable
  5682. * it when quitting.
  5683. */
  5684. if(!ivideo->sisvga_enabled)
  5685. pci_disable_device(pdev);
  5686. /* Unregister the framebuffer */
  5687. if(ivideo->registered) {
  5688. unregister_framebuffer(sis_fb_info);
  5689. framebuffer_release(sis_fb_info);
  5690. }
  5691. /* OK, our ivideo is gone for good from here. */
  5692. /* TODO: Restore the initial mode
  5693. * This sounds easy but is as good as impossible
  5694. * on many machines with SiS chip and video bridge
  5695. * since text modes are always set up differently
  5696. * from machine to machine. Depends on the type
  5697. * of integration between chipset and bridge.
  5698. */
  5699. if(registered && modechanged)
  5700. printk(KERN_INFO
  5701. "sisfb: Restoring of text mode not supported yet\n");
  5702. };
  5703. static struct pci_driver sisfb_driver = {
  5704. .name = "sisfb",
  5705. .id_table = sisfb_pci_table,
  5706. .probe = sisfb_probe,
  5707. .remove = sisfb_remove,
  5708. };
  5709. static int __init sisfb_init(void)
  5710. {
  5711. #ifndef MODULE
  5712. char *options = NULL;
  5713. if(fb_get_options("sisfb", &options))
  5714. return -ENODEV;
  5715. sisfb_setup(options);
  5716. #endif
  5717. return pci_register_driver(&sisfb_driver);
  5718. }
  5719. #ifndef MODULE
  5720. module_init(sisfb_init);
  5721. #endif
  5722. /*****************************************************/
  5723. /* MODULE */
  5724. /*****************************************************/
  5725. #ifdef MODULE
  5726. static char *mode = NULL;
  5727. static int vesa = -1;
  5728. static unsigned int rate = 0;
  5729. static unsigned int crt1off = 1;
  5730. static unsigned int mem = 0;
  5731. static char *forcecrt2type = NULL;
  5732. static int forcecrt1 = -1;
  5733. static int pdc = -1;
  5734. static int pdc1 = -1;
  5735. static int noaccel = -1;
  5736. static int noypan = -1;
  5737. static int nomax = -1;
  5738. static int userom = -1;
  5739. static int useoem = -1;
  5740. static char *tvstandard = NULL;
  5741. static int nocrt2rate = 0;
  5742. static int scalelcd = -1;
  5743. static char *specialtiming = NULL;
  5744. static int lvdshl = -1;
  5745. static int tvxposoffset = 0, tvyposoffset = 0;
  5746. #if !defined(__i386__) && !defined(__x86_64__)
  5747. static int resetcard = 0;
  5748. static int videoram = 0;
  5749. #endif
  5750. static int __init sisfb_init_module(void)
  5751. {
  5752. sisfb_setdefaultparms();
  5753. if(rate)
  5754. sisfb_parm_rate = rate;
  5755. if((scalelcd == 0) || (scalelcd == 1))
  5756. sisfb_scalelcd = scalelcd ^ 1;
  5757. /* Need to check crt2 type first for fstn/dstn */
  5758. if(forcecrt2type)
  5759. sisfb_search_crt2type(forcecrt2type);
  5760. if(tvstandard)
  5761. sisfb_search_tvstd(tvstandard);
  5762. if(mode)
  5763. sisfb_search_mode(mode, false);
  5764. else if(vesa != -1)
  5765. sisfb_search_vesamode(vesa, false);
  5766. sisfb_crt1off = (crt1off == 0) ? 1 : 0;
  5767. sisfb_forcecrt1 = forcecrt1;
  5768. if(forcecrt1 == 1)
  5769. sisfb_crt1off = 0;
  5770. else if(forcecrt1 == 0)
  5771. sisfb_crt1off = 1;
  5772. if(noaccel == 1)
  5773. sisfb_accel = 0;
  5774. else if(noaccel == 0)
  5775. sisfb_accel = 1;
  5776. if(noypan == 1)
  5777. sisfb_ypan = 0;
  5778. else if(noypan == 0)
  5779. sisfb_ypan = 1;
  5780. if(nomax == 1)
  5781. sisfb_max = 0;
  5782. else if(nomax == 0)
  5783. sisfb_max = 1;
  5784. if(mem)
  5785. sisfb_parm_mem = mem;
  5786. if(userom != -1)
  5787. sisfb_userom = userom;
  5788. if(useoem != -1)
  5789. sisfb_useoem = useoem;
  5790. if(pdc != -1)
  5791. sisfb_pdc = (pdc & 0x7f);
  5792. if(pdc1 != -1)
  5793. sisfb_pdca = (pdc1 & 0x1f);
  5794. sisfb_nocrt2rate = nocrt2rate;
  5795. if(specialtiming)
  5796. sisfb_search_specialtiming(specialtiming);
  5797. if((lvdshl >= 0) && (lvdshl <= 3))
  5798. sisfb_lvdshl = lvdshl;
  5799. sisfb_tvxposoffset = tvxposoffset;
  5800. sisfb_tvyposoffset = tvyposoffset;
  5801. #if !defined(__i386__) && !defined(__x86_64__)
  5802. sisfb_resetcard = (resetcard) ? 1 : 0;
  5803. if(videoram)
  5804. sisfb_videoram = videoram;
  5805. #endif
  5806. return sisfb_init();
  5807. }
  5808. static void __exit sisfb_remove_module(void)
  5809. {
  5810. pci_unregister_driver(&sisfb_driver);
  5811. printk(KERN_DEBUG "sisfb: Module unloaded\n");
  5812. }
  5813. module_init(sisfb_init_module);
  5814. module_exit(sisfb_remove_module);
  5815. MODULE_DESCRIPTION("SiS 300/540/630/730/315/55x/65x/661/74x/330/76x/34x, XGI V3XT/V5/V8/Z7 framebuffer device driver");
  5816. MODULE_LICENSE("GPL");
  5817. MODULE_AUTHOR("Thomas Winischhofer <thomas@winischhofer.net>, Others");
  5818. module_param(mem, int, 0);
  5819. module_param(noaccel, int, 0);
  5820. module_param(noypan, int, 0);
  5821. module_param(nomax, int, 0);
  5822. module_param(userom, int, 0);
  5823. module_param(useoem, int, 0);
  5824. module_param(mode, charp, 0);
  5825. module_param(vesa, int, 0);
  5826. module_param(rate, int, 0);
  5827. module_param(forcecrt1, int, 0);
  5828. module_param(forcecrt2type, charp, 0);
  5829. module_param(scalelcd, int, 0);
  5830. module_param(pdc, int, 0);
  5831. module_param(pdc1, int, 0);
  5832. module_param(specialtiming, charp, 0);
  5833. module_param(lvdshl, int, 0);
  5834. module_param(tvstandard, charp, 0);
  5835. module_param(tvxposoffset, int, 0);
  5836. module_param(tvyposoffset, int, 0);
  5837. module_param(nocrt2rate, int, 0);
  5838. #if !defined(__i386__) && !defined(__x86_64__)
  5839. module_param(resetcard, int, 0);
  5840. module_param(videoram, int, 0);
  5841. #endif
  5842. MODULE_PARM_DESC(mem,
  5843. "\nDetermines the beginning of the video memory heap in KB. This heap is used\n"
  5844. "for video RAM management for eg. DRM/DRI. On 300 series, the default depends\n"
  5845. "on the amount of video RAM available. If 8MB of video RAM or less is available,\n"
  5846. "the heap starts at 4096KB, if between 8 and 16MB are available at 8192KB,\n"
  5847. "otherwise at 12288KB. On 315/330/340 series, the heap size is 32KB by default.\n"
  5848. "The value is to be specified without 'KB'.\n");
  5849. MODULE_PARM_DESC(noaccel,
  5850. "\nIf set to anything other than 0, 2D acceleration will be disabled.\n"
  5851. "(default: 0)\n");
  5852. MODULE_PARM_DESC(noypan,
  5853. "\nIf set to anything other than 0, y-panning will be disabled and scrolling\n"
  5854. "will be performed by redrawing the screen. (default: 0)\n");
  5855. MODULE_PARM_DESC(nomax,
  5856. "\nIf y-panning is enabled, sisfb will by default use the entire available video\n"
  5857. "memory for the virtual screen in order to optimize scrolling performance. If\n"
  5858. "this is set to anything other than 0, sisfb will not do this and thereby \n"
  5859. "enable the user to positively specify a virtual Y size of the screen using\n"
  5860. "fbset. (default: 0)\n");
  5861. MODULE_PARM_DESC(mode,
  5862. "\nSelects the desired default display mode in the format XxYxDepth,\n"
  5863. "eg. 1024x768x16. Other formats supported include XxY-Depth and\n"
  5864. "XxY-Depth@Rate. If the parameter is only one (decimal or hexadecimal)\n"
  5865. "number, it will be interpreted as a VESA mode number. (default: 800x600x8)\n");
  5866. MODULE_PARM_DESC(vesa,
  5867. "\nSelects the desired default display mode by VESA defined mode number, eg.\n"
  5868. "0x117 (default: 0x0103)\n");
  5869. MODULE_PARM_DESC(rate,
  5870. "\nSelects the desired vertical refresh rate for CRT1 (external VGA) in Hz.\n"
  5871. "If the mode is specified in the format XxY-Depth@Rate, this parameter\n"
  5872. "will be ignored (default: 60)\n");
  5873. MODULE_PARM_DESC(forcecrt1,
  5874. "\nNormally, the driver autodetects whether or not CRT1 (external VGA) is \n"
  5875. "connected. With this option, the detection can be overridden (1=CRT1 ON,\n"
  5876. "0=CRT1 OFF) (default: [autodetected])\n");
  5877. MODULE_PARM_DESC(forcecrt2type,
  5878. "\nIf this option is omitted, the driver autodetects CRT2 output devices, such as\n"
  5879. "LCD, TV or secondary VGA. With this option, this autodetection can be\n"
  5880. "overridden. Possible parameters are LCD, TV, VGA or NONE. NONE disables CRT2.\n"
  5881. "On systems with a SiS video bridge, parameters SVIDEO, COMPOSITE or SCART can\n"
  5882. "be used instead of TV to override the TV detection. Furthermore, on systems\n"
  5883. "with a SiS video bridge, SVIDEO+COMPOSITE, HIVISION, YPBPR480I, YPBPR480P,\n"
  5884. "YPBPR720P and YPBPR1080I are understood. However, whether or not these work\n"
  5885. "depends on the very hardware in use. (default: [autodetected])\n");
  5886. MODULE_PARM_DESC(scalelcd,
  5887. "\nSetting this to 1 will force the driver to scale the LCD image to the panel's\n"
  5888. "native resolution. Setting it to 0 will disable scaling; LVDS panels will\n"
  5889. "show black bars around the image, TMDS panels will probably do the scaling\n"
  5890. "themselves. Default: 1 on LVDS panels, 0 on TMDS panels\n");
  5891. MODULE_PARM_DESC(pdc,
  5892. "\nThis is for manually selecting the LCD panel delay compensation. The driver\n"
  5893. "should detect this correctly in most cases; however, sometimes this is not\n"
  5894. "possible. If you see 'small waves' on the LCD, try setting this to 4, 32 or 24\n"
  5895. "on a 300 series chipset; 6 on other chipsets. If the problem persists, try\n"
  5896. "other values (on 300 series: between 4 and 60 in steps of 4; otherwise: any\n"
  5897. "value from 0 to 31). (default: autodetected, if LCD is active during start)\n");
  5898. #ifdef CONFIG_FB_SIS_315
  5899. MODULE_PARM_DESC(pdc1,
  5900. "\nThis is same as pdc, but for LCD-via CRT1. Hence, this is for the 315/330/340\n"
  5901. "series only. (default: autodetected if LCD is in LCD-via-CRT1 mode during\n"
  5902. "startup) - Note: currently, this has no effect because LCD-via-CRT1 is not\n"
  5903. "implemented yet.\n");
  5904. #endif
  5905. MODULE_PARM_DESC(specialtiming,
  5906. "\nPlease refer to documentation for more information on this option.\n");
  5907. MODULE_PARM_DESC(lvdshl,
  5908. "\nPlease refer to documentation for more information on this option.\n");
  5909. MODULE_PARM_DESC(tvstandard,
  5910. "\nThis allows overriding the BIOS default for the TV standard. Valid choices are\n"
  5911. "pal, ntsc, palm and paln. (default: [auto; pal or ntsc only])\n");
  5912. MODULE_PARM_DESC(tvxposoffset,
  5913. "\nRelocate TV output horizontally. Possible parameters: -32 through 32.\n"
  5914. "Default: 0\n");
  5915. MODULE_PARM_DESC(tvyposoffset,
  5916. "\nRelocate TV output vertically. Possible parameters: -32 through 32.\n"
  5917. "Default: 0\n");
  5918. MODULE_PARM_DESC(nocrt2rate,
  5919. "\nSetting this to 1 will force the driver to use the default refresh rate for\n"
  5920. "CRT2 if CRT2 type is VGA. (default: 0, use same rate as CRT1)\n");
  5921. #if !defined(__i386__) && !defined(__x86_64__)
  5922. #ifdef CONFIG_FB_SIS_300
  5923. MODULE_PARM_DESC(resetcard,
  5924. "\nSet this to 1 in order to reset (POST) the card on non-x86 machines where\n"
  5925. "the BIOS did not POST the card (only supported for SiS 300/305 and XGI cards\n"
  5926. "currently). Default: 0\n");
  5927. MODULE_PARM_DESC(videoram,
  5928. "\nSet this to the amount of video RAM (in kilobyte) the card has. Required on\n"
  5929. "some non-x86 architectures where the memory auto detection fails. Only\n"
  5930. "relevant if resetcard is set, too. SiS300/305 only. Default: [auto-detect]\n");
  5931. #endif
  5932. #endif
  5933. #endif /* /MODULE */
  5934. /* _GPL only for new symbols. */
  5935. EXPORT_SYMBOL(sis_malloc);
  5936. EXPORT_SYMBOL(sis_free);
  5937. EXPORT_SYMBOL_GPL(sis_malloc_new);
  5938. EXPORT_SYMBOL_GPL(sis_free_new);