qla_mbx.c 126 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/gfp.h>
  11. /*
  12. * qla2x00_mailbox_command
  13. * Issue mailbox command and waits for completion.
  14. *
  15. * Input:
  16. * ha = adapter block pointer.
  17. * mcp = driver internal mbx struct pointer.
  18. *
  19. * Output:
  20. * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
  21. *
  22. * Returns:
  23. * 0 : QLA_SUCCESS = cmd performed success
  24. * 1 : QLA_FUNCTION_FAILED (error encountered)
  25. * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
  26. *
  27. * Context:
  28. * Kernel context.
  29. */
  30. static int
  31. qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
  32. {
  33. int rval;
  34. unsigned long flags = 0;
  35. device_reg_t __iomem *reg;
  36. uint8_t abort_active;
  37. uint8_t io_lock_on;
  38. uint16_t command = 0;
  39. uint16_t *iptr;
  40. uint16_t __iomem *optr;
  41. uint32_t cnt;
  42. uint32_t mboxes;
  43. unsigned long wait_time;
  44. struct qla_hw_data *ha = vha->hw;
  45. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  46. ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
  47. if (ha->pdev->error_state > pci_channel_io_frozen) {
  48. ql_log(ql_log_warn, vha, 0x1001,
  49. "error_state is greater than pci_channel_io_frozen, "
  50. "exiting.\n");
  51. return QLA_FUNCTION_TIMEOUT;
  52. }
  53. if (vha->device_flags & DFLG_DEV_FAILED) {
  54. ql_log(ql_log_warn, vha, 0x1002,
  55. "Device in failed state, exiting.\n");
  56. return QLA_FUNCTION_TIMEOUT;
  57. }
  58. reg = ha->iobase;
  59. io_lock_on = base_vha->flags.init_done;
  60. rval = QLA_SUCCESS;
  61. abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  62. if (ha->flags.pci_channel_io_perm_failure) {
  63. ql_log(ql_log_warn, vha, 0x1003,
  64. "Perm failure on EEH timeout MBX, exiting.\n");
  65. return QLA_FUNCTION_TIMEOUT;
  66. }
  67. if (IS_QLA82XX(ha) && ha->flags.isp82xx_fw_hung) {
  68. /* Setting Link-Down error */
  69. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  70. ql_log(ql_log_warn, vha, 0x1004,
  71. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  72. return QLA_FUNCTION_TIMEOUT;
  73. }
  74. /*
  75. * Wait for active mailbox commands to finish by waiting at most tov
  76. * seconds. This is to serialize actual issuing of mailbox cmds during
  77. * non ISP abort time.
  78. */
  79. if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
  80. /* Timeout occurred. Return error. */
  81. ql_log(ql_log_warn, vha, 0x1005,
  82. "Cmd access timeout, cmd=0x%x, Exiting.\n",
  83. mcp->mb[0]);
  84. return QLA_FUNCTION_TIMEOUT;
  85. }
  86. ha->flags.mbox_busy = 1;
  87. /* Save mailbox command for debug */
  88. ha->mcp = mcp;
  89. ql_dbg(ql_dbg_mbx, vha, 0x1006,
  90. "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
  91. spin_lock_irqsave(&ha->hardware_lock, flags);
  92. /* Load mailbox registers. */
  93. if (IS_QLA82XX(ha))
  94. optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
  95. else if (IS_FWI2_CAPABLE(ha) && !IS_QLA82XX(ha))
  96. optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
  97. else
  98. optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
  99. iptr = mcp->mb;
  100. command = mcp->mb[0];
  101. mboxes = mcp->out_mb;
  102. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  103. if (IS_QLA2200(ha) && cnt == 8)
  104. optr =
  105. (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
  106. if (mboxes & BIT_0)
  107. WRT_REG_WORD(optr, *iptr);
  108. mboxes >>= 1;
  109. optr++;
  110. iptr++;
  111. }
  112. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1111,
  113. "Loaded MBX registers (displayed in bytes) =.\n");
  114. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1112,
  115. (uint8_t *)mcp->mb, 16);
  116. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1113,
  117. ".\n");
  118. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1114,
  119. ((uint8_t *)mcp->mb + 0x10), 16);
  120. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1115,
  121. ".\n");
  122. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1116,
  123. ((uint8_t *)mcp->mb + 0x20), 8);
  124. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
  125. "I/O Address = %p.\n", optr);
  126. ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x100e);
  127. /* Issue set host interrupt command to send cmd out. */
  128. ha->flags.mbox_int = 0;
  129. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  130. /* Unlock mbx registers and wait for interrupt */
  131. ql_dbg(ql_dbg_mbx, vha, 0x100f,
  132. "Going to unlock irq & waiting for interrupts. "
  133. "jiffies=%lx.\n", jiffies);
  134. /* Wait for mbx cmd completion until timeout */
  135. if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
  136. set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  137. if (IS_QLA82XX(ha)) {
  138. if (RD_REG_DWORD(&reg->isp82.hint) &
  139. HINT_MBX_INT_PENDING) {
  140. spin_unlock_irqrestore(&ha->hardware_lock,
  141. flags);
  142. ha->flags.mbox_busy = 0;
  143. ql_dbg(ql_dbg_mbx, vha, 0x1010,
  144. "Pending mailbox timeout, exiting.\n");
  145. rval = QLA_FUNCTION_TIMEOUT;
  146. goto premature_exit;
  147. }
  148. WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
  149. } else if (IS_FWI2_CAPABLE(ha))
  150. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
  151. else
  152. WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
  153. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  154. wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
  155. clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  156. } else {
  157. ql_dbg(ql_dbg_mbx, vha, 0x1011,
  158. "Cmd=%x Polling Mode.\n", command);
  159. if (IS_QLA82XX(ha)) {
  160. if (RD_REG_DWORD(&reg->isp82.hint) &
  161. HINT_MBX_INT_PENDING) {
  162. spin_unlock_irqrestore(&ha->hardware_lock,
  163. flags);
  164. ha->flags.mbox_busy = 0;
  165. ql_dbg(ql_dbg_mbx, vha, 0x1012,
  166. "Pending mailbox timeout, exiting.\n");
  167. rval = QLA_FUNCTION_TIMEOUT;
  168. goto premature_exit;
  169. }
  170. WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
  171. } else if (IS_FWI2_CAPABLE(ha))
  172. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
  173. else
  174. WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
  175. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  176. wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
  177. while (!ha->flags.mbox_int) {
  178. if (time_after(jiffies, wait_time))
  179. break;
  180. /* Check for pending interrupts. */
  181. qla2x00_poll(ha->rsp_q_map[0]);
  182. if (!ha->flags.mbox_int &&
  183. !(IS_QLA2200(ha) &&
  184. command == MBC_LOAD_RISC_RAM_EXTENDED))
  185. msleep(10);
  186. } /* while */
  187. ql_dbg(ql_dbg_mbx, vha, 0x1013,
  188. "Waited %d sec.\n",
  189. (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
  190. }
  191. /* Check whether we timed out */
  192. if (ha->flags.mbox_int) {
  193. uint16_t *iptr2;
  194. ql_dbg(ql_dbg_mbx, vha, 0x1014,
  195. "Cmd=%x completed.\n", command);
  196. /* Got interrupt. Clear the flag. */
  197. ha->flags.mbox_int = 0;
  198. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  199. if ((IS_QLA82XX(ha) && ha->flags.isp82xx_fw_hung)) {
  200. ha->flags.mbox_busy = 0;
  201. /* Setting Link-Down error */
  202. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  203. ha->mcp = NULL;
  204. rval = QLA_FUNCTION_FAILED;
  205. ql_log(ql_log_warn, vha, 0x1015,
  206. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  207. goto premature_exit;
  208. }
  209. if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
  210. rval = QLA_FUNCTION_FAILED;
  211. /* Load return mailbox registers. */
  212. iptr2 = mcp->mb;
  213. iptr = (uint16_t *)&ha->mailbox_out[0];
  214. mboxes = mcp->in_mb;
  215. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  216. if (mboxes & BIT_0)
  217. *iptr2 = *iptr;
  218. mboxes >>= 1;
  219. iptr2++;
  220. iptr++;
  221. }
  222. } else {
  223. uint16_t mb0;
  224. uint32_t ictrl;
  225. if (IS_FWI2_CAPABLE(ha)) {
  226. mb0 = RD_REG_WORD(&reg->isp24.mailbox0);
  227. ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
  228. } else {
  229. mb0 = RD_MAILBOX_REG(ha, &reg->isp, 0);
  230. ictrl = RD_REG_WORD(&reg->isp.ictrl);
  231. }
  232. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
  233. "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
  234. "mb[0]=0x%x\n", command, ictrl, jiffies, mb0);
  235. ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
  236. /*
  237. * Attempt to capture a firmware dump for further analysis
  238. * of the current firmware state
  239. */
  240. ha->isp_ops->fw_dump(vha, 0);
  241. rval = QLA_FUNCTION_TIMEOUT;
  242. }
  243. ha->flags.mbox_busy = 0;
  244. /* Clean up */
  245. ha->mcp = NULL;
  246. if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
  247. ql_dbg(ql_dbg_mbx, vha, 0x101a,
  248. "Checking for additional resp interrupt.\n");
  249. /* polling mode for non isp_abort commands. */
  250. qla2x00_poll(ha->rsp_q_map[0]);
  251. }
  252. if (rval == QLA_FUNCTION_TIMEOUT &&
  253. mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
  254. if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
  255. ha->flags.eeh_busy) {
  256. /* not in dpc. schedule it for dpc to take over. */
  257. ql_dbg(ql_dbg_mbx, vha, 0x101b,
  258. "Timeout, schedule isp_abort_needed.\n");
  259. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  260. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  261. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  262. if (IS_QLA82XX(ha)) {
  263. ql_dbg(ql_dbg_mbx, vha, 0x112a,
  264. "disabling pause transmit on port "
  265. "0 & 1.\n");
  266. qla82xx_wr_32(ha,
  267. QLA82XX_CRB_NIU + 0x98,
  268. CRB_NIU_XG_PAUSE_CTL_P0|
  269. CRB_NIU_XG_PAUSE_CTL_P1);
  270. }
  271. ql_log(ql_log_info, base_vha, 0x101c,
  272. "Mailbox cmd timeout occurred, cmd=0x%x, "
  273. "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
  274. "abort.\n", command, mcp->mb[0],
  275. ha->flags.eeh_busy);
  276. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  277. qla2xxx_wake_dpc(vha);
  278. }
  279. } else if (!abort_active) {
  280. /* call abort directly since we are in the DPC thread */
  281. ql_dbg(ql_dbg_mbx, vha, 0x101d,
  282. "Timeout, calling abort_isp.\n");
  283. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  284. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  285. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  286. if (IS_QLA82XX(ha)) {
  287. ql_dbg(ql_dbg_mbx, vha, 0x112b,
  288. "disabling pause transmit on port "
  289. "0 & 1.\n");
  290. qla82xx_wr_32(ha,
  291. QLA82XX_CRB_NIU + 0x98,
  292. CRB_NIU_XG_PAUSE_CTL_P0|
  293. CRB_NIU_XG_PAUSE_CTL_P1);
  294. }
  295. ql_log(ql_log_info, base_vha, 0x101e,
  296. "Mailbox cmd timeout occurred, cmd=0x%x, "
  297. "mb[0]=0x%x. Scheduling ISP abort ",
  298. command, mcp->mb[0]);
  299. set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  300. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  301. /* Allow next mbx cmd to come in. */
  302. complete(&ha->mbx_cmd_comp);
  303. if (ha->isp_ops->abort_isp(vha)) {
  304. /* Failed. retry later. */
  305. set_bit(ISP_ABORT_NEEDED,
  306. &vha->dpc_flags);
  307. }
  308. clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  309. ql_dbg(ql_dbg_mbx, vha, 0x101f,
  310. "Finished abort_isp.\n");
  311. goto mbx_done;
  312. }
  313. }
  314. }
  315. premature_exit:
  316. /* Allow next mbx cmd to come in. */
  317. complete(&ha->mbx_cmd_comp);
  318. mbx_done:
  319. if (rval) {
  320. ql_log(ql_log_warn, base_vha, 0x1020,
  321. "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
  322. mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
  323. } else {
  324. ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
  325. }
  326. return rval;
  327. }
  328. int
  329. qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
  330. uint32_t risc_code_size)
  331. {
  332. int rval;
  333. struct qla_hw_data *ha = vha->hw;
  334. mbx_cmd_t mc;
  335. mbx_cmd_t *mcp = &mc;
  336. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
  337. "Entered %s.\n", __func__);
  338. if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
  339. mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
  340. mcp->mb[8] = MSW(risc_addr);
  341. mcp->out_mb = MBX_8|MBX_0;
  342. } else {
  343. mcp->mb[0] = MBC_LOAD_RISC_RAM;
  344. mcp->out_mb = MBX_0;
  345. }
  346. mcp->mb[1] = LSW(risc_addr);
  347. mcp->mb[2] = MSW(req_dma);
  348. mcp->mb[3] = LSW(req_dma);
  349. mcp->mb[6] = MSW(MSD(req_dma));
  350. mcp->mb[7] = LSW(MSD(req_dma));
  351. mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
  352. if (IS_FWI2_CAPABLE(ha)) {
  353. mcp->mb[4] = MSW(risc_code_size);
  354. mcp->mb[5] = LSW(risc_code_size);
  355. mcp->out_mb |= MBX_5|MBX_4;
  356. } else {
  357. mcp->mb[4] = LSW(risc_code_size);
  358. mcp->out_mb |= MBX_4;
  359. }
  360. mcp->in_mb = MBX_0;
  361. mcp->tov = MBX_TOV_SECONDS;
  362. mcp->flags = 0;
  363. rval = qla2x00_mailbox_command(vha, mcp);
  364. if (rval != QLA_SUCCESS) {
  365. ql_dbg(ql_dbg_mbx, vha, 0x1023,
  366. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  367. } else {
  368. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
  369. "Done %s.\n", __func__);
  370. }
  371. return rval;
  372. }
  373. #define EXTENDED_BB_CREDITS BIT_0
  374. /*
  375. * qla2x00_execute_fw
  376. * Start adapter firmware.
  377. *
  378. * Input:
  379. * ha = adapter block pointer.
  380. * TARGET_QUEUE_LOCK must be released.
  381. * ADAPTER_STATE_LOCK must be released.
  382. *
  383. * Returns:
  384. * qla2x00 local function return status code.
  385. *
  386. * Context:
  387. * Kernel context.
  388. */
  389. int
  390. qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
  391. {
  392. int rval;
  393. struct qla_hw_data *ha = vha->hw;
  394. mbx_cmd_t mc;
  395. mbx_cmd_t *mcp = &mc;
  396. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
  397. "Entered %s.\n", __func__);
  398. mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
  399. mcp->out_mb = MBX_0;
  400. mcp->in_mb = MBX_0;
  401. if (IS_FWI2_CAPABLE(ha)) {
  402. mcp->mb[1] = MSW(risc_addr);
  403. mcp->mb[2] = LSW(risc_addr);
  404. mcp->mb[3] = 0;
  405. if (IS_QLA81XX(ha) || IS_QLA83XX(ha)) {
  406. struct nvram_81xx *nv = ha->nvram;
  407. mcp->mb[4] = (nv->enhanced_features &
  408. EXTENDED_BB_CREDITS);
  409. } else
  410. mcp->mb[4] = 0;
  411. mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
  412. mcp->in_mb |= MBX_1;
  413. } else {
  414. mcp->mb[1] = LSW(risc_addr);
  415. mcp->out_mb |= MBX_1;
  416. if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  417. mcp->mb[2] = 0;
  418. mcp->out_mb |= MBX_2;
  419. }
  420. }
  421. mcp->tov = MBX_TOV_SECONDS;
  422. mcp->flags = 0;
  423. rval = qla2x00_mailbox_command(vha, mcp);
  424. if (rval != QLA_SUCCESS) {
  425. ql_dbg(ql_dbg_mbx, vha, 0x1026,
  426. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  427. } else {
  428. if (IS_FWI2_CAPABLE(ha)) {
  429. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027,
  430. "Done exchanges=%x.\n", mcp->mb[1]);
  431. } else {
  432. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
  433. "Done %s.\n", __func__);
  434. }
  435. }
  436. return rval;
  437. }
  438. /*
  439. * qla2x00_get_fw_version
  440. * Get firmware version.
  441. *
  442. * Input:
  443. * ha: adapter state pointer.
  444. * major: pointer for major number.
  445. * minor: pointer for minor number.
  446. * subminor: pointer for subminor number.
  447. *
  448. * Returns:
  449. * qla2x00 local function return status code.
  450. *
  451. * Context:
  452. * Kernel context.
  453. */
  454. int
  455. qla2x00_get_fw_version(scsi_qla_host_t *vha)
  456. {
  457. int rval;
  458. mbx_cmd_t mc;
  459. mbx_cmd_t *mcp = &mc;
  460. struct qla_hw_data *ha = vha->hw;
  461. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
  462. "Entered %s.\n", __func__);
  463. mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
  464. mcp->out_mb = MBX_0;
  465. mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  466. if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha))
  467. mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
  468. if (IS_FWI2_CAPABLE(ha))
  469. mcp->in_mb |= MBX_17|MBX_16|MBX_15;
  470. mcp->flags = 0;
  471. mcp->tov = MBX_TOV_SECONDS;
  472. rval = qla2x00_mailbox_command(vha, mcp);
  473. if (rval != QLA_SUCCESS)
  474. goto failed;
  475. /* Return mailbox data. */
  476. ha->fw_major_version = mcp->mb[1];
  477. ha->fw_minor_version = mcp->mb[2];
  478. ha->fw_subminor_version = mcp->mb[3];
  479. ha->fw_attributes = mcp->mb[6];
  480. if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
  481. ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
  482. else
  483. ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
  484. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw)) {
  485. ha->mpi_version[0] = mcp->mb[10] & 0xff;
  486. ha->mpi_version[1] = mcp->mb[11] >> 8;
  487. ha->mpi_version[2] = mcp->mb[11] & 0xff;
  488. ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
  489. ha->phy_version[0] = mcp->mb[8] & 0xff;
  490. ha->phy_version[1] = mcp->mb[9] >> 8;
  491. ha->phy_version[2] = mcp->mb[9] & 0xff;
  492. }
  493. if (IS_FWI2_CAPABLE(ha)) {
  494. ha->fw_attributes_h = mcp->mb[15];
  495. ha->fw_attributes_ext[0] = mcp->mb[16];
  496. ha->fw_attributes_ext[1] = mcp->mb[17];
  497. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
  498. "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
  499. __func__, mcp->mb[15], mcp->mb[6]);
  500. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
  501. "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
  502. __func__, mcp->mb[17], mcp->mb[16]);
  503. }
  504. failed:
  505. if (rval != QLA_SUCCESS) {
  506. /*EMPTY*/
  507. ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
  508. } else {
  509. /*EMPTY*/
  510. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
  511. "Done %s.\n", __func__);
  512. }
  513. return rval;
  514. }
  515. /*
  516. * qla2x00_get_fw_options
  517. * Set firmware options.
  518. *
  519. * Input:
  520. * ha = adapter block pointer.
  521. * fwopt = pointer for firmware options.
  522. *
  523. * Returns:
  524. * qla2x00 local function return status code.
  525. *
  526. * Context:
  527. * Kernel context.
  528. */
  529. int
  530. qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
  531. {
  532. int rval;
  533. mbx_cmd_t mc;
  534. mbx_cmd_t *mcp = &mc;
  535. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
  536. "Entered %s.\n", __func__);
  537. mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
  538. mcp->out_mb = MBX_0;
  539. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  540. mcp->tov = MBX_TOV_SECONDS;
  541. mcp->flags = 0;
  542. rval = qla2x00_mailbox_command(vha, mcp);
  543. if (rval != QLA_SUCCESS) {
  544. /*EMPTY*/
  545. ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
  546. } else {
  547. fwopts[0] = mcp->mb[0];
  548. fwopts[1] = mcp->mb[1];
  549. fwopts[2] = mcp->mb[2];
  550. fwopts[3] = mcp->mb[3];
  551. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
  552. "Done %s.\n", __func__);
  553. }
  554. return rval;
  555. }
  556. /*
  557. * qla2x00_set_fw_options
  558. * Set firmware options.
  559. *
  560. * Input:
  561. * ha = adapter block pointer.
  562. * fwopt = pointer for firmware options.
  563. *
  564. * Returns:
  565. * qla2x00 local function return status code.
  566. *
  567. * Context:
  568. * Kernel context.
  569. */
  570. int
  571. qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
  572. {
  573. int rval;
  574. mbx_cmd_t mc;
  575. mbx_cmd_t *mcp = &mc;
  576. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
  577. "Entered %s.\n", __func__);
  578. mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
  579. mcp->mb[1] = fwopts[1];
  580. mcp->mb[2] = fwopts[2];
  581. mcp->mb[3] = fwopts[3];
  582. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  583. mcp->in_mb = MBX_0;
  584. if (IS_FWI2_CAPABLE(vha->hw)) {
  585. mcp->in_mb |= MBX_1;
  586. } else {
  587. mcp->mb[10] = fwopts[10];
  588. mcp->mb[11] = fwopts[11];
  589. mcp->mb[12] = 0; /* Undocumented, but used */
  590. mcp->out_mb |= MBX_12|MBX_11|MBX_10;
  591. }
  592. mcp->tov = MBX_TOV_SECONDS;
  593. mcp->flags = 0;
  594. rval = qla2x00_mailbox_command(vha, mcp);
  595. fwopts[0] = mcp->mb[0];
  596. if (rval != QLA_SUCCESS) {
  597. /*EMPTY*/
  598. ql_dbg(ql_dbg_mbx, vha, 0x1030,
  599. "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
  600. } else {
  601. /*EMPTY*/
  602. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
  603. "Done %s.\n", __func__);
  604. }
  605. return rval;
  606. }
  607. /*
  608. * qla2x00_mbx_reg_test
  609. * Mailbox register wrap test.
  610. *
  611. * Input:
  612. * ha = adapter block pointer.
  613. * TARGET_QUEUE_LOCK must be released.
  614. * ADAPTER_STATE_LOCK must be released.
  615. *
  616. * Returns:
  617. * qla2x00 local function return status code.
  618. *
  619. * Context:
  620. * Kernel context.
  621. */
  622. int
  623. qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
  624. {
  625. int rval;
  626. mbx_cmd_t mc;
  627. mbx_cmd_t *mcp = &mc;
  628. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
  629. "Entered %s.\n", __func__);
  630. mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
  631. mcp->mb[1] = 0xAAAA;
  632. mcp->mb[2] = 0x5555;
  633. mcp->mb[3] = 0xAA55;
  634. mcp->mb[4] = 0x55AA;
  635. mcp->mb[5] = 0xA5A5;
  636. mcp->mb[6] = 0x5A5A;
  637. mcp->mb[7] = 0x2525;
  638. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  639. mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  640. mcp->tov = MBX_TOV_SECONDS;
  641. mcp->flags = 0;
  642. rval = qla2x00_mailbox_command(vha, mcp);
  643. if (rval == QLA_SUCCESS) {
  644. if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
  645. mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
  646. rval = QLA_FUNCTION_FAILED;
  647. if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
  648. mcp->mb[7] != 0x2525)
  649. rval = QLA_FUNCTION_FAILED;
  650. }
  651. if (rval != QLA_SUCCESS) {
  652. /*EMPTY*/
  653. ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
  654. } else {
  655. /*EMPTY*/
  656. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
  657. "Done %s.\n", __func__);
  658. }
  659. return rval;
  660. }
  661. /*
  662. * qla2x00_verify_checksum
  663. * Verify firmware checksum.
  664. *
  665. * Input:
  666. * ha = adapter block pointer.
  667. * TARGET_QUEUE_LOCK must be released.
  668. * ADAPTER_STATE_LOCK must be released.
  669. *
  670. * Returns:
  671. * qla2x00 local function return status code.
  672. *
  673. * Context:
  674. * Kernel context.
  675. */
  676. int
  677. qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
  678. {
  679. int rval;
  680. mbx_cmd_t mc;
  681. mbx_cmd_t *mcp = &mc;
  682. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
  683. "Entered %s.\n", __func__);
  684. mcp->mb[0] = MBC_VERIFY_CHECKSUM;
  685. mcp->out_mb = MBX_0;
  686. mcp->in_mb = MBX_0;
  687. if (IS_FWI2_CAPABLE(vha->hw)) {
  688. mcp->mb[1] = MSW(risc_addr);
  689. mcp->mb[2] = LSW(risc_addr);
  690. mcp->out_mb |= MBX_2|MBX_1;
  691. mcp->in_mb |= MBX_2|MBX_1;
  692. } else {
  693. mcp->mb[1] = LSW(risc_addr);
  694. mcp->out_mb |= MBX_1;
  695. mcp->in_mb |= MBX_1;
  696. }
  697. mcp->tov = MBX_TOV_SECONDS;
  698. mcp->flags = 0;
  699. rval = qla2x00_mailbox_command(vha, mcp);
  700. if (rval != QLA_SUCCESS) {
  701. ql_dbg(ql_dbg_mbx, vha, 0x1036,
  702. "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
  703. (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
  704. } else {
  705. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
  706. "Done %s.\n", __func__);
  707. }
  708. return rval;
  709. }
  710. /*
  711. * qla2x00_issue_iocb
  712. * Issue IOCB using mailbox command
  713. *
  714. * Input:
  715. * ha = adapter state pointer.
  716. * buffer = buffer pointer.
  717. * phys_addr = physical address of buffer.
  718. * size = size of buffer.
  719. * TARGET_QUEUE_LOCK must be released.
  720. * ADAPTER_STATE_LOCK must be released.
  721. *
  722. * Returns:
  723. * qla2x00 local function return status code.
  724. *
  725. * Context:
  726. * Kernel context.
  727. */
  728. int
  729. qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
  730. dma_addr_t phys_addr, size_t size, uint32_t tov)
  731. {
  732. int rval;
  733. mbx_cmd_t mc;
  734. mbx_cmd_t *mcp = &mc;
  735. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
  736. "Entered %s.\n", __func__);
  737. mcp->mb[0] = MBC_IOCB_COMMAND_A64;
  738. mcp->mb[1] = 0;
  739. mcp->mb[2] = MSW(phys_addr);
  740. mcp->mb[3] = LSW(phys_addr);
  741. mcp->mb[6] = MSW(MSD(phys_addr));
  742. mcp->mb[7] = LSW(MSD(phys_addr));
  743. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  744. mcp->in_mb = MBX_2|MBX_0;
  745. mcp->tov = tov;
  746. mcp->flags = 0;
  747. rval = qla2x00_mailbox_command(vha, mcp);
  748. if (rval != QLA_SUCCESS) {
  749. /*EMPTY*/
  750. ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
  751. } else {
  752. sts_entry_t *sts_entry = (sts_entry_t *) buffer;
  753. /* Mask reserved bits. */
  754. sts_entry->entry_status &=
  755. IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
  756. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
  757. "Done %s.\n", __func__);
  758. }
  759. return rval;
  760. }
  761. int
  762. qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
  763. size_t size)
  764. {
  765. return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
  766. MBX_TOV_SECONDS);
  767. }
  768. /*
  769. * qla2x00_abort_command
  770. * Abort command aborts a specified IOCB.
  771. *
  772. * Input:
  773. * ha = adapter block pointer.
  774. * sp = SB structure pointer.
  775. *
  776. * Returns:
  777. * qla2x00 local function return status code.
  778. *
  779. * Context:
  780. * Kernel context.
  781. */
  782. int
  783. qla2x00_abort_command(srb_t *sp)
  784. {
  785. unsigned long flags = 0;
  786. int rval;
  787. uint32_t handle = 0;
  788. mbx_cmd_t mc;
  789. mbx_cmd_t *mcp = &mc;
  790. fc_port_t *fcport = sp->fcport;
  791. scsi_qla_host_t *vha = fcport->vha;
  792. struct qla_hw_data *ha = vha->hw;
  793. struct req_que *req = vha->req;
  794. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  795. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
  796. "Entered %s.\n", __func__);
  797. spin_lock_irqsave(&ha->hardware_lock, flags);
  798. for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
  799. if (req->outstanding_cmds[handle] == sp)
  800. break;
  801. }
  802. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  803. if (handle == req->num_outstanding_cmds) {
  804. /* command not found */
  805. return QLA_FUNCTION_FAILED;
  806. }
  807. mcp->mb[0] = MBC_ABORT_COMMAND;
  808. if (HAS_EXTENDED_IDS(ha))
  809. mcp->mb[1] = fcport->loop_id;
  810. else
  811. mcp->mb[1] = fcport->loop_id << 8;
  812. mcp->mb[2] = (uint16_t)handle;
  813. mcp->mb[3] = (uint16_t)(handle >> 16);
  814. mcp->mb[6] = (uint16_t)cmd->device->lun;
  815. mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  816. mcp->in_mb = MBX_0;
  817. mcp->tov = MBX_TOV_SECONDS;
  818. mcp->flags = 0;
  819. rval = qla2x00_mailbox_command(vha, mcp);
  820. if (rval != QLA_SUCCESS) {
  821. ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
  822. } else {
  823. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
  824. "Done %s.\n", __func__);
  825. }
  826. return rval;
  827. }
  828. int
  829. qla2x00_abort_target(struct fc_port *fcport, unsigned int l, int tag)
  830. {
  831. int rval, rval2;
  832. mbx_cmd_t mc;
  833. mbx_cmd_t *mcp = &mc;
  834. scsi_qla_host_t *vha;
  835. struct req_que *req;
  836. struct rsp_que *rsp;
  837. l = l;
  838. vha = fcport->vha;
  839. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
  840. "Entered %s.\n", __func__);
  841. req = vha->hw->req_q_map[0];
  842. rsp = req->rsp;
  843. mcp->mb[0] = MBC_ABORT_TARGET;
  844. mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
  845. if (HAS_EXTENDED_IDS(vha->hw)) {
  846. mcp->mb[1] = fcport->loop_id;
  847. mcp->mb[10] = 0;
  848. mcp->out_mb |= MBX_10;
  849. } else {
  850. mcp->mb[1] = fcport->loop_id << 8;
  851. }
  852. mcp->mb[2] = vha->hw->loop_reset_delay;
  853. mcp->mb[9] = vha->vp_idx;
  854. mcp->in_mb = MBX_0;
  855. mcp->tov = MBX_TOV_SECONDS;
  856. mcp->flags = 0;
  857. rval = qla2x00_mailbox_command(vha, mcp);
  858. if (rval != QLA_SUCCESS) {
  859. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
  860. "Failed=%x.\n", rval);
  861. }
  862. /* Issue marker IOCB. */
  863. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
  864. MK_SYNC_ID);
  865. if (rval2 != QLA_SUCCESS) {
  866. ql_dbg(ql_dbg_mbx, vha, 0x1040,
  867. "Failed to issue marker IOCB (%x).\n", rval2);
  868. } else {
  869. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
  870. "Done %s.\n", __func__);
  871. }
  872. return rval;
  873. }
  874. int
  875. qla2x00_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
  876. {
  877. int rval, rval2;
  878. mbx_cmd_t mc;
  879. mbx_cmd_t *mcp = &mc;
  880. scsi_qla_host_t *vha;
  881. struct req_que *req;
  882. struct rsp_que *rsp;
  883. vha = fcport->vha;
  884. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
  885. "Entered %s.\n", __func__);
  886. req = vha->hw->req_q_map[0];
  887. rsp = req->rsp;
  888. mcp->mb[0] = MBC_LUN_RESET;
  889. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  890. if (HAS_EXTENDED_IDS(vha->hw))
  891. mcp->mb[1] = fcport->loop_id;
  892. else
  893. mcp->mb[1] = fcport->loop_id << 8;
  894. mcp->mb[2] = l;
  895. mcp->mb[3] = 0;
  896. mcp->mb[9] = vha->vp_idx;
  897. mcp->in_mb = MBX_0;
  898. mcp->tov = MBX_TOV_SECONDS;
  899. mcp->flags = 0;
  900. rval = qla2x00_mailbox_command(vha, mcp);
  901. if (rval != QLA_SUCCESS) {
  902. ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
  903. }
  904. /* Issue marker IOCB. */
  905. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
  906. MK_SYNC_ID_LUN);
  907. if (rval2 != QLA_SUCCESS) {
  908. ql_dbg(ql_dbg_mbx, vha, 0x1044,
  909. "Failed to issue marker IOCB (%x).\n", rval2);
  910. } else {
  911. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
  912. "Done %s.\n", __func__);
  913. }
  914. return rval;
  915. }
  916. /*
  917. * qla2x00_get_adapter_id
  918. * Get adapter ID and topology.
  919. *
  920. * Input:
  921. * ha = adapter block pointer.
  922. * id = pointer for loop ID.
  923. * al_pa = pointer for AL_PA.
  924. * area = pointer for area.
  925. * domain = pointer for domain.
  926. * top = pointer for topology.
  927. * TARGET_QUEUE_LOCK must be released.
  928. * ADAPTER_STATE_LOCK must be released.
  929. *
  930. * Returns:
  931. * qla2x00 local function return status code.
  932. *
  933. * Context:
  934. * Kernel context.
  935. */
  936. int
  937. qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
  938. uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
  939. {
  940. int rval;
  941. mbx_cmd_t mc;
  942. mbx_cmd_t *mcp = &mc;
  943. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
  944. "Entered %s.\n", __func__);
  945. mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
  946. mcp->mb[9] = vha->vp_idx;
  947. mcp->out_mb = MBX_9|MBX_0;
  948. mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  949. if (IS_CNA_CAPABLE(vha->hw))
  950. mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
  951. mcp->tov = MBX_TOV_SECONDS;
  952. mcp->flags = 0;
  953. rval = qla2x00_mailbox_command(vha, mcp);
  954. if (mcp->mb[0] == MBS_COMMAND_ERROR)
  955. rval = QLA_COMMAND_ERROR;
  956. else if (mcp->mb[0] == MBS_INVALID_COMMAND)
  957. rval = QLA_INVALID_COMMAND;
  958. /* Return data. */
  959. *id = mcp->mb[1];
  960. *al_pa = LSB(mcp->mb[2]);
  961. *area = MSB(mcp->mb[2]);
  962. *domain = LSB(mcp->mb[3]);
  963. *top = mcp->mb[6];
  964. *sw_cap = mcp->mb[7];
  965. if (rval != QLA_SUCCESS) {
  966. /*EMPTY*/
  967. ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
  968. } else {
  969. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
  970. "Done %s.\n", __func__);
  971. if (IS_CNA_CAPABLE(vha->hw)) {
  972. vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
  973. vha->fcoe_fcf_idx = mcp->mb[10];
  974. vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
  975. vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
  976. vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
  977. vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
  978. vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
  979. vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
  980. }
  981. }
  982. return rval;
  983. }
  984. /*
  985. * qla2x00_get_retry_cnt
  986. * Get current firmware login retry count and delay.
  987. *
  988. * Input:
  989. * ha = adapter block pointer.
  990. * retry_cnt = pointer to login retry count.
  991. * tov = pointer to login timeout value.
  992. *
  993. * Returns:
  994. * qla2x00 local function return status code.
  995. *
  996. * Context:
  997. * Kernel context.
  998. */
  999. int
  1000. qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
  1001. uint16_t *r_a_tov)
  1002. {
  1003. int rval;
  1004. uint16_t ratov;
  1005. mbx_cmd_t mc;
  1006. mbx_cmd_t *mcp = &mc;
  1007. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
  1008. "Entered %s.\n", __func__);
  1009. mcp->mb[0] = MBC_GET_RETRY_COUNT;
  1010. mcp->out_mb = MBX_0;
  1011. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1012. mcp->tov = MBX_TOV_SECONDS;
  1013. mcp->flags = 0;
  1014. rval = qla2x00_mailbox_command(vha, mcp);
  1015. if (rval != QLA_SUCCESS) {
  1016. /*EMPTY*/
  1017. ql_dbg(ql_dbg_mbx, vha, 0x104a,
  1018. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  1019. } else {
  1020. /* Convert returned data and check our values. */
  1021. *r_a_tov = mcp->mb[3] / 2;
  1022. ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
  1023. if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
  1024. /* Update to the larger values */
  1025. *retry_cnt = (uint8_t)mcp->mb[1];
  1026. *tov = ratov;
  1027. }
  1028. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
  1029. "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
  1030. }
  1031. return rval;
  1032. }
  1033. /*
  1034. * qla2x00_init_firmware
  1035. * Initialize adapter firmware.
  1036. *
  1037. * Input:
  1038. * ha = adapter block pointer.
  1039. * dptr = Initialization control block pointer.
  1040. * size = size of initialization control block.
  1041. * TARGET_QUEUE_LOCK must be released.
  1042. * ADAPTER_STATE_LOCK must be released.
  1043. *
  1044. * Returns:
  1045. * qla2x00 local function return status code.
  1046. *
  1047. * Context:
  1048. * Kernel context.
  1049. */
  1050. int
  1051. qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
  1052. {
  1053. int rval;
  1054. mbx_cmd_t mc;
  1055. mbx_cmd_t *mcp = &mc;
  1056. struct qla_hw_data *ha = vha->hw;
  1057. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
  1058. "Entered %s.\n", __func__);
  1059. if (IS_QLA82XX(ha) && ql2xdbwr)
  1060. qla82xx_wr_32(ha, ha->nxdb_wr_ptr,
  1061. (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
  1062. if (ha->flags.npiv_supported)
  1063. mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
  1064. else
  1065. mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
  1066. mcp->mb[1] = 0;
  1067. mcp->mb[2] = MSW(ha->init_cb_dma);
  1068. mcp->mb[3] = LSW(ha->init_cb_dma);
  1069. mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
  1070. mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
  1071. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1072. if ((IS_QLA81XX(ha) || IS_QLA83XX(ha)) && ha->ex_init_cb->ex_version) {
  1073. mcp->mb[1] = BIT_0;
  1074. mcp->mb[10] = MSW(ha->ex_init_cb_dma);
  1075. mcp->mb[11] = LSW(ha->ex_init_cb_dma);
  1076. mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
  1077. mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
  1078. mcp->mb[14] = sizeof(*ha->ex_init_cb);
  1079. mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
  1080. }
  1081. /* 1 and 2 should normally be captured. */
  1082. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  1083. if (IS_QLA83XX(ha))
  1084. /* mb3 is additional info about the installed SFP. */
  1085. mcp->in_mb |= MBX_3;
  1086. mcp->buf_size = size;
  1087. mcp->flags = MBX_DMA_OUT;
  1088. mcp->tov = MBX_TOV_SECONDS;
  1089. rval = qla2x00_mailbox_command(vha, mcp);
  1090. if (rval != QLA_SUCCESS) {
  1091. /*EMPTY*/
  1092. ql_dbg(ql_dbg_mbx, vha, 0x104d,
  1093. "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
  1094. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
  1095. } else {
  1096. /*EMPTY*/
  1097. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
  1098. "Done %s.\n", __func__);
  1099. }
  1100. return rval;
  1101. }
  1102. /*
  1103. * qla2x00_get_node_name_list
  1104. * Issue get node name list mailbox command, kmalloc()
  1105. * and return the resulting list. Caller must kfree() it!
  1106. *
  1107. * Input:
  1108. * ha = adapter state pointer.
  1109. * out_data = resulting list
  1110. * out_len = length of the resulting list
  1111. *
  1112. * Returns:
  1113. * qla2x00 local function return status code.
  1114. *
  1115. * Context:
  1116. * Kernel context.
  1117. */
  1118. int
  1119. qla2x00_get_node_name_list(scsi_qla_host_t *vha, void **out_data, int *out_len)
  1120. {
  1121. struct qla_hw_data *ha = vha->hw;
  1122. struct qla_port_24xx_data *list = NULL;
  1123. void *pmap;
  1124. mbx_cmd_t mc;
  1125. dma_addr_t pmap_dma;
  1126. ulong dma_size;
  1127. int rval, left;
  1128. left = 1;
  1129. while (left > 0) {
  1130. dma_size = left * sizeof(*list);
  1131. pmap = dma_alloc_coherent(&ha->pdev->dev, dma_size,
  1132. &pmap_dma, GFP_KERNEL);
  1133. if (!pmap) {
  1134. ql_log(ql_log_warn, vha, 0x113f,
  1135. "%s(%ld): DMA Alloc failed of %ld\n",
  1136. __func__, vha->host_no, dma_size);
  1137. rval = QLA_MEMORY_ALLOC_FAILED;
  1138. goto out;
  1139. }
  1140. mc.mb[0] = MBC_PORT_NODE_NAME_LIST;
  1141. mc.mb[1] = BIT_1 | BIT_3;
  1142. mc.mb[2] = MSW(pmap_dma);
  1143. mc.mb[3] = LSW(pmap_dma);
  1144. mc.mb[6] = MSW(MSD(pmap_dma));
  1145. mc.mb[7] = LSW(MSD(pmap_dma));
  1146. mc.mb[8] = dma_size;
  1147. mc.out_mb = MBX_0|MBX_1|MBX_2|MBX_3|MBX_6|MBX_7|MBX_8;
  1148. mc.in_mb = MBX_0|MBX_1;
  1149. mc.tov = 30;
  1150. mc.flags = MBX_DMA_IN;
  1151. rval = qla2x00_mailbox_command(vha, &mc);
  1152. if (rval != QLA_SUCCESS) {
  1153. if ((mc.mb[0] == MBS_COMMAND_ERROR) &&
  1154. (mc.mb[1] == 0xA)) {
  1155. left += le16_to_cpu(mc.mb[2]) /
  1156. sizeof(struct qla_port_24xx_data);
  1157. goto restart;
  1158. }
  1159. goto out_free;
  1160. }
  1161. left = 0;
  1162. list = kzalloc(dma_size, GFP_KERNEL);
  1163. if (!list) {
  1164. ql_log(ql_log_warn, vha, 0x1140,
  1165. "%s(%ld): failed to allocate node names list "
  1166. "structure.\n", __func__, vha->host_no);
  1167. rval = QLA_MEMORY_ALLOC_FAILED;
  1168. goto out_free;
  1169. }
  1170. memcpy(list, pmap, dma_size);
  1171. restart:
  1172. dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
  1173. }
  1174. *out_data = list;
  1175. *out_len = dma_size;
  1176. out:
  1177. return rval;
  1178. out_free:
  1179. dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
  1180. return rval;
  1181. }
  1182. /*
  1183. * qla2x00_get_port_database
  1184. * Issue normal/enhanced get port database mailbox command
  1185. * and copy device name as necessary.
  1186. *
  1187. * Input:
  1188. * ha = adapter state pointer.
  1189. * dev = structure pointer.
  1190. * opt = enhanced cmd option byte.
  1191. *
  1192. * Returns:
  1193. * qla2x00 local function return status code.
  1194. *
  1195. * Context:
  1196. * Kernel context.
  1197. */
  1198. int
  1199. qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
  1200. {
  1201. int rval;
  1202. mbx_cmd_t mc;
  1203. mbx_cmd_t *mcp = &mc;
  1204. port_database_t *pd;
  1205. struct port_database_24xx *pd24;
  1206. dma_addr_t pd_dma;
  1207. struct qla_hw_data *ha = vha->hw;
  1208. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
  1209. "Entered %s.\n", __func__);
  1210. pd24 = NULL;
  1211. pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
  1212. if (pd == NULL) {
  1213. ql_log(ql_log_warn, vha, 0x1050,
  1214. "Failed to allocate port database structure.\n");
  1215. return QLA_MEMORY_ALLOC_FAILED;
  1216. }
  1217. memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
  1218. mcp->mb[0] = MBC_GET_PORT_DATABASE;
  1219. if (opt != 0 && !IS_FWI2_CAPABLE(ha))
  1220. mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
  1221. mcp->mb[2] = MSW(pd_dma);
  1222. mcp->mb[3] = LSW(pd_dma);
  1223. mcp->mb[6] = MSW(MSD(pd_dma));
  1224. mcp->mb[7] = LSW(MSD(pd_dma));
  1225. mcp->mb[9] = vha->vp_idx;
  1226. mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  1227. mcp->in_mb = MBX_0;
  1228. if (IS_FWI2_CAPABLE(ha)) {
  1229. mcp->mb[1] = fcport->loop_id;
  1230. mcp->mb[10] = opt;
  1231. mcp->out_mb |= MBX_10|MBX_1;
  1232. mcp->in_mb |= MBX_1;
  1233. } else if (HAS_EXTENDED_IDS(ha)) {
  1234. mcp->mb[1] = fcport->loop_id;
  1235. mcp->mb[10] = opt;
  1236. mcp->out_mb |= MBX_10|MBX_1;
  1237. } else {
  1238. mcp->mb[1] = fcport->loop_id << 8 | opt;
  1239. mcp->out_mb |= MBX_1;
  1240. }
  1241. mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
  1242. PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
  1243. mcp->flags = MBX_DMA_IN;
  1244. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1245. rval = qla2x00_mailbox_command(vha, mcp);
  1246. if (rval != QLA_SUCCESS)
  1247. goto gpd_error_out;
  1248. if (IS_FWI2_CAPABLE(ha)) {
  1249. uint64_t zero = 0;
  1250. pd24 = (struct port_database_24xx *) pd;
  1251. /* Check for logged in state. */
  1252. if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
  1253. pd24->last_login_state != PDS_PRLI_COMPLETE) {
  1254. ql_dbg(ql_dbg_mbx, vha, 0x1051,
  1255. "Unable to verify login-state (%x/%x) for "
  1256. "loop_id %x.\n", pd24->current_login_state,
  1257. pd24->last_login_state, fcport->loop_id);
  1258. rval = QLA_FUNCTION_FAILED;
  1259. goto gpd_error_out;
  1260. }
  1261. if (fcport->loop_id == FC_NO_LOOP_ID ||
  1262. (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
  1263. memcmp(fcport->port_name, pd24->port_name, 8))) {
  1264. /* We lost the device mid way. */
  1265. rval = QLA_NOT_LOGGED_IN;
  1266. goto gpd_error_out;
  1267. }
  1268. /* Names are little-endian. */
  1269. memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
  1270. memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
  1271. /* Get port_id of device. */
  1272. fcport->d_id.b.domain = pd24->port_id[0];
  1273. fcport->d_id.b.area = pd24->port_id[1];
  1274. fcport->d_id.b.al_pa = pd24->port_id[2];
  1275. fcport->d_id.b.rsvd_1 = 0;
  1276. /* If not target must be initiator or unknown type. */
  1277. if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
  1278. fcport->port_type = FCT_INITIATOR;
  1279. else
  1280. fcport->port_type = FCT_TARGET;
  1281. /* Passback COS information. */
  1282. fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
  1283. FC_COS_CLASS2 : FC_COS_CLASS3;
  1284. if (pd24->prli_svc_param_word_3[0] & BIT_7)
  1285. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1286. } else {
  1287. uint64_t zero = 0;
  1288. /* Check for logged in state. */
  1289. if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
  1290. pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
  1291. ql_dbg(ql_dbg_mbx, vha, 0x100a,
  1292. "Unable to verify login-state (%x/%x) - "
  1293. "portid=%02x%02x%02x.\n", pd->master_state,
  1294. pd->slave_state, fcport->d_id.b.domain,
  1295. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  1296. rval = QLA_FUNCTION_FAILED;
  1297. goto gpd_error_out;
  1298. }
  1299. if (fcport->loop_id == FC_NO_LOOP_ID ||
  1300. (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
  1301. memcmp(fcport->port_name, pd->port_name, 8))) {
  1302. /* We lost the device mid way. */
  1303. rval = QLA_NOT_LOGGED_IN;
  1304. goto gpd_error_out;
  1305. }
  1306. /* Names are little-endian. */
  1307. memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
  1308. memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
  1309. /* Get port_id of device. */
  1310. fcport->d_id.b.domain = pd->port_id[0];
  1311. fcport->d_id.b.area = pd->port_id[3];
  1312. fcport->d_id.b.al_pa = pd->port_id[2];
  1313. fcport->d_id.b.rsvd_1 = 0;
  1314. /* If not target must be initiator or unknown type. */
  1315. if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
  1316. fcport->port_type = FCT_INITIATOR;
  1317. else
  1318. fcport->port_type = FCT_TARGET;
  1319. /* Passback COS information. */
  1320. fcport->supported_classes = (pd->options & BIT_4) ?
  1321. FC_COS_CLASS2: FC_COS_CLASS3;
  1322. }
  1323. gpd_error_out:
  1324. dma_pool_free(ha->s_dma_pool, pd, pd_dma);
  1325. if (rval != QLA_SUCCESS) {
  1326. ql_dbg(ql_dbg_mbx, vha, 0x1052,
  1327. "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
  1328. mcp->mb[0], mcp->mb[1]);
  1329. } else {
  1330. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
  1331. "Done %s.\n", __func__);
  1332. }
  1333. return rval;
  1334. }
  1335. /*
  1336. * qla2x00_get_firmware_state
  1337. * Get adapter firmware state.
  1338. *
  1339. * Input:
  1340. * ha = adapter block pointer.
  1341. * dptr = pointer for firmware state.
  1342. * TARGET_QUEUE_LOCK must be released.
  1343. * ADAPTER_STATE_LOCK must be released.
  1344. *
  1345. * Returns:
  1346. * qla2x00 local function return status code.
  1347. *
  1348. * Context:
  1349. * Kernel context.
  1350. */
  1351. int
  1352. qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
  1353. {
  1354. int rval;
  1355. mbx_cmd_t mc;
  1356. mbx_cmd_t *mcp = &mc;
  1357. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
  1358. "Entered %s.\n", __func__);
  1359. mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
  1360. mcp->out_mb = MBX_0;
  1361. if (IS_FWI2_CAPABLE(vha->hw))
  1362. mcp->in_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  1363. else
  1364. mcp->in_mb = MBX_1|MBX_0;
  1365. mcp->tov = MBX_TOV_SECONDS;
  1366. mcp->flags = 0;
  1367. rval = qla2x00_mailbox_command(vha, mcp);
  1368. /* Return firmware states. */
  1369. states[0] = mcp->mb[1];
  1370. if (IS_FWI2_CAPABLE(vha->hw)) {
  1371. states[1] = mcp->mb[2];
  1372. states[2] = mcp->mb[3];
  1373. states[3] = mcp->mb[4];
  1374. states[4] = mcp->mb[5];
  1375. }
  1376. if (rval != QLA_SUCCESS) {
  1377. /*EMPTY*/
  1378. ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
  1379. } else {
  1380. /*EMPTY*/
  1381. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
  1382. "Done %s.\n", __func__);
  1383. }
  1384. return rval;
  1385. }
  1386. /*
  1387. * qla2x00_get_port_name
  1388. * Issue get port name mailbox command.
  1389. * Returned name is in big endian format.
  1390. *
  1391. * Input:
  1392. * ha = adapter block pointer.
  1393. * loop_id = loop ID of device.
  1394. * name = pointer for name.
  1395. * TARGET_QUEUE_LOCK must be released.
  1396. * ADAPTER_STATE_LOCK must be released.
  1397. *
  1398. * Returns:
  1399. * qla2x00 local function return status code.
  1400. *
  1401. * Context:
  1402. * Kernel context.
  1403. */
  1404. int
  1405. qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
  1406. uint8_t opt)
  1407. {
  1408. int rval;
  1409. mbx_cmd_t mc;
  1410. mbx_cmd_t *mcp = &mc;
  1411. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
  1412. "Entered %s.\n", __func__);
  1413. mcp->mb[0] = MBC_GET_PORT_NAME;
  1414. mcp->mb[9] = vha->vp_idx;
  1415. mcp->out_mb = MBX_9|MBX_1|MBX_0;
  1416. if (HAS_EXTENDED_IDS(vha->hw)) {
  1417. mcp->mb[1] = loop_id;
  1418. mcp->mb[10] = opt;
  1419. mcp->out_mb |= MBX_10;
  1420. } else {
  1421. mcp->mb[1] = loop_id << 8 | opt;
  1422. }
  1423. mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1424. mcp->tov = MBX_TOV_SECONDS;
  1425. mcp->flags = 0;
  1426. rval = qla2x00_mailbox_command(vha, mcp);
  1427. if (rval != QLA_SUCCESS) {
  1428. /*EMPTY*/
  1429. ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
  1430. } else {
  1431. if (name != NULL) {
  1432. /* This function returns name in big endian. */
  1433. name[0] = MSB(mcp->mb[2]);
  1434. name[1] = LSB(mcp->mb[2]);
  1435. name[2] = MSB(mcp->mb[3]);
  1436. name[3] = LSB(mcp->mb[3]);
  1437. name[4] = MSB(mcp->mb[6]);
  1438. name[5] = LSB(mcp->mb[6]);
  1439. name[6] = MSB(mcp->mb[7]);
  1440. name[7] = LSB(mcp->mb[7]);
  1441. }
  1442. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
  1443. "Done %s.\n", __func__);
  1444. }
  1445. return rval;
  1446. }
  1447. /*
  1448. * qla24xx_link_initialization
  1449. * Issue link initialization mailbox command.
  1450. *
  1451. * Input:
  1452. * ha = adapter block pointer.
  1453. * TARGET_QUEUE_LOCK must be released.
  1454. * ADAPTER_STATE_LOCK must be released.
  1455. *
  1456. * Returns:
  1457. * qla2x00 local function return status code.
  1458. *
  1459. * Context:
  1460. * Kernel context.
  1461. */
  1462. int
  1463. qla24xx_link_initialize(scsi_qla_host_t *vha)
  1464. {
  1465. int rval;
  1466. mbx_cmd_t mc;
  1467. mbx_cmd_t *mcp = &mc;
  1468. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
  1469. "Entered %s.\n", __func__);
  1470. if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
  1471. return QLA_FUNCTION_FAILED;
  1472. mcp->mb[0] = MBC_LINK_INITIALIZATION;
  1473. mcp->mb[1] = BIT_6|BIT_4;
  1474. mcp->mb[2] = 0;
  1475. mcp->mb[3] = 0;
  1476. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1477. mcp->in_mb = MBX_0;
  1478. mcp->tov = MBX_TOV_SECONDS;
  1479. mcp->flags = 0;
  1480. rval = qla2x00_mailbox_command(vha, mcp);
  1481. if (rval != QLA_SUCCESS) {
  1482. ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
  1483. } else {
  1484. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
  1485. "Done %s.\n", __func__);
  1486. }
  1487. return rval;
  1488. }
  1489. /*
  1490. * qla2x00_lip_reset
  1491. * Issue LIP reset mailbox command.
  1492. *
  1493. * Input:
  1494. * ha = adapter block pointer.
  1495. * TARGET_QUEUE_LOCK must be released.
  1496. * ADAPTER_STATE_LOCK must be released.
  1497. *
  1498. * Returns:
  1499. * qla2x00 local function return status code.
  1500. *
  1501. * Context:
  1502. * Kernel context.
  1503. */
  1504. int
  1505. qla2x00_lip_reset(scsi_qla_host_t *vha)
  1506. {
  1507. int rval;
  1508. mbx_cmd_t mc;
  1509. mbx_cmd_t *mcp = &mc;
  1510. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
  1511. "Entered %s.\n", __func__);
  1512. if (IS_CNA_CAPABLE(vha->hw)) {
  1513. /* Logout across all FCFs. */
  1514. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1515. mcp->mb[1] = BIT_1;
  1516. mcp->mb[2] = 0;
  1517. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  1518. } else if (IS_FWI2_CAPABLE(vha->hw)) {
  1519. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1520. mcp->mb[1] = BIT_6;
  1521. mcp->mb[2] = 0;
  1522. mcp->mb[3] = vha->hw->loop_reset_delay;
  1523. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1524. } else {
  1525. mcp->mb[0] = MBC_LIP_RESET;
  1526. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1527. if (HAS_EXTENDED_IDS(vha->hw)) {
  1528. mcp->mb[1] = 0x00ff;
  1529. mcp->mb[10] = 0;
  1530. mcp->out_mb |= MBX_10;
  1531. } else {
  1532. mcp->mb[1] = 0xff00;
  1533. }
  1534. mcp->mb[2] = vha->hw->loop_reset_delay;
  1535. mcp->mb[3] = 0;
  1536. }
  1537. mcp->in_mb = MBX_0;
  1538. mcp->tov = MBX_TOV_SECONDS;
  1539. mcp->flags = 0;
  1540. rval = qla2x00_mailbox_command(vha, mcp);
  1541. if (rval != QLA_SUCCESS) {
  1542. /*EMPTY*/
  1543. ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
  1544. } else {
  1545. /*EMPTY*/
  1546. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
  1547. "Done %s.\n", __func__);
  1548. }
  1549. return rval;
  1550. }
  1551. /*
  1552. * qla2x00_send_sns
  1553. * Send SNS command.
  1554. *
  1555. * Input:
  1556. * ha = adapter block pointer.
  1557. * sns = pointer for command.
  1558. * cmd_size = command size.
  1559. * buf_size = response/command size.
  1560. * TARGET_QUEUE_LOCK must be released.
  1561. * ADAPTER_STATE_LOCK must be released.
  1562. *
  1563. * Returns:
  1564. * qla2x00 local function return status code.
  1565. *
  1566. * Context:
  1567. * Kernel context.
  1568. */
  1569. int
  1570. qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
  1571. uint16_t cmd_size, size_t buf_size)
  1572. {
  1573. int rval;
  1574. mbx_cmd_t mc;
  1575. mbx_cmd_t *mcp = &mc;
  1576. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
  1577. "Entered %s.\n", __func__);
  1578. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
  1579. "Retry cnt=%d ratov=%d total tov=%d.\n",
  1580. vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
  1581. mcp->mb[0] = MBC_SEND_SNS_COMMAND;
  1582. mcp->mb[1] = cmd_size;
  1583. mcp->mb[2] = MSW(sns_phys_address);
  1584. mcp->mb[3] = LSW(sns_phys_address);
  1585. mcp->mb[6] = MSW(MSD(sns_phys_address));
  1586. mcp->mb[7] = LSW(MSD(sns_phys_address));
  1587. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1588. mcp->in_mb = MBX_0|MBX_1;
  1589. mcp->buf_size = buf_size;
  1590. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
  1591. mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
  1592. rval = qla2x00_mailbox_command(vha, mcp);
  1593. if (rval != QLA_SUCCESS) {
  1594. /*EMPTY*/
  1595. ql_dbg(ql_dbg_mbx, vha, 0x105f,
  1596. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  1597. rval, mcp->mb[0], mcp->mb[1]);
  1598. } else {
  1599. /*EMPTY*/
  1600. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
  1601. "Done %s.\n", __func__);
  1602. }
  1603. return rval;
  1604. }
  1605. int
  1606. qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1607. uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
  1608. {
  1609. int rval;
  1610. struct logio_entry_24xx *lg;
  1611. dma_addr_t lg_dma;
  1612. uint32_t iop[2];
  1613. struct qla_hw_data *ha = vha->hw;
  1614. struct req_que *req;
  1615. struct rsp_que *rsp;
  1616. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
  1617. "Entered %s.\n", __func__);
  1618. if (ha->flags.cpu_affinity_enabled)
  1619. req = ha->req_q_map[0];
  1620. else
  1621. req = vha->req;
  1622. rsp = req->rsp;
  1623. lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
  1624. if (lg == NULL) {
  1625. ql_log(ql_log_warn, vha, 0x1062,
  1626. "Failed to allocate login IOCB.\n");
  1627. return QLA_MEMORY_ALLOC_FAILED;
  1628. }
  1629. memset(lg, 0, sizeof(struct logio_entry_24xx));
  1630. lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
  1631. lg->entry_count = 1;
  1632. lg->handle = MAKE_HANDLE(req->id, lg->handle);
  1633. lg->nport_handle = cpu_to_le16(loop_id);
  1634. lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI);
  1635. if (opt & BIT_0)
  1636. lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI);
  1637. if (opt & BIT_1)
  1638. lg->control_flags |= __constant_cpu_to_le16(LCF_SKIP_PRLI);
  1639. lg->port_id[0] = al_pa;
  1640. lg->port_id[1] = area;
  1641. lg->port_id[2] = domain;
  1642. lg->vp_index = vha->vp_idx;
  1643. rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
  1644. (ha->r_a_tov / 10 * 2) + 2);
  1645. if (rval != QLA_SUCCESS) {
  1646. ql_dbg(ql_dbg_mbx, vha, 0x1063,
  1647. "Failed to issue login IOCB (%x).\n", rval);
  1648. } else if (lg->entry_status != 0) {
  1649. ql_dbg(ql_dbg_mbx, vha, 0x1064,
  1650. "Failed to complete IOCB -- error status (%x).\n",
  1651. lg->entry_status);
  1652. rval = QLA_FUNCTION_FAILED;
  1653. } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1654. iop[0] = le32_to_cpu(lg->io_parameter[0]);
  1655. iop[1] = le32_to_cpu(lg->io_parameter[1]);
  1656. ql_dbg(ql_dbg_mbx, vha, 0x1065,
  1657. "Failed to complete IOCB -- completion status (%x) "
  1658. "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
  1659. iop[0], iop[1]);
  1660. switch (iop[0]) {
  1661. case LSC_SCODE_PORTID_USED:
  1662. mb[0] = MBS_PORT_ID_USED;
  1663. mb[1] = LSW(iop[1]);
  1664. break;
  1665. case LSC_SCODE_NPORT_USED:
  1666. mb[0] = MBS_LOOP_ID_USED;
  1667. break;
  1668. case LSC_SCODE_NOLINK:
  1669. case LSC_SCODE_NOIOCB:
  1670. case LSC_SCODE_NOXCB:
  1671. case LSC_SCODE_CMD_FAILED:
  1672. case LSC_SCODE_NOFABRIC:
  1673. case LSC_SCODE_FW_NOT_READY:
  1674. case LSC_SCODE_NOT_LOGGED_IN:
  1675. case LSC_SCODE_NOPCB:
  1676. case LSC_SCODE_ELS_REJECT:
  1677. case LSC_SCODE_CMD_PARAM_ERR:
  1678. case LSC_SCODE_NONPORT:
  1679. case LSC_SCODE_LOGGED_IN:
  1680. case LSC_SCODE_NOFLOGI_ACC:
  1681. default:
  1682. mb[0] = MBS_COMMAND_ERROR;
  1683. break;
  1684. }
  1685. } else {
  1686. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
  1687. "Done %s.\n", __func__);
  1688. iop[0] = le32_to_cpu(lg->io_parameter[0]);
  1689. mb[0] = MBS_COMMAND_COMPLETE;
  1690. mb[1] = 0;
  1691. if (iop[0] & BIT_4) {
  1692. if (iop[0] & BIT_8)
  1693. mb[1] |= BIT_1;
  1694. } else
  1695. mb[1] = BIT_0;
  1696. /* Passback COS information. */
  1697. mb[10] = 0;
  1698. if (lg->io_parameter[7] || lg->io_parameter[8])
  1699. mb[10] |= BIT_0; /* Class 2. */
  1700. if (lg->io_parameter[9] || lg->io_parameter[10])
  1701. mb[10] |= BIT_1; /* Class 3. */
  1702. if (lg->io_parameter[0] & __constant_cpu_to_le32(BIT_7))
  1703. mb[10] |= BIT_7; /* Confirmed Completion
  1704. * Allowed
  1705. */
  1706. }
  1707. dma_pool_free(ha->s_dma_pool, lg, lg_dma);
  1708. return rval;
  1709. }
  1710. /*
  1711. * qla2x00_login_fabric
  1712. * Issue login fabric port mailbox command.
  1713. *
  1714. * Input:
  1715. * ha = adapter block pointer.
  1716. * loop_id = device loop ID.
  1717. * domain = device domain.
  1718. * area = device area.
  1719. * al_pa = device AL_PA.
  1720. * status = pointer for return status.
  1721. * opt = command options.
  1722. * TARGET_QUEUE_LOCK must be released.
  1723. * ADAPTER_STATE_LOCK must be released.
  1724. *
  1725. * Returns:
  1726. * qla2x00 local function return status code.
  1727. *
  1728. * Context:
  1729. * Kernel context.
  1730. */
  1731. int
  1732. qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1733. uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
  1734. {
  1735. int rval;
  1736. mbx_cmd_t mc;
  1737. mbx_cmd_t *mcp = &mc;
  1738. struct qla_hw_data *ha = vha->hw;
  1739. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
  1740. "Entered %s.\n", __func__);
  1741. mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
  1742. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1743. if (HAS_EXTENDED_IDS(ha)) {
  1744. mcp->mb[1] = loop_id;
  1745. mcp->mb[10] = opt;
  1746. mcp->out_mb |= MBX_10;
  1747. } else {
  1748. mcp->mb[1] = (loop_id << 8) | opt;
  1749. }
  1750. mcp->mb[2] = domain;
  1751. mcp->mb[3] = area << 8 | al_pa;
  1752. mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
  1753. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1754. mcp->flags = 0;
  1755. rval = qla2x00_mailbox_command(vha, mcp);
  1756. /* Return mailbox statuses. */
  1757. if (mb != NULL) {
  1758. mb[0] = mcp->mb[0];
  1759. mb[1] = mcp->mb[1];
  1760. mb[2] = mcp->mb[2];
  1761. mb[6] = mcp->mb[6];
  1762. mb[7] = mcp->mb[7];
  1763. /* COS retrieved from Get-Port-Database mailbox command. */
  1764. mb[10] = 0;
  1765. }
  1766. if (rval != QLA_SUCCESS) {
  1767. /* RLU tmp code: need to change main mailbox_command function to
  1768. * return ok even when the mailbox completion value is not
  1769. * SUCCESS. The caller needs to be responsible to interpret
  1770. * the return values of this mailbox command if we're not
  1771. * to change too much of the existing code.
  1772. */
  1773. if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
  1774. mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
  1775. mcp->mb[0] == 0x4006)
  1776. rval = QLA_SUCCESS;
  1777. /*EMPTY*/
  1778. ql_dbg(ql_dbg_mbx, vha, 0x1068,
  1779. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  1780. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  1781. } else {
  1782. /*EMPTY*/
  1783. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
  1784. "Done %s.\n", __func__);
  1785. }
  1786. return rval;
  1787. }
  1788. /*
  1789. * qla2x00_login_local_device
  1790. * Issue login loop port mailbox command.
  1791. *
  1792. * Input:
  1793. * ha = adapter block pointer.
  1794. * loop_id = device loop ID.
  1795. * opt = command options.
  1796. *
  1797. * Returns:
  1798. * Return status code.
  1799. *
  1800. * Context:
  1801. * Kernel context.
  1802. *
  1803. */
  1804. int
  1805. qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
  1806. uint16_t *mb_ret, uint8_t opt)
  1807. {
  1808. int rval;
  1809. mbx_cmd_t mc;
  1810. mbx_cmd_t *mcp = &mc;
  1811. struct qla_hw_data *ha = vha->hw;
  1812. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
  1813. "Entered %s.\n", __func__);
  1814. if (IS_FWI2_CAPABLE(ha))
  1815. return qla24xx_login_fabric(vha, fcport->loop_id,
  1816. fcport->d_id.b.domain, fcport->d_id.b.area,
  1817. fcport->d_id.b.al_pa, mb_ret, opt);
  1818. mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
  1819. if (HAS_EXTENDED_IDS(ha))
  1820. mcp->mb[1] = fcport->loop_id;
  1821. else
  1822. mcp->mb[1] = fcport->loop_id << 8;
  1823. mcp->mb[2] = opt;
  1824. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  1825. mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
  1826. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1827. mcp->flags = 0;
  1828. rval = qla2x00_mailbox_command(vha, mcp);
  1829. /* Return mailbox statuses. */
  1830. if (mb_ret != NULL) {
  1831. mb_ret[0] = mcp->mb[0];
  1832. mb_ret[1] = mcp->mb[1];
  1833. mb_ret[6] = mcp->mb[6];
  1834. mb_ret[7] = mcp->mb[7];
  1835. }
  1836. if (rval != QLA_SUCCESS) {
  1837. /* AV tmp code: need to change main mailbox_command function to
  1838. * return ok even when the mailbox completion value is not
  1839. * SUCCESS. The caller needs to be responsible to interpret
  1840. * the return values of this mailbox command if we're not
  1841. * to change too much of the existing code.
  1842. */
  1843. if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
  1844. rval = QLA_SUCCESS;
  1845. ql_dbg(ql_dbg_mbx, vha, 0x106b,
  1846. "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
  1847. rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
  1848. } else {
  1849. /*EMPTY*/
  1850. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
  1851. "Done %s.\n", __func__);
  1852. }
  1853. return (rval);
  1854. }
  1855. int
  1856. qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1857. uint8_t area, uint8_t al_pa)
  1858. {
  1859. int rval;
  1860. struct logio_entry_24xx *lg;
  1861. dma_addr_t lg_dma;
  1862. struct qla_hw_data *ha = vha->hw;
  1863. struct req_que *req;
  1864. struct rsp_que *rsp;
  1865. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
  1866. "Entered %s.\n", __func__);
  1867. lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
  1868. if (lg == NULL) {
  1869. ql_log(ql_log_warn, vha, 0x106e,
  1870. "Failed to allocate logout IOCB.\n");
  1871. return QLA_MEMORY_ALLOC_FAILED;
  1872. }
  1873. memset(lg, 0, sizeof(struct logio_entry_24xx));
  1874. if (ql2xmaxqueues > 1)
  1875. req = ha->req_q_map[0];
  1876. else
  1877. req = vha->req;
  1878. rsp = req->rsp;
  1879. lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
  1880. lg->entry_count = 1;
  1881. lg->handle = MAKE_HANDLE(req->id, lg->handle);
  1882. lg->nport_handle = cpu_to_le16(loop_id);
  1883. lg->control_flags =
  1884. __constant_cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
  1885. LCF_FREE_NPORT);
  1886. lg->port_id[0] = al_pa;
  1887. lg->port_id[1] = area;
  1888. lg->port_id[2] = domain;
  1889. lg->vp_index = vha->vp_idx;
  1890. rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
  1891. (ha->r_a_tov / 10 * 2) + 2);
  1892. if (rval != QLA_SUCCESS) {
  1893. ql_dbg(ql_dbg_mbx, vha, 0x106f,
  1894. "Failed to issue logout IOCB (%x).\n", rval);
  1895. } else if (lg->entry_status != 0) {
  1896. ql_dbg(ql_dbg_mbx, vha, 0x1070,
  1897. "Failed to complete IOCB -- error status (%x).\n",
  1898. lg->entry_status);
  1899. rval = QLA_FUNCTION_FAILED;
  1900. } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1901. ql_dbg(ql_dbg_mbx, vha, 0x1071,
  1902. "Failed to complete IOCB -- completion status (%x) "
  1903. "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
  1904. le32_to_cpu(lg->io_parameter[0]),
  1905. le32_to_cpu(lg->io_parameter[1]));
  1906. } else {
  1907. /*EMPTY*/
  1908. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
  1909. "Done %s.\n", __func__);
  1910. }
  1911. dma_pool_free(ha->s_dma_pool, lg, lg_dma);
  1912. return rval;
  1913. }
  1914. /*
  1915. * qla2x00_fabric_logout
  1916. * Issue logout fabric port mailbox command.
  1917. *
  1918. * Input:
  1919. * ha = adapter block pointer.
  1920. * loop_id = device loop ID.
  1921. * TARGET_QUEUE_LOCK must be released.
  1922. * ADAPTER_STATE_LOCK must be released.
  1923. *
  1924. * Returns:
  1925. * qla2x00 local function return status code.
  1926. *
  1927. * Context:
  1928. * Kernel context.
  1929. */
  1930. int
  1931. qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1932. uint8_t area, uint8_t al_pa)
  1933. {
  1934. int rval;
  1935. mbx_cmd_t mc;
  1936. mbx_cmd_t *mcp = &mc;
  1937. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
  1938. "Entered %s.\n", __func__);
  1939. mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
  1940. mcp->out_mb = MBX_1|MBX_0;
  1941. if (HAS_EXTENDED_IDS(vha->hw)) {
  1942. mcp->mb[1] = loop_id;
  1943. mcp->mb[10] = 0;
  1944. mcp->out_mb |= MBX_10;
  1945. } else {
  1946. mcp->mb[1] = loop_id << 8;
  1947. }
  1948. mcp->in_mb = MBX_1|MBX_0;
  1949. mcp->tov = MBX_TOV_SECONDS;
  1950. mcp->flags = 0;
  1951. rval = qla2x00_mailbox_command(vha, mcp);
  1952. if (rval != QLA_SUCCESS) {
  1953. /*EMPTY*/
  1954. ql_dbg(ql_dbg_mbx, vha, 0x1074,
  1955. "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
  1956. } else {
  1957. /*EMPTY*/
  1958. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
  1959. "Done %s.\n", __func__);
  1960. }
  1961. return rval;
  1962. }
  1963. /*
  1964. * qla2x00_full_login_lip
  1965. * Issue full login LIP mailbox command.
  1966. *
  1967. * Input:
  1968. * ha = adapter block pointer.
  1969. * TARGET_QUEUE_LOCK must be released.
  1970. * ADAPTER_STATE_LOCK must be released.
  1971. *
  1972. * Returns:
  1973. * qla2x00 local function return status code.
  1974. *
  1975. * Context:
  1976. * Kernel context.
  1977. */
  1978. int
  1979. qla2x00_full_login_lip(scsi_qla_host_t *vha)
  1980. {
  1981. int rval;
  1982. mbx_cmd_t mc;
  1983. mbx_cmd_t *mcp = &mc;
  1984. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
  1985. "Entered %s.\n", __func__);
  1986. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1987. mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
  1988. mcp->mb[2] = 0;
  1989. mcp->mb[3] = 0;
  1990. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1991. mcp->in_mb = MBX_0;
  1992. mcp->tov = MBX_TOV_SECONDS;
  1993. mcp->flags = 0;
  1994. rval = qla2x00_mailbox_command(vha, mcp);
  1995. if (rval != QLA_SUCCESS) {
  1996. /*EMPTY*/
  1997. ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
  1998. } else {
  1999. /*EMPTY*/
  2000. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
  2001. "Done %s.\n", __func__);
  2002. }
  2003. return rval;
  2004. }
  2005. /*
  2006. * qla2x00_get_id_list
  2007. *
  2008. * Input:
  2009. * ha = adapter block pointer.
  2010. *
  2011. * Returns:
  2012. * qla2x00 local function return status code.
  2013. *
  2014. * Context:
  2015. * Kernel context.
  2016. */
  2017. int
  2018. qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
  2019. uint16_t *entries)
  2020. {
  2021. int rval;
  2022. mbx_cmd_t mc;
  2023. mbx_cmd_t *mcp = &mc;
  2024. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
  2025. "Entered %s.\n", __func__);
  2026. if (id_list == NULL)
  2027. return QLA_FUNCTION_FAILED;
  2028. mcp->mb[0] = MBC_GET_ID_LIST;
  2029. mcp->out_mb = MBX_0;
  2030. if (IS_FWI2_CAPABLE(vha->hw)) {
  2031. mcp->mb[2] = MSW(id_list_dma);
  2032. mcp->mb[3] = LSW(id_list_dma);
  2033. mcp->mb[6] = MSW(MSD(id_list_dma));
  2034. mcp->mb[7] = LSW(MSD(id_list_dma));
  2035. mcp->mb[8] = 0;
  2036. mcp->mb[9] = vha->vp_idx;
  2037. mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
  2038. } else {
  2039. mcp->mb[1] = MSW(id_list_dma);
  2040. mcp->mb[2] = LSW(id_list_dma);
  2041. mcp->mb[3] = MSW(MSD(id_list_dma));
  2042. mcp->mb[6] = LSW(MSD(id_list_dma));
  2043. mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
  2044. }
  2045. mcp->in_mb = MBX_1|MBX_0;
  2046. mcp->tov = MBX_TOV_SECONDS;
  2047. mcp->flags = 0;
  2048. rval = qla2x00_mailbox_command(vha, mcp);
  2049. if (rval != QLA_SUCCESS) {
  2050. /*EMPTY*/
  2051. ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
  2052. } else {
  2053. *entries = mcp->mb[1];
  2054. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
  2055. "Done %s.\n", __func__);
  2056. }
  2057. return rval;
  2058. }
  2059. /*
  2060. * qla2x00_get_resource_cnts
  2061. * Get current firmware resource counts.
  2062. *
  2063. * Input:
  2064. * ha = adapter block pointer.
  2065. *
  2066. * Returns:
  2067. * qla2x00 local function return status code.
  2068. *
  2069. * Context:
  2070. * Kernel context.
  2071. */
  2072. int
  2073. qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt,
  2074. uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt,
  2075. uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs)
  2076. {
  2077. int rval;
  2078. mbx_cmd_t mc;
  2079. mbx_cmd_t *mcp = &mc;
  2080. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
  2081. "Entered %s.\n", __func__);
  2082. mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
  2083. mcp->out_mb = MBX_0;
  2084. mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  2085. if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw))
  2086. mcp->in_mb |= MBX_12;
  2087. mcp->tov = MBX_TOV_SECONDS;
  2088. mcp->flags = 0;
  2089. rval = qla2x00_mailbox_command(vha, mcp);
  2090. if (rval != QLA_SUCCESS) {
  2091. /*EMPTY*/
  2092. ql_dbg(ql_dbg_mbx, vha, 0x107d,
  2093. "Failed mb[0]=%x.\n", mcp->mb[0]);
  2094. } else {
  2095. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
  2096. "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
  2097. "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
  2098. mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
  2099. mcp->mb[11], mcp->mb[12]);
  2100. if (cur_xchg_cnt)
  2101. *cur_xchg_cnt = mcp->mb[3];
  2102. if (orig_xchg_cnt)
  2103. *orig_xchg_cnt = mcp->mb[6];
  2104. if (cur_iocb_cnt)
  2105. *cur_iocb_cnt = mcp->mb[7];
  2106. if (orig_iocb_cnt)
  2107. *orig_iocb_cnt = mcp->mb[10];
  2108. if (vha->hw->flags.npiv_supported && max_npiv_vports)
  2109. *max_npiv_vports = mcp->mb[11];
  2110. if ((IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw)) && max_fcfs)
  2111. *max_fcfs = mcp->mb[12];
  2112. }
  2113. return (rval);
  2114. }
  2115. /*
  2116. * qla2x00_get_fcal_position_map
  2117. * Get FCAL (LILP) position map using mailbox command
  2118. *
  2119. * Input:
  2120. * ha = adapter state pointer.
  2121. * pos_map = buffer pointer (can be NULL).
  2122. *
  2123. * Returns:
  2124. * qla2x00 local function return status code.
  2125. *
  2126. * Context:
  2127. * Kernel context.
  2128. */
  2129. int
  2130. qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
  2131. {
  2132. int rval;
  2133. mbx_cmd_t mc;
  2134. mbx_cmd_t *mcp = &mc;
  2135. char *pmap;
  2136. dma_addr_t pmap_dma;
  2137. struct qla_hw_data *ha = vha->hw;
  2138. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
  2139. "Entered %s.\n", __func__);
  2140. pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
  2141. if (pmap == NULL) {
  2142. ql_log(ql_log_warn, vha, 0x1080,
  2143. "Memory alloc failed.\n");
  2144. return QLA_MEMORY_ALLOC_FAILED;
  2145. }
  2146. memset(pmap, 0, FCAL_MAP_SIZE);
  2147. mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
  2148. mcp->mb[2] = MSW(pmap_dma);
  2149. mcp->mb[3] = LSW(pmap_dma);
  2150. mcp->mb[6] = MSW(MSD(pmap_dma));
  2151. mcp->mb[7] = LSW(MSD(pmap_dma));
  2152. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2153. mcp->in_mb = MBX_1|MBX_0;
  2154. mcp->buf_size = FCAL_MAP_SIZE;
  2155. mcp->flags = MBX_DMA_IN;
  2156. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  2157. rval = qla2x00_mailbox_command(vha, mcp);
  2158. if (rval == QLA_SUCCESS) {
  2159. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
  2160. "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
  2161. mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
  2162. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
  2163. pmap, pmap[0] + 1);
  2164. if (pos_map)
  2165. memcpy(pos_map, pmap, FCAL_MAP_SIZE);
  2166. }
  2167. dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
  2168. if (rval != QLA_SUCCESS) {
  2169. ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
  2170. } else {
  2171. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
  2172. "Done %s.\n", __func__);
  2173. }
  2174. return rval;
  2175. }
  2176. /*
  2177. * qla2x00_get_link_status
  2178. *
  2179. * Input:
  2180. * ha = adapter block pointer.
  2181. * loop_id = device loop ID.
  2182. * ret_buf = pointer to link status return buffer.
  2183. *
  2184. * Returns:
  2185. * 0 = success.
  2186. * BIT_0 = mem alloc error.
  2187. * BIT_1 = mailbox error.
  2188. */
  2189. int
  2190. qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
  2191. struct link_statistics *stats, dma_addr_t stats_dma)
  2192. {
  2193. int rval;
  2194. mbx_cmd_t mc;
  2195. mbx_cmd_t *mcp = &mc;
  2196. uint32_t *siter, *diter, dwords;
  2197. struct qla_hw_data *ha = vha->hw;
  2198. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
  2199. "Entered %s.\n", __func__);
  2200. mcp->mb[0] = MBC_GET_LINK_STATUS;
  2201. mcp->mb[2] = MSW(stats_dma);
  2202. mcp->mb[3] = LSW(stats_dma);
  2203. mcp->mb[6] = MSW(MSD(stats_dma));
  2204. mcp->mb[7] = LSW(MSD(stats_dma));
  2205. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2206. mcp->in_mb = MBX_0;
  2207. if (IS_FWI2_CAPABLE(ha)) {
  2208. mcp->mb[1] = loop_id;
  2209. mcp->mb[4] = 0;
  2210. mcp->mb[10] = 0;
  2211. mcp->out_mb |= MBX_10|MBX_4|MBX_1;
  2212. mcp->in_mb |= MBX_1;
  2213. } else if (HAS_EXTENDED_IDS(ha)) {
  2214. mcp->mb[1] = loop_id;
  2215. mcp->mb[10] = 0;
  2216. mcp->out_mb |= MBX_10|MBX_1;
  2217. } else {
  2218. mcp->mb[1] = loop_id << 8;
  2219. mcp->out_mb |= MBX_1;
  2220. }
  2221. mcp->tov = MBX_TOV_SECONDS;
  2222. mcp->flags = IOCTL_CMD;
  2223. rval = qla2x00_mailbox_command(vha, mcp);
  2224. if (rval == QLA_SUCCESS) {
  2225. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2226. ql_dbg(ql_dbg_mbx, vha, 0x1085,
  2227. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2228. rval = QLA_FUNCTION_FAILED;
  2229. } else {
  2230. /* Copy over data -- firmware data is LE. */
  2231. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
  2232. "Done %s.\n", __func__);
  2233. dwords = offsetof(struct link_statistics, unused1) / 4;
  2234. siter = diter = &stats->link_fail_cnt;
  2235. while (dwords--)
  2236. *diter++ = le32_to_cpu(*siter++);
  2237. }
  2238. } else {
  2239. /* Failed. */
  2240. ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
  2241. }
  2242. return rval;
  2243. }
  2244. int
  2245. qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
  2246. dma_addr_t stats_dma)
  2247. {
  2248. int rval;
  2249. mbx_cmd_t mc;
  2250. mbx_cmd_t *mcp = &mc;
  2251. uint32_t *siter, *diter, dwords;
  2252. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
  2253. "Entered %s.\n", __func__);
  2254. mcp->mb[0] = MBC_GET_LINK_PRIV_STATS;
  2255. mcp->mb[2] = MSW(stats_dma);
  2256. mcp->mb[3] = LSW(stats_dma);
  2257. mcp->mb[6] = MSW(MSD(stats_dma));
  2258. mcp->mb[7] = LSW(MSD(stats_dma));
  2259. mcp->mb[8] = sizeof(struct link_statistics) / 4;
  2260. mcp->mb[9] = vha->vp_idx;
  2261. mcp->mb[10] = 0;
  2262. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2263. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  2264. mcp->tov = MBX_TOV_SECONDS;
  2265. mcp->flags = IOCTL_CMD;
  2266. rval = qla2x00_mailbox_command(vha, mcp);
  2267. if (rval == QLA_SUCCESS) {
  2268. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2269. ql_dbg(ql_dbg_mbx, vha, 0x1089,
  2270. "Failed mb[0]=%x.\n", mcp->mb[0]);
  2271. rval = QLA_FUNCTION_FAILED;
  2272. } else {
  2273. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
  2274. "Done %s.\n", __func__);
  2275. /* Copy over data -- firmware data is LE. */
  2276. dwords = sizeof(struct link_statistics) / 4;
  2277. siter = diter = &stats->link_fail_cnt;
  2278. while (dwords--)
  2279. *diter++ = le32_to_cpu(*siter++);
  2280. }
  2281. } else {
  2282. /* Failed. */
  2283. ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
  2284. }
  2285. return rval;
  2286. }
  2287. int
  2288. qla24xx_abort_command(srb_t *sp)
  2289. {
  2290. int rval;
  2291. unsigned long flags = 0;
  2292. struct abort_entry_24xx *abt;
  2293. dma_addr_t abt_dma;
  2294. uint32_t handle;
  2295. fc_port_t *fcport = sp->fcport;
  2296. struct scsi_qla_host *vha = fcport->vha;
  2297. struct qla_hw_data *ha = vha->hw;
  2298. struct req_que *req = vha->req;
  2299. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
  2300. "Entered %s.\n", __func__);
  2301. spin_lock_irqsave(&ha->hardware_lock, flags);
  2302. for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
  2303. if (req->outstanding_cmds[handle] == sp)
  2304. break;
  2305. }
  2306. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2307. if (handle == req->num_outstanding_cmds) {
  2308. /* Command not found. */
  2309. return QLA_FUNCTION_FAILED;
  2310. }
  2311. abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
  2312. if (abt == NULL) {
  2313. ql_log(ql_log_warn, vha, 0x108d,
  2314. "Failed to allocate abort IOCB.\n");
  2315. return QLA_MEMORY_ALLOC_FAILED;
  2316. }
  2317. memset(abt, 0, sizeof(struct abort_entry_24xx));
  2318. abt->entry_type = ABORT_IOCB_TYPE;
  2319. abt->entry_count = 1;
  2320. abt->handle = MAKE_HANDLE(req->id, abt->handle);
  2321. abt->nport_handle = cpu_to_le16(fcport->loop_id);
  2322. abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
  2323. abt->port_id[0] = fcport->d_id.b.al_pa;
  2324. abt->port_id[1] = fcport->d_id.b.area;
  2325. abt->port_id[2] = fcport->d_id.b.domain;
  2326. abt->vp_index = fcport->vha->vp_idx;
  2327. abt->req_que_no = cpu_to_le16(req->id);
  2328. rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
  2329. if (rval != QLA_SUCCESS) {
  2330. ql_dbg(ql_dbg_mbx, vha, 0x108e,
  2331. "Failed to issue IOCB (%x).\n", rval);
  2332. } else if (abt->entry_status != 0) {
  2333. ql_dbg(ql_dbg_mbx, vha, 0x108f,
  2334. "Failed to complete IOCB -- error status (%x).\n",
  2335. abt->entry_status);
  2336. rval = QLA_FUNCTION_FAILED;
  2337. } else if (abt->nport_handle != __constant_cpu_to_le16(0)) {
  2338. ql_dbg(ql_dbg_mbx, vha, 0x1090,
  2339. "Failed to complete IOCB -- completion status (%x).\n",
  2340. le16_to_cpu(abt->nport_handle));
  2341. rval = QLA_FUNCTION_FAILED;
  2342. } else {
  2343. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
  2344. "Done %s.\n", __func__);
  2345. }
  2346. dma_pool_free(ha->s_dma_pool, abt, abt_dma);
  2347. return rval;
  2348. }
  2349. struct tsk_mgmt_cmd {
  2350. union {
  2351. struct tsk_mgmt_entry tsk;
  2352. struct sts_entry_24xx sts;
  2353. } p;
  2354. };
  2355. static int
  2356. __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
  2357. unsigned int l, int tag)
  2358. {
  2359. int rval, rval2;
  2360. struct tsk_mgmt_cmd *tsk;
  2361. struct sts_entry_24xx *sts;
  2362. dma_addr_t tsk_dma;
  2363. scsi_qla_host_t *vha;
  2364. struct qla_hw_data *ha;
  2365. struct req_que *req;
  2366. struct rsp_que *rsp;
  2367. vha = fcport->vha;
  2368. ha = vha->hw;
  2369. req = vha->req;
  2370. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
  2371. "Entered %s.\n", __func__);
  2372. if (ha->flags.cpu_affinity_enabled)
  2373. rsp = ha->rsp_q_map[tag + 1];
  2374. else
  2375. rsp = req->rsp;
  2376. tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
  2377. if (tsk == NULL) {
  2378. ql_log(ql_log_warn, vha, 0x1093,
  2379. "Failed to allocate task management IOCB.\n");
  2380. return QLA_MEMORY_ALLOC_FAILED;
  2381. }
  2382. memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
  2383. tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
  2384. tsk->p.tsk.entry_count = 1;
  2385. tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
  2386. tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
  2387. tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
  2388. tsk->p.tsk.control_flags = cpu_to_le32(type);
  2389. tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
  2390. tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
  2391. tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
  2392. tsk->p.tsk.vp_index = fcport->vha->vp_idx;
  2393. if (type == TCF_LUN_RESET) {
  2394. int_to_scsilun(l, &tsk->p.tsk.lun);
  2395. host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
  2396. sizeof(tsk->p.tsk.lun));
  2397. }
  2398. sts = &tsk->p.sts;
  2399. rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
  2400. if (rval != QLA_SUCCESS) {
  2401. ql_dbg(ql_dbg_mbx, vha, 0x1094,
  2402. "Failed to issue %s reset IOCB (%x).\n", name, rval);
  2403. } else if (sts->entry_status != 0) {
  2404. ql_dbg(ql_dbg_mbx, vha, 0x1095,
  2405. "Failed to complete IOCB -- error status (%x).\n",
  2406. sts->entry_status);
  2407. rval = QLA_FUNCTION_FAILED;
  2408. } else if (sts->comp_status !=
  2409. __constant_cpu_to_le16(CS_COMPLETE)) {
  2410. ql_dbg(ql_dbg_mbx, vha, 0x1096,
  2411. "Failed to complete IOCB -- completion status (%x).\n",
  2412. le16_to_cpu(sts->comp_status));
  2413. rval = QLA_FUNCTION_FAILED;
  2414. } else if (le16_to_cpu(sts->scsi_status) &
  2415. SS_RESPONSE_INFO_LEN_VALID) {
  2416. if (le32_to_cpu(sts->rsp_data_len) < 4) {
  2417. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
  2418. "Ignoring inconsistent data length -- not enough "
  2419. "response info (%d).\n",
  2420. le32_to_cpu(sts->rsp_data_len));
  2421. } else if (sts->data[3]) {
  2422. ql_dbg(ql_dbg_mbx, vha, 0x1098,
  2423. "Failed to complete IOCB -- response (%x).\n",
  2424. sts->data[3]);
  2425. rval = QLA_FUNCTION_FAILED;
  2426. }
  2427. }
  2428. /* Issue marker IOCB. */
  2429. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
  2430. type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
  2431. if (rval2 != QLA_SUCCESS) {
  2432. ql_dbg(ql_dbg_mbx, vha, 0x1099,
  2433. "Failed to issue marker IOCB (%x).\n", rval2);
  2434. } else {
  2435. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
  2436. "Done %s.\n", __func__);
  2437. }
  2438. dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
  2439. return rval;
  2440. }
  2441. int
  2442. qla24xx_abort_target(struct fc_port *fcport, unsigned int l, int tag)
  2443. {
  2444. struct qla_hw_data *ha = fcport->vha->hw;
  2445. if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
  2446. return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
  2447. return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
  2448. }
  2449. int
  2450. qla24xx_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
  2451. {
  2452. struct qla_hw_data *ha = fcport->vha->hw;
  2453. if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
  2454. return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
  2455. return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
  2456. }
  2457. int
  2458. qla2x00_system_error(scsi_qla_host_t *vha)
  2459. {
  2460. int rval;
  2461. mbx_cmd_t mc;
  2462. mbx_cmd_t *mcp = &mc;
  2463. struct qla_hw_data *ha = vha->hw;
  2464. if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
  2465. return QLA_FUNCTION_FAILED;
  2466. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
  2467. "Entered %s.\n", __func__);
  2468. mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
  2469. mcp->out_mb = MBX_0;
  2470. mcp->in_mb = MBX_0;
  2471. mcp->tov = 5;
  2472. mcp->flags = 0;
  2473. rval = qla2x00_mailbox_command(vha, mcp);
  2474. if (rval != QLA_SUCCESS) {
  2475. ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
  2476. } else {
  2477. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
  2478. "Done %s.\n", __func__);
  2479. }
  2480. return rval;
  2481. }
  2482. /**
  2483. * qla2x00_set_serdes_params() -
  2484. * @ha: HA context
  2485. *
  2486. * Returns
  2487. */
  2488. int
  2489. qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
  2490. uint16_t sw_em_2g, uint16_t sw_em_4g)
  2491. {
  2492. int rval;
  2493. mbx_cmd_t mc;
  2494. mbx_cmd_t *mcp = &mc;
  2495. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
  2496. "Entered %s.\n", __func__);
  2497. mcp->mb[0] = MBC_SERDES_PARAMS;
  2498. mcp->mb[1] = BIT_0;
  2499. mcp->mb[2] = sw_em_1g | BIT_15;
  2500. mcp->mb[3] = sw_em_2g | BIT_15;
  2501. mcp->mb[4] = sw_em_4g | BIT_15;
  2502. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2503. mcp->in_mb = MBX_0;
  2504. mcp->tov = MBX_TOV_SECONDS;
  2505. mcp->flags = 0;
  2506. rval = qla2x00_mailbox_command(vha, mcp);
  2507. if (rval != QLA_SUCCESS) {
  2508. /*EMPTY*/
  2509. ql_dbg(ql_dbg_mbx, vha, 0x109f,
  2510. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2511. } else {
  2512. /*EMPTY*/
  2513. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
  2514. "Done %s.\n", __func__);
  2515. }
  2516. return rval;
  2517. }
  2518. int
  2519. qla2x00_stop_firmware(scsi_qla_host_t *vha)
  2520. {
  2521. int rval;
  2522. mbx_cmd_t mc;
  2523. mbx_cmd_t *mcp = &mc;
  2524. if (!IS_FWI2_CAPABLE(vha->hw))
  2525. return QLA_FUNCTION_FAILED;
  2526. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
  2527. "Entered %s.\n", __func__);
  2528. mcp->mb[0] = MBC_STOP_FIRMWARE;
  2529. mcp->mb[1] = 0;
  2530. mcp->out_mb = MBX_1|MBX_0;
  2531. mcp->in_mb = MBX_0;
  2532. mcp->tov = 5;
  2533. mcp->flags = 0;
  2534. rval = qla2x00_mailbox_command(vha, mcp);
  2535. if (rval != QLA_SUCCESS) {
  2536. ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
  2537. if (mcp->mb[0] == MBS_INVALID_COMMAND)
  2538. rval = QLA_INVALID_COMMAND;
  2539. } else {
  2540. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
  2541. "Done %s.\n", __func__);
  2542. }
  2543. return rval;
  2544. }
  2545. int
  2546. qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
  2547. uint16_t buffers)
  2548. {
  2549. int rval;
  2550. mbx_cmd_t mc;
  2551. mbx_cmd_t *mcp = &mc;
  2552. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
  2553. "Entered %s.\n", __func__);
  2554. if (!IS_FWI2_CAPABLE(vha->hw))
  2555. return QLA_FUNCTION_FAILED;
  2556. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2557. return QLA_FUNCTION_FAILED;
  2558. mcp->mb[0] = MBC_TRACE_CONTROL;
  2559. mcp->mb[1] = TC_EFT_ENABLE;
  2560. mcp->mb[2] = LSW(eft_dma);
  2561. mcp->mb[3] = MSW(eft_dma);
  2562. mcp->mb[4] = LSW(MSD(eft_dma));
  2563. mcp->mb[5] = MSW(MSD(eft_dma));
  2564. mcp->mb[6] = buffers;
  2565. mcp->mb[7] = TC_AEN_DISABLE;
  2566. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2567. mcp->in_mb = MBX_1|MBX_0;
  2568. mcp->tov = MBX_TOV_SECONDS;
  2569. mcp->flags = 0;
  2570. rval = qla2x00_mailbox_command(vha, mcp);
  2571. if (rval != QLA_SUCCESS) {
  2572. ql_dbg(ql_dbg_mbx, vha, 0x10a5,
  2573. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2574. rval, mcp->mb[0], mcp->mb[1]);
  2575. } else {
  2576. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
  2577. "Done %s.\n", __func__);
  2578. }
  2579. return rval;
  2580. }
  2581. int
  2582. qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
  2583. {
  2584. int rval;
  2585. mbx_cmd_t mc;
  2586. mbx_cmd_t *mcp = &mc;
  2587. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
  2588. "Entered %s.\n", __func__);
  2589. if (!IS_FWI2_CAPABLE(vha->hw))
  2590. return QLA_FUNCTION_FAILED;
  2591. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2592. return QLA_FUNCTION_FAILED;
  2593. mcp->mb[0] = MBC_TRACE_CONTROL;
  2594. mcp->mb[1] = TC_EFT_DISABLE;
  2595. mcp->out_mb = MBX_1|MBX_0;
  2596. mcp->in_mb = MBX_1|MBX_0;
  2597. mcp->tov = MBX_TOV_SECONDS;
  2598. mcp->flags = 0;
  2599. rval = qla2x00_mailbox_command(vha, mcp);
  2600. if (rval != QLA_SUCCESS) {
  2601. ql_dbg(ql_dbg_mbx, vha, 0x10a8,
  2602. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2603. rval, mcp->mb[0], mcp->mb[1]);
  2604. } else {
  2605. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
  2606. "Done %s.\n", __func__);
  2607. }
  2608. return rval;
  2609. }
  2610. int
  2611. qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
  2612. uint16_t buffers, uint16_t *mb, uint32_t *dwords)
  2613. {
  2614. int rval;
  2615. mbx_cmd_t mc;
  2616. mbx_cmd_t *mcp = &mc;
  2617. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
  2618. "Entered %s.\n", __func__);
  2619. if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
  2620. !IS_QLA83XX(vha->hw))
  2621. return QLA_FUNCTION_FAILED;
  2622. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2623. return QLA_FUNCTION_FAILED;
  2624. mcp->mb[0] = MBC_TRACE_CONTROL;
  2625. mcp->mb[1] = TC_FCE_ENABLE;
  2626. mcp->mb[2] = LSW(fce_dma);
  2627. mcp->mb[3] = MSW(fce_dma);
  2628. mcp->mb[4] = LSW(MSD(fce_dma));
  2629. mcp->mb[5] = MSW(MSD(fce_dma));
  2630. mcp->mb[6] = buffers;
  2631. mcp->mb[7] = TC_AEN_DISABLE;
  2632. mcp->mb[8] = 0;
  2633. mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
  2634. mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
  2635. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
  2636. MBX_1|MBX_0;
  2637. mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2638. mcp->tov = MBX_TOV_SECONDS;
  2639. mcp->flags = 0;
  2640. rval = qla2x00_mailbox_command(vha, mcp);
  2641. if (rval != QLA_SUCCESS) {
  2642. ql_dbg(ql_dbg_mbx, vha, 0x10ab,
  2643. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2644. rval, mcp->mb[0], mcp->mb[1]);
  2645. } else {
  2646. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
  2647. "Done %s.\n", __func__);
  2648. if (mb)
  2649. memcpy(mb, mcp->mb, 8 * sizeof(*mb));
  2650. if (dwords)
  2651. *dwords = buffers;
  2652. }
  2653. return rval;
  2654. }
  2655. int
  2656. qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
  2657. {
  2658. int rval;
  2659. mbx_cmd_t mc;
  2660. mbx_cmd_t *mcp = &mc;
  2661. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
  2662. "Entered %s.\n", __func__);
  2663. if (!IS_FWI2_CAPABLE(vha->hw))
  2664. return QLA_FUNCTION_FAILED;
  2665. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2666. return QLA_FUNCTION_FAILED;
  2667. mcp->mb[0] = MBC_TRACE_CONTROL;
  2668. mcp->mb[1] = TC_FCE_DISABLE;
  2669. mcp->mb[2] = TC_FCE_DISABLE_TRACE;
  2670. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  2671. mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
  2672. MBX_1|MBX_0;
  2673. mcp->tov = MBX_TOV_SECONDS;
  2674. mcp->flags = 0;
  2675. rval = qla2x00_mailbox_command(vha, mcp);
  2676. if (rval != QLA_SUCCESS) {
  2677. ql_dbg(ql_dbg_mbx, vha, 0x10ae,
  2678. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2679. rval, mcp->mb[0], mcp->mb[1]);
  2680. } else {
  2681. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
  2682. "Done %s.\n", __func__);
  2683. if (wr)
  2684. *wr = (uint64_t) mcp->mb[5] << 48 |
  2685. (uint64_t) mcp->mb[4] << 32 |
  2686. (uint64_t) mcp->mb[3] << 16 |
  2687. (uint64_t) mcp->mb[2];
  2688. if (rd)
  2689. *rd = (uint64_t) mcp->mb[9] << 48 |
  2690. (uint64_t) mcp->mb[8] << 32 |
  2691. (uint64_t) mcp->mb[7] << 16 |
  2692. (uint64_t) mcp->mb[6];
  2693. }
  2694. return rval;
  2695. }
  2696. int
  2697. qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
  2698. uint16_t *port_speed, uint16_t *mb)
  2699. {
  2700. int rval;
  2701. mbx_cmd_t mc;
  2702. mbx_cmd_t *mcp = &mc;
  2703. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
  2704. "Entered %s.\n", __func__);
  2705. if (!IS_IIDMA_CAPABLE(vha->hw))
  2706. return QLA_FUNCTION_FAILED;
  2707. mcp->mb[0] = MBC_PORT_PARAMS;
  2708. mcp->mb[1] = loop_id;
  2709. mcp->mb[2] = mcp->mb[3] = 0;
  2710. mcp->mb[9] = vha->vp_idx;
  2711. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  2712. mcp->in_mb = MBX_3|MBX_1|MBX_0;
  2713. mcp->tov = MBX_TOV_SECONDS;
  2714. mcp->flags = 0;
  2715. rval = qla2x00_mailbox_command(vha, mcp);
  2716. /* Return mailbox statuses. */
  2717. if (mb != NULL) {
  2718. mb[0] = mcp->mb[0];
  2719. mb[1] = mcp->mb[1];
  2720. mb[3] = mcp->mb[3];
  2721. }
  2722. if (rval != QLA_SUCCESS) {
  2723. ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
  2724. } else {
  2725. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
  2726. "Done %s.\n", __func__);
  2727. if (port_speed)
  2728. *port_speed = mcp->mb[3];
  2729. }
  2730. return rval;
  2731. }
  2732. int
  2733. qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
  2734. uint16_t port_speed, uint16_t *mb)
  2735. {
  2736. int rval;
  2737. mbx_cmd_t mc;
  2738. mbx_cmd_t *mcp = &mc;
  2739. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
  2740. "Entered %s.\n", __func__);
  2741. if (!IS_IIDMA_CAPABLE(vha->hw))
  2742. return QLA_FUNCTION_FAILED;
  2743. mcp->mb[0] = MBC_PORT_PARAMS;
  2744. mcp->mb[1] = loop_id;
  2745. mcp->mb[2] = BIT_0;
  2746. if (IS_CNA_CAPABLE(vha->hw))
  2747. mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
  2748. else
  2749. mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
  2750. mcp->mb[9] = vha->vp_idx;
  2751. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  2752. mcp->in_mb = MBX_3|MBX_1|MBX_0;
  2753. mcp->tov = MBX_TOV_SECONDS;
  2754. mcp->flags = 0;
  2755. rval = qla2x00_mailbox_command(vha, mcp);
  2756. /* Return mailbox statuses. */
  2757. if (mb != NULL) {
  2758. mb[0] = mcp->mb[0];
  2759. mb[1] = mcp->mb[1];
  2760. mb[3] = mcp->mb[3];
  2761. }
  2762. if (rval != QLA_SUCCESS) {
  2763. ql_dbg(ql_dbg_mbx, vha, 0x10b4,
  2764. "Failed=%x.\n", rval);
  2765. } else {
  2766. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
  2767. "Done %s.\n", __func__);
  2768. }
  2769. return rval;
  2770. }
  2771. void
  2772. qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
  2773. struct vp_rpt_id_entry_24xx *rptid_entry)
  2774. {
  2775. uint8_t vp_idx;
  2776. uint16_t stat = le16_to_cpu(rptid_entry->vp_idx);
  2777. struct qla_hw_data *ha = vha->hw;
  2778. scsi_qla_host_t *vp;
  2779. unsigned long flags;
  2780. int found;
  2781. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
  2782. "Entered %s.\n", __func__);
  2783. if (rptid_entry->entry_status != 0)
  2784. return;
  2785. if (rptid_entry->format == 0) {
  2786. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7,
  2787. "Format 0 : Number of VPs setup %d, number of "
  2788. "VPs acquired %d.\n",
  2789. MSB(le16_to_cpu(rptid_entry->vp_count)),
  2790. LSB(le16_to_cpu(rptid_entry->vp_count)));
  2791. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8,
  2792. "Primary port id %02x%02x%02x.\n",
  2793. rptid_entry->port_id[2], rptid_entry->port_id[1],
  2794. rptid_entry->port_id[0]);
  2795. } else if (rptid_entry->format == 1) {
  2796. vp_idx = LSB(stat);
  2797. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9,
  2798. "Format 1: VP[%d] enabled - status %d - with "
  2799. "port id %02x%02x%02x.\n", vp_idx, MSB(stat),
  2800. rptid_entry->port_id[2], rptid_entry->port_id[1],
  2801. rptid_entry->port_id[0]);
  2802. vp = vha;
  2803. if (vp_idx == 0 && (MSB(stat) != 1))
  2804. goto reg_needed;
  2805. if (MSB(stat) != 0 && MSB(stat) != 2) {
  2806. ql_dbg(ql_dbg_mbx, vha, 0x10ba,
  2807. "Could not acquire ID for VP[%d].\n", vp_idx);
  2808. return;
  2809. }
  2810. found = 0;
  2811. spin_lock_irqsave(&ha->vport_slock, flags);
  2812. list_for_each_entry(vp, &ha->vp_list, list) {
  2813. if (vp_idx == vp->vp_idx) {
  2814. found = 1;
  2815. break;
  2816. }
  2817. }
  2818. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2819. if (!found)
  2820. return;
  2821. vp->d_id.b.domain = rptid_entry->port_id[2];
  2822. vp->d_id.b.area = rptid_entry->port_id[1];
  2823. vp->d_id.b.al_pa = rptid_entry->port_id[0];
  2824. /*
  2825. * Cannot configure here as we are still sitting on the
  2826. * response queue. Handle it in dpc context.
  2827. */
  2828. set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
  2829. reg_needed:
  2830. set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
  2831. set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
  2832. set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
  2833. qla2xxx_wake_dpc(vha);
  2834. }
  2835. }
  2836. /*
  2837. * qla24xx_modify_vp_config
  2838. * Change VP configuration for vha
  2839. *
  2840. * Input:
  2841. * vha = adapter block pointer.
  2842. *
  2843. * Returns:
  2844. * qla2xxx local function return status code.
  2845. *
  2846. * Context:
  2847. * Kernel context.
  2848. */
  2849. int
  2850. qla24xx_modify_vp_config(scsi_qla_host_t *vha)
  2851. {
  2852. int rval;
  2853. struct vp_config_entry_24xx *vpmod;
  2854. dma_addr_t vpmod_dma;
  2855. struct qla_hw_data *ha = vha->hw;
  2856. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2857. /* This can be called by the parent */
  2858. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
  2859. "Entered %s.\n", __func__);
  2860. vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
  2861. if (!vpmod) {
  2862. ql_log(ql_log_warn, vha, 0x10bc,
  2863. "Failed to allocate modify VP IOCB.\n");
  2864. return QLA_MEMORY_ALLOC_FAILED;
  2865. }
  2866. memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
  2867. vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
  2868. vpmod->entry_count = 1;
  2869. vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
  2870. vpmod->vp_count = 1;
  2871. vpmod->vp_index1 = vha->vp_idx;
  2872. vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
  2873. qlt_modify_vp_config(vha, vpmod);
  2874. memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
  2875. memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
  2876. vpmod->entry_count = 1;
  2877. rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
  2878. if (rval != QLA_SUCCESS) {
  2879. ql_dbg(ql_dbg_mbx, vha, 0x10bd,
  2880. "Failed to issue VP config IOCB (%x).\n", rval);
  2881. } else if (vpmod->comp_status != 0) {
  2882. ql_dbg(ql_dbg_mbx, vha, 0x10be,
  2883. "Failed to complete IOCB -- error status (%x).\n",
  2884. vpmod->comp_status);
  2885. rval = QLA_FUNCTION_FAILED;
  2886. } else if (vpmod->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  2887. ql_dbg(ql_dbg_mbx, vha, 0x10bf,
  2888. "Failed to complete IOCB -- completion status (%x).\n",
  2889. le16_to_cpu(vpmod->comp_status));
  2890. rval = QLA_FUNCTION_FAILED;
  2891. } else {
  2892. /* EMPTY */
  2893. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
  2894. "Done %s.\n", __func__);
  2895. fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
  2896. }
  2897. dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
  2898. return rval;
  2899. }
  2900. /*
  2901. * qla24xx_control_vp
  2902. * Enable a virtual port for given host
  2903. *
  2904. * Input:
  2905. * ha = adapter block pointer.
  2906. * vhba = virtual adapter (unused)
  2907. * index = index number for enabled VP
  2908. *
  2909. * Returns:
  2910. * qla2xxx local function return status code.
  2911. *
  2912. * Context:
  2913. * Kernel context.
  2914. */
  2915. int
  2916. qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
  2917. {
  2918. int rval;
  2919. int map, pos;
  2920. struct vp_ctrl_entry_24xx *vce;
  2921. dma_addr_t vce_dma;
  2922. struct qla_hw_data *ha = vha->hw;
  2923. int vp_index = vha->vp_idx;
  2924. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2925. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1,
  2926. "Entered %s enabling index %d.\n", __func__, vp_index);
  2927. if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
  2928. return QLA_PARAMETER_ERROR;
  2929. vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
  2930. if (!vce) {
  2931. ql_log(ql_log_warn, vha, 0x10c2,
  2932. "Failed to allocate VP control IOCB.\n");
  2933. return QLA_MEMORY_ALLOC_FAILED;
  2934. }
  2935. memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
  2936. vce->entry_type = VP_CTRL_IOCB_TYPE;
  2937. vce->entry_count = 1;
  2938. vce->command = cpu_to_le16(cmd);
  2939. vce->vp_count = __constant_cpu_to_le16(1);
  2940. /* index map in firmware starts with 1; decrement index
  2941. * this is ok as we never use index 0
  2942. */
  2943. map = (vp_index - 1) / 8;
  2944. pos = (vp_index - 1) & 7;
  2945. mutex_lock(&ha->vport_lock);
  2946. vce->vp_idx_map[map] |= 1 << pos;
  2947. mutex_unlock(&ha->vport_lock);
  2948. rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
  2949. if (rval != QLA_SUCCESS) {
  2950. ql_dbg(ql_dbg_mbx, vha, 0x10c3,
  2951. "Failed to issue VP control IOCB (%x).\n", rval);
  2952. } else if (vce->entry_status != 0) {
  2953. ql_dbg(ql_dbg_mbx, vha, 0x10c4,
  2954. "Failed to complete IOCB -- error status (%x).\n",
  2955. vce->entry_status);
  2956. rval = QLA_FUNCTION_FAILED;
  2957. } else if (vce->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  2958. ql_dbg(ql_dbg_mbx, vha, 0x10c5,
  2959. "Failed to complet IOCB -- completion status (%x).\n",
  2960. le16_to_cpu(vce->comp_status));
  2961. rval = QLA_FUNCTION_FAILED;
  2962. } else {
  2963. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6,
  2964. "Done %s.\n", __func__);
  2965. }
  2966. dma_pool_free(ha->s_dma_pool, vce, vce_dma);
  2967. return rval;
  2968. }
  2969. /*
  2970. * qla2x00_send_change_request
  2971. * Receive or disable RSCN request from fabric controller
  2972. *
  2973. * Input:
  2974. * ha = adapter block pointer
  2975. * format = registration format:
  2976. * 0 - Reserved
  2977. * 1 - Fabric detected registration
  2978. * 2 - N_port detected registration
  2979. * 3 - Full registration
  2980. * FF - clear registration
  2981. * vp_idx = Virtual port index
  2982. *
  2983. * Returns:
  2984. * qla2x00 local function return status code.
  2985. *
  2986. * Context:
  2987. * Kernel Context
  2988. */
  2989. int
  2990. qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
  2991. uint16_t vp_idx)
  2992. {
  2993. int rval;
  2994. mbx_cmd_t mc;
  2995. mbx_cmd_t *mcp = &mc;
  2996. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
  2997. "Entered %s.\n", __func__);
  2998. mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
  2999. mcp->mb[1] = format;
  3000. mcp->mb[9] = vp_idx;
  3001. mcp->out_mb = MBX_9|MBX_1|MBX_0;
  3002. mcp->in_mb = MBX_0|MBX_1;
  3003. mcp->tov = MBX_TOV_SECONDS;
  3004. mcp->flags = 0;
  3005. rval = qla2x00_mailbox_command(vha, mcp);
  3006. if (rval == QLA_SUCCESS) {
  3007. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  3008. rval = BIT_1;
  3009. }
  3010. } else
  3011. rval = BIT_1;
  3012. return rval;
  3013. }
  3014. int
  3015. qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
  3016. uint32_t size)
  3017. {
  3018. int rval;
  3019. mbx_cmd_t mc;
  3020. mbx_cmd_t *mcp = &mc;
  3021. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
  3022. "Entered %s.\n", __func__);
  3023. if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
  3024. mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
  3025. mcp->mb[8] = MSW(addr);
  3026. mcp->out_mb = MBX_8|MBX_0;
  3027. } else {
  3028. mcp->mb[0] = MBC_DUMP_RISC_RAM;
  3029. mcp->out_mb = MBX_0;
  3030. }
  3031. mcp->mb[1] = LSW(addr);
  3032. mcp->mb[2] = MSW(req_dma);
  3033. mcp->mb[3] = LSW(req_dma);
  3034. mcp->mb[6] = MSW(MSD(req_dma));
  3035. mcp->mb[7] = LSW(MSD(req_dma));
  3036. mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
  3037. if (IS_FWI2_CAPABLE(vha->hw)) {
  3038. mcp->mb[4] = MSW(size);
  3039. mcp->mb[5] = LSW(size);
  3040. mcp->out_mb |= MBX_5|MBX_4;
  3041. } else {
  3042. mcp->mb[4] = LSW(size);
  3043. mcp->out_mb |= MBX_4;
  3044. }
  3045. mcp->in_mb = MBX_0;
  3046. mcp->tov = MBX_TOV_SECONDS;
  3047. mcp->flags = 0;
  3048. rval = qla2x00_mailbox_command(vha, mcp);
  3049. if (rval != QLA_SUCCESS) {
  3050. ql_dbg(ql_dbg_mbx, vha, 0x1008,
  3051. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3052. } else {
  3053. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
  3054. "Done %s.\n", __func__);
  3055. }
  3056. return rval;
  3057. }
  3058. /* 84XX Support **************************************************************/
  3059. struct cs84xx_mgmt_cmd {
  3060. union {
  3061. struct verify_chip_entry_84xx req;
  3062. struct verify_chip_rsp_84xx rsp;
  3063. } p;
  3064. };
  3065. int
  3066. qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
  3067. {
  3068. int rval, retry;
  3069. struct cs84xx_mgmt_cmd *mn;
  3070. dma_addr_t mn_dma;
  3071. uint16_t options;
  3072. unsigned long flags;
  3073. struct qla_hw_data *ha = vha->hw;
  3074. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
  3075. "Entered %s.\n", __func__);
  3076. mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
  3077. if (mn == NULL) {
  3078. return QLA_MEMORY_ALLOC_FAILED;
  3079. }
  3080. /* Force Update? */
  3081. options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
  3082. /* Diagnostic firmware? */
  3083. /* options |= MENLO_DIAG_FW; */
  3084. /* We update the firmware with only one data sequence. */
  3085. options |= VCO_END_OF_DATA;
  3086. do {
  3087. retry = 0;
  3088. memset(mn, 0, sizeof(*mn));
  3089. mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
  3090. mn->p.req.entry_count = 1;
  3091. mn->p.req.options = cpu_to_le16(options);
  3092. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
  3093. "Dump of Verify Request.\n");
  3094. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
  3095. (uint8_t *)mn, sizeof(*mn));
  3096. rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
  3097. if (rval != QLA_SUCCESS) {
  3098. ql_dbg(ql_dbg_mbx, vha, 0x10cb,
  3099. "Failed to issue verify IOCB (%x).\n", rval);
  3100. goto verify_done;
  3101. }
  3102. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
  3103. "Dump of Verify Response.\n");
  3104. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
  3105. (uint8_t *)mn, sizeof(*mn));
  3106. status[0] = le16_to_cpu(mn->p.rsp.comp_status);
  3107. status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
  3108. le16_to_cpu(mn->p.rsp.failure_code) : 0;
  3109. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
  3110. "cs=%x fc=%x.\n", status[0], status[1]);
  3111. if (status[0] != CS_COMPLETE) {
  3112. rval = QLA_FUNCTION_FAILED;
  3113. if (!(options & VCO_DONT_UPDATE_FW)) {
  3114. ql_dbg(ql_dbg_mbx, vha, 0x10cf,
  3115. "Firmware update failed. Retrying "
  3116. "without update firmware.\n");
  3117. options |= VCO_DONT_UPDATE_FW;
  3118. options &= ~VCO_FORCE_UPDATE;
  3119. retry = 1;
  3120. }
  3121. } else {
  3122. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
  3123. "Firmware updated to %x.\n",
  3124. le32_to_cpu(mn->p.rsp.fw_ver));
  3125. /* NOTE: we only update OP firmware. */
  3126. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  3127. ha->cs84xx->op_fw_version =
  3128. le32_to_cpu(mn->p.rsp.fw_ver);
  3129. spin_unlock_irqrestore(&ha->cs84xx->access_lock,
  3130. flags);
  3131. }
  3132. } while (retry);
  3133. verify_done:
  3134. dma_pool_free(ha->s_dma_pool, mn, mn_dma);
  3135. if (rval != QLA_SUCCESS) {
  3136. ql_dbg(ql_dbg_mbx, vha, 0x10d1,
  3137. "Failed=%x.\n", rval);
  3138. } else {
  3139. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
  3140. "Done %s.\n", __func__);
  3141. }
  3142. return rval;
  3143. }
  3144. int
  3145. qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
  3146. {
  3147. int rval;
  3148. unsigned long flags;
  3149. mbx_cmd_t mc;
  3150. mbx_cmd_t *mcp = &mc;
  3151. struct device_reg_25xxmq __iomem *reg;
  3152. struct qla_hw_data *ha = vha->hw;
  3153. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
  3154. "Entered %s.\n", __func__);
  3155. mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
  3156. mcp->mb[1] = req->options;
  3157. mcp->mb[2] = MSW(LSD(req->dma));
  3158. mcp->mb[3] = LSW(LSD(req->dma));
  3159. mcp->mb[6] = MSW(MSD(req->dma));
  3160. mcp->mb[7] = LSW(MSD(req->dma));
  3161. mcp->mb[5] = req->length;
  3162. if (req->rsp)
  3163. mcp->mb[10] = req->rsp->id;
  3164. mcp->mb[12] = req->qos;
  3165. mcp->mb[11] = req->vp_idx;
  3166. mcp->mb[13] = req->rid;
  3167. if (IS_QLA83XX(ha))
  3168. mcp->mb[15] = 0;
  3169. reg = (struct device_reg_25xxmq __iomem *)((ha->mqiobase) +
  3170. QLA_QUE_PAGE * req->id);
  3171. mcp->mb[4] = req->id;
  3172. /* que in ptr index */
  3173. mcp->mb[8] = 0;
  3174. /* que out ptr index */
  3175. mcp->mb[9] = 0;
  3176. mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
  3177. MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3178. mcp->in_mb = MBX_0;
  3179. mcp->flags = MBX_DMA_OUT;
  3180. mcp->tov = MBX_TOV_SECONDS * 2;
  3181. if (IS_QLA81XX(ha) || IS_QLA83XX(ha))
  3182. mcp->in_mb |= MBX_1;
  3183. if (IS_QLA83XX(ha)) {
  3184. mcp->out_mb |= MBX_15;
  3185. /* debug q create issue in SR-IOV */
  3186. mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
  3187. }
  3188. spin_lock_irqsave(&ha->hardware_lock, flags);
  3189. if (!(req->options & BIT_0)) {
  3190. WRT_REG_DWORD(&reg->req_q_in, 0);
  3191. if (!IS_QLA83XX(ha))
  3192. WRT_REG_DWORD(&reg->req_q_out, 0);
  3193. }
  3194. req->req_q_in = &reg->req_q_in;
  3195. req->req_q_out = &reg->req_q_out;
  3196. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3197. rval = qla2x00_mailbox_command(vha, mcp);
  3198. if (rval != QLA_SUCCESS) {
  3199. ql_dbg(ql_dbg_mbx, vha, 0x10d4,
  3200. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3201. } else {
  3202. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
  3203. "Done %s.\n", __func__);
  3204. }
  3205. return rval;
  3206. }
  3207. int
  3208. qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
  3209. {
  3210. int rval;
  3211. unsigned long flags;
  3212. mbx_cmd_t mc;
  3213. mbx_cmd_t *mcp = &mc;
  3214. struct device_reg_25xxmq __iomem *reg;
  3215. struct qla_hw_data *ha = vha->hw;
  3216. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
  3217. "Entered %s.\n", __func__);
  3218. mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
  3219. mcp->mb[1] = rsp->options;
  3220. mcp->mb[2] = MSW(LSD(rsp->dma));
  3221. mcp->mb[3] = LSW(LSD(rsp->dma));
  3222. mcp->mb[6] = MSW(MSD(rsp->dma));
  3223. mcp->mb[7] = LSW(MSD(rsp->dma));
  3224. mcp->mb[5] = rsp->length;
  3225. mcp->mb[14] = rsp->msix->entry;
  3226. mcp->mb[13] = rsp->rid;
  3227. if (IS_QLA83XX(ha))
  3228. mcp->mb[15] = 0;
  3229. reg = (struct device_reg_25xxmq __iomem *)((ha->mqiobase) +
  3230. QLA_QUE_PAGE * rsp->id);
  3231. mcp->mb[4] = rsp->id;
  3232. /* que in ptr index */
  3233. mcp->mb[8] = 0;
  3234. /* que out ptr index */
  3235. mcp->mb[9] = 0;
  3236. mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
  3237. |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3238. mcp->in_mb = MBX_0;
  3239. mcp->flags = MBX_DMA_OUT;
  3240. mcp->tov = MBX_TOV_SECONDS * 2;
  3241. if (IS_QLA81XX(ha)) {
  3242. mcp->out_mb |= MBX_12|MBX_11|MBX_10;
  3243. mcp->in_mb |= MBX_1;
  3244. } else if (IS_QLA83XX(ha)) {
  3245. mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
  3246. mcp->in_mb |= MBX_1;
  3247. /* debug q create issue in SR-IOV */
  3248. mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
  3249. }
  3250. spin_lock_irqsave(&ha->hardware_lock, flags);
  3251. if (!(rsp->options & BIT_0)) {
  3252. WRT_REG_DWORD(&reg->rsp_q_out, 0);
  3253. if (!IS_QLA83XX(ha))
  3254. WRT_REG_DWORD(&reg->rsp_q_in, 0);
  3255. }
  3256. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3257. rval = qla2x00_mailbox_command(vha, mcp);
  3258. if (rval != QLA_SUCCESS) {
  3259. ql_dbg(ql_dbg_mbx, vha, 0x10d7,
  3260. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3261. } else {
  3262. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
  3263. "Done %s.\n", __func__);
  3264. }
  3265. return rval;
  3266. }
  3267. int
  3268. qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
  3269. {
  3270. int rval;
  3271. mbx_cmd_t mc;
  3272. mbx_cmd_t *mcp = &mc;
  3273. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
  3274. "Entered %s.\n", __func__);
  3275. mcp->mb[0] = MBC_IDC_ACK;
  3276. memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
  3277. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3278. mcp->in_mb = MBX_0;
  3279. mcp->tov = MBX_TOV_SECONDS;
  3280. mcp->flags = 0;
  3281. rval = qla2x00_mailbox_command(vha, mcp);
  3282. if (rval != QLA_SUCCESS) {
  3283. ql_dbg(ql_dbg_mbx, vha, 0x10da,
  3284. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3285. } else {
  3286. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
  3287. "Done %s.\n", __func__);
  3288. }
  3289. return rval;
  3290. }
  3291. int
  3292. qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
  3293. {
  3294. int rval;
  3295. mbx_cmd_t mc;
  3296. mbx_cmd_t *mcp = &mc;
  3297. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
  3298. "Entered %s.\n", __func__);
  3299. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
  3300. return QLA_FUNCTION_FAILED;
  3301. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3302. mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
  3303. mcp->out_mb = MBX_1|MBX_0;
  3304. mcp->in_mb = MBX_1|MBX_0;
  3305. mcp->tov = MBX_TOV_SECONDS;
  3306. mcp->flags = 0;
  3307. rval = qla2x00_mailbox_command(vha, mcp);
  3308. if (rval != QLA_SUCCESS) {
  3309. ql_dbg(ql_dbg_mbx, vha, 0x10dd,
  3310. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3311. rval, mcp->mb[0], mcp->mb[1]);
  3312. } else {
  3313. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
  3314. "Done %s.\n", __func__);
  3315. *sector_size = mcp->mb[1];
  3316. }
  3317. return rval;
  3318. }
  3319. int
  3320. qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
  3321. {
  3322. int rval;
  3323. mbx_cmd_t mc;
  3324. mbx_cmd_t *mcp = &mc;
  3325. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
  3326. return QLA_FUNCTION_FAILED;
  3327. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
  3328. "Entered %s.\n", __func__);
  3329. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3330. mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
  3331. FAC_OPT_CMD_WRITE_PROTECT;
  3332. mcp->out_mb = MBX_1|MBX_0;
  3333. mcp->in_mb = MBX_1|MBX_0;
  3334. mcp->tov = MBX_TOV_SECONDS;
  3335. mcp->flags = 0;
  3336. rval = qla2x00_mailbox_command(vha, mcp);
  3337. if (rval != QLA_SUCCESS) {
  3338. ql_dbg(ql_dbg_mbx, vha, 0x10e0,
  3339. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3340. rval, mcp->mb[0], mcp->mb[1]);
  3341. } else {
  3342. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
  3343. "Done %s.\n", __func__);
  3344. }
  3345. return rval;
  3346. }
  3347. int
  3348. qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
  3349. {
  3350. int rval;
  3351. mbx_cmd_t mc;
  3352. mbx_cmd_t *mcp = &mc;
  3353. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
  3354. return QLA_FUNCTION_FAILED;
  3355. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
  3356. "Entered %s.\n", __func__);
  3357. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3358. mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
  3359. mcp->mb[2] = LSW(start);
  3360. mcp->mb[3] = MSW(start);
  3361. mcp->mb[4] = LSW(finish);
  3362. mcp->mb[5] = MSW(finish);
  3363. mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3364. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3365. mcp->tov = MBX_TOV_SECONDS;
  3366. mcp->flags = 0;
  3367. rval = qla2x00_mailbox_command(vha, mcp);
  3368. if (rval != QLA_SUCCESS) {
  3369. ql_dbg(ql_dbg_mbx, vha, 0x10e3,
  3370. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3371. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3372. } else {
  3373. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
  3374. "Done %s.\n", __func__);
  3375. }
  3376. return rval;
  3377. }
  3378. int
  3379. qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
  3380. {
  3381. int rval = 0;
  3382. mbx_cmd_t mc;
  3383. mbx_cmd_t *mcp = &mc;
  3384. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
  3385. "Entered %s.\n", __func__);
  3386. mcp->mb[0] = MBC_RESTART_MPI_FW;
  3387. mcp->out_mb = MBX_0;
  3388. mcp->in_mb = MBX_0|MBX_1;
  3389. mcp->tov = MBX_TOV_SECONDS;
  3390. mcp->flags = 0;
  3391. rval = qla2x00_mailbox_command(vha, mcp);
  3392. if (rval != QLA_SUCCESS) {
  3393. ql_dbg(ql_dbg_mbx, vha, 0x10e6,
  3394. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3395. rval, mcp->mb[0], mcp->mb[1]);
  3396. } else {
  3397. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
  3398. "Done %s.\n", __func__);
  3399. }
  3400. return rval;
  3401. }
  3402. int
  3403. qla2x00_set_driver_version(scsi_qla_host_t *vha, char *version)
  3404. {
  3405. int rval;
  3406. mbx_cmd_t mc;
  3407. mbx_cmd_t *mcp = &mc;
  3408. int len;
  3409. uint16_t dwlen;
  3410. uint8_t *str;
  3411. dma_addr_t str_dma;
  3412. struct qla_hw_data *ha = vha->hw;
  3413. if (!IS_FWI2_CAPABLE(ha) || IS_QLA82XX(ha))
  3414. return QLA_FUNCTION_FAILED;
  3415. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1155,
  3416. "Entered %s.\n", __func__);
  3417. str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma);
  3418. if (!str) {
  3419. ql_log(ql_log_warn, vha, 0x1156,
  3420. "Failed to allocate driver version param.\n");
  3421. return QLA_MEMORY_ALLOC_FAILED;
  3422. }
  3423. memcpy(str, "\x7\x3\x11\x0", 4);
  3424. dwlen = str[0];
  3425. len = dwlen * sizeof(uint32_t) - 4;
  3426. memset(str + 4, 0, len);
  3427. if (len > strlen(version))
  3428. len = strlen(version);
  3429. memcpy(str + 4, version, len);
  3430. mcp->mb[0] = MBC_SET_RNID_PARAMS;
  3431. mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen;
  3432. mcp->mb[2] = MSW(LSD(str_dma));
  3433. mcp->mb[3] = LSW(LSD(str_dma));
  3434. mcp->mb[6] = MSW(MSD(str_dma));
  3435. mcp->mb[7] = LSW(MSD(str_dma));
  3436. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3437. mcp->in_mb = MBX_0;
  3438. mcp->tov = MBX_TOV_SECONDS;
  3439. mcp->flags = 0;
  3440. rval = qla2x00_mailbox_command(vha, mcp);
  3441. if (rval != QLA_SUCCESS) {
  3442. ql_dbg(ql_dbg_mbx, vha, 0x1157,
  3443. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3444. } else {
  3445. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1158,
  3446. "Done %s.\n", __func__);
  3447. }
  3448. dma_pool_free(ha->s_dma_pool, str, str_dma);
  3449. return rval;
  3450. }
  3451. static int
  3452. qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
  3453. {
  3454. int rval;
  3455. mbx_cmd_t mc;
  3456. mbx_cmd_t *mcp = &mc;
  3457. if (!IS_FWI2_CAPABLE(vha->hw))
  3458. return QLA_FUNCTION_FAILED;
  3459. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
  3460. "Entered %s.\n", __func__);
  3461. mcp->mb[0] = MBC_GET_RNID_PARAMS;
  3462. mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
  3463. mcp->out_mb = MBX_1|MBX_0;
  3464. mcp->in_mb = MBX_1|MBX_0;
  3465. mcp->tov = MBX_TOV_SECONDS;
  3466. mcp->flags = 0;
  3467. rval = qla2x00_mailbox_command(vha, mcp);
  3468. *temp = mcp->mb[1];
  3469. if (rval != QLA_SUCCESS) {
  3470. ql_dbg(ql_dbg_mbx, vha, 0x115a,
  3471. "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
  3472. } else {
  3473. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
  3474. "Done %s.\n", __func__);
  3475. }
  3476. return rval;
  3477. }
  3478. int
  3479. qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
  3480. uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
  3481. {
  3482. int rval;
  3483. mbx_cmd_t mc;
  3484. mbx_cmd_t *mcp = &mc;
  3485. struct qla_hw_data *ha = vha->hw;
  3486. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
  3487. "Entered %s.\n", __func__);
  3488. if (!IS_FWI2_CAPABLE(ha))
  3489. return QLA_FUNCTION_FAILED;
  3490. if (len == 1)
  3491. opt |= BIT_0;
  3492. mcp->mb[0] = MBC_READ_SFP;
  3493. mcp->mb[1] = dev;
  3494. mcp->mb[2] = MSW(sfp_dma);
  3495. mcp->mb[3] = LSW(sfp_dma);
  3496. mcp->mb[6] = MSW(MSD(sfp_dma));
  3497. mcp->mb[7] = LSW(MSD(sfp_dma));
  3498. mcp->mb[8] = len;
  3499. mcp->mb[9] = off;
  3500. mcp->mb[10] = opt;
  3501. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3502. mcp->in_mb = MBX_1|MBX_0;
  3503. mcp->tov = MBX_TOV_SECONDS;
  3504. mcp->flags = 0;
  3505. rval = qla2x00_mailbox_command(vha, mcp);
  3506. if (opt & BIT_0)
  3507. *sfp = mcp->mb[1];
  3508. if (rval != QLA_SUCCESS) {
  3509. ql_dbg(ql_dbg_mbx, vha, 0x10e9,
  3510. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3511. } else {
  3512. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
  3513. "Done %s.\n", __func__);
  3514. }
  3515. return rval;
  3516. }
  3517. int
  3518. qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
  3519. uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
  3520. {
  3521. int rval;
  3522. mbx_cmd_t mc;
  3523. mbx_cmd_t *mcp = &mc;
  3524. struct qla_hw_data *ha = vha->hw;
  3525. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
  3526. "Entered %s.\n", __func__);
  3527. if (!IS_FWI2_CAPABLE(ha))
  3528. return QLA_FUNCTION_FAILED;
  3529. if (len == 1)
  3530. opt |= BIT_0;
  3531. if (opt & BIT_0)
  3532. len = *sfp;
  3533. mcp->mb[0] = MBC_WRITE_SFP;
  3534. mcp->mb[1] = dev;
  3535. mcp->mb[2] = MSW(sfp_dma);
  3536. mcp->mb[3] = LSW(sfp_dma);
  3537. mcp->mb[6] = MSW(MSD(sfp_dma));
  3538. mcp->mb[7] = LSW(MSD(sfp_dma));
  3539. mcp->mb[8] = len;
  3540. mcp->mb[9] = off;
  3541. mcp->mb[10] = opt;
  3542. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3543. mcp->in_mb = MBX_1|MBX_0;
  3544. mcp->tov = MBX_TOV_SECONDS;
  3545. mcp->flags = 0;
  3546. rval = qla2x00_mailbox_command(vha, mcp);
  3547. if (rval != QLA_SUCCESS) {
  3548. ql_dbg(ql_dbg_mbx, vha, 0x10ec,
  3549. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3550. } else {
  3551. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
  3552. "Done %s.\n", __func__);
  3553. }
  3554. return rval;
  3555. }
  3556. int
  3557. qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
  3558. uint16_t size_in_bytes, uint16_t *actual_size)
  3559. {
  3560. int rval;
  3561. mbx_cmd_t mc;
  3562. mbx_cmd_t *mcp = &mc;
  3563. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
  3564. "Entered %s.\n", __func__);
  3565. if (!IS_CNA_CAPABLE(vha->hw))
  3566. return QLA_FUNCTION_FAILED;
  3567. mcp->mb[0] = MBC_GET_XGMAC_STATS;
  3568. mcp->mb[2] = MSW(stats_dma);
  3569. mcp->mb[3] = LSW(stats_dma);
  3570. mcp->mb[6] = MSW(MSD(stats_dma));
  3571. mcp->mb[7] = LSW(MSD(stats_dma));
  3572. mcp->mb[8] = size_in_bytes >> 2;
  3573. mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  3574. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3575. mcp->tov = MBX_TOV_SECONDS;
  3576. mcp->flags = 0;
  3577. rval = qla2x00_mailbox_command(vha, mcp);
  3578. if (rval != QLA_SUCCESS) {
  3579. ql_dbg(ql_dbg_mbx, vha, 0x10ef,
  3580. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3581. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3582. } else {
  3583. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
  3584. "Done %s.\n", __func__);
  3585. *actual_size = mcp->mb[2] << 2;
  3586. }
  3587. return rval;
  3588. }
  3589. int
  3590. qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
  3591. uint16_t size)
  3592. {
  3593. int rval;
  3594. mbx_cmd_t mc;
  3595. mbx_cmd_t *mcp = &mc;
  3596. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
  3597. "Entered %s.\n", __func__);
  3598. if (!IS_CNA_CAPABLE(vha->hw))
  3599. return QLA_FUNCTION_FAILED;
  3600. mcp->mb[0] = MBC_GET_DCBX_PARAMS;
  3601. mcp->mb[1] = 0;
  3602. mcp->mb[2] = MSW(tlv_dma);
  3603. mcp->mb[3] = LSW(tlv_dma);
  3604. mcp->mb[6] = MSW(MSD(tlv_dma));
  3605. mcp->mb[7] = LSW(MSD(tlv_dma));
  3606. mcp->mb[8] = size;
  3607. mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3608. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3609. mcp->tov = MBX_TOV_SECONDS;
  3610. mcp->flags = 0;
  3611. rval = qla2x00_mailbox_command(vha, mcp);
  3612. if (rval != QLA_SUCCESS) {
  3613. ql_dbg(ql_dbg_mbx, vha, 0x10f2,
  3614. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3615. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3616. } else {
  3617. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
  3618. "Done %s.\n", __func__);
  3619. }
  3620. return rval;
  3621. }
  3622. int
  3623. qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
  3624. {
  3625. int rval;
  3626. mbx_cmd_t mc;
  3627. mbx_cmd_t *mcp = &mc;
  3628. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
  3629. "Entered %s.\n", __func__);
  3630. if (!IS_FWI2_CAPABLE(vha->hw))
  3631. return QLA_FUNCTION_FAILED;
  3632. mcp->mb[0] = MBC_READ_RAM_EXTENDED;
  3633. mcp->mb[1] = LSW(risc_addr);
  3634. mcp->mb[8] = MSW(risc_addr);
  3635. mcp->out_mb = MBX_8|MBX_1|MBX_0;
  3636. mcp->in_mb = MBX_3|MBX_2|MBX_0;
  3637. mcp->tov = 30;
  3638. mcp->flags = 0;
  3639. rval = qla2x00_mailbox_command(vha, mcp);
  3640. if (rval != QLA_SUCCESS) {
  3641. ql_dbg(ql_dbg_mbx, vha, 0x10f5,
  3642. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3643. } else {
  3644. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
  3645. "Done %s.\n", __func__);
  3646. *data = mcp->mb[3] << 16 | mcp->mb[2];
  3647. }
  3648. return rval;
  3649. }
  3650. int
  3651. qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
  3652. uint16_t *mresp)
  3653. {
  3654. int rval;
  3655. mbx_cmd_t mc;
  3656. mbx_cmd_t *mcp = &mc;
  3657. uint32_t iter_cnt = 0x1;
  3658. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
  3659. "Entered %s.\n", __func__);
  3660. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3661. mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
  3662. mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
  3663. /* transfer count */
  3664. mcp->mb[10] = LSW(mreq->transfer_size);
  3665. mcp->mb[11] = MSW(mreq->transfer_size);
  3666. /* send data address */
  3667. mcp->mb[14] = LSW(mreq->send_dma);
  3668. mcp->mb[15] = MSW(mreq->send_dma);
  3669. mcp->mb[20] = LSW(MSD(mreq->send_dma));
  3670. mcp->mb[21] = MSW(MSD(mreq->send_dma));
  3671. /* receive data address */
  3672. mcp->mb[16] = LSW(mreq->rcv_dma);
  3673. mcp->mb[17] = MSW(mreq->rcv_dma);
  3674. mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
  3675. mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
  3676. /* Iteration count */
  3677. mcp->mb[18] = LSW(iter_cnt);
  3678. mcp->mb[19] = MSW(iter_cnt);
  3679. mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
  3680. MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
  3681. if (IS_CNA_CAPABLE(vha->hw))
  3682. mcp->out_mb |= MBX_2;
  3683. mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
  3684. mcp->buf_size = mreq->transfer_size;
  3685. mcp->tov = MBX_TOV_SECONDS;
  3686. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3687. rval = qla2x00_mailbox_command(vha, mcp);
  3688. if (rval != QLA_SUCCESS) {
  3689. ql_dbg(ql_dbg_mbx, vha, 0x10f8,
  3690. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
  3691. "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
  3692. mcp->mb[3], mcp->mb[18], mcp->mb[19]);
  3693. } else {
  3694. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
  3695. "Done %s.\n", __func__);
  3696. }
  3697. /* Copy mailbox information */
  3698. memcpy( mresp, mcp->mb, 64);
  3699. return rval;
  3700. }
  3701. int
  3702. qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
  3703. uint16_t *mresp)
  3704. {
  3705. int rval;
  3706. mbx_cmd_t mc;
  3707. mbx_cmd_t *mcp = &mc;
  3708. struct qla_hw_data *ha = vha->hw;
  3709. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
  3710. "Entered %s.\n", __func__);
  3711. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3712. mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
  3713. mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */
  3714. if (IS_CNA_CAPABLE(ha)) {
  3715. mcp->mb[1] |= BIT_15;
  3716. mcp->mb[2] = vha->fcoe_fcf_idx;
  3717. }
  3718. mcp->mb[16] = LSW(mreq->rcv_dma);
  3719. mcp->mb[17] = MSW(mreq->rcv_dma);
  3720. mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
  3721. mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
  3722. mcp->mb[10] = LSW(mreq->transfer_size);
  3723. mcp->mb[14] = LSW(mreq->send_dma);
  3724. mcp->mb[15] = MSW(mreq->send_dma);
  3725. mcp->mb[20] = LSW(MSD(mreq->send_dma));
  3726. mcp->mb[21] = MSW(MSD(mreq->send_dma));
  3727. mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
  3728. MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
  3729. if (IS_CNA_CAPABLE(ha))
  3730. mcp->out_mb |= MBX_2;
  3731. mcp->in_mb = MBX_0;
  3732. if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
  3733. IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
  3734. mcp->in_mb |= MBX_1;
  3735. if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
  3736. mcp->in_mb |= MBX_3;
  3737. mcp->tov = MBX_TOV_SECONDS;
  3738. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3739. mcp->buf_size = mreq->transfer_size;
  3740. rval = qla2x00_mailbox_command(vha, mcp);
  3741. if (rval != QLA_SUCCESS) {
  3742. ql_dbg(ql_dbg_mbx, vha, 0x10fb,
  3743. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3744. rval, mcp->mb[0], mcp->mb[1]);
  3745. } else {
  3746. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
  3747. "Done %s.\n", __func__);
  3748. }
  3749. /* Copy mailbox information */
  3750. memcpy(mresp, mcp->mb, 64);
  3751. return rval;
  3752. }
  3753. int
  3754. qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
  3755. {
  3756. int rval;
  3757. mbx_cmd_t mc;
  3758. mbx_cmd_t *mcp = &mc;
  3759. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
  3760. "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
  3761. mcp->mb[0] = MBC_ISP84XX_RESET;
  3762. mcp->mb[1] = enable_diagnostic;
  3763. mcp->out_mb = MBX_1|MBX_0;
  3764. mcp->in_mb = MBX_1|MBX_0;
  3765. mcp->tov = MBX_TOV_SECONDS;
  3766. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3767. rval = qla2x00_mailbox_command(vha, mcp);
  3768. if (rval != QLA_SUCCESS)
  3769. ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
  3770. else
  3771. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
  3772. "Done %s.\n", __func__);
  3773. return rval;
  3774. }
  3775. int
  3776. qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
  3777. {
  3778. int rval;
  3779. mbx_cmd_t mc;
  3780. mbx_cmd_t *mcp = &mc;
  3781. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
  3782. "Entered %s.\n", __func__);
  3783. if (!IS_FWI2_CAPABLE(vha->hw))
  3784. return QLA_FUNCTION_FAILED;
  3785. mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
  3786. mcp->mb[1] = LSW(risc_addr);
  3787. mcp->mb[2] = LSW(data);
  3788. mcp->mb[3] = MSW(data);
  3789. mcp->mb[8] = MSW(risc_addr);
  3790. mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
  3791. mcp->in_mb = MBX_0;
  3792. mcp->tov = 30;
  3793. mcp->flags = 0;
  3794. rval = qla2x00_mailbox_command(vha, mcp);
  3795. if (rval != QLA_SUCCESS) {
  3796. ql_dbg(ql_dbg_mbx, vha, 0x1101,
  3797. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3798. } else {
  3799. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
  3800. "Done %s.\n", __func__);
  3801. }
  3802. return rval;
  3803. }
  3804. int
  3805. qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
  3806. {
  3807. int rval;
  3808. uint32_t stat, timer;
  3809. uint16_t mb0 = 0;
  3810. struct qla_hw_data *ha = vha->hw;
  3811. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  3812. rval = QLA_SUCCESS;
  3813. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
  3814. "Entered %s.\n", __func__);
  3815. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  3816. /* Write the MBC data to the registers */
  3817. WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
  3818. WRT_REG_WORD(&reg->mailbox1, mb[0]);
  3819. WRT_REG_WORD(&reg->mailbox2, mb[1]);
  3820. WRT_REG_WORD(&reg->mailbox3, mb[2]);
  3821. WRT_REG_WORD(&reg->mailbox4, mb[3]);
  3822. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
  3823. /* Poll for MBC interrupt */
  3824. for (timer = 6000000; timer; timer--) {
  3825. /* Check for pending interrupts. */
  3826. stat = RD_REG_DWORD(&reg->host_status);
  3827. if (stat & HSRX_RISC_INT) {
  3828. stat &= 0xff;
  3829. if (stat == 0x1 || stat == 0x2 ||
  3830. stat == 0x10 || stat == 0x11) {
  3831. set_bit(MBX_INTERRUPT,
  3832. &ha->mbx_cmd_flags);
  3833. mb0 = RD_REG_WORD(&reg->mailbox0);
  3834. WRT_REG_DWORD(&reg->hccr,
  3835. HCCRX_CLR_RISC_INT);
  3836. RD_REG_DWORD(&reg->hccr);
  3837. break;
  3838. }
  3839. }
  3840. udelay(5);
  3841. }
  3842. if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
  3843. rval = mb0 & MBS_MASK;
  3844. else
  3845. rval = QLA_FUNCTION_FAILED;
  3846. if (rval != QLA_SUCCESS) {
  3847. ql_dbg(ql_dbg_mbx, vha, 0x1104,
  3848. "Failed=%x mb[0]=%x.\n", rval, mb[0]);
  3849. } else {
  3850. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
  3851. "Done %s.\n", __func__);
  3852. }
  3853. return rval;
  3854. }
  3855. int
  3856. qla2x00_get_data_rate(scsi_qla_host_t *vha)
  3857. {
  3858. int rval;
  3859. mbx_cmd_t mc;
  3860. mbx_cmd_t *mcp = &mc;
  3861. struct qla_hw_data *ha = vha->hw;
  3862. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
  3863. "Entered %s.\n", __func__);
  3864. if (!IS_FWI2_CAPABLE(ha))
  3865. return QLA_FUNCTION_FAILED;
  3866. mcp->mb[0] = MBC_DATA_RATE;
  3867. mcp->mb[1] = 0;
  3868. mcp->out_mb = MBX_1|MBX_0;
  3869. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3870. if (IS_QLA83XX(ha))
  3871. mcp->in_mb |= MBX_3;
  3872. mcp->tov = MBX_TOV_SECONDS;
  3873. mcp->flags = 0;
  3874. rval = qla2x00_mailbox_command(vha, mcp);
  3875. if (rval != QLA_SUCCESS) {
  3876. ql_dbg(ql_dbg_mbx, vha, 0x1107,
  3877. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3878. } else {
  3879. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
  3880. "Done %s.\n", __func__);
  3881. if (mcp->mb[1] != 0x7)
  3882. ha->link_data_rate = mcp->mb[1];
  3883. }
  3884. return rval;
  3885. }
  3886. int
  3887. qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
  3888. {
  3889. int rval;
  3890. mbx_cmd_t mc;
  3891. mbx_cmd_t *mcp = &mc;
  3892. struct qla_hw_data *ha = vha->hw;
  3893. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
  3894. "Entered %s.\n", __func__);
  3895. if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha))
  3896. return QLA_FUNCTION_FAILED;
  3897. mcp->mb[0] = MBC_GET_PORT_CONFIG;
  3898. mcp->out_mb = MBX_0;
  3899. mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3900. mcp->tov = MBX_TOV_SECONDS;
  3901. mcp->flags = 0;
  3902. rval = qla2x00_mailbox_command(vha, mcp);
  3903. if (rval != QLA_SUCCESS) {
  3904. ql_dbg(ql_dbg_mbx, vha, 0x110a,
  3905. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3906. } else {
  3907. /* Copy all bits to preserve original value */
  3908. memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
  3909. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
  3910. "Done %s.\n", __func__);
  3911. }
  3912. return rval;
  3913. }
  3914. int
  3915. qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
  3916. {
  3917. int rval;
  3918. mbx_cmd_t mc;
  3919. mbx_cmd_t *mcp = &mc;
  3920. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
  3921. "Entered %s.\n", __func__);
  3922. mcp->mb[0] = MBC_SET_PORT_CONFIG;
  3923. /* Copy all bits to preserve original setting */
  3924. memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
  3925. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3926. mcp->in_mb = MBX_0;
  3927. mcp->tov = MBX_TOV_SECONDS;
  3928. mcp->flags = 0;
  3929. rval = qla2x00_mailbox_command(vha, mcp);
  3930. if (rval != QLA_SUCCESS) {
  3931. ql_dbg(ql_dbg_mbx, vha, 0x110d,
  3932. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3933. } else
  3934. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
  3935. "Done %s.\n", __func__);
  3936. return rval;
  3937. }
  3938. int
  3939. qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
  3940. uint16_t *mb)
  3941. {
  3942. int rval;
  3943. mbx_cmd_t mc;
  3944. mbx_cmd_t *mcp = &mc;
  3945. struct qla_hw_data *ha = vha->hw;
  3946. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
  3947. "Entered %s.\n", __func__);
  3948. if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
  3949. return QLA_FUNCTION_FAILED;
  3950. mcp->mb[0] = MBC_PORT_PARAMS;
  3951. mcp->mb[1] = loop_id;
  3952. if (ha->flags.fcp_prio_enabled)
  3953. mcp->mb[2] = BIT_1;
  3954. else
  3955. mcp->mb[2] = BIT_2;
  3956. mcp->mb[4] = priority & 0xf;
  3957. mcp->mb[9] = vha->vp_idx;
  3958. mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3959. mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
  3960. mcp->tov = 30;
  3961. mcp->flags = 0;
  3962. rval = qla2x00_mailbox_command(vha, mcp);
  3963. if (mb != NULL) {
  3964. mb[0] = mcp->mb[0];
  3965. mb[1] = mcp->mb[1];
  3966. mb[3] = mcp->mb[3];
  3967. mb[4] = mcp->mb[4];
  3968. }
  3969. if (rval != QLA_SUCCESS) {
  3970. ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
  3971. } else {
  3972. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
  3973. "Done %s.\n", __func__);
  3974. }
  3975. return rval;
  3976. }
  3977. int
  3978. qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
  3979. {
  3980. int rval = QLA_FUNCTION_FAILED;
  3981. struct qla_hw_data *ha = vha->hw;
  3982. uint8_t byte;
  3983. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ca,
  3984. "Entered %s.\n", __func__);
  3985. if (ha->thermal_support & THERMAL_SUPPORT_I2C) {
  3986. rval = qla2x00_read_sfp(vha, 0, &byte,
  3987. 0x98, 0x1, 1, BIT_13|BIT_12|BIT_0);
  3988. *temp = byte;
  3989. if (rval == QLA_SUCCESS)
  3990. goto done;
  3991. ql_log(ql_log_warn, vha, 0x10c9,
  3992. "Thermal not supported by I2C.\n");
  3993. ha->thermal_support &= ~THERMAL_SUPPORT_I2C;
  3994. }
  3995. if (ha->thermal_support & THERMAL_SUPPORT_ISP) {
  3996. rval = qla2x00_read_asic_temperature(vha, temp);
  3997. if (rval == QLA_SUCCESS)
  3998. goto done;
  3999. ql_log(ql_log_warn, vha, 0x1019,
  4000. "Thermal not supported by ISP.\n");
  4001. ha->thermal_support &= ~THERMAL_SUPPORT_ISP;
  4002. }
  4003. ql_log(ql_log_warn, vha, 0x1150,
  4004. "Thermal not supported by this card "
  4005. "(ignoring further requests).\n");
  4006. return rval;
  4007. done:
  4008. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1018,
  4009. "Done %s.\n", __func__);
  4010. return rval;
  4011. }
  4012. int
  4013. qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
  4014. {
  4015. int rval;
  4016. struct qla_hw_data *ha = vha->hw;
  4017. mbx_cmd_t mc;
  4018. mbx_cmd_t *mcp = &mc;
  4019. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
  4020. "Entered %s.\n", __func__);
  4021. if (!IS_FWI2_CAPABLE(ha))
  4022. return QLA_FUNCTION_FAILED;
  4023. memset(mcp, 0, sizeof(mbx_cmd_t));
  4024. mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
  4025. mcp->mb[1] = 1;
  4026. mcp->out_mb = MBX_1|MBX_0;
  4027. mcp->in_mb = MBX_0;
  4028. mcp->tov = 30;
  4029. mcp->flags = 0;
  4030. rval = qla2x00_mailbox_command(vha, mcp);
  4031. if (rval != QLA_SUCCESS) {
  4032. ql_dbg(ql_dbg_mbx, vha, 0x1016,
  4033. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4034. } else {
  4035. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
  4036. "Done %s.\n", __func__);
  4037. }
  4038. return rval;
  4039. }
  4040. int
  4041. qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
  4042. {
  4043. int rval;
  4044. struct qla_hw_data *ha = vha->hw;
  4045. mbx_cmd_t mc;
  4046. mbx_cmd_t *mcp = &mc;
  4047. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
  4048. "Entered %s.\n", __func__);
  4049. if (!IS_QLA82XX(ha))
  4050. return QLA_FUNCTION_FAILED;
  4051. memset(mcp, 0, sizeof(mbx_cmd_t));
  4052. mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
  4053. mcp->mb[1] = 0;
  4054. mcp->out_mb = MBX_1|MBX_0;
  4055. mcp->in_mb = MBX_0;
  4056. mcp->tov = 30;
  4057. mcp->flags = 0;
  4058. rval = qla2x00_mailbox_command(vha, mcp);
  4059. if (rval != QLA_SUCCESS) {
  4060. ql_dbg(ql_dbg_mbx, vha, 0x100c,
  4061. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4062. } else {
  4063. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
  4064. "Done %s.\n", __func__);
  4065. }
  4066. return rval;
  4067. }
  4068. int
  4069. qla82xx_md_get_template_size(scsi_qla_host_t *vha)
  4070. {
  4071. struct qla_hw_data *ha = vha->hw;
  4072. mbx_cmd_t mc;
  4073. mbx_cmd_t *mcp = &mc;
  4074. int rval = QLA_FUNCTION_FAILED;
  4075. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
  4076. "Entered %s.\n", __func__);
  4077. memset(mcp->mb, 0 , sizeof(mcp->mb));
  4078. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4079. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4080. mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
  4081. mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
  4082. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  4083. mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  4084. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4085. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  4086. mcp->tov = MBX_TOV_SECONDS;
  4087. rval = qla2x00_mailbox_command(vha, mcp);
  4088. /* Always copy back return mailbox values. */
  4089. if (rval != QLA_SUCCESS) {
  4090. ql_dbg(ql_dbg_mbx, vha, 0x1120,
  4091. "mailbox command FAILED=0x%x, subcode=%x.\n",
  4092. (mcp->mb[1] << 16) | mcp->mb[0],
  4093. (mcp->mb[3] << 16) | mcp->mb[2]);
  4094. } else {
  4095. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
  4096. "Done %s.\n", __func__);
  4097. ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
  4098. if (!ha->md_template_size) {
  4099. ql_dbg(ql_dbg_mbx, vha, 0x1122,
  4100. "Null template size obtained.\n");
  4101. rval = QLA_FUNCTION_FAILED;
  4102. }
  4103. }
  4104. return rval;
  4105. }
  4106. int
  4107. qla82xx_md_get_template(scsi_qla_host_t *vha)
  4108. {
  4109. struct qla_hw_data *ha = vha->hw;
  4110. mbx_cmd_t mc;
  4111. mbx_cmd_t *mcp = &mc;
  4112. int rval = QLA_FUNCTION_FAILED;
  4113. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
  4114. "Entered %s.\n", __func__);
  4115. ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
  4116. ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
  4117. if (!ha->md_tmplt_hdr) {
  4118. ql_log(ql_log_warn, vha, 0x1124,
  4119. "Unable to allocate memory for Minidump template.\n");
  4120. return rval;
  4121. }
  4122. memset(mcp->mb, 0 , sizeof(mcp->mb));
  4123. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4124. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4125. mcp->mb[2] = LSW(RQST_TMPLT);
  4126. mcp->mb[3] = MSW(RQST_TMPLT);
  4127. mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
  4128. mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
  4129. mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
  4130. mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
  4131. mcp->mb[8] = LSW(ha->md_template_size);
  4132. mcp->mb[9] = MSW(ha->md_template_size);
  4133. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  4134. mcp->tov = MBX_TOV_SECONDS;
  4135. mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
  4136. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4137. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  4138. rval = qla2x00_mailbox_command(vha, mcp);
  4139. if (rval != QLA_SUCCESS) {
  4140. ql_dbg(ql_dbg_mbx, vha, 0x1125,
  4141. "mailbox command FAILED=0x%x, subcode=%x.\n",
  4142. ((mcp->mb[1] << 16) | mcp->mb[0]),
  4143. ((mcp->mb[3] << 16) | mcp->mb[2]));
  4144. } else
  4145. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
  4146. "Done %s.\n", __func__);
  4147. return rval;
  4148. }
  4149. int
  4150. qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
  4151. {
  4152. int rval;
  4153. struct qla_hw_data *ha = vha->hw;
  4154. mbx_cmd_t mc;
  4155. mbx_cmd_t *mcp = &mc;
  4156. if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
  4157. return QLA_FUNCTION_FAILED;
  4158. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
  4159. "Entered %s.\n", __func__);
  4160. memset(mcp, 0, sizeof(mbx_cmd_t));
  4161. mcp->mb[0] = MBC_SET_LED_CONFIG;
  4162. mcp->mb[1] = led_cfg[0];
  4163. mcp->mb[2] = led_cfg[1];
  4164. if (IS_QLA8031(ha)) {
  4165. mcp->mb[3] = led_cfg[2];
  4166. mcp->mb[4] = led_cfg[3];
  4167. mcp->mb[5] = led_cfg[4];
  4168. mcp->mb[6] = led_cfg[5];
  4169. }
  4170. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  4171. if (IS_QLA8031(ha))
  4172. mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
  4173. mcp->in_mb = MBX_0;
  4174. mcp->tov = 30;
  4175. mcp->flags = 0;
  4176. rval = qla2x00_mailbox_command(vha, mcp);
  4177. if (rval != QLA_SUCCESS) {
  4178. ql_dbg(ql_dbg_mbx, vha, 0x1134,
  4179. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4180. } else {
  4181. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
  4182. "Done %s.\n", __func__);
  4183. }
  4184. return rval;
  4185. }
  4186. int
  4187. qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
  4188. {
  4189. int rval;
  4190. struct qla_hw_data *ha = vha->hw;
  4191. mbx_cmd_t mc;
  4192. mbx_cmd_t *mcp = &mc;
  4193. if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
  4194. return QLA_FUNCTION_FAILED;
  4195. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
  4196. "Entered %s.\n", __func__);
  4197. memset(mcp, 0, sizeof(mbx_cmd_t));
  4198. mcp->mb[0] = MBC_GET_LED_CONFIG;
  4199. mcp->out_mb = MBX_0;
  4200. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  4201. if (IS_QLA8031(ha))
  4202. mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
  4203. mcp->tov = 30;
  4204. mcp->flags = 0;
  4205. rval = qla2x00_mailbox_command(vha, mcp);
  4206. if (rval != QLA_SUCCESS) {
  4207. ql_dbg(ql_dbg_mbx, vha, 0x1137,
  4208. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4209. } else {
  4210. led_cfg[0] = mcp->mb[1];
  4211. led_cfg[1] = mcp->mb[2];
  4212. if (IS_QLA8031(ha)) {
  4213. led_cfg[2] = mcp->mb[3];
  4214. led_cfg[3] = mcp->mb[4];
  4215. led_cfg[4] = mcp->mb[5];
  4216. led_cfg[5] = mcp->mb[6];
  4217. }
  4218. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
  4219. "Done %s.\n", __func__);
  4220. }
  4221. return rval;
  4222. }
  4223. int
  4224. qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
  4225. {
  4226. int rval;
  4227. struct qla_hw_data *ha = vha->hw;
  4228. mbx_cmd_t mc;
  4229. mbx_cmd_t *mcp = &mc;
  4230. if (!IS_QLA82XX(ha))
  4231. return QLA_FUNCTION_FAILED;
  4232. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
  4233. "Entered %s.\n", __func__);
  4234. memset(mcp, 0, sizeof(mbx_cmd_t));
  4235. mcp->mb[0] = MBC_SET_LED_CONFIG;
  4236. if (enable)
  4237. mcp->mb[7] = 0xE;
  4238. else
  4239. mcp->mb[7] = 0xD;
  4240. mcp->out_mb = MBX_7|MBX_0;
  4241. mcp->in_mb = MBX_0;
  4242. mcp->tov = MBX_TOV_SECONDS;
  4243. mcp->flags = 0;
  4244. rval = qla2x00_mailbox_command(vha, mcp);
  4245. if (rval != QLA_SUCCESS) {
  4246. ql_dbg(ql_dbg_mbx, vha, 0x1128,
  4247. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4248. } else {
  4249. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
  4250. "Done %s.\n", __func__);
  4251. }
  4252. return rval;
  4253. }
  4254. int
  4255. qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
  4256. {
  4257. int rval;
  4258. struct qla_hw_data *ha = vha->hw;
  4259. mbx_cmd_t mc;
  4260. mbx_cmd_t *mcp = &mc;
  4261. if (!IS_QLA83XX(ha))
  4262. return QLA_FUNCTION_FAILED;
  4263. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
  4264. "Entered %s.\n", __func__);
  4265. mcp->mb[0] = MBC_WRITE_REMOTE_REG;
  4266. mcp->mb[1] = LSW(reg);
  4267. mcp->mb[2] = MSW(reg);
  4268. mcp->mb[3] = LSW(data);
  4269. mcp->mb[4] = MSW(data);
  4270. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4271. mcp->in_mb = MBX_1|MBX_0;
  4272. mcp->tov = MBX_TOV_SECONDS;
  4273. mcp->flags = 0;
  4274. rval = qla2x00_mailbox_command(vha, mcp);
  4275. if (rval != QLA_SUCCESS) {
  4276. ql_dbg(ql_dbg_mbx, vha, 0x1131,
  4277. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4278. } else {
  4279. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
  4280. "Done %s.\n", __func__);
  4281. }
  4282. return rval;
  4283. }
  4284. int
  4285. qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
  4286. {
  4287. int rval;
  4288. struct qla_hw_data *ha = vha->hw;
  4289. mbx_cmd_t mc;
  4290. mbx_cmd_t *mcp = &mc;
  4291. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  4292. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
  4293. "Implicit LOGO Unsupported.\n");
  4294. return QLA_FUNCTION_FAILED;
  4295. }
  4296. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
  4297. "Entering %s.\n", __func__);
  4298. /* Perform Implicit LOGO. */
  4299. mcp->mb[0] = MBC_PORT_LOGOUT;
  4300. mcp->mb[1] = fcport->loop_id;
  4301. mcp->mb[10] = BIT_15;
  4302. mcp->out_mb = MBX_10|MBX_1|MBX_0;
  4303. mcp->in_mb = MBX_0;
  4304. mcp->tov = MBX_TOV_SECONDS;
  4305. mcp->flags = 0;
  4306. rval = qla2x00_mailbox_command(vha, mcp);
  4307. if (rval != QLA_SUCCESS)
  4308. ql_dbg(ql_dbg_mbx, vha, 0x113d,
  4309. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4310. else
  4311. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
  4312. "Done %s.\n", __func__);
  4313. return rval;
  4314. }
  4315. int
  4316. qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
  4317. {
  4318. int rval;
  4319. mbx_cmd_t mc;
  4320. mbx_cmd_t *mcp = &mc;
  4321. struct qla_hw_data *ha = vha->hw;
  4322. unsigned long retry_max_time = jiffies + (2 * HZ);
  4323. if (!IS_QLA83XX(ha))
  4324. return QLA_FUNCTION_FAILED;
  4325. ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
  4326. retry_rd_reg:
  4327. mcp->mb[0] = MBC_READ_REMOTE_REG;
  4328. mcp->mb[1] = LSW(reg);
  4329. mcp->mb[2] = MSW(reg);
  4330. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  4331. mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
  4332. mcp->tov = MBX_TOV_SECONDS;
  4333. mcp->flags = 0;
  4334. rval = qla2x00_mailbox_command(vha, mcp);
  4335. if (rval != QLA_SUCCESS) {
  4336. ql_dbg(ql_dbg_mbx, vha, 0x114c,
  4337. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  4338. rval, mcp->mb[0], mcp->mb[1]);
  4339. } else {
  4340. *data = (mcp->mb[3] | (mcp->mb[4] << 16));
  4341. if (*data == QLA8XXX_BAD_VALUE) {
  4342. /*
  4343. * During soft-reset CAMRAM register reads might
  4344. * return 0xbad0bad0. So retry for MAX of 2 sec
  4345. * while reading camram registers.
  4346. */
  4347. if (time_after(jiffies, retry_max_time)) {
  4348. ql_dbg(ql_dbg_mbx, vha, 0x1141,
  4349. "Failure to read CAMRAM register. "
  4350. "data=0x%x.\n", *data);
  4351. return QLA_FUNCTION_FAILED;
  4352. }
  4353. msleep(100);
  4354. goto retry_rd_reg;
  4355. }
  4356. ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
  4357. }
  4358. return rval;
  4359. }
  4360. int
  4361. qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
  4362. {
  4363. int rval;
  4364. mbx_cmd_t mc;
  4365. mbx_cmd_t *mcp = &mc;
  4366. struct qla_hw_data *ha = vha->hw;
  4367. if (!IS_QLA83XX(ha))
  4368. return QLA_FUNCTION_FAILED;
  4369. ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
  4370. mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
  4371. mcp->out_mb = MBX_0;
  4372. mcp->in_mb = MBX_1|MBX_0;
  4373. mcp->tov = MBX_TOV_SECONDS;
  4374. mcp->flags = 0;
  4375. rval = qla2x00_mailbox_command(vha, mcp);
  4376. if (rval != QLA_SUCCESS) {
  4377. ql_dbg(ql_dbg_mbx, vha, 0x1144,
  4378. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  4379. rval, mcp->mb[0], mcp->mb[1]);
  4380. ha->isp_ops->fw_dump(vha, 0);
  4381. } else {
  4382. ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
  4383. }
  4384. return rval;
  4385. }
  4386. int
  4387. qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
  4388. uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
  4389. {
  4390. int rval;
  4391. mbx_cmd_t mc;
  4392. mbx_cmd_t *mcp = &mc;
  4393. uint8_t subcode = (uint8_t)options;
  4394. struct qla_hw_data *ha = vha->hw;
  4395. if (!IS_QLA8031(ha))
  4396. return QLA_FUNCTION_FAILED;
  4397. ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
  4398. mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
  4399. mcp->mb[1] = options;
  4400. mcp->out_mb = MBX_1|MBX_0;
  4401. if (subcode & BIT_2) {
  4402. mcp->mb[2] = LSW(start_addr);
  4403. mcp->mb[3] = MSW(start_addr);
  4404. mcp->mb[4] = LSW(end_addr);
  4405. mcp->mb[5] = MSW(end_addr);
  4406. mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
  4407. }
  4408. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  4409. if (!(subcode & (BIT_2 | BIT_5)))
  4410. mcp->in_mb |= MBX_4|MBX_3;
  4411. mcp->tov = MBX_TOV_SECONDS;
  4412. mcp->flags = 0;
  4413. rval = qla2x00_mailbox_command(vha, mcp);
  4414. if (rval != QLA_SUCCESS) {
  4415. ql_dbg(ql_dbg_mbx, vha, 0x1147,
  4416. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
  4417. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
  4418. mcp->mb[4]);
  4419. ha->isp_ops->fw_dump(vha, 0);
  4420. } else {
  4421. if (subcode & BIT_5)
  4422. *sector_size = mcp->mb[1];
  4423. else if (subcode & (BIT_6 | BIT_7)) {
  4424. ql_dbg(ql_dbg_mbx, vha, 0x1148,
  4425. "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
  4426. } else if (subcode & (BIT_3 | BIT_4)) {
  4427. ql_dbg(ql_dbg_mbx, vha, 0x1149,
  4428. "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
  4429. }
  4430. ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
  4431. }
  4432. return rval;
  4433. }
  4434. int
  4435. qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
  4436. uint32_t size)
  4437. {
  4438. int rval;
  4439. mbx_cmd_t mc;
  4440. mbx_cmd_t *mcp = &mc;
  4441. if (!IS_MCTP_CAPABLE(vha->hw))
  4442. return QLA_FUNCTION_FAILED;
  4443. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
  4444. "Entered %s.\n", __func__);
  4445. mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
  4446. mcp->mb[1] = LSW(addr);
  4447. mcp->mb[2] = MSW(req_dma);
  4448. mcp->mb[3] = LSW(req_dma);
  4449. mcp->mb[4] = MSW(size);
  4450. mcp->mb[5] = LSW(size);
  4451. mcp->mb[6] = MSW(MSD(req_dma));
  4452. mcp->mb[7] = LSW(MSD(req_dma));
  4453. mcp->mb[8] = MSW(addr);
  4454. /* Setting RAM ID to valid */
  4455. mcp->mb[10] |= BIT_7;
  4456. /* For MCTP RAM ID is 0x40 */
  4457. mcp->mb[10] |= 0x40;
  4458. mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
  4459. MBX_0;
  4460. mcp->in_mb = MBX_0;
  4461. mcp->tov = MBX_TOV_SECONDS;
  4462. mcp->flags = 0;
  4463. rval = qla2x00_mailbox_command(vha, mcp);
  4464. if (rval != QLA_SUCCESS) {
  4465. ql_dbg(ql_dbg_mbx, vha, 0x114e,
  4466. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4467. } else {
  4468. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
  4469. "Done %s.\n", __func__);
  4470. }
  4471. return rval;
  4472. }