qla_isr.c 82 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058
  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <scsi/scsi_tcq.h>
  12. #include <scsi/scsi_bsg_fc.h>
  13. #include <scsi/scsi_eh.h>
  14. #include "qla_target.h"
  15. static void qla2x00_mbx_completion(scsi_qla_host_t *, uint16_t);
  16. static void qla2x00_process_completed_request(struct scsi_qla_host *,
  17. struct req_que *, uint32_t);
  18. static void qla2x00_status_entry(scsi_qla_host_t *, struct rsp_que *, void *);
  19. static void qla2x00_status_cont_entry(struct rsp_que *, sts_cont_entry_t *);
  20. static void qla2x00_error_entry(scsi_qla_host_t *, struct rsp_que *,
  21. sts_entry_t *);
  22. /**
  23. * qla2100_intr_handler() - Process interrupts for the ISP2100 and ISP2200.
  24. * @irq:
  25. * @dev_id: SCSI driver HA context
  26. *
  27. * Called by system whenever the host adapter generates an interrupt.
  28. *
  29. * Returns handled flag.
  30. */
  31. irqreturn_t
  32. qla2100_intr_handler(int irq, void *dev_id)
  33. {
  34. scsi_qla_host_t *vha;
  35. struct qla_hw_data *ha;
  36. struct device_reg_2xxx __iomem *reg;
  37. int status;
  38. unsigned long iter;
  39. uint16_t hccr;
  40. uint16_t mb[4];
  41. struct rsp_que *rsp;
  42. unsigned long flags;
  43. rsp = (struct rsp_que *) dev_id;
  44. if (!rsp) {
  45. ql_log(ql_log_info, NULL, 0x505d,
  46. "%s: NULL response queue pointer.\n", __func__);
  47. return (IRQ_NONE);
  48. }
  49. ha = rsp->hw;
  50. reg = &ha->iobase->isp;
  51. status = 0;
  52. spin_lock_irqsave(&ha->hardware_lock, flags);
  53. vha = pci_get_drvdata(ha->pdev);
  54. for (iter = 50; iter--; ) {
  55. hccr = RD_REG_WORD(&reg->hccr);
  56. if (hccr & HCCR_RISC_PAUSE) {
  57. if (pci_channel_offline(ha->pdev))
  58. break;
  59. /*
  60. * Issue a "HARD" reset in order for the RISC interrupt
  61. * bit to be cleared. Schedule a big hammer to get
  62. * out of the RISC PAUSED state.
  63. */
  64. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  65. RD_REG_WORD(&reg->hccr);
  66. ha->isp_ops->fw_dump(vha, 1);
  67. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  68. break;
  69. } else if ((RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) == 0)
  70. break;
  71. if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
  72. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  73. RD_REG_WORD(&reg->hccr);
  74. /* Get mailbox data. */
  75. mb[0] = RD_MAILBOX_REG(ha, reg, 0);
  76. if (mb[0] > 0x3fff && mb[0] < 0x8000) {
  77. qla2x00_mbx_completion(vha, mb[0]);
  78. status |= MBX_INTERRUPT;
  79. } else if (mb[0] > 0x7fff && mb[0] < 0xc000) {
  80. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  81. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  82. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  83. qla2x00_async_event(vha, rsp, mb);
  84. } else {
  85. /*EMPTY*/
  86. ql_dbg(ql_dbg_async, vha, 0x5025,
  87. "Unrecognized interrupt type (%d).\n",
  88. mb[0]);
  89. }
  90. /* Release mailbox registers. */
  91. WRT_REG_WORD(&reg->semaphore, 0);
  92. RD_REG_WORD(&reg->semaphore);
  93. } else {
  94. qla2x00_process_response_queue(rsp);
  95. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  96. RD_REG_WORD(&reg->hccr);
  97. }
  98. }
  99. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  100. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  101. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  102. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  103. complete(&ha->mbx_intr_comp);
  104. }
  105. return (IRQ_HANDLED);
  106. }
  107. /**
  108. * qla2300_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
  109. * @irq:
  110. * @dev_id: SCSI driver HA context
  111. *
  112. * Called by system whenever the host adapter generates an interrupt.
  113. *
  114. * Returns handled flag.
  115. */
  116. irqreturn_t
  117. qla2300_intr_handler(int irq, void *dev_id)
  118. {
  119. scsi_qla_host_t *vha;
  120. struct device_reg_2xxx __iomem *reg;
  121. int status;
  122. unsigned long iter;
  123. uint32_t stat;
  124. uint16_t hccr;
  125. uint16_t mb[4];
  126. struct rsp_que *rsp;
  127. struct qla_hw_data *ha;
  128. unsigned long flags;
  129. rsp = (struct rsp_que *) dev_id;
  130. if (!rsp) {
  131. ql_log(ql_log_info, NULL, 0x5058,
  132. "%s: NULL response queue pointer.\n", __func__);
  133. return (IRQ_NONE);
  134. }
  135. ha = rsp->hw;
  136. reg = &ha->iobase->isp;
  137. status = 0;
  138. spin_lock_irqsave(&ha->hardware_lock, flags);
  139. vha = pci_get_drvdata(ha->pdev);
  140. for (iter = 50; iter--; ) {
  141. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  142. if (stat & HSR_RISC_PAUSED) {
  143. if (unlikely(pci_channel_offline(ha->pdev)))
  144. break;
  145. hccr = RD_REG_WORD(&reg->hccr);
  146. if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
  147. ql_log(ql_log_warn, vha, 0x5026,
  148. "Parity error -- HCCR=%x, Dumping "
  149. "firmware.\n", hccr);
  150. else
  151. ql_log(ql_log_warn, vha, 0x5027,
  152. "RISC paused -- HCCR=%x, Dumping "
  153. "firmware.\n", hccr);
  154. /*
  155. * Issue a "HARD" reset in order for the RISC
  156. * interrupt bit to be cleared. Schedule a big
  157. * hammer to get out of the RISC PAUSED state.
  158. */
  159. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  160. RD_REG_WORD(&reg->hccr);
  161. ha->isp_ops->fw_dump(vha, 1);
  162. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  163. break;
  164. } else if ((stat & HSR_RISC_INT) == 0)
  165. break;
  166. switch (stat & 0xff) {
  167. case 0x1:
  168. case 0x2:
  169. case 0x10:
  170. case 0x11:
  171. qla2x00_mbx_completion(vha, MSW(stat));
  172. status |= MBX_INTERRUPT;
  173. /* Release mailbox registers. */
  174. WRT_REG_WORD(&reg->semaphore, 0);
  175. break;
  176. case 0x12:
  177. mb[0] = MSW(stat);
  178. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  179. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  180. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  181. qla2x00_async_event(vha, rsp, mb);
  182. break;
  183. case 0x13:
  184. qla2x00_process_response_queue(rsp);
  185. break;
  186. case 0x15:
  187. mb[0] = MBA_CMPLT_1_16BIT;
  188. mb[1] = MSW(stat);
  189. qla2x00_async_event(vha, rsp, mb);
  190. break;
  191. case 0x16:
  192. mb[0] = MBA_SCSI_COMPLETION;
  193. mb[1] = MSW(stat);
  194. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  195. qla2x00_async_event(vha, rsp, mb);
  196. break;
  197. default:
  198. ql_dbg(ql_dbg_async, vha, 0x5028,
  199. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  200. break;
  201. }
  202. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  203. RD_REG_WORD_RELAXED(&reg->hccr);
  204. }
  205. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  206. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  207. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  208. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  209. complete(&ha->mbx_intr_comp);
  210. }
  211. return (IRQ_HANDLED);
  212. }
  213. /**
  214. * qla2x00_mbx_completion() - Process mailbox command completions.
  215. * @ha: SCSI driver HA context
  216. * @mb0: Mailbox0 register
  217. */
  218. static void
  219. qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  220. {
  221. uint16_t cnt;
  222. uint32_t mboxes;
  223. uint16_t __iomem *wptr;
  224. struct qla_hw_data *ha = vha->hw;
  225. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  226. /* Read all mbox registers? */
  227. mboxes = (1 << ha->mbx_count) - 1;
  228. if (!ha->mcp)
  229. ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERROR.\n");
  230. else
  231. mboxes = ha->mcp->in_mb;
  232. /* Load return mailbox registers. */
  233. ha->flags.mbox_int = 1;
  234. ha->mailbox_out[0] = mb0;
  235. mboxes >>= 1;
  236. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1);
  237. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  238. if (IS_QLA2200(ha) && cnt == 8)
  239. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8);
  240. if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0))
  241. ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr);
  242. else if (mboxes & BIT_0)
  243. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  244. wptr++;
  245. mboxes >>= 1;
  246. }
  247. }
  248. static void
  249. qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
  250. {
  251. static char *event[] =
  252. { "Complete", "Request Notification", "Time Extension" };
  253. int rval;
  254. struct device_reg_24xx __iomem *reg24 = &vha->hw->iobase->isp24;
  255. uint16_t __iomem *wptr;
  256. uint16_t cnt, timeout, mb[QLA_IDC_ACK_REGS];
  257. /* Seed data -- mailbox1 -> mailbox7. */
  258. wptr = (uint16_t __iomem *)&reg24->mailbox1;
  259. for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++)
  260. mb[cnt] = RD_REG_WORD(wptr);
  261. ql_dbg(ql_dbg_async, vha, 0x5021,
  262. "Inter-Driver Communication %s -- "
  263. "%04x %04x %04x %04x %04x %04x %04x.\n",
  264. event[aen & 0xff], mb[0], mb[1], mb[2], mb[3],
  265. mb[4], mb[5], mb[6]);
  266. if ((aen == MBA_IDC_COMPLETE && mb[1] >> 15)) {
  267. vha->hw->flags.idc_compl_status = 1;
  268. if (vha->hw->notify_dcbx_comp)
  269. complete(&vha->hw->dcbx_comp);
  270. }
  271. /* Acknowledgement needed? [Notify && non-zero timeout]. */
  272. timeout = (descr >> 8) & 0xf;
  273. if (aen != MBA_IDC_NOTIFY || !timeout)
  274. return;
  275. ql_dbg(ql_dbg_async, vha, 0x5022,
  276. "%lu Inter-Driver Communication %s -- ACK timeout=%d.\n",
  277. vha->host_no, event[aen & 0xff], timeout);
  278. rval = qla2x00_post_idc_ack_work(vha, mb);
  279. if (rval != QLA_SUCCESS)
  280. ql_log(ql_log_warn, vha, 0x5023,
  281. "IDC failed to post ACK.\n");
  282. }
  283. #define LS_UNKNOWN 2
  284. const char *
  285. qla2x00_get_link_speed_str(struct qla_hw_data *ha, uint16_t speed)
  286. {
  287. static const char * const link_speeds[] = {
  288. "1", "2", "?", "4", "8", "16", "10"
  289. };
  290. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  291. return link_speeds[0];
  292. else if (speed == 0x13)
  293. return link_speeds[6];
  294. else if (speed < 6)
  295. return link_speeds[speed];
  296. else
  297. return link_speeds[LS_UNKNOWN];
  298. }
  299. static void
  300. qla83xx_handle_8200_aen(scsi_qla_host_t *vha, uint16_t *mb)
  301. {
  302. struct qla_hw_data *ha = vha->hw;
  303. /*
  304. * 8200 AEN Interpretation:
  305. * mb[0] = AEN code
  306. * mb[1] = AEN Reason code
  307. * mb[2] = LSW of Peg-Halt Status-1 Register
  308. * mb[6] = MSW of Peg-Halt Status-1 Register
  309. * mb[3] = LSW of Peg-Halt Status-2 register
  310. * mb[7] = MSW of Peg-Halt Status-2 register
  311. * mb[4] = IDC Device-State Register value
  312. * mb[5] = IDC Driver-Presence Register value
  313. */
  314. ql_dbg(ql_dbg_async, vha, 0x506b, "AEN Code: mb[0] = 0x%x AEN reason: "
  315. "mb[1] = 0x%x PH-status1: mb[2] = 0x%x PH-status1: mb[6] = 0x%x.\n",
  316. mb[0], mb[1], mb[2], mb[6]);
  317. ql_dbg(ql_dbg_async, vha, 0x506c, "PH-status2: mb[3] = 0x%x "
  318. "PH-status2: mb[7] = 0x%x Device-State: mb[4] = 0x%x "
  319. "Drv-Presence: mb[5] = 0x%x.\n", mb[3], mb[7], mb[4], mb[5]);
  320. if (mb[1] & (IDC_PEG_HALT_STATUS_CHANGE | IDC_NIC_FW_REPORTED_FAILURE |
  321. IDC_HEARTBEAT_FAILURE)) {
  322. ha->flags.nic_core_hung = 1;
  323. ql_log(ql_log_warn, vha, 0x5060,
  324. "83XX: F/W Error Reported: Check if reset required.\n");
  325. if (mb[1] & IDC_PEG_HALT_STATUS_CHANGE) {
  326. uint32_t protocol_engine_id, fw_err_code, err_level;
  327. /*
  328. * IDC_PEG_HALT_STATUS_CHANGE interpretation:
  329. * - PEG-Halt Status-1 Register:
  330. * (LSW = mb[2], MSW = mb[6])
  331. * Bits 0-7 = protocol-engine ID
  332. * Bits 8-28 = f/w error code
  333. * Bits 29-31 = Error-level
  334. * Error-level 0x1 = Non-Fatal error
  335. * Error-level 0x2 = Recoverable Fatal error
  336. * Error-level 0x4 = UnRecoverable Fatal error
  337. * - PEG-Halt Status-2 Register:
  338. * (LSW = mb[3], MSW = mb[7])
  339. */
  340. protocol_engine_id = (mb[2] & 0xff);
  341. fw_err_code = (((mb[2] & 0xff00) >> 8) |
  342. ((mb[6] & 0x1fff) << 8));
  343. err_level = ((mb[6] & 0xe000) >> 13);
  344. ql_log(ql_log_warn, vha, 0x5061, "PegHalt Status-1 "
  345. "Register: protocol_engine_id=0x%x "
  346. "fw_err_code=0x%x err_level=0x%x.\n",
  347. protocol_engine_id, fw_err_code, err_level);
  348. ql_log(ql_log_warn, vha, 0x5062, "PegHalt Status-2 "
  349. "Register: 0x%x%x.\n", mb[7], mb[3]);
  350. if (err_level == ERR_LEVEL_NON_FATAL) {
  351. ql_log(ql_log_warn, vha, 0x5063,
  352. "Not a fatal error, f/w has recovered "
  353. "iteself.\n");
  354. } else if (err_level == ERR_LEVEL_RECOVERABLE_FATAL) {
  355. ql_log(ql_log_fatal, vha, 0x5064,
  356. "Recoverable Fatal error: Chip reset "
  357. "required.\n");
  358. qla83xx_schedule_work(vha,
  359. QLA83XX_NIC_CORE_RESET);
  360. } else if (err_level == ERR_LEVEL_UNRECOVERABLE_FATAL) {
  361. ql_log(ql_log_fatal, vha, 0x5065,
  362. "Unrecoverable Fatal error: Set FAILED "
  363. "state, reboot required.\n");
  364. qla83xx_schedule_work(vha,
  365. QLA83XX_NIC_CORE_UNRECOVERABLE);
  366. }
  367. }
  368. if (mb[1] & IDC_NIC_FW_REPORTED_FAILURE) {
  369. uint16_t peg_fw_state, nw_interface_link_up;
  370. uint16_t nw_interface_signal_detect, sfp_status;
  371. uint16_t htbt_counter, htbt_monitor_enable;
  372. uint16_t sfp_additonal_info, sfp_multirate;
  373. uint16_t sfp_tx_fault, link_speed, dcbx_status;
  374. /*
  375. * IDC_NIC_FW_REPORTED_FAILURE interpretation:
  376. * - PEG-to-FC Status Register:
  377. * (LSW = mb[2], MSW = mb[6])
  378. * Bits 0-7 = Peg-Firmware state
  379. * Bit 8 = N/W Interface Link-up
  380. * Bit 9 = N/W Interface signal detected
  381. * Bits 10-11 = SFP Status
  382. * SFP Status 0x0 = SFP+ transceiver not expected
  383. * SFP Status 0x1 = SFP+ transceiver not present
  384. * SFP Status 0x2 = SFP+ transceiver invalid
  385. * SFP Status 0x3 = SFP+ transceiver present and
  386. * valid
  387. * Bits 12-14 = Heartbeat Counter
  388. * Bit 15 = Heartbeat Monitor Enable
  389. * Bits 16-17 = SFP Additional Info
  390. * SFP info 0x0 = Unregocnized transceiver for
  391. * Ethernet
  392. * SFP info 0x1 = SFP+ brand validation failed
  393. * SFP info 0x2 = SFP+ speed validation failed
  394. * SFP info 0x3 = SFP+ access error
  395. * Bit 18 = SFP Multirate
  396. * Bit 19 = SFP Tx Fault
  397. * Bits 20-22 = Link Speed
  398. * Bits 23-27 = Reserved
  399. * Bits 28-30 = DCBX Status
  400. * DCBX Status 0x0 = DCBX Disabled
  401. * DCBX Status 0x1 = DCBX Enabled
  402. * DCBX Status 0x2 = DCBX Exchange error
  403. * Bit 31 = Reserved
  404. */
  405. peg_fw_state = (mb[2] & 0x00ff);
  406. nw_interface_link_up = ((mb[2] & 0x0100) >> 8);
  407. nw_interface_signal_detect = ((mb[2] & 0x0200) >> 9);
  408. sfp_status = ((mb[2] & 0x0c00) >> 10);
  409. htbt_counter = ((mb[2] & 0x7000) >> 12);
  410. htbt_monitor_enable = ((mb[2] & 0x8000) >> 15);
  411. sfp_additonal_info = (mb[6] & 0x0003);
  412. sfp_multirate = ((mb[6] & 0x0004) >> 2);
  413. sfp_tx_fault = ((mb[6] & 0x0008) >> 3);
  414. link_speed = ((mb[6] & 0x0070) >> 4);
  415. dcbx_status = ((mb[6] & 0x7000) >> 12);
  416. ql_log(ql_log_warn, vha, 0x5066,
  417. "Peg-to-Fc Status Register:\n"
  418. "peg_fw_state=0x%x, nw_interface_link_up=0x%x, "
  419. "nw_interface_signal_detect=0x%x"
  420. "\nsfp_statis=0x%x.\n ", peg_fw_state,
  421. nw_interface_link_up, nw_interface_signal_detect,
  422. sfp_status);
  423. ql_log(ql_log_warn, vha, 0x5067,
  424. "htbt_counter=0x%x, htbt_monitor_enable=0x%x, "
  425. "sfp_additonal_info=0x%x, sfp_multirate=0x%x.\n ",
  426. htbt_counter, htbt_monitor_enable,
  427. sfp_additonal_info, sfp_multirate);
  428. ql_log(ql_log_warn, vha, 0x5068,
  429. "sfp_tx_fault=0x%x, link_state=0x%x, "
  430. "dcbx_status=0x%x.\n", sfp_tx_fault, link_speed,
  431. dcbx_status);
  432. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  433. }
  434. if (mb[1] & IDC_HEARTBEAT_FAILURE) {
  435. ql_log(ql_log_warn, vha, 0x5069,
  436. "Heartbeat Failure encountered, chip reset "
  437. "required.\n");
  438. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  439. }
  440. }
  441. if (mb[1] & IDC_DEVICE_STATE_CHANGE) {
  442. ql_log(ql_log_info, vha, 0x506a,
  443. "IDC Device-State changed = 0x%x.\n", mb[4]);
  444. if (ha->flags.nic_core_reset_owner)
  445. return;
  446. qla83xx_schedule_work(vha, MBA_IDC_AEN);
  447. }
  448. }
  449. int
  450. qla2x00_is_a_vp_did(scsi_qla_host_t *vha, uint32_t rscn_entry)
  451. {
  452. struct qla_hw_data *ha = vha->hw;
  453. scsi_qla_host_t *vp;
  454. uint32_t vp_did;
  455. unsigned long flags;
  456. int ret = 0;
  457. if (!ha->num_vhosts)
  458. return ret;
  459. spin_lock_irqsave(&ha->vport_slock, flags);
  460. list_for_each_entry(vp, &ha->vp_list, list) {
  461. vp_did = vp->d_id.b24;
  462. if (vp_did == rscn_entry) {
  463. ret = 1;
  464. break;
  465. }
  466. }
  467. spin_unlock_irqrestore(&ha->vport_slock, flags);
  468. return ret;
  469. }
  470. /**
  471. * qla2x00_async_event() - Process aynchronous events.
  472. * @ha: SCSI driver HA context
  473. * @mb: Mailbox registers (0 - 3)
  474. */
  475. void
  476. qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
  477. {
  478. uint16_t handle_cnt;
  479. uint16_t cnt, mbx;
  480. uint32_t handles[5];
  481. struct qla_hw_data *ha = vha->hw;
  482. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  483. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  484. struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
  485. uint32_t rscn_entry, host_pid;
  486. unsigned long flags;
  487. /* Setup to process RIO completion. */
  488. handle_cnt = 0;
  489. if (IS_CNA_CAPABLE(ha))
  490. goto skip_rio;
  491. switch (mb[0]) {
  492. case MBA_SCSI_COMPLETION:
  493. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  494. handle_cnt = 1;
  495. break;
  496. case MBA_CMPLT_1_16BIT:
  497. handles[0] = mb[1];
  498. handle_cnt = 1;
  499. mb[0] = MBA_SCSI_COMPLETION;
  500. break;
  501. case MBA_CMPLT_2_16BIT:
  502. handles[0] = mb[1];
  503. handles[1] = mb[2];
  504. handle_cnt = 2;
  505. mb[0] = MBA_SCSI_COMPLETION;
  506. break;
  507. case MBA_CMPLT_3_16BIT:
  508. handles[0] = mb[1];
  509. handles[1] = mb[2];
  510. handles[2] = mb[3];
  511. handle_cnt = 3;
  512. mb[0] = MBA_SCSI_COMPLETION;
  513. break;
  514. case MBA_CMPLT_4_16BIT:
  515. handles[0] = mb[1];
  516. handles[1] = mb[2];
  517. handles[2] = mb[3];
  518. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  519. handle_cnt = 4;
  520. mb[0] = MBA_SCSI_COMPLETION;
  521. break;
  522. case MBA_CMPLT_5_16BIT:
  523. handles[0] = mb[1];
  524. handles[1] = mb[2];
  525. handles[2] = mb[3];
  526. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  527. handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7);
  528. handle_cnt = 5;
  529. mb[0] = MBA_SCSI_COMPLETION;
  530. break;
  531. case MBA_CMPLT_2_32BIT:
  532. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  533. handles[1] = le32_to_cpu(
  534. ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) |
  535. RD_MAILBOX_REG(ha, reg, 6));
  536. handle_cnt = 2;
  537. mb[0] = MBA_SCSI_COMPLETION;
  538. break;
  539. default:
  540. break;
  541. }
  542. skip_rio:
  543. switch (mb[0]) {
  544. case MBA_SCSI_COMPLETION: /* Fast Post */
  545. if (!vha->flags.online)
  546. break;
  547. for (cnt = 0; cnt < handle_cnt; cnt++)
  548. qla2x00_process_completed_request(vha, rsp->req,
  549. handles[cnt]);
  550. break;
  551. case MBA_RESET: /* Reset */
  552. ql_dbg(ql_dbg_async, vha, 0x5002,
  553. "Asynchronous RESET.\n");
  554. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  555. break;
  556. case MBA_SYSTEM_ERR: /* System Error */
  557. mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha)) ?
  558. RD_REG_WORD(&reg24->mailbox7) : 0;
  559. ql_log(ql_log_warn, vha, 0x5003,
  560. "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh "
  561. "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
  562. ha->isp_ops->fw_dump(vha, 1);
  563. if (IS_FWI2_CAPABLE(ha)) {
  564. if (mb[1] == 0 && mb[2] == 0) {
  565. ql_log(ql_log_fatal, vha, 0x5004,
  566. "Unrecoverable Hardware Error: adapter "
  567. "marked OFFLINE!\n");
  568. vha->flags.online = 0;
  569. vha->device_flags |= DFLG_DEV_FAILED;
  570. } else {
  571. /* Check to see if MPI timeout occurred */
  572. if ((mbx & MBX_3) && (ha->flags.port0))
  573. set_bit(MPI_RESET_NEEDED,
  574. &vha->dpc_flags);
  575. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  576. }
  577. } else if (mb[1] == 0) {
  578. ql_log(ql_log_fatal, vha, 0x5005,
  579. "Unrecoverable Hardware Error: adapter marked "
  580. "OFFLINE!\n");
  581. vha->flags.online = 0;
  582. vha->device_flags |= DFLG_DEV_FAILED;
  583. } else
  584. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  585. break;
  586. case MBA_REQ_TRANSFER_ERR: /* Request Transfer Error */
  587. ql_log(ql_log_warn, vha, 0x5006,
  588. "ISP Request Transfer Error (%x).\n", mb[1]);
  589. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  590. break;
  591. case MBA_RSP_TRANSFER_ERR: /* Response Transfer Error */
  592. ql_log(ql_log_warn, vha, 0x5007,
  593. "ISP Response Transfer Error.\n");
  594. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  595. break;
  596. case MBA_WAKEUP_THRES: /* Request Queue Wake-up */
  597. ql_dbg(ql_dbg_async, vha, 0x5008,
  598. "Asynchronous WAKEUP_THRES.\n");
  599. break;
  600. case MBA_LIP_OCCURRED: /* Loop Initialization Procedure */
  601. ql_dbg(ql_dbg_async, vha, 0x5009,
  602. "LIP occurred (%x).\n", mb[1]);
  603. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  604. atomic_set(&vha->loop_state, LOOP_DOWN);
  605. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  606. qla2x00_mark_all_devices_lost(vha, 1);
  607. }
  608. if (vha->vp_idx) {
  609. atomic_set(&vha->vp_state, VP_FAILED);
  610. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  611. }
  612. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  613. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  614. vha->flags.management_server_logged_in = 0;
  615. qla2x00_post_aen_work(vha, FCH_EVT_LIP, mb[1]);
  616. break;
  617. case MBA_LOOP_UP: /* Loop Up Event */
  618. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  619. ha->link_data_rate = PORT_SPEED_1GB;
  620. else
  621. ha->link_data_rate = mb[1];
  622. ql_dbg(ql_dbg_async, vha, 0x500a,
  623. "LOOP UP detected (%s Gbps).\n",
  624. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  625. vha->flags.management_server_logged_in = 0;
  626. qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, ha->link_data_rate);
  627. break;
  628. case MBA_LOOP_DOWN: /* Loop Down Event */
  629. mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha))
  630. ? RD_REG_WORD(&reg24->mailbox4) : 0;
  631. mbx = IS_QLA82XX(ha) ? RD_REG_WORD(&reg82->mailbox_out[4]) : mbx;
  632. ql_dbg(ql_dbg_async, vha, 0x500b,
  633. "LOOP DOWN detected (%x %x %x %x).\n",
  634. mb[1], mb[2], mb[3], mbx);
  635. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  636. atomic_set(&vha->loop_state, LOOP_DOWN);
  637. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  638. vha->device_flags |= DFLG_NO_CABLE;
  639. qla2x00_mark_all_devices_lost(vha, 1);
  640. }
  641. if (vha->vp_idx) {
  642. atomic_set(&vha->vp_state, VP_FAILED);
  643. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  644. }
  645. vha->flags.management_server_logged_in = 0;
  646. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  647. qla2x00_post_aen_work(vha, FCH_EVT_LINKDOWN, 0);
  648. break;
  649. case MBA_LIP_RESET: /* LIP reset occurred */
  650. ql_dbg(ql_dbg_async, vha, 0x500c,
  651. "LIP reset occurred (%x).\n", mb[1]);
  652. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  653. atomic_set(&vha->loop_state, LOOP_DOWN);
  654. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  655. qla2x00_mark_all_devices_lost(vha, 1);
  656. }
  657. if (vha->vp_idx) {
  658. atomic_set(&vha->vp_state, VP_FAILED);
  659. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  660. }
  661. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  662. ha->operating_mode = LOOP;
  663. vha->flags.management_server_logged_in = 0;
  664. qla2x00_post_aen_work(vha, FCH_EVT_LIPRESET, mb[1]);
  665. break;
  666. /* case MBA_DCBX_COMPLETE: */
  667. case MBA_POINT_TO_POINT: /* Point-to-Point */
  668. if (IS_QLA2100(ha))
  669. break;
  670. if (IS_QLA81XX(ha) || IS_QLA82XX(ha) || IS_QLA8031(ha)) {
  671. ql_dbg(ql_dbg_async, vha, 0x500d,
  672. "DCBX Completed -- %04x %04x %04x.\n",
  673. mb[1], mb[2], mb[3]);
  674. if (ha->notify_dcbx_comp)
  675. complete(&ha->dcbx_comp);
  676. } else
  677. ql_dbg(ql_dbg_async, vha, 0x500e,
  678. "Asynchronous P2P MODE received.\n");
  679. /*
  680. * Until there's a transition from loop down to loop up, treat
  681. * this as loop down only.
  682. */
  683. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  684. atomic_set(&vha->loop_state, LOOP_DOWN);
  685. if (!atomic_read(&vha->loop_down_timer))
  686. atomic_set(&vha->loop_down_timer,
  687. LOOP_DOWN_TIME);
  688. qla2x00_mark_all_devices_lost(vha, 1);
  689. }
  690. if (vha->vp_idx) {
  691. atomic_set(&vha->vp_state, VP_FAILED);
  692. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  693. }
  694. if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)))
  695. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  696. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  697. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  698. ha->flags.gpsc_supported = 1;
  699. vha->flags.management_server_logged_in = 0;
  700. break;
  701. case MBA_CHG_IN_CONNECTION: /* Change in connection mode */
  702. if (IS_QLA2100(ha))
  703. break;
  704. ql_dbg(ql_dbg_async, vha, 0x500f,
  705. "Configuration change detected: value=%x.\n", mb[1]);
  706. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  707. atomic_set(&vha->loop_state, LOOP_DOWN);
  708. if (!atomic_read(&vha->loop_down_timer))
  709. atomic_set(&vha->loop_down_timer,
  710. LOOP_DOWN_TIME);
  711. qla2x00_mark_all_devices_lost(vha, 1);
  712. }
  713. if (vha->vp_idx) {
  714. atomic_set(&vha->vp_state, VP_FAILED);
  715. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  716. }
  717. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  718. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  719. break;
  720. case MBA_PORT_UPDATE: /* Port database update */
  721. /*
  722. * Handle only global and vn-port update events
  723. *
  724. * Relevant inputs:
  725. * mb[1] = N_Port handle of changed port
  726. * OR 0xffff for global event
  727. * mb[2] = New login state
  728. * 7 = Port logged out
  729. * mb[3] = LSB is vp_idx, 0xff = all vps
  730. *
  731. * Skip processing if:
  732. * Event is global, vp_idx is NOT all vps,
  733. * vp_idx does not match
  734. * Event is not global, vp_idx does not match
  735. */
  736. if (IS_QLA2XXX_MIDTYPE(ha) &&
  737. ((mb[1] == 0xffff && (mb[3] & 0xff) != 0xff) ||
  738. (mb[1] != 0xffff)) && vha->vp_idx != (mb[3] & 0xff))
  739. break;
  740. /* Global event -- port logout or port unavailable. */
  741. if (mb[1] == 0xffff && mb[2] == 0x7) {
  742. ql_dbg(ql_dbg_async, vha, 0x5010,
  743. "Port unavailable %04x %04x %04x.\n",
  744. mb[1], mb[2], mb[3]);
  745. ql_log(ql_log_warn, vha, 0x505e,
  746. "Link is offline.\n");
  747. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  748. atomic_set(&vha->loop_state, LOOP_DOWN);
  749. atomic_set(&vha->loop_down_timer,
  750. LOOP_DOWN_TIME);
  751. vha->device_flags |= DFLG_NO_CABLE;
  752. qla2x00_mark_all_devices_lost(vha, 1);
  753. }
  754. if (vha->vp_idx) {
  755. atomic_set(&vha->vp_state, VP_FAILED);
  756. fc_vport_set_state(vha->fc_vport,
  757. FC_VPORT_FAILED);
  758. qla2x00_mark_all_devices_lost(vha, 1);
  759. }
  760. vha->flags.management_server_logged_in = 0;
  761. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  762. break;
  763. }
  764. /*
  765. * If PORT UPDATE is global (received LIP_OCCURRED/LIP_RESET
  766. * event etc. earlier indicating loop is down) then process
  767. * it. Otherwise ignore it and Wait for RSCN to come in.
  768. */
  769. atomic_set(&vha->loop_down_timer, 0);
  770. if (mb[1] != 0xffff || (mb[2] != 0x6 && mb[2] != 0x4)) {
  771. ql_dbg(ql_dbg_async, vha, 0x5011,
  772. "Asynchronous PORT UPDATE ignored %04x/%04x/%04x.\n",
  773. mb[1], mb[2], mb[3]);
  774. qlt_async_event(mb[0], vha, mb);
  775. break;
  776. }
  777. ql_dbg(ql_dbg_async, vha, 0x5012,
  778. "Port database changed %04x %04x %04x.\n",
  779. mb[1], mb[2], mb[3]);
  780. ql_log(ql_log_warn, vha, 0x505f,
  781. "Link is operational (%s Gbps).\n",
  782. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  783. /*
  784. * Mark all devices as missing so we will login again.
  785. */
  786. atomic_set(&vha->loop_state, LOOP_UP);
  787. qla2x00_mark_all_devices_lost(vha, 1);
  788. if (vha->vp_idx == 0 && !qla_ini_mode_enabled(vha))
  789. set_bit(SCR_PENDING, &vha->dpc_flags);
  790. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  791. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  792. qlt_async_event(mb[0], vha, mb);
  793. break;
  794. case MBA_RSCN_UPDATE: /* State Change Registration */
  795. /* Check if the Vport has issued a SCR */
  796. if (vha->vp_idx && test_bit(VP_SCR_NEEDED, &vha->vp_flags))
  797. break;
  798. /* Only handle SCNs for our Vport index. */
  799. if (ha->flags.npiv_supported && vha->vp_idx != (mb[3] & 0xff))
  800. break;
  801. ql_dbg(ql_dbg_async, vha, 0x5013,
  802. "RSCN database changed -- %04x %04x %04x.\n",
  803. mb[1], mb[2], mb[3]);
  804. rscn_entry = ((mb[1] & 0xff) << 16) | mb[2];
  805. host_pid = (vha->d_id.b.domain << 16) | (vha->d_id.b.area << 8)
  806. | vha->d_id.b.al_pa;
  807. if (rscn_entry == host_pid) {
  808. ql_dbg(ql_dbg_async, vha, 0x5014,
  809. "Ignoring RSCN update to local host "
  810. "port ID (%06x).\n", host_pid);
  811. break;
  812. }
  813. /* Ignore reserved bits from RSCN-payload. */
  814. rscn_entry = ((mb[1] & 0x3ff) << 16) | mb[2];
  815. /* Skip RSCNs for virtual ports on the same physical port */
  816. if (qla2x00_is_a_vp_did(vha, rscn_entry))
  817. break;
  818. atomic_set(&vha->loop_down_timer, 0);
  819. vha->flags.management_server_logged_in = 0;
  820. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  821. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  822. qla2x00_post_aen_work(vha, FCH_EVT_RSCN, rscn_entry);
  823. break;
  824. /* case MBA_RIO_RESPONSE: */
  825. case MBA_ZIO_RESPONSE:
  826. ql_dbg(ql_dbg_async, vha, 0x5015,
  827. "[R|Z]IO update completion.\n");
  828. if (IS_FWI2_CAPABLE(ha))
  829. qla24xx_process_response_queue(vha, rsp);
  830. else
  831. qla2x00_process_response_queue(rsp);
  832. break;
  833. case MBA_DISCARD_RND_FRAME:
  834. ql_dbg(ql_dbg_async, vha, 0x5016,
  835. "Discard RND Frame -- %04x %04x %04x.\n",
  836. mb[1], mb[2], mb[3]);
  837. break;
  838. case MBA_TRACE_NOTIFICATION:
  839. ql_dbg(ql_dbg_async, vha, 0x5017,
  840. "Trace Notification -- %04x %04x.\n", mb[1], mb[2]);
  841. break;
  842. case MBA_ISP84XX_ALERT:
  843. ql_dbg(ql_dbg_async, vha, 0x5018,
  844. "ISP84XX Alert Notification -- %04x %04x %04x.\n",
  845. mb[1], mb[2], mb[3]);
  846. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  847. switch (mb[1]) {
  848. case A84_PANIC_RECOVERY:
  849. ql_log(ql_log_info, vha, 0x5019,
  850. "Alert 84XX: panic recovery %04x %04x.\n",
  851. mb[2], mb[3]);
  852. break;
  853. case A84_OP_LOGIN_COMPLETE:
  854. ha->cs84xx->op_fw_version = mb[3] << 16 | mb[2];
  855. ql_log(ql_log_info, vha, 0x501a,
  856. "Alert 84XX: firmware version %x.\n",
  857. ha->cs84xx->op_fw_version);
  858. break;
  859. case A84_DIAG_LOGIN_COMPLETE:
  860. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  861. ql_log(ql_log_info, vha, 0x501b,
  862. "Alert 84XX: diagnostic firmware version %x.\n",
  863. ha->cs84xx->diag_fw_version);
  864. break;
  865. case A84_GOLD_LOGIN_COMPLETE:
  866. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  867. ha->cs84xx->fw_update = 1;
  868. ql_log(ql_log_info, vha, 0x501c,
  869. "Alert 84XX: gold firmware version %x.\n",
  870. ha->cs84xx->gold_fw_version);
  871. break;
  872. default:
  873. ql_log(ql_log_warn, vha, 0x501d,
  874. "Alert 84xx: Invalid Alert %04x %04x %04x.\n",
  875. mb[1], mb[2], mb[3]);
  876. }
  877. spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags);
  878. break;
  879. case MBA_DCBX_START:
  880. ql_dbg(ql_dbg_async, vha, 0x501e,
  881. "DCBX Started -- %04x %04x %04x.\n",
  882. mb[1], mb[2], mb[3]);
  883. break;
  884. case MBA_DCBX_PARAM_UPDATE:
  885. ql_dbg(ql_dbg_async, vha, 0x501f,
  886. "DCBX Parameters Updated -- %04x %04x %04x.\n",
  887. mb[1], mb[2], mb[3]);
  888. break;
  889. case MBA_FCF_CONF_ERR:
  890. ql_dbg(ql_dbg_async, vha, 0x5020,
  891. "FCF Configuration Error -- %04x %04x %04x.\n",
  892. mb[1], mb[2], mb[3]);
  893. break;
  894. case MBA_IDC_NOTIFY:
  895. if (IS_QLA8031(vha->hw)) {
  896. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  897. if (((mb[2] & 0x7fff) == MBC_PORT_RESET ||
  898. (mb[2] & 0x7fff) == MBC_SET_PORT_CONFIG) &&
  899. (mb[4] & INTERNAL_LOOPBACK_MASK) != 0) {
  900. set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
  901. /*
  902. * Extend loop down timer since port is active.
  903. */
  904. if (atomic_read(&vha->loop_state) == LOOP_DOWN)
  905. atomic_set(&vha->loop_down_timer,
  906. LOOP_DOWN_TIME);
  907. qla2xxx_wake_dpc(vha);
  908. }
  909. }
  910. case MBA_IDC_COMPLETE:
  911. if (ha->notify_lb_portup_comp)
  912. complete(&ha->lb_portup_comp);
  913. /* Fallthru */
  914. case MBA_IDC_TIME_EXT:
  915. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw))
  916. qla81xx_idc_event(vha, mb[0], mb[1]);
  917. break;
  918. case MBA_IDC_AEN:
  919. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  920. mb[5] = RD_REG_WORD(&reg24->mailbox5);
  921. mb[6] = RD_REG_WORD(&reg24->mailbox6);
  922. mb[7] = RD_REG_WORD(&reg24->mailbox7);
  923. qla83xx_handle_8200_aen(vha, mb);
  924. break;
  925. default:
  926. ql_dbg(ql_dbg_async, vha, 0x5057,
  927. "Unknown AEN:%04x %04x %04x %04x\n",
  928. mb[0], mb[1], mb[2], mb[3]);
  929. }
  930. qlt_async_event(mb[0], vha, mb);
  931. if (!vha->vp_idx && ha->num_vhosts)
  932. qla2x00_alert_all_vps(rsp, mb);
  933. }
  934. /**
  935. * qla2x00_process_completed_request() - Process a Fast Post response.
  936. * @ha: SCSI driver HA context
  937. * @index: SRB index
  938. */
  939. static void
  940. qla2x00_process_completed_request(struct scsi_qla_host *vha,
  941. struct req_que *req, uint32_t index)
  942. {
  943. srb_t *sp;
  944. struct qla_hw_data *ha = vha->hw;
  945. /* Validate handle. */
  946. if (index >= req->num_outstanding_cmds) {
  947. ql_log(ql_log_warn, vha, 0x3014,
  948. "Invalid SCSI command index (%x).\n", index);
  949. if (IS_QLA82XX(ha))
  950. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  951. else
  952. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  953. return;
  954. }
  955. sp = req->outstanding_cmds[index];
  956. if (sp) {
  957. /* Free outstanding command slot. */
  958. req->outstanding_cmds[index] = NULL;
  959. /* Save ISP completion status */
  960. sp->done(ha, sp, DID_OK << 16);
  961. } else {
  962. ql_log(ql_log_warn, vha, 0x3016, "Invalid SCSI SRB.\n");
  963. if (IS_QLA82XX(ha))
  964. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  965. else
  966. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  967. }
  968. }
  969. static srb_t *
  970. qla2x00_get_sp_from_handle(scsi_qla_host_t *vha, const char *func,
  971. struct req_que *req, void *iocb)
  972. {
  973. struct qla_hw_data *ha = vha->hw;
  974. sts_entry_t *pkt = iocb;
  975. srb_t *sp = NULL;
  976. uint16_t index;
  977. index = LSW(pkt->handle);
  978. if (index >= req->num_outstanding_cmds) {
  979. ql_log(ql_log_warn, vha, 0x5031,
  980. "Invalid command index (%x).\n", index);
  981. if (IS_QLA82XX(ha))
  982. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  983. else
  984. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  985. goto done;
  986. }
  987. sp = req->outstanding_cmds[index];
  988. if (!sp) {
  989. ql_log(ql_log_warn, vha, 0x5032,
  990. "Invalid completion handle (%x) -- timed-out.\n", index);
  991. return sp;
  992. }
  993. if (sp->handle != index) {
  994. ql_log(ql_log_warn, vha, 0x5033,
  995. "SRB handle (%x) mismatch %x.\n", sp->handle, index);
  996. return NULL;
  997. }
  998. req->outstanding_cmds[index] = NULL;
  999. done:
  1000. return sp;
  1001. }
  1002. static void
  1003. qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1004. struct mbx_entry *mbx)
  1005. {
  1006. const char func[] = "MBX-IOCB";
  1007. const char *type;
  1008. fc_port_t *fcport;
  1009. srb_t *sp;
  1010. struct srb_iocb *lio;
  1011. uint16_t *data;
  1012. uint16_t status;
  1013. sp = qla2x00_get_sp_from_handle(vha, func, req, mbx);
  1014. if (!sp)
  1015. return;
  1016. lio = &sp->u.iocb_cmd;
  1017. type = sp->name;
  1018. fcport = sp->fcport;
  1019. data = lio->u.logio.data;
  1020. data[0] = MBS_COMMAND_ERROR;
  1021. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1022. QLA_LOGIO_LOGIN_RETRIED : 0;
  1023. if (mbx->entry_status) {
  1024. ql_dbg(ql_dbg_async, vha, 0x5043,
  1025. "Async-%s error entry - hdl=%x portid=%02x%02x%02x "
  1026. "entry-status=%x status=%x state-flag=%x "
  1027. "status-flags=%x.\n", type, sp->handle,
  1028. fcport->d_id.b.domain, fcport->d_id.b.area,
  1029. fcport->d_id.b.al_pa, mbx->entry_status,
  1030. le16_to_cpu(mbx->status), le16_to_cpu(mbx->state_flags),
  1031. le16_to_cpu(mbx->status_flags));
  1032. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
  1033. (uint8_t *)mbx, sizeof(*mbx));
  1034. goto logio_done;
  1035. }
  1036. status = le16_to_cpu(mbx->status);
  1037. if (status == 0x30 && sp->type == SRB_LOGIN_CMD &&
  1038. le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE)
  1039. status = 0;
  1040. if (!status && le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE) {
  1041. ql_dbg(ql_dbg_async, vha, 0x5045,
  1042. "Async-%s complete - hdl=%x portid=%02x%02x%02x mbx1=%x.\n",
  1043. type, sp->handle, fcport->d_id.b.domain,
  1044. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1045. le16_to_cpu(mbx->mb1));
  1046. data[0] = MBS_COMMAND_COMPLETE;
  1047. if (sp->type == SRB_LOGIN_CMD) {
  1048. fcport->port_type = FCT_TARGET;
  1049. if (le16_to_cpu(mbx->mb1) & BIT_0)
  1050. fcport->port_type = FCT_INITIATOR;
  1051. else if (le16_to_cpu(mbx->mb1) & BIT_1)
  1052. fcport->flags |= FCF_FCP2_DEVICE;
  1053. }
  1054. goto logio_done;
  1055. }
  1056. data[0] = le16_to_cpu(mbx->mb0);
  1057. switch (data[0]) {
  1058. case MBS_PORT_ID_USED:
  1059. data[1] = le16_to_cpu(mbx->mb1);
  1060. break;
  1061. case MBS_LOOP_ID_USED:
  1062. break;
  1063. default:
  1064. data[0] = MBS_COMMAND_ERROR;
  1065. break;
  1066. }
  1067. ql_log(ql_log_warn, vha, 0x5046,
  1068. "Async-%s failed - hdl=%x portid=%02x%02x%02x status=%x "
  1069. "mb0=%x mb1=%x mb2=%x mb6=%x mb7=%x.\n", type, sp->handle,
  1070. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1071. status, le16_to_cpu(mbx->mb0), le16_to_cpu(mbx->mb1),
  1072. le16_to_cpu(mbx->mb2), le16_to_cpu(mbx->mb6),
  1073. le16_to_cpu(mbx->mb7));
  1074. logio_done:
  1075. sp->done(vha, sp, 0);
  1076. }
  1077. static void
  1078. qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1079. sts_entry_t *pkt, int iocb_type)
  1080. {
  1081. const char func[] = "CT_IOCB";
  1082. const char *type;
  1083. srb_t *sp;
  1084. struct fc_bsg_job *bsg_job;
  1085. uint16_t comp_status;
  1086. int res;
  1087. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1088. if (!sp)
  1089. return;
  1090. bsg_job = sp->u.bsg_job;
  1091. type = "ct pass-through";
  1092. comp_status = le16_to_cpu(pkt->comp_status);
  1093. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1094. * fc payload to the caller
  1095. */
  1096. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1097. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1098. if (comp_status != CS_COMPLETE) {
  1099. if (comp_status == CS_DATA_UNDERRUN) {
  1100. res = DID_OK << 16;
  1101. bsg_job->reply->reply_payload_rcv_len =
  1102. le16_to_cpu(((sts_entry_t *)pkt)->rsp_info_len);
  1103. ql_log(ql_log_warn, vha, 0x5048,
  1104. "CT pass-through-%s error "
  1105. "comp_status-status=0x%x total_byte = 0x%x.\n",
  1106. type, comp_status,
  1107. bsg_job->reply->reply_payload_rcv_len);
  1108. } else {
  1109. ql_log(ql_log_warn, vha, 0x5049,
  1110. "CT pass-through-%s error "
  1111. "comp_status-status=0x%x.\n", type, comp_status);
  1112. res = DID_ERROR << 16;
  1113. bsg_job->reply->reply_payload_rcv_len = 0;
  1114. }
  1115. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
  1116. (uint8_t *)pkt, sizeof(*pkt));
  1117. } else {
  1118. res = DID_OK << 16;
  1119. bsg_job->reply->reply_payload_rcv_len =
  1120. bsg_job->reply_payload.payload_len;
  1121. bsg_job->reply_len = 0;
  1122. }
  1123. sp->done(vha, sp, res);
  1124. }
  1125. static void
  1126. qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1127. struct sts_entry_24xx *pkt, int iocb_type)
  1128. {
  1129. const char func[] = "ELS_CT_IOCB";
  1130. const char *type;
  1131. srb_t *sp;
  1132. struct fc_bsg_job *bsg_job;
  1133. uint16_t comp_status;
  1134. uint32_t fw_status[3];
  1135. uint8_t* fw_sts_ptr;
  1136. int res;
  1137. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1138. if (!sp)
  1139. return;
  1140. bsg_job = sp->u.bsg_job;
  1141. type = NULL;
  1142. switch (sp->type) {
  1143. case SRB_ELS_CMD_RPT:
  1144. case SRB_ELS_CMD_HST:
  1145. type = "els";
  1146. break;
  1147. case SRB_CT_CMD:
  1148. type = "ct pass-through";
  1149. break;
  1150. default:
  1151. ql_dbg(ql_dbg_user, vha, 0x503e,
  1152. "Unrecognized SRB: (%p) type=%d.\n", sp, sp->type);
  1153. return;
  1154. }
  1155. comp_status = fw_status[0] = le16_to_cpu(pkt->comp_status);
  1156. fw_status[1] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_1);
  1157. fw_status[2] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_2);
  1158. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1159. * fc payload to the caller
  1160. */
  1161. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1162. bsg_job->reply_len = sizeof(struct fc_bsg_reply) + sizeof(fw_status);
  1163. if (comp_status != CS_COMPLETE) {
  1164. if (comp_status == CS_DATA_UNDERRUN) {
  1165. res = DID_OK << 16;
  1166. bsg_job->reply->reply_payload_rcv_len =
  1167. le16_to_cpu(((struct els_sts_entry_24xx *)pkt)->total_byte_count);
  1168. ql_dbg(ql_dbg_user, vha, 0x503f,
  1169. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1170. "error subcode 1=0x%x error subcode 2=0x%x total_byte = 0x%x.\n",
  1171. type, sp->handle, comp_status, fw_status[1], fw_status[2],
  1172. le16_to_cpu(((struct els_sts_entry_24xx *)
  1173. pkt)->total_byte_count));
  1174. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1175. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1176. }
  1177. else {
  1178. ql_dbg(ql_dbg_user, vha, 0x5040,
  1179. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1180. "error subcode 1=0x%x error subcode 2=0x%x.\n",
  1181. type, sp->handle, comp_status,
  1182. le16_to_cpu(((struct els_sts_entry_24xx *)
  1183. pkt)->error_subcode_1),
  1184. le16_to_cpu(((struct els_sts_entry_24xx *)
  1185. pkt)->error_subcode_2));
  1186. res = DID_ERROR << 16;
  1187. bsg_job->reply->reply_payload_rcv_len = 0;
  1188. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1189. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1190. }
  1191. ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
  1192. (uint8_t *)pkt, sizeof(*pkt));
  1193. }
  1194. else {
  1195. res = DID_OK << 16;
  1196. bsg_job->reply->reply_payload_rcv_len = bsg_job->reply_payload.payload_len;
  1197. bsg_job->reply_len = 0;
  1198. }
  1199. sp->done(vha, sp, res);
  1200. }
  1201. static void
  1202. qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
  1203. struct logio_entry_24xx *logio)
  1204. {
  1205. const char func[] = "LOGIO-IOCB";
  1206. const char *type;
  1207. fc_port_t *fcport;
  1208. srb_t *sp;
  1209. struct srb_iocb *lio;
  1210. uint16_t *data;
  1211. uint32_t iop[2];
  1212. sp = qla2x00_get_sp_from_handle(vha, func, req, logio);
  1213. if (!sp)
  1214. return;
  1215. lio = &sp->u.iocb_cmd;
  1216. type = sp->name;
  1217. fcport = sp->fcport;
  1218. data = lio->u.logio.data;
  1219. data[0] = MBS_COMMAND_ERROR;
  1220. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1221. QLA_LOGIO_LOGIN_RETRIED : 0;
  1222. if (logio->entry_status) {
  1223. ql_log(ql_log_warn, fcport->vha, 0x5034,
  1224. "Async-%s error entry - hdl=%x"
  1225. "portid=%02x%02x%02x entry-status=%x.\n",
  1226. type, sp->handle, fcport->d_id.b.domain,
  1227. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1228. logio->entry_status);
  1229. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
  1230. (uint8_t *)logio, sizeof(*logio));
  1231. goto logio_done;
  1232. }
  1233. if (le16_to_cpu(logio->comp_status) == CS_COMPLETE) {
  1234. ql_dbg(ql_dbg_async, fcport->vha, 0x5036,
  1235. "Async-%s complete - hdl=%x portid=%02x%02x%02x "
  1236. "iop0=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1237. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1238. le32_to_cpu(logio->io_parameter[0]));
  1239. data[0] = MBS_COMMAND_COMPLETE;
  1240. if (sp->type != SRB_LOGIN_CMD)
  1241. goto logio_done;
  1242. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1243. if (iop[0] & BIT_4) {
  1244. fcport->port_type = FCT_TARGET;
  1245. if (iop[0] & BIT_8)
  1246. fcport->flags |= FCF_FCP2_DEVICE;
  1247. } else if (iop[0] & BIT_5)
  1248. fcport->port_type = FCT_INITIATOR;
  1249. if (iop[0] & BIT_7)
  1250. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1251. if (logio->io_parameter[7] || logio->io_parameter[8])
  1252. fcport->supported_classes |= FC_COS_CLASS2;
  1253. if (logio->io_parameter[9] || logio->io_parameter[10])
  1254. fcport->supported_classes |= FC_COS_CLASS3;
  1255. goto logio_done;
  1256. }
  1257. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1258. iop[1] = le32_to_cpu(logio->io_parameter[1]);
  1259. switch (iop[0]) {
  1260. case LSC_SCODE_PORTID_USED:
  1261. data[0] = MBS_PORT_ID_USED;
  1262. data[1] = LSW(iop[1]);
  1263. break;
  1264. case LSC_SCODE_NPORT_USED:
  1265. data[0] = MBS_LOOP_ID_USED;
  1266. break;
  1267. default:
  1268. data[0] = MBS_COMMAND_ERROR;
  1269. break;
  1270. }
  1271. ql_dbg(ql_dbg_async, fcport->vha, 0x5037,
  1272. "Async-%s failed - hdl=%x portid=%02x%02x%02x comp=%x "
  1273. "iop0=%x iop1=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1274. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1275. le16_to_cpu(logio->comp_status),
  1276. le32_to_cpu(logio->io_parameter[0]),
  1277. le32_to_cpu(logio->io_parameter[1]));
  1278. logio_done:
  1279. sp->done(vha, sp, 0);
  1280. }
  1281. static void
  1282. qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1283. struct tsk_mgmt_entry *tsk)
  1284. {
  1285. const char func[] = "TMF-IOCB";
  1286. const char *type;
  1287. fc_port_t *fcport;
  1288. srb_t *sp;
  1289. struct srb_iocb *iocb;
  1290. struct sts_entry_24xx *sts = (struct sts_entry_24xx *)tsk;
  1291. int error = 1;
  1292. sp = qla2x00_get_sp_from_handle(vha, func, req, tsk);
  1293. if (!sp)
  1294. return;
  1295. iocb = &sp->u.iocb_cmd;
  1296. type = sp->name;
  1297. fcport = sp->fcport;
  1298. if (sts->entry_status) {
  1299. ql_log(ql_log_warn, fcport->vha, 0x5038,
  1300. "Async-%s error - hdl=%x entry-status(%x).\n",
  1301. type, sp->handle, sts->entry_status);
  1302. } else if (sts->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1303. ql_log(ql_log_warn, fcport->vha, 0x5039,
  1304. "Async-%s error - hdl=%x completion status(%x).\n",
  1305. type, sp->handle, sts->comp_status);
  1306. } else if (!(le16_to_cpu(sts->scsi_status) &
  1307. SS_RESPONSE_INFO_LEN_VALID)) {
  1308. ql_log(ql_log_warn, fcport->vha, 0x503a,
  1309. "Async-%s error - hdl=%x no response info(%x).\n",
  1310. type, sp->handle, sts->scsi_status);
  1311. } else if (le32_to_cpu(sts->rsp_data_len) < 4) {
  1312. ql_log(ql_log_warn, fcport->vha, 0x503b,
  1313. "Async-%s error - hdl=%x not enough response(%d).\n",
  1314. type, sp->handle, sts->rsp_data_len);
  1315. } else if (sts->data[3]) {
  1316. ql_log(ql_log_warn, fcport->vha, 0x503c,
  1317. "Async-%s error - hdl=%x response(%x).\n",
  1318. type, sp->handle, sts->data[3]);
  1319. } else {
  1320. error = 0;
  1321. }
  1322. if (error) {
  1323. iocb->u.tmf.data = error;
  1324. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
  1325. (uint8_t *)sts, sizeof(*sts));
  1326. }
  1327. sp->done(vha, sp, 0);
  1328. }
  1329. /**
  1330. * qla2x00_process_response_queue() - Process response queue entries.
  1331. * @ha: SCSI driver HA context
  1332. */
  1333. void
  1334. qla2x00_process_response_queue(struct rsp_que *rsp)
  1335. {
  1336. struct scsi_qla_host *vha;
  1337. struct qla_hw_data *ha = rsp->hw;
  1338. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1339. sts_entry_t *pkt;
  1340. uint16_t handle_cnt;
  1341. uint16_t cnt;
  1342. vha = pci_get_drvdata(ha->pdev);
  1343. if (!vha->flags.online)
  1344. return;
  1345. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  1346. pkt = (sts_entry_t *)rsp->ring_ptr;
  1347. rsp->ring_index++;
  1348. if (rsp->ring_index == rsp->length) {
  1349. rsp->ring_index = 0;
  1350. rsp->ring_ptr = rsp->ring;
  1351. } else {
  1352. rsp->ring_ptr++;
  1353. }
  1354. if (pkt->entry_status != 0) {
  1355. qla2x00_error_entry(vha, rsp, pkt);
  1356. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1357. wmb();
  1358. continue;
  1359. }
  1360. switch (pkt->entry_type) {
  1361. case STATUS_TYPE:
  1362. qla2x00_status_entry(vha, rsp, pkt);
  1363. break;
  1364. case STATUS_TYPE_21:
  1365. handle_cnt = ((sts21_entry_t *)pkt)->handle_count;
  1366. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1367. qla2x00_process_completed_request(vha, rsp->req,
  1368. ((sts21_entry_t *)pkt)->handle[cnt]);
  1369. }
  1370. break;
  1371. case STATUS_TYPE_22:
  1372. handle_cnt = ((sts22_entry_t *)pkt)->handle_count;
  1373. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1374. qla2x00_process_completed_request(vha, rsp->req,
  1375. ((sts22_entry_t *)pkt)->handle[cnt]);
  1376. }
  1377. break;
  1378. case STATUS_CONT_TYPE:
  1379. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  1380. break;
  1381. case MBX_IOCB_TYPE:
  1382. qla2x00_mbx_iocb_entry(vha, rsp->req,
  1383. (struct mbx_entry *)pkt);
  1384. break;
  1385. case CT_IOCB_TYPE:
  1386. qla2x00_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  1387. break;
  1388. default:
  1389. /* Type Not Supported. */
  1390. ql_log(ql_log_warn, vha, 0x504a,
  1391. "Received unknown response pkt type %x "
  1392. "entry status=%x.\n",
  1393. pkt->entry_type, pkt->entry_status);
  1394. break;
  1395. }
  1396. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1397. wmb();
  1398. }
  1399. /* Adjust ring index */
  1400. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), rsp->ring_index);
  1401. }
  1402. static inline void
  1403. qla2x00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1404. uint32_t sense_len, struct rsp_que *rsp, int res)
  1405. {
  1406. struct scsi_qla_host *vha = sp->fcport->vha;
  1407. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1408. uint32_t track_sense_len;
  1409. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1410. sense_len = SCSI_SENSE_BUFFERSIZE;
  1411. SET_CMD_SENSE_LEN(sp, sense_len);
  1412. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1413. track_sense_len = sense_len;
  1414. if (sense_len > par_sense_len)
  1415. sense_len = par_sense_len;
  1416. memcpy(cp->sense_buffer, sense_data, sense_len);
  1417. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1418. track_sense_len -= sense_len;
  1419. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1420. if (track_sense_len != 0) {
  1421. rsp->status_srb = sp;
  1422. cp->result = res;
  1423. }
  1424. if (sense_len) {
  1425. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x301c,
  1426. "Check condition Sense data, nexus%ld:%d:%d cmd=%p.\n",
  1427. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1428. cp);
  1429. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302b,
  1430. cp->sense_buffer, sense_len);
  1431. }
  1432. }
  1433. struct scsi_dif_tuple {
  1434. __be16 guard; /* Checksum */
  1435. __be16 app_tag; /* APPL identifier */
  1436. __be32 ref_tag; /* Target LBA or indirect LBA */
  1437. };
  1438. /*
  1439. * Checks the guard or meta-data for the type of error
  1440. * detected by the HBA. In case of errors, we set the
  1441. * ASC/ASCQ fields in the sense buffer with ILLEGAL_REQUEST
  1442. * to indicate to the kernel that the HBA detected error.
  1443. */
  1444. static inline int
  1445. qla2x00_handle_dif_error(srb_t *sp, struct sts_entry_24xx *sts24)
  1446. {
  1447. struct scsi_qla_host *vha = sp->fcport->vha;
  1448. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  1449. uint8_t *ap = &sts24->data[12];
  1450. uint8_t *ep = &sts24->data[20];
  1451. uint32_t e_ref_tag, a_ref_tag;
  1452. uint16_t e_app_tag, a_app_tag;
  1453. uint16_t e_guard, a_guard;
  1454. /*
  1455. * swab32 of the "data" field in the beginning of qla2x00_status_entry()
  1456. * would make guard field appear at offset 2
  1457. */
  1458. a_guard = le16_to_cpu(*(uint16_t *)(ap + 2));
  1459. a_app_tag = le16_to_cpu(*(uint16_t *)(ap + 0));
  1460. a_ref_tag = le32_to_cpu(*(uint32_t *)(ap + 4));
  1461. e_guard = le16_to_cpu(*(uint16_t *)(ep + 2));
  1462. e_app_tag = le16_to_cpu(*(uint16_t *)(ep + 0));
  1463. e_ref_tag = le32_to_cpu(*(uint32_t *)(ep + 4));
  1464. ql_dbg(ql_dbg_io, vha, 0x3023,
  1465. "iocb(s) %p Returned STATUS.\n", sts24);
  1466. ql_dbg(ql_dbg_io, vha, 0x3024,
  1467. "DIF ERROR in cmd 0x%x lba 0x%llx act ref"
  1468. " tag=0x%x, exp ref_tag=0x%x, act app tag=0x%x, exp app"
  1469. " tag=0x%x, act guard=0x%x, exp guard=0x%x.\n",
  1470. cmd->cmnd[0], (u64)scsi_get_lba(cmd), a_ref_tag, e_ref_tag,
  1471. a_app_tag, e_app_tag, a_guard, e_guard);
  1472. /*
  1473. * Ignore sector if:
  1474. * For type 3: ref & app tag is all 'f's
  1475. * For type 0,1,2: app tag is all 'f's
  1476. */
  1477. if ((a_app_tag == 0xffff) &&
  1478. ((scsi_get_prot_type(cmd) != SCSI_PROT_DIF_TYPE3) ||
  1479. (a_ref_tag == 0xffffffff))) {
  1480. uint32_t blocks_done, resid;
  1481. sector_t lba_s = scsi_get_lba(cmd);
  1482. /* 2TB boundary case covered automatically with this */
  1483. blocks_done = e_ref_tag - (uint32_t)lba_s + 1;
  1484. resid = scsi_bufflen(cmd) - (blocks_done *
  1485. cmd->device->sector_size);
  1486. scsi_set_resid(cmd, resid);
  1487. cmd->result = DID_OK << 16;
  1488. /* Update protection tag */
  1489. if (scsi_prot_sg_count(cmd)) {
  1490. uint32_t i, j = 0, k = 0, num_ent;
  1491. struct scatterlist *sg;
  1492. struct sd_dif_tuple *spt;
  1493. /* Patch the corresponding protection tags */
  1494. scsi_for_each_prot_sg(cmd, sg,
  1495. scsi_prot_sg_count(cmd), i) {
  1496. num_ent = sg_dma_len(sg) / 8;
  1497. if (k + num_ent < blocks_done) {
  1498. k += num_ent;
  1499. continue;
  1500. }
  1501. j = blocks_done - k - 1;
  1502. k = blocks_done;
  1503. break;
  1504. }
  1505. if (k != blocks_done) {
  1506. ql_log(ql_log_warn, vha, 0x302f,
  1507. "unexpected tag values tag:lba=%x:%llx)\n",
  1508. e_ref_tag, (unsigned long long)lba_s);
  1509. return 1;
  1510. }
  1511. spt = page_address(sg_page(sg)) + sg->offset;
  1512. spt += j;
  1513. spt->app_tag = 0xffff;
  1514. if (scsi_get_prot_type(cmd) == SCSI_PROT_DIF_TYPE3)
  1515. spt->ref_tag = 0xffffffff;
  1516. }
  1517. return 0;
  1518. }
  1519. /* check guard */
  1520. if (e_guard != a_guard) {
  1521. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1522. 0x10, 0x1);
  1523. set_driver_byte(cmd, DRIVER_SENSE);
  1524. set_host_byte(cmd, DID_ABORT);
  1525. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1526. return 1;
  1527. }
  1528. /* check ref tag */
  1529. if (e_ref_tag != a_ref_tag) {
  1530. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1531. 0x10, 0x3);
  1532. set_driver_byte(cmd, DRIVER_SENSE);
  1533. set_host_byte(cmd, DID_ABORT);
  1534. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1535. return 1;
  1536. }
  1537. /* check appl tag */
  1538. if (e_app_tag != a_app_tag) {
  1539. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1540. 0x10, 0x2);
  1541. set_driver_byte(cmd, DRIVER_SENSE);
  1542. set_host_byte(cmd, DID_ABORT);
  1543. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1544. return 1;
  1545. }
  1546. return 1;
  1547. }
  1548. static void
  1549. qla25xx_process_bidir_status_iocb(scsi_qla_host_t *vha, void *pkt,
  1550. struct req_que *req, uint32_t index)
  1551. {
  1552. struct qla_hw_data *ha = vha->hw;
  1553. srb_t *sp;
  1554. uint16_t comp_status;
  1555. uint16_t scsi_status;
  1556. uint16_t thread_id;
  1557. uint32_t rval = EXT_STATUS_OK;
  1558. struct fc_bsg_job *bsg_job = NULL;
  1559. sts_entry_t *sts;
  1560. struct sts_entry_24xx *sts24;
  1561. sts = (sts_entry_t *) pkt;
  1562. sts24 = (struct sts_entry_24xx *) pkt;
  1563. /* Validate handle. */
  1564. if (index >= req->num_outstanding_cmds) {
  1565. ql_log(ql_log_warn, vha, 0x70af,
  1566. "Invalid SCSI completion handle 0x%x.\n", index);
  1567. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1568. return;
  1569. }
  1570. sp = req->outstanding_cmds[index];
  1571. if (sp) {
  1572. /* Free outstanding command slot. */
  1573. req->outstanding_cmds[index] = NULL;
  1574. bsg_job = sp->u.bsg_job;
  1575. } else {
  1576. ql_log(ql_log_warn, vha, 0x70b0,
  1577. "Req:%d: Invalid ISP SCSI completion handle(0x%x)\n",
  1578. req->id, index);
  1579. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1580. return;
  1581. }
  1582. if (IS_FWI2_CAPABLE(ha)) {
  1583. comp_status = le16_to_cpu(sts24->comp_status);
  1584. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1585. } else {
  1586. comp_status = le16_to_cpu(sts->comp_status);
  1587. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1588. }
  1589. thread_id = bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  1590. switch (comp_status) {
  1591. case CS_COMPLETE:
  1592. if (scsi_status == 0) {
  1593. bsg_job->reply->reply_payload_rcv_len =
  1594. bsg_job->reply_payload.payload_len;
  1595. rval = EXT_STATUS_OK;
  1596. }
  1597. goto done;
  1598. case CS_DATA_OVERRUN:
  1599. ql_dbg(ql_dbg_user, vha, 0x70b1,
  1600. "Command completed with date overrun thread_id=%d\n",
  1601. thread_id);
  1602. rval = EXT_STATUS_DATA_OVERRUN;
  1603. break;
  1604. case CS_DATA_UNDERRUN:
  1605. ql_dbg(ql_dbg_user, vha, 0x70b2,
  1606. "Command completed with date underrun thread_id=%d\n",
  1607. thread_id);
  1608. rval = EXT_STATUS_DATA_UNDERRUN;
  1609. break;
  1610. case CS_BIDIR_RD_OVERRUN:
  1611. ql_dbg(ql_dbg_user, vha, 0x70b3,
  1612. "Command completed with read data overrun thread_id=%d\n",
  1613. thread_id);
  1614. rval = EXT_STATUS_DATA_OVERRUN;
  1615. break;
  1616. case CS_BIDIR_RD_WR_OVERRUN:
  1617. ql_dbg(ql_dbg_user, vha, 0x70b4,
  1618. "Command completed with read and write data overrun "
  1619. "thread_id=%d\n", thread_id);
  1620. rval = EXT_STATUS_DATA_OVERRUN;
  1621. break;
  1622. case CS_BIDIR_RD_OVERRUN_WR_UNDERRUN:
  1623. ql_dbg(ql_dbg_user, vha, 0x70b5,
  1624. "Command completed with read data over and write data "
  1625. "underrun thread_id=%d\n", thread_id);
  1626. rval = EXT_STATUS_DATA_OVERRUN;
  1627. break;
  1628. case CS_BIDIR_RD_UNDERRUN:
  1629. ql_dbg(ql_dbg_user, vha, 0x70b6,
  1630. "Command completed with read data data underrun "
  1631. "thread_id=%d\n", thread_id);
  1632. rval = EXT_STATUS_DATA_UNDERRUN;
  1633. break;
  1634. case CS_BIDIR_RD_UNDERRUN_WR_OVERRUN:
  1635. ql_dbg(ql_dbg_user, vha, 0x70b7,
  1636. "Command completed with read data under and write data "
  1637. "overrun thread_id=%d\n", thread_id);
  1638. rval = EXT_STATUS_DATA_UNDERRUN;
  1639. break;
  1640. case CS_BIDIR_RD_WR_UNDERRUN:
  1641. ql_dbg(ql_dbg_user, vha, 0x70b8,
  1642. "Command completed with read and write data underrun "
  1643. "thread_id=%d\n", thread_id);
  1644. rval = EXT_STATUS_DATA_UNDERRUN;
  1645. break;
  1646. case CS_BIDIR_DMA:
  1647. ql_dbg(ql_dbg_user, vha, 0x70b9,
  1648. "Command completed with data DMA error thread_id=%d\n",
  1649. thread_id);
  1650. rval = EXT_STATUS_DMA_ERR;
  1651. break;
  1652. case CS_TIMEOUT:
  1653. ql_dbg(ql_dbg_user, vha, 0x70ba,
  1654. "Command completed with timeout thread_id=%d\n",
  1655. thread_id);
  1656. rval = EXT_STATUS_TIMEOUT;
  1657. break;
  1658. default:
  1659. ql_dbg(ql_dbg_user, vha, 0x70bb,
  1660. "Command completed with completion status=0x%x "
  1661. "thread_id=%d\n", comp_status, thread_id);
  1662. rval = EXT_STATUS_ERR;
  1663. break;
  1664. }
  1665. bsg_job->reply->reply_payload_rcv_len = 0;
  1666. done:
  1667. /* Return the vendor specific reply to API */
  1668. bsg_job->reply->reply_data.vendor_reply.vendor_rsp[0] = rval;
  1669. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1670. /* Always return DID_OK, bsg will send the vendor specific response
  1671. * in this case only */
  1672. sp->done(vha, sp, (DID_OK << 6));
  1673. }
  1674. /**
  1675. * qla2x00_status_entry() - Process a Status IOCB entry.
  1676. * @ha: SCSI driver HA context
  1677. * @pkt: Entry pointer
  1678. */
  1679. static void
  1680. qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1681. {
  1682. srb_t *sp;
  1683. fc_port_t *fcport;
  1684. struct scsi_cmnd *cp;
  1685. sts_entry_t *sts;
  1686. struct sts_entry_24xx *sts24;
  1687. uint16_t comp_status;
  1688. uint16_t scsi_status;
  1689. uint16_t ox_id;
  1690. uint8_t lscsi_status;
  1691. int32_t resid;
  1692. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1693. fw_resid_len;
  1694. uint8_t *rsp_info, *sense_data;
  1695. struct qla_hw_data *ha = vha->hw;
  1696. uint32_t handle;
  1697. uint16_t que;
  1698. struct req_que *req;
  1699. int logit = 1;
  1700. int res = 0;
  1701. uint16_t state_flags = 0;
  1702. sts = (sts_entry_t *) pkt;
  1703. sts24 = (struct sts_entry_24xx *) pkt;
  1704. if (IS_FWI2_CAPABLE(ha)) {
  1705. comp_status = le16_to_cpu(sts24->comp_status);
  1706. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1707. state_flags = le16_to_cpu(sts24->state_flags);
  1708. } else {
  1709. comp_status = le16_to_cpu(sts->comp_status);
  1710. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1711. }
  1712. handle = (uint32_t) LSW(sts->handle);
  1713. que = MSW(sts->handle);
  1714. req = ha->req_q_map[que];
  1715. /* Validate handle. */
  1716. if (handle < req->num_outstanding_cmds)
  1717. sp = req->outstanding_cmds[handle];
  1718. else
  1719. sp = NULL;
  1720. if (sp == NULL) {
  1721. ql_dbg(ql_dbg_io, vha, 0x3017,
  1722. "Invalid status handle (0x%x).\n", sts->handle);
  1723. if (IS_QLA82XX(ha))
  1724. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1725. else
  1726. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1727. qla2xxx_wake_dpc(vha);
  1728. return;
  1729. }
  1730. if (unlikely((state_flags & BIT_1) && (sp->type == SRB_BIDI_CMD))) {
  1731. qla25xx_process_bidir_status_iocb(vha, pkt, req, handle);
  1732. return;
  1733. }
  1734. /* Fast path completion. */
  1735. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  1736. qla2x00_do_host_ramp_up(vha);
  1737. qla2x00_process_completed_request(vha, req, handle);
  1738. return;
  1739. }
  1740. req->outstanding_cmds[handle] = NULL;
  1741. cp = GET_CMD_SP(sp);
  1742. if (cp == NULL) {
  1743. ql_dbg(ql_dbg_io, vha, 0x3018,
  1744. "Command already returned (0x%x/%p).\n",
  1745. sts->handle, sp);
  1746. return;
  1747. }
  1748. lscsi_status = scsi_status & STATUS_MASK;
  1749. fcport = sp->fcport;
  1750. ox_id = 0;
  1751. sense_len = par_sense_len = rsp_info_len = resid_len =
  1752. fw_resid_len = 0;
  1753. if (IS_FWI2_CAPABLE(ha)) {
  1754. if (scsi_status & SS_SENSE_LEN_VALID)
  1755. sense_len = le32_to_cpu(sts24->sense_len);
  1756. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1757. rsp_info_len = le32_to_cpu(sts24->rsp_data_len);
  1758. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER))
  1759. resid_len = le32_to_cpu(sts24->rsp_residual_count);
  1760. if (comp_status == CS_DATA_UNDERRUN)
  1761. fw_resid_len = le32_to_cpu(sts24->residual_len);
  1762. rsp_info = sts24->data;
  1763. sense_data = sts24->data;
  1764. host_to_fcp_swap(sts24->data, sizeof(sts24->data));
  1765. ox_id = le16_to_cpu(sts24->ox_id);
  1766. par_sense_len = sizeof(sts24->data);
  1767. } else {
  1768. if (scsi_status & SS_SENSE_LEN_VALID)
  1769. sense_len = le16_to_cpu(sts->req_sense_length);
  1770. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1771. rsp_info_len = le16_to_cpu(sts->rsp_info_len);
  1772. resid_len = le32_to_cpu(sts->residual_length);
  1773. rsp_info = sts->rsp_info;
  1774. sense_data = sts->req_sense_data;
  1775. par_sense_len = sizeof(sts->req_sense_data);
  1776. }
  1777. /* Check for any FCP transport errors. */
  1778. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID) {
  1779. /* Sense data lies beyond any FCP RESPONSE data. */
  1780. if (IS_FWI2_CAPABLE(ha)) {
  1781. sense_data += rsp_info_len;
  1782. par_sense_len -= rsp_info_len;
  1783. }
  1784. if (rsp_info_len > 3 && rsp_info[3]) {
  1785. ql_dbg(ql_dbg_io, fcport->vha, 0x3019,
  1786. "FCP I/O protocol failure (0x%x/0x%x).\n",
  1787. rsp_info_len, rsp_info[3]);
  1788. res = DID_BUS_BUSY << 16;
  1789. goto out;
  1790. }
  1791. }
  1792. /* Check for overrun. */
  1793. if (IS_FWI2_CAPABLE(ha) && comp_status == CS_COMPLETE &&
  1794. scsi_status & SS_RESIDUAL_OVER)
  1795. comp_status = CS_DATA_OVERRUN;
  1796. /*
  1797. * Based on Host and scsi status generate status code for Linux
  1798. */
  1799. switch (comp_status) {
  1800. case CS_COMPLETE:
  1801. case CS_QUEUE_FULL:
  1802. if (scsi_status == 0) {
  1803. res = DID_OK << 16;
  1804. break;
  1805. }
  1806. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER)) {
  1807. resid = resid_len;
  1808. scsi_set_resid(cp, resid);
  1809. if (!lscsi_status &&
  1810. ((unsigned)(scsi_bufflen(cp) - resid) <
  1811. cp->underflow)) {
  1812. ql_dbg(ql_dbg_io, fcport->vha, 0x301a,
  1813. "Mid-layer underflow "
  1814. "detected (0x%x of 0x%x bytes).\n",
  1815. resid, scsi_bufflen(cp));
  1816. res = DID_ERROR << 16;
  1817. break;
  1818. }
  1819. }
  1820. res = DID_OK << 16 | lscsi_status;
  1821. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1822. ql_dbg(ql_dbg_io, fcport->vha, 0x301b,
  1823. "QUEUE FULL detected.\n");
  1824. break;
  1825. }
  1826. logit = 0;
  1827. if (lscsi_status != SS_CHECK_CONDITION)
  1828. break;
  1829. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1830. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1831. break;
  1832. qla2x00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  1833. rsp, res);
  1834. break;
  1835. case CS_DATA_UNDERRUN:
  1836. /* Use F/W calculated residual length. */
  1837. resid = IS_FWI2_CAPABLE(ha) ? fw_resid_len : resid_len;
  1838. scsi_set_resid(cp, resid);
  1839. if (scsi_status & SS_RESIDUAL_UNDER) {
  1840. if (IS_FWI2_CAPABLE(ha) && fw_resid_len != resid_len) {
  1841. ql_dbg(ql_dbg_io, fcport->vha, 0x301d,
  1842. "Dropped frame(s) detected "
  1843. "(0x%x of 0x%x bytes).\n",
  1844. resid, scsi_bufflen(cp));
  1845. res = DID_ERROR << 16 | lscsi_status;
  1846. goto check_scsi_status;
  1847. }
  1848. if (!lscsi_status &&
  1849. ((unsigned)(scsi_bufflen(cp) - resid) <
  1850. cp->underflow)) {
  1851. ql_dbg(ql_dbg_io, fcport->vha, 0x301e,
  1852. "Mid-layer underflow "
  1853. "detected (0x%x of 0x%x bytes).\n",
  1854. resid, scsi_bufflen(cp));
  1855. res = DID_ERROR << 16;
  1856. break;
  1857. }
  1858. } else if (lscsi_status != SAM_STAT_TASK_SET_FULL &&
  1859. lscsi_status != SAM_STAT_BUSY) {
  1860. /*
  1861. * scsi status of task set and busy are considered to be
  1862. * task not completed.
  1863. */
  1864. ql_dbg(ql_dbg_io, fcport->vha, 0x301f,
  1865. "Dropped frame(s) detected (0x%x "
  1866. "of 0x%x bytes).\n", resid,
  1867. scsi_bufflen(cp));
  1868. res = DID_ERROR << 16 | lscsi_status;
  1869. goto check_scsi_status;
  1870. } else {
  1871. ql_dbg(ql_dbg_io, fcport->vha, 0x3030,
  1872. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  1873. scsi_status, lscsi_status);
  1874. }
  1875. res = DID_OK << 16 | lscsi_status;
  1876. logit = 0;
  1877. check_scsi_status:
  1878. /*
  1879. * Check to see if SCSI Status is non zero. If so report SCSI
  1880. * Status.
  1881. */
  1882. if (lscsi_status != 0) {
  1883. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1884. ql_dbg(ql_dbg_io, fcport->vha, 0x3020,
  1885. "QUEUE FULL detected.\n");
  1886. logit = 1;
  1887. break;
  1888. }
  1889. if (lscsi_status != SS_CHECK_CONDITION)
  1890. break;
  1891. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1892. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1893. break;
  1894. qla2x00_handle_sense(sp, sense_data, par_sense_len,
  1895. sense_len, rsp, res);
  1896. }
  1897. break;
  1898. case CS_PORT_LOGGED_OUT:
  1899. case CS_PORT_CONFIG_CHG:
  1900. case CS_PORT_BUSY:
  1901. case CS_INCOMPLETE:
  1902. case CS_PORT_UNAVAILABLE:
  1903. case CS_TIMEOUT:
  1904. case CS_RESET:
  1905. /*
  1906. * We are going to have the fc class block the rport
  1907. * while we try to recover so instruct the mid layer
  1908. * to requeue until the class decides how to handle this.
  1909. */
  1910. res = DID_TRANSPORT_DISRUPTED << 16;
  1911. if (comp_status == CS_TIMEOUT) {
  1912. if (IS_FWI2_CAPABLE(ha))
  1913. break;
  1914. else if ((le16_to_cpu(sts->status_flags) &
  1915. SF_LOGOUT_SENT) == 0)
  1916. break;
  1917. }
  1918. ql_dbg(ql_dbg_io, fcport->vha, 0x3021,
  1919. "Port down status: port-state=0x%x.\n",
  1920. atomic_read(&fcport->state));
  1921. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1922. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  1923. break;
  1924. case CS_ABORTED:
  1925. res = DID_RESET << 16;
  1926. break;
  1927. case CS_DIF_ERROR:
  1928. logit = qla2x00_handle_dif_error(sp, sts24);
  1929. res = cp->result;
  1930. break;
  1931. case CS_TRANSPORT:
  1932. res = DID_ERROR << 16;
  1933. if (!IS_PI_SPLIT_DET_CAPABLE(ha))
  1934. break;
  1935. if (state_flags & BIT_4)
  1936. scmd_printk(KERN_WARNING, cp,
  1937. "Unsupported device '%s' found.\n",
  1938. cp->device->vendor);
  1939. break;
  1940. default:
  1941. res = DID_ERROR << 16;
  1942. break;
  1943. }
  1944. out:
  1945. if (logit)
  1946. ql_dbg(ql_dbg_io, fcport->vha, 0x3022,
  1947. "FCP command status: 0x%x-0x%x (0x%x) "
  1948. "nexus=%ld:%d:%d portid=%02x%02x%02x oxid=0x%x "
  1949. "cdb=%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x len=0x%x "
  1950. "rsp_info=0x%x resid=0x%x fw_resid=0x%x.\n",
  1951. comp_status, scsi_status, res, vha->host_no,
  1952. cp->device->id, cp->device->lun, fcport->d_id.b.domain,
  1953. fcport->d_id.b.area, fcport->d_id.b.al_pa, ox_id,
  1954. cp->cmnd[0], cp->cmnd[1], cp->cmnd[2], cp->cmnd[3],
  1955. cp->cmnd[4], cp->cmnd[5], cp->cmnd[6], cp->cmnd[7],
  1956. cp->cmnd[8], cp->cmnd[9], scsi_bufflen(cp), rsp_info_len,
  1957. resid_len, fw_resid_len);
  1958. if (!res)
  1959. qla2x00_do_host_ramp_up(vha);
  1960. if (rsp->status_srb == NULL)
  1961. sp->done(ha, sp, res);
  1962. }
  1963. /**
  1964. * qla2x00_status_cont_entry() - Process a Status Continuations entry.
  1965. * @ha: SCSI driver HA context
  1966. * @pkt: Entry pointer
  1967. *
  1968. * Extended sense data.
  1969. */
  1970. static void
  1971. qla2x00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  1972. {
  1973. uint8_t sense_sz = 0;
  1974. struct qla_hw_data *ha = rsp->hw;
  1975. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  1976. srb_t *sp = rsp->status_srb;
  1977. struct scsi_cmnd *cp;
  1978. uint32_t sense_len;
  1979. uint8_t *sense_ptr;
  1980. if (!sp || !GET_CMD_SENSE_LEN(sp))
  1981. return;
  1982. sense_len = GET_CMD_SENSE_LEN(sp);
  1983. sense_ptr = GET_CMD_SENSE_PTR(sp);
  1984. cp = GET_CMD_SP(sp);
  1985. if (cp == NULL) {
  1986. ql_log(ql_log_warn, vha, 0x3025,
  1987. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  1988. rsp->status_srb = NULL;
  1989. return;
  1990. }
  1991. if (sense_len > sizeof(pkt->data))
  1992. sense_sz = sizeof(pkt->data);
  1993. else
  1994. sense_sz = sense_len;
  1995. /* Move sense data. */
  1996. if (IS_FWI2_CAPABLE(ha))
  1997. host_to_fcp_swap(pkt->data, sizeof(pkt->data));
  1998. memcpy(sense_ptr, pkt->data, sense_sz);
  1999. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302c,
  2000. sense_ptr, sense_sz);
  2001. sense_len -= sense_sz;
  2002. sense_ptr += sense_sz;
  2003. SET_CMD_SENSE_PTR(sp, sense_ptr);
  2004. SET_CMD_SENSE_LEN(sp, sense_len);
  2005. /* Place command on done queue. */
  2006. if (sense_len == 0) {
  2007. rsp->status_srb = NULL;
  2008. sp->done(ha, sp, cp->result);
  2009. }
  2010. }
  2011. /**
  2012. * qla2x00_error_entry() - Process an error entry.
  2013. * @ha: SCSI driver HA context
  2014. * @pkt: Entry pointer
  2015. */
  2016. static void
  2017. qla2x00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, sts_entry_t *pkt)
  2018. {
  2019. srb_t *sp;
  2020. struct qla_hw_data *ha = vha->hw;
  2021. const char func[] = "ERROR-IOCB";
  2022. uint16_t que = MSW(pkt->handle);
  2023. struct req_que *req = NULL;
  2024. int res = DID_ERROR << 16;
  2025. ql_dbg(ql_dbg_async, vha, 0x502a,
  2026. "type of error status in response: 0x%x\n", pkt->entry_status);
  2027. if (que >= ha->max_req_queues || !ha->req_q_map[que])
  2028. goto fatal;
  2029. req = ha->req_q_map[que];
  2030. if (pkt->entry_status & RF_BUSY)
  2031. res = DID_BUS_BUSY << 16;
  2032. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2033. if (sp) {
  2034. sp->done(ha, sp, res);
  2035. return;
  2036. }
  2037. fatal:
  2038. ql_log(ql_log_warn, vha, 0x5030,
  2039. "Error entry - invalid handle/queue.\n");
  2040. if (IS_QLA82XX(ha))
  2041. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  2042. else
  2043. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2044. qla2xxx_wake_dpc(vha);
  2045. }
  2046. /**
  2047. * qla24xx_mbx_completion() - Process mailbox command completions.
  2048. * @ha: SCSI driver HA context
  2049. * @mb0: Mailbox0 register
  2050. */
  2051. static void
  2052. qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  2053. {
  2054. uint16_t cnt;
  2055. uint32_t mboxes;
  2056. uint16_t __iomem *wptr;
  2057. struct qla_hw_data *ha = vha->hw;
  2058. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2059. /* Read all mbox registers? */
  2060. mboxes = (1 << ha->mbx_count) - 1;
  2061. if (!ha->mcp)
  2062. ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERROR.\n");
  2063. else
  2064. mboxes = ha->mcp->in_mb;
  2065. /* Load return mailbox registers. */
  2066. ha->flags.mbox_int = 1;
  2067. ha->mailbox_out[0] = mb0;
  2068. mboxes >>= 1;
  2069. wptr = (uint16_t __iomem *)&reg->mailbox1;
  2070. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2071. if (mboxes & BIT_0)
  2072. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  2073. mboxes >>= 1;
  2074. wptr++;
  2075. }
  2076. }
  2077. /**
  2078. * qla24xx_process_response_queue() - Process response queue entries.
  2079. * @ha: SCSI driver HA context
  2080. */
  2081. void qla24xx_process_response_queue(struct scsi_qla_host *vha,
  2082. struct rsp_que *rsp)
  2083. {
  2084. struct sts_entry_24xx *pkt;
  2085. struct qla_hw_data *ha = vha->hw;
  2086. if (!vha->flags.online)
  2087. return;
  2088. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  2089. pkt = (struct sts_entry_24xx *)rsp->ring_ptr;
  2090. rsp->ring_index++;
  2091. if (rsp->ring_index == rsp->length) {
  2092. rsp->ring_index = 0;
  2093. rsp->ring_ptr = rsp->ring;
  2094. } else {
  2095. rsp->ring_ptr++;
  2096. }
  2097. if (pkt->entry_status != 0) {
  2098. qla2x00_error_entry(vha, rsp, (sts_entry_t *) pkt);
  2099. (void)qlt_24xx_process_response_error(vha, pkt);
  2100. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2101. wmb();
  2102. continue;
  2103. }
  2104. switch (pkt->entry_type) {
  2105. case STATUS_TYPE:
  2106. qla2x00_status_entry(vha, rsp, pkt);
  2107. break;
  2108. case STATUS_CONT_TYPE:
  2109. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2110. break;
  2111. case VP_RPT_ID_IOCB_TYPE:
  2112. qla24xx_report_id_acquisition(vha,
  2113. (struct vp_rpt_id_entry_24xx *)pkt);
  2114. break;
  2115. case LOGINOUT_PORT_IOCB_TYPE:
  2116. qla24xx_logio_entry(vha, rsp->req,
  2117. (struct logio_entry_24xx *)pkt);
  2118. break;
  2119. case TSK_MGMT_IOCB_TYPE:
  2120. qla24xx_tm_iocb_entry(vha, rsp->req,
  2121. (struct tsk_mgmt_entry *)pkt);
  2122. break;
  2123. case CT_IOCB_TYPE:
  2124. qla24xx_els_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  2125. break;
  2126. case ELS_IOCB_TYPE:
  2127. qla24xx_els_ct_entry(vha, rsp->req, pkt, ELS_IOCB_TYPE);
  2128. break;
  2129. case ABTS_RECV_24XX:
  2130. /* ensure that the ATIO queue is empty */
  2131. qlt_24xx_process_atio_queue(vha);
  2132. case ABTS_RESP_24XX:
  2133. case CTIO_TYPE7:
  2134. case NOTIFY_ACK_TYPE:
  2135. qlt_response_pkt_all_vps(vha, (response_t *)pkt);
  2136. break;
  2137. case MARKER_TYPE:
  2138. /* Do nothing in this case, this check is to prevent it
  2139. * from falling into default case
  2140. */
  2141. break;
  2142. default:
  2143. /* Type Not Supported. */
  2144. ql_dbg(ql_dbg_async, vha, 0x5042,
  2145. "Received unknown response pkt type %x "
  2146. "entry status=%x.\n",
  2147. pkt->entry_type, pkt->entry_status);
  2148. break;
  2149. }
  2150. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2151. wmb();
  2152. }
  2153. /* Adjust ring index */
  2154. if (IS_QLA82XX(ha)) {
  2155. struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
  2156. WRT_REG_DWORD(&reg->rsp_q_out[0], rsp->ring_index);
  2157. } else
  2158. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2159. }
  2160. static void
  2161. qla2xxx_check_risc_status(scsi_qla_host_t *vha)
  2162. {
  2163. int rval;
  2164. uint32_t cnt;
  2165. struct qla_hw_data *ha = vha->hw;
  2166. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2167. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
  2168. return;
  2169. rval = QLA_SUCCESS;
  2170. WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
  2171. RD_REG_DWORD(&reg->iobase_addr);
  2172. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2173. for (cnt = 10000; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2174. rval == QLA_SUCCESS; cnt--) {
  2175. if (cnt) {
  2176. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2177. udelay(10);
  2178. } else
  2179. rval = QLA_FUNCTION_TIMEOUT;
  2180. }
  2181. if (rval == QLA_SUCCESS)
  2182. goto next_test;
  2183. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2184. for (cnt = 100; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2185. rval == QLA_SUCCESS; cnt--) {
  2186. if (cnt) {
  2187. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2188. udelay(10);
  2189. } else
  2190. rval = QLA_FUNCTION_TIMEOUT;
  2191. }
  2192. if (rval != QLA_SUCCESS)
  2193. goto done;
  2194. next_test:
  2195. if (RD_REG_DWORD(&reg->iobase_c8) & BIT_3)
  2196. ql_log(ql_log_info, vha, 0x504c,
  2197. "Additional code -- 0x55AA.\n");
  2198. done:
  2199. WRT_REG_DWORD(&reg->iobase_window, 0x0000);
  2200. RD_REG_DWORD(&reg->iobase_window);
  2201. }
  2202. /**
  2203. * qla24xx_intr_handler() - Process interrupts for the ISP23xx and ISP24xx.
  2204. * @irq:
  2205. * @dev_id: SCSI driver HA context
  2206. *
  2207. * Called by system whenever the host adapter generates an interrupt.
  2208. *
  2209. * Returns handled flag.
  2210. */
  2211. irqreturn_t
  2212. qla24xx_intr_handler(int irq, void *dev_id)
  2213. {
  2214. scsi_qla_host_t *vha;
  2215. struct qla_hw_data *ha;
  2216. struct device_reg_24xx __iomem *reg;
  2217. int status;
  2218. unsigned long iter;
  2219. uint32_t stat;
  2220. uint32_t hccr;
  2221. uint16_t mb[8];
  2222. struct rsp_que *rsp;
  2223. unsigned long flags;
  2224. rsp = (struct rsp_que *) dev_id;
  2225. if (!rsp) {
  2226. ql_log(ql_log_info, NULL, 0x5059,
  2227. "%s: NULL response queue pointer.\n", __func__);
  2228. return IRQ_NONE;
  2229. }
  2230. ha = rsp->hw;
  2231. reg = &ha->iobase->isp24;
  2232. status = 0;
  2233. if (unlikely(pci_channel_offline(ha->pdev)))
  2234. return IRQ_HANDLED;
  2235. spin_lock_irqsave(&ha->hardware_lock, flags);
  2236. vha = pci_get_drvdata(ha->pdev);
  2237. for (iter = 50; iter--; ) {
  2238. stat = RD_REG_DWORD(&reg->host_status);
  2239. if (stat & HSRX_RISC_PAUSED) {
  2240. if (unlikely(pci_channel_offline(ha->pdev)))
  2241. break;
  2242. hccr = RD_REG_DWORD(&reg->hccr);
  2243. ql_log(ql_log_warn, vha, 0x504b,
  2244. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2245. hccr);
  2246. qla2xxx_check_risc_status(vha);
  2247. ha->isp_ops->fw_dump(vha, 1);
  2248. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2249. break;
  2250. } else if ((stat & HSRX_RISC_INT) == 0)
  2251. break;
  2252. switch (stat & 0xff) {
  2253. case INTR_ROM_MB_SUCCESS:
  2254. case INTR_ROM_MB_FAILED:
  2255. case INTR_MB_SUCCESS:
  2256. case INTR_MB_FAILED:
  2257. qla24xx_mbx_completion(vha, MSW(stat));
  2258. status |= MBX_INTERRUPT;
  2259. break;
  2260. case INTR_ASYNC_EVENT:
  2261. mb[0] = MSW(stat);
  2262. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2263. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2264. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2265. qla2x00_async_event(vha, rsp, mb);
  2266. break;
  2267. case INTR_RSP_QUE_UPDATE:
  2268. case INTR_RSP_QUE_UPDATE_83XX:
  2269. qla24xx_process_response_queue(vha, rsp);
  2270. break;
  2271. case INTR_ATIO_QUE_UPDATE:
  2272. qlt_24xx_process_atio_queue(vha);
  2273. break;
  2274. case INTR_ATIO_RSP_QUE_UPDATE:
  2275. qlt_24xx_process_atio_queue(vha);
  2276. qla24xx_process_response_queue(vha, rsp);
  2277. break;
  2278. default:
  2279. ql_dbg(ql_dbg_async, vha, 0x504f,
  2280. "Unrecognized interrupt type (%d).\n", stat * 0xff);
  2281. break;
  2282. }
  2283. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2284. RD_REG_DWORD_RELAXED(&reg->hccr);
  2285. if (unlikely(IS_QLA83XX(ha) && (ha->pdev->revision == 1)))
  2286. ndelay(3500);
  2287. }
  2288. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2289. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  2290. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  2291. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  2292. complete(&ha->mbx_intr_comp);
  2293. }
  2294. return IRQ_HANDLED;
  2295. }
  2296. static irqreturn_t
  2297. qla24xx_msix_rsp_q(int irq, void *dev_id)
  2298. {
  2299. struct qla_hw_data *ha;
  2300. struct rsp_que *rsp;
  2301. struct device_reg_24xx __iomem *reg;
  2302. struct scsi_qla_host *vha;
  2303. unsigned long flags;
  2304. rsp = (struct rsp_que *) dev_id;
  2305. if (!rsp) {
  2306. ql_log(ql_log_info, NULL, 0x505a,
  2307. "%s: NULL response queue pointer.\n", __func__);
  2308. return IRQ_NONE;
  2309. }
  2310. ha = rsp->hw;
  2311. reg = &ha->iobase->isp24;
  2312. spin_lock_irqsave(&ha->hardware_lock, flags);
  2313. vha = pci_get_drvdata(ha->pdev);
  2314. qla24xx_process_response_queue(vha, rsp);
  2315. if (!ha->flags.disable_msix_handshake) {
  2316. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2317. RD_REG_DWORD_RELAXED(&reg->hccr);
  2318. }
  2319. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2320. return IRQ_HANDLED;
  2321. }
  2322. static irqreturn_t
  2323. qla25xx_msix_rsp_q(int irq, void *dev_id)
  2324. {
  2325. struct qla_hw_data *ha;
  2326. struct rsp_que *rsp;
  2327. struct device_reg_24xx __iomem *reg;
  2328. unsigned long flags;
  2329. rsp = (struct rsp_que *) dev_id;
  2330. if (!rsp) {
  2331. ql_log(ql_log_info, NULL, 0x505b,
  2332. "%s: NULL response queue pointer.\n", __func__);
  2333. return IRQ_NONE;
  2334. }
  2335. ha = rsp->hw;
  2336. /* Clear the interrupt, if enabled, for this response queue */
  2337. if (!ha->flags.disable_msix_handshake) {
  2338. reg = &ha->iobase->isp24;
  2339. spin_lock_irqsave(&ha->hardware_lock, flags);
  2340. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2341. RD_REG_DWORD_RELAXED(&reg->hccr);
  2342. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2343. }
  2344. queue_work_on((int) (rsp->id - 1), ha->wq, &rsp->q_work);
  2345. return IRQ_HANDLED;
  2346. }
  2347. static irqreturn_t
  2348. qla24xx_msix_default(int irq, void *dev_id)
  2349. {
  2350. scsi_qla_host_t *vha;
  2351. struct qla_hw_data *ha;
  2352. struct rsp_que *rsp;
  2353. struct device_reg_24xx __iomem *reg;
  2354. int status;
  2355. uint32_t stat;
  2356. uint32_t hccr;
  2357. uint16_t mb[8];
  2358. unsigned long flags;
  2359. rsp = (struct rsp_que *) dev_id;
  2360. if (!rsp) {
  2361. ql_log(ql_log_info, NULL, 0x505c,
  2362. "%s: NULL response queue pointer.\n", __func__);
  2363. return IRQ_NONE;
  2364. }
  2365. ha = rsp->hw;
  2366. reg = &ha->iobase->isp24;
  2367. status = 0;
  2368. spin_lock_irqsave(&ha->hardware_lock, flags);
  2369. vha = pci_get_drvdata(ha->pdev);
  2370. do {
  2371. stat = RD_REG_DWORD(&reg->host_status);
  2372. if (stat & HSRX_RISC_PAUSED) {
  2373. if (unlikely(pci_channel_offline(ha->pdev)))
  2374. break;
  2375. hccr = RD_REG_DWORD(&reg->hccr);
  2376. ql_log(ql_log_info, vha, 0x5050,
  2377. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2378. hccr);
  2379. qla2xxx_check_risc_status(vha);
  2380. ha->isp_ops->fw_dump(vha, 1);
  2381. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2382. break;
  2383. } else if ((stat & HSRX_RISC_INT) == 0)
  2384. break;
  2385. switch (stat & 0xff) {
  2386. case INTR_ROM_MB_SUCCESS:
  2387. case INTR_ROM_MB_FAILED:
  2388. case INTR_MB_SUCCESS:
  2389. case INTR_MB_FAILED:
  2390. qla24xx_mbx_completion(vha, MSW(stat));
  2391. status |= MBX_INTERRUPT;
  2392. break;
  2393. case INTR_ASYNC_EVENT:
  2394. mb[0] = MSW(stat);
  2395. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2396. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2397. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2398. qla2x00_async_event(vha, rsp, mb);
  2399. break;
  2400. case INTR_RSP_QUE_UPDATE:
  2401. case INTR_RSP_QUE_UPDATE_83XX:
  2402. qla24xx_process_response_queue(vha, rsp);
  2403. break;
  2404. case INTR_ATIO_QUE_UPDATE:
  2405. qlt_24xx_process_atio_queue(vha);
  2406. break;
  2407. case INTR_ATIO_RSP_QUE_UPDATE:
  2408. qlt_24xx_process_atio_queue(vha);
  2409. qla24xx_process_response_queue(vha, rsp);
  2410. break;
  2411. default:
  2412. ql_dbg(ql_dbg_async, vha, 0x5051,
  2413. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  2414. break;
  2415. }
  2416. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2417. } while (0);
  2418. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2419. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  2420. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  2421. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  2422. complete(&ha->mbx_intr_comp);
  2423. }
  2424. return IRQ_HANDLED;
  2425. }
  2426. /* Interrupt handling helpers. */
  2427. struct qla_init_msix_entry {
  2428. const char *name;
  2429. irq_handler_t handler;
  2430. };
  2431. static struct qla_init_msix_entry msix_entries[3] = {
  2432. { "qla2xxx (default)", qla24xx_msix_default },
  2433. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2434. { "qla2xxx (multiq)", qla25xx_msix_rsp_q },
  2435. };
  2436. static struct qla_init_msix_entry qla82xx_msix_entries[2] = {
  2437. { "qla2xxx (default)", qla82xx_msix_default },
  2438. { "qla2xxx (rsp_q)", qla82xx_msix_rsp_q },
  2439. };
  2440. static struct qla_init_msix_entry qla83xx_msix_entries[3] = {
  2441. { "qla2xxx (default)", qla24xx_msix_default },
  2442. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2443. { "qla2xxx (atio_q)", qla83xx_msix_atio_q },
  2444. };
  2445. static void
  2446. qla24xx_disable_msix(struct qla_hw_data *ha)
  2447. {
  2448. int i;
  2449. struct qla_msix_entry *qentry;
  2450. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2451. for (i = 0; i < ha->msix_count; i++) {
  2452. qentry = &ha->msix_entries[i];
  2453. if (qentry->have_irq)
  2454. free_irq(qentry->vector, qentry->rsp);
  2455. }
  2456. pci_disable_msix(ha->pdev);
  2457. kfree(ha->msix_entries);
  2458. ha->msix_entries = NULL;
  2459. ha->flags.msix_enabled = 0;
  2460. ql_dbg(ql_dbg_init, vha, 0x0042,
  2461. "Disabled the MSI.\n");
  2462. }
  2463. static int
  2464. qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp)
  2465. {
  2466. #define MIN_MSIX_COUNT 2
  2467. int i, ret;
  2468. struct msix_entry *entries;
  2469. struct qla_msix_entry *qentry;
  2470. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2471. entries = kzalloc(sizeof(struct msix_entry) * ha->msix_count,
  2472. GFP_KERNEL);
  2473. if (!entries) {
  2474. ql_log(ql_log_warn, vha, 0x00bc,
  2475. "Failed to allocate memory for msix_entry.\n");
  2476. return -ENOMEM;
  2477. }
  2478. for (i = 0; i < ha->msix_count; i++)
  2479. entries[i].entry = i;
  2480. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2481. if (ret) {
  2482. if (ret < MIN_MSIX_COUNT)
  2483. goto msix_failed;
  2484. ql_log(ql_log_warn, vha, 0x00c6,
  2485. "MSI-X: Failed to enable support "
  2486. "-- %d/%d\n Retry with %d vectors.\n",
  2487. ha->msix_count, ret, ret);
  2488. ha->msix_count = ret;
  2489. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2490. if (ret) {
  2491. msix_failed:
  2492. ql_log(ql_log_fatal, vha, 0x00c7,
  2493. "MSI-X: Failed to enable support, "
  2494. "giving up -- %d/%d.\n",
  2495. ha->msix_count, ret);
  2496. goto msix_out;
  2497. }
  2498. ha->max_rsp_queues = ha->msix_count - 1;
  2499. }
  2500. ha->msix_entries = kzalloc(sizeof(struct qla_msix_entry) *
  2501. ha->msix_count, GFP_KERNEL);
  2502. if (!ha->msix_entries) {
  2503. ql_log(ql_log_fatal, vha, 0x00c8,
  2504. "Failed to allocate memory for ha->msix_entries.\n");
  2505. ret = -ENOMEM;
  2506. goto msix_out;
  2507. }
  2508. ha->flags.msix_enabled = 1;
  2509. for (i = 0; i < ha->msix_count; i++) {
  2510. qentry = &ha->msix_entries[i];
  2511. qentry->vector = entries[i].vector;
  2512. qentry->entry = entries[i].entry;
  2513. qentry->have_irq = 0;
  2514. qentry->rsp = NULL;
  2515. }
  2516. /* Enable MSI-X vectors for the base queue */
  2517. for (i = 0; i < ha->msix_count; i++) {
  2518. qentry = &ha->msix_entries[i];
  2519. if (QLA_TGT_MODE_ENABLED() && IS_ATIO_MSIX_CAPABLE(ha)) {
  2520. ret = request_irq(qentry->vector,
  2521. qla83xx_msix_entries[i].handler,
  2522. 0, qla83xx_msix_entries[i].name, rsp);
  2523. } else if (IS_QLA82XX(ha)) {
  2524. ret = request_irq(qentry->vector,
  2525. qla82xx_msix_entries[i].handler,
  2526. 0, qla82xx_msix_entries[i].name, rsp);
  2527. } else {
  2528. ret = request_irq(qentry->vector,
  2529. msix_entries[i].handler,
  2530. 0, msix_entries[i].name, rsp);
  2531. }
  2532. if (ret) {
  2533. ql_log(ql_log_fatal, vha, 0x00cb,
  2534. "MSI-X: unable to register handler -- %x/%d.\n",
  2535. qentry->vector, ret);
  2536. qla24xx_disable_msix(ha);
  2537. ha->mqenable = 0;
  2538. goto msix_out;
  2539. }
  2540. qentry->have_irq = 1;
  2541. qentry->rsp = rsp;
  2542. rsp->msix = qentry;
  2543. }
  2544. /* Enable MSI-X vector for response queue update for queue 0 */
  2545. if (IS_QLA83XX(ha)) {
  2546. if (ha->msixbase && ha->mqiobase &&
  2547. (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2548. ha->mqenable = 1;
  2549. } else
  2550. if (ha->mqiobase
  2551. && (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2552. ha->mqenable = 1;
  2553. ql_dbg(ql_dbg_multiq, vha, 0xc005,
  2554. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2555. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2556. ql_dbg(ql_dbg_init, vha, 0x0055,
  2557. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2558. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2559. msix_out:
  2560. kfree(entries);
  2561. return ret;
  2562. }
  2563. int
  2564. qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
  2565. {
  2566. int ret;
  2567. device_reg_t __iomem *reg = ha->iobase;
  2568. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2569. /* If possible, enable MSI-X. */
  2570. if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2571. !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
  2572. goto skip_msi;
  2573. if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  2574. (ha->pdev->subsystem_device == 0x7040 ||
  2575. ha->pdev->subsystem_device == 0x7041 ||
  2576. ha->pdev->subsystem_device == 0x1705)) {
  2577. ql_log(ql_log_warn, vha, 0x0034,
  2578. "MSI-X: Unsupported ISP 2432 SSVID/SSDID (0x%X,0x%X).\n",
  2579. ha->pdev->subsystem_vendor,
  2580. ha->pdev->subsystem_device);
  2581. goto skip_msi;
  2582. }
  2583. if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX)) {
  2584. ql_log(ql_log_warn, vha, 0x0035,
  2585. "MSI-X; Unsupported ISP2432 (0x%X, 0x%X).\n",
  2586. ha->pdev->revision, QLA_MSIX_CHIP_REV_24XX);
  2587. goto skip_msix;
  2588. }
  2589. ret = qla24xx_enable_msix(ha, rsp);
  2590. if (!ret) {
  2591. ql_dbg(ql_dbg_init, vha, 0x0036,
  2592. "MSI-X: Enabled (0x%X, 0x%X).\n",
  2593. ha->chip_revision, ha->fw_attributes);
  2594. goto clear_risc_ints;
  2595. }
  2596. ql_log(ql_log_info, vha, 0x0037,
  2597. "MSI-X Falling back-to MSI mode -%d.\n", ret);
  2598. skip_msix:
  2599. if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2600. !IS_QLA8001(ha) && !IS_QLA82XX(ha))
  2601. goto skip_msi;
  2602. ret = pci_enable_msi(ha->pdev);
  2603. if (!ret) {
  2604. ql_dbg(ql_dbg_init, vha, 0x0038,
  2605. "MSI: Enabled.\n");
  2606. ha->flags.msi_enabled = 1;
  2607. } else
  2608. ql_log(ql_log_warn, vha, 0x0039,
  2609. "MSI-X; Falling back-to INTa mode -- %d.\n", ret);
  2610. /* Skip INTx on ISP82xx. */
  2611. if (!ha->flags.msi_enabled && IS_QLA82XX(ha))
  2612. return QLA_FUNCTION_FAILED;
  2613. skip_msi:
  2614. ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler,
  2615. ha->flags.msi_enabled ? 0 : IRQF_SHARED,
  2616. QLA2XXX_DRIVER_NAME, rsp);
  2617. if (ret) {
  2618. ql_log(ql_log_warn, vha, 0x003a,
  2619. "Failed to reserve interrupt %d already in use.\n",
  2620. ha->pdev->irq);
  2621. goto fail;
  2622. } else if (!ha->flags.msi_enabled)
  2623. ql_dbg(ql_dbg_init, vha, 0x0125,
  2624. "INTa mode: Enabled.\n");
  2625. clear_risc_ints:
  2626. spin_lock_irq(&ha->hardware_lock);
  2627. if (!IS_FWI2_CAPABLE(ha))
  2628. WRT_REG_WORD(&reg->isp.semaphore, 0);
  2629. spin_unlock_irq(&ha->hardware_lock);
  2630. fail:
  2631. return ret;
  2632. }
  2633. void
  2634. qla2x00_free_irqs(scsi_qla_host_t *vha)
  2635. {
  2636. struct qla_hw_data *ha = vha->hw;
  2637. struct rsp_que *rsp;
  2638. /*
  2639. * We need to check that ha->rsp_q_map is valid in case we are called
  2640. * from a probe failure context.
  2641. */
  2642. if (!ha->rsp_q_map || !ha->rsp_q_map[0])
  2643. return;
  2644. rsp = ha->rsp_q_map[0];
  2645. if (ha->flags.msix_enabled)
  2646. qla24xx_disable_msix(ha);
  2647. else if (ha->flags.msi_enabled) {
  2648. free_irq(ha->pdev->irq, rsp);
  2649. pci_disable_msi(ha->pdev);
  2650. } else
  2651. free_irq(ha->pdev->irq, rsp);
  2652. }
  2653. int qla25xx_request_irq(struct rsp_que *rsp)
  2654. {
  2655. struct qla_hw_data *ha = rsp->hw;
  2656. struct qla_init_msix_entry *intr = &msix_entries[2];
  2657. struct qla_msix_entry *msix = rsp->msix;
  2658. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2659. int ret;
  2660. ret = request_irq(msix->vector, intr->handler, 0, intr->name, rsp);
  2661. if (ret) {
  2662. ql_log(ql_log_fatal, vha, 0x00e6,
  2663. "MSI-X: Unable to register handler -- %x/%d.\n",
  2664. msix->vector, ret);
  2665. return ret;
  2666. }
  2667. msix->have_irq = 1;
  2668. msix->rsp = rsp;
  2669. return ret;
  2670. }