qla_def.h 92 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #ifndef __QLA_DEF_H
  8. #define __QLA_DEF_H
  9. #include <linux/kernel.h>
  10. #include <linux/init.h>
  11. #include <linux/types.h>
  12. #include <linux/module.h>
  13. #include <linux/list.h>
  14. #include <linux/pci.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/sched.h>
  17. #include <linux/slab.h>
  18. #include <linux/dmapool.h>
  19. #include <linux/mempool.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/completion.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/workqueue.h>
  24. #include <linux/firmware.h>
  25. #include <linux/aer.h>
  26. #include <linux/mutex.h>
  27. #include <scsi/scsi.h>
  28. #include <scsi/scsi_host.h>
  29. #include <scsi/scsi_device.h>
  30. #include <scsi/scsi_cmnd.h>
  31. #include <scsi/scsi_transport_fc.h>
  32. #include <scsi/scsi_bsg_fc.h>
  33. #include "qla_bsg.h"
  34. #include "qla_nx.h"
  35. #define QLA2XXX_DRIVER_NAME "qla2xxx"
  36. #define QLA2XXX_APIDEV "ql2xapidev"
  37. #define QLA2XXX_MANUFACTURER "QLogic Corporation"
  38. /*
  39. * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
  40. * but that's fine as we don't look at the last 24 ones for
  41. * ISP2100 HBAs.
  42. */
  43. #define MAILBOX_REGISTER_COUNT_2100 8
  44. #define MAILBOX_REGISTER_COUNT_2200 24
  45. #define MAILBOX_REGISTER_COUNT 32
  46. #define QLA2200A_RISC_ROM_VER 4
  47. #define FPM_2300 6
  48. #define FPM_2310 7
  49. #include "qla_settings.h"
  50. /*
  51. * Data bit definitions
  52. */
  53. #define BIT_0 0x1
  54. #define BIT_1 0x2
  55. #define BIT_2 0x4
  56. #define BIT_3 0x8
  57. #define BIT_4 0x10
  58. #define BIT_5 0x20
  59. #define BIT_6 0x40
  60. #define BIT_7 0x80
  61. #define BIT_8 0x100
  62. #define BIT_9 0x200
  63. #define BIT_10 0x400
  64. #define BIT_11 0x800
  65. #define BIT_12 0x1000
  66. #define BIT_13 0x2000
  67. #define BIT_14 0x4000
  68. #define BIT_15 0x8000
  69. #define BIT_16 0x10000
  70. #define BIT_17 0x20000
  71. #define BIT_18 0x40000
  72. #define BIT_19 0x80000
  73. #define BIT_20 0x100000
  74. #define BIT_21 0x200000
  75. #define BIT_22 0x400000
  76. #define BIT_23 0x800000
  77. #define BIT_24 0x1000000
  78. #define BIT_25 0x2000000
  79. #define BIT_26 0x4000000
  80. #define BIT_27 0x8000000
  81. #define BIT_28 0x10000000
  82. #define BIT_29 0x20000000
  83. #define BIT_30 0x40000000
  84. #define BIT_31 0x80000000
  85. #define LSB(x) ((uint8_t)(x))
  86. #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
  87. #define LSW(x) ((uint16_t)(x))
  88. #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
  89. #define LSD(x) ((uint32_t)((uint64_t)(x)))
  90. #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
  91. #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
  92. /*
  93. * I/O register
  94. */
  95. #define RD_REG_BYTE(addr) readb(addr)
  96. #define RD_REG_WORD(addr) readw(addr)
  97. #define RD_REG_DWORD(addr) readl(addr)
  98. #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
  99. #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
  100. #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
  101. #define WRT_REG_BYTE(addr, data) writeb(data,addr)
  102. #define WRT_REG_WORD(addr, data) writew(data,addr)
  103. #define WRT_REG_DWORD(addr, data) writel(data,addr)
  104. /*
  105. * ISP83XX specific remote register addresses
  106. */
  107. #define QLA83XX_LED_PORT0 0x00201320
  108. #define QLA83XX_LED_PORT1 0x00201328
  109. #define QLA83XX_IDC_DEV_STATE 0x22102384
  110. #define QLA83XX_IDC_MAJOR_VERSION 0x22102380
  111. #define QLA83XX_IDC_MINOR_VERSION 0x22102398
  112. #define QLA83XX_IDC_DRV_PRESENCE 0x22102388
  113. #define QLA83XX_IDC_DRIVER_ACK 0x2210238c
  114. #define QLA83XX_IDC_CONTROL 0x22102390
  115. #define QLA83XX_IDC_AUDIT 0x22102394
  116. #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
  117. #define QLA83XX_DRIVER_LOCKID 0x22102104
  118. #define QLA83XX_DRIVER_LOCK 0x8111c028
  119. #define QLA83XX_DRIVER_UNLOCK 0x8111c02c
  120. #define QLA83XX_FLASH_LOCKID 0x22102100
  121. #define QLA83XX_FLASH_LOCK 0x8111c010
  122. #define QLA83XX_FLASH_UNLOCK 0x8111c014
  123. #define QLA83XX_DEV_PARTINFO1 0x221023e0
  124. #define QLA83XX_DEV_PARTINFO2 0x221023e4
  125. #define QLA83XX_FW_HEARTBEAT 0x221020b0
  126. #define QLA83XX_PEG_HALT_STATUS1 0x221020a8
  127. #define QLA83XX_PEG_HALT_STATUS2 0x221020ac
  128. /* 83XX: Macros defining 8200 AEN Reason codes */
  129. #define IDC_DEVICE_STATE_CHANGE BIT_0
  130. #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
  131. #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
  132. #define IDC_HEARTBEAT_FAILURE BIT_3
  133. /* 83XX: Macros defining 8200 AEN Error-levels */
  134. #define ERR_LEVEL_NON_FATAL 0x1
  135. #define ERR_LEVEL_RECOVERABLE_FATAL 0x2
  136. #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
  137. /* 83XX: Macros for IDC Version */
  138. #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
  139. #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
  140. /* 83XX: Macros for scheduling dpc tasks */
  141. #define QLA83XX_NIC_CORE_RESET 0x1
  142. #define QLA83XX_IDC_STATE_HANDLER 0x2
  143. #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
  144. /* 83XX: Macros for defining IDC-Control bits */
  145. #define QLA83XX_IDC_RESET_DISABLED BIT_0
  146. #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
  147. /* 83XX: Macros for different timeouts */
  148. #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
  149. #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
  150. #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
  151. /* 83XX: Macros for defining class in DEV-Partition Info register */
  152. #define QLA83XX_CLASS_TYPE_NONE 0x0
  153. #define QLA83XX_CLASS_TYPE_NIC 0x1
  154. #define QLA83XX_CLASS_TYPE_FCOE 0x2
  155. #define QLA83XX_CLASS_TYPE_ISCSI 0x3
  156. /* 83XX: Macros for IDC Lock-Recovery stages */
  157. #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
  158. * lock-recovery
  159. */
  160. #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
  161. /* 83XX: Macros for IDC Audit type */
  162. #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
  163. * dev-state change to NEED-RESET
  164. * or NEED-QUIESCENT
  165. */
  166. #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
  167. * reset-recovery completion is
  168. * second
  169. */
  170. /*
  171. * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
  172. * 133Mhz slot.
  173. */
  174. #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
  175. #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
  176. /*
  177. * Fibre Channel device definitions.
  178. */
  179. #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
  180. #define MAX_FIBRE_DEVICES_2100 512
  181. #define MAX_FIBRE_DEVICES_2400 2048
  182. #define MAX_FIBRE_DEVICES_LOOP 128
  183. #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
  184. #define LOOPID_MAP_SIZE (ha->max_fibre_devices)
  185. #define MAX_FIBRE_LUNS 0xFFFF
  186. #define MAX_HOST_COUNT 16
  187. /*
  188. * Host adapter default definitions.
  189. */
  190. #define MAX_BUSES 1 /* We only have one bus today */
  191. #define MIN_LUNS 8
  192. #define MAX_LUNS MAX_FIBRE_LUNS
  193. #define MAX_CMDS_PER_LUN 255
  194. /*
  195. * Fibre Channel device definitions.
  196. */
  197. #define SNS_LAST_LOOP_ID_2100 0xfe
  198. #define SNS_LAST_LOOP_ID_2300 0x7ff
  199. #define LAST_LOCAL_LOOP_ID 0x7d
  200. #define SNS_FL_PORT 0x7e
  201. #define FABRIC_CONTROLLER 0x7f
  202. #define SIMPLE_NAME_SERVER 0x80
  203. #define SNS_FIRST_LOOP_ID 0x81
  204. #define MANAGEMENT_SERVER 0xfe
  205. #define BROADCAST 0xff
  206. /*
  207. * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
  208. * valid range of an N-PORT id is 0 through 0x7ef.
  209. */
  210. #define NPH_LAST_HANDLE 0x7ef
  211. #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
  212. #define NPH_SNS 0x7fc /* FFFFFC */
  213. #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
  214. #define NPH_F_PORT 0x7fe /* FFFFFE */
  215. #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
  216. #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
  217. #include "qla_fw.h"
  218. /*
  219. * Timeout timer counts in seconds
  220. */
  221. #define PORT_RETRY_TIME 1
  222. #define LOOP_DOWN_TIMEOUT 60
  223. #define LOOP_DOWN_TIME 255 /* 240 */
  224. #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
  225. #define DEFAULT_OUTSTANDING_COMMANDS 1024
  226. #define MIN_OUTSTANDING_COMMANDS 128
  227. /* ISP request and response entry counts (37-65535) */
  228. #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
  229. #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
  230. #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
  231. #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
  232. #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
  233. #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
  234. #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
  235. struct req_que;
  236. /*
  237. * (sd.h is not exported, hence local inclusion)
  238. * Data Integrity Field tuple.
  239. */
  240. struct sd_dif_tuple {
  241. __be16 guard_tag; /* Checksum */
  242. __be16 app_tag; /* Opaque storage */
  243. __be32 ref_tag; /* Target LBA or indirect LBA */
  244. };
  245. /*
  246. * SCSI Request Block
  247. */
  248. struct srb_cmd {
  249. struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
  250. uint32_t request_sense_length;
  251. uint8_t *request_sense_ptr;
  252. void *ctx;
  253. };
  254. /*
  255. * SRB flag definitions
  256. */
  257. #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
  258. #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
  259. #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
  260. #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
  261. #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
  262. /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
  263. #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
  264. /*
  265. * SRB extensions.
  266. */
  267. struct srb_iocb {
  268. union {
  269. struct {
  270. uint16_t flags;
  271. #define SRB_LOGIN_RETRIED BIT_0
  272. #define SRB_LOGIN_COND_PLOGI BIT_1
  273. #define SRB_LOGIN_SKIP_PRLI BIT_2
  274. uint16_t data[2];
  275. } logio;
  276. struct {
  277. /*
  278. * Values for flags field below are as
  279. * defined in tsk_mgmt_entry struct
  280. * for control_flags field in qla_fw.h.
  281. */
  282. uint32_t flags;
  283. uint32_t lun;
  284. uint32_t data;
  285. } tmf;
  286. } u;
  287. struct timer_list timer;
  288. void (*timeout)(void *);
  289. };
  290. /* Values for srb_ctx type */
  291. #define SRB_LOGIN_CMD 1
  292. #define SRB_LOGOUT_CMD 2
  293. #define SRB_ELS_CMD_RPT 3
  294. #define SRB_ELS_CMD_HST 4
  295. #define SRB_CT_CMD 5
  296. #define SRB_ADISC_CMD 6
  297. #define SRB_TM_CMD 7
  298. #define SRB_SCSI_CMD 8
  299. #define SRB_BIDI_CMD 9
  300. typedef struct srb {
  301. atomic_t ref_count;
  302. struct fc_port *fcport;
  303. uint32_t handle;
  304. uint16_t flags;
  305. uint16_t type;
  306. char *name;
  307. int iocbs;
  308. union {
  309. struct srb_iocb iocb_cmd;
  310. struct fc_bsg_job *bsg_job;
  311. struct srb_cmd scmd;
  312. } u;
  313. void (*done)(void *, void *, int);
  314. void (*free)(void *, void *);
  315. } srb_t;
  316. #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
  317. #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd)
  318. #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx)
  319. #define GET_CMD_SENSE_LEN(sp) \
  320. (sp->u.scmd.request_sense_length)
  321. #define SET_CMD_SENSE_LEN(sp, len) \
  322. (sp->u.scmd.request_sense_length = len)
  323. #define GET_CMD_SENSE_PTR(sp) \
  324. (sp->u.scmd.request_sense_ptr)
  325. #define SET_CMD_SENSE_PTR(sp, ptr) \
  326. (sp->u.scmd.request_sense_ptr = ptr)
  327. struct msg_echo_lb {
  328. dma_addr_t send_dma;
  329. dma_addr_t rcv_dma;
  330. uint16_t req_sg_cnt;
  331. uint16_t rsp_sg_cnt;
  332. uint16_t options;
  333. uint32_t transfer_size;
  334. };
  335. /*
  336. * ISP I/O Register Set structure definitions.
  337. */
  338. struct device_reg_2xxx {
  339. uint16_t flash_address; /* Flash BIOS address */
  340. uint16_t flash_data; /* Flash BIOS data */
  341. uint16_t unused_1[1]; /* Gap */
  342. uint16_t ctrl_status; /* Control/Status */
  343. #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
  344. #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
  345. #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
  346. uint16_t ictrl; /* Interrupt control */
  347. #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
  348. #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
  349. uint16_t istatus; /* Interrupt status */
  350. #define ISR_RISC_INT BIT_3 /* RISC interrupt */
  351. uint16_t semaphore; /* Semaphore */
  352. uint16_t nvram; /* NVRAM register. */
  353. #define NVR_DESELECT 0
  354. #define NVR_BUSY BIT_15
  355. #define NVR_WRT_ENABLE BIT_14 /* Write enable */
  356. #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
  357. #define NVR_DATA_IN BIT_3
  358. #define NVR_DATA_OUT BIT_2
  359. #define NVR_SELECT BIT_1
  360. #define NVR_CLOCK BIT_0
  361. #define NVR_WAIT_CNT 20000
  362. union {
  363. struct {
  364. uint16_t mailbox0;
  365. uint16_t mailbox1;
  366. uint16_t mailbox2;
  367. uint16_t mailbox3;
  368. uint16_t mailbox4;
  369. uint16_t mailbox5;
  370. uint16_t mailbox6;
  371. uint16_t mailbox7;
  372. uint16_t unused_2[59]; /* Gap */
  373. } __attribute__((packed)) isp2100;
  374. struct {
  375. /* Request Queue */
  376. uint16_t req_q_in; /* In-Pointer */
  377. uint16_t req_q_out; /* Out-Pointer */
  378. /* Response Queue */
  379. uint16_t rsp_q_in; /* In-Pointer */
  380. uint16_t rsp_q_out; /* Out-Pointer */
  381. /* RISC to Host Status */
  382. uint32_t host_status;
  383. #define HSR_RISC_INT BIT_15 /* RISC interrupt */
  384. #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
  385. /* Host to Host Semaphore */
  386. uint16_t host_semaphore;
  387. uint16_t unused_3[17]; /* Gap */
  388. uint16_t mailbox0;
  389. uint16_t mailbox1;
  390. uint16_t mailbox2;
  391. uint16_t mailbox3;
  392. uint16_t mailbox4;
  393. uint16_t mailbox5;
  394. uint16_t mailbox6;
  395. uint16_t mailbox7;
  396. uint16_t mailbox8;
  397. uint16_t mailbox9;
  398. uint16_t mailbox10;
  399. uint16_t mailbox11;
  400. uint16_t mailbox12;
  401. uint16_t mailbox13;
  402. uint16_t mailbox14;
  403. uint16_t mailbox15;
  404. uint16_t mailbox16;
  405. uint16_t mailbox17;
  406. uint16_t mailbox18;
  407. uint16_t mailbox19;
  408. uint16_t mailbox20;
  409. uint16_t mailbox21;
  410. uint16_t mailbox22;
  411. uint16_t mailbox23;
  412. uint16_t mailbox24;
  413. uint16_t mailbox25;
  414. uint16_t mailbox26;
  415. uint16_t mailbox27;
  416. uint16_t mailbox28;
  417. uint16_t mailbox29;
  418. uint16_t mailbox30;
  419. uint16_t mailbox31;
  420. uint16_t fb_cmd;
  421. uint16_t unused_4[10]; /* Gap */
  422. } __attribute__((packed)) isp2300;
  423. } u;
  424. uint16_t fpm_diag_config;
  425. uint16_t unused_5[0x4]; /* Gap */
  426. uint16_t risc_hw;
  427. uint16_t unused_5_1; /* Gap */
  428. uint16_t pcr; /* Processor Control Register. */
  429. uint16_t unused_6[0x5]; /* Gap */
  430. uint16_t mctr; /* Memory Configuration and Timing. */
  431. uint16_t unused_7[0x3]; /* Gap */
  432. uint16_t fb_cmd_2100; /* Unused on 23XX */
  433. uint16_t unused_8[0x3]; /* Gap */
  434. uint16_t hccr; /* Host command & control register. */
  435. #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
  436. #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
  437. /* HCCR commands */
  438. #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
  439. #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
  440. #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
  441. #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
  442. #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
  443. #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
  444. #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
  445. #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
  446. uint16_t unused_9[5]; /* Gap */
  447. uint16_t gpiod; /* GPIO Data register. */
  448. uint16_t gpioe; /* GPIO Enable register. */
  449. #define GPIO_LED_MASK 0x00C0
  450. #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
  451. #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
  452. #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
  453. #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
  454. #define GPIO_LED_ALL_OFF 0x0000
  455. #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
  456. #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
  457. union {
  458. struct {
  459. uint16_t unused_10[8]; /* Gap */
  460. uint16_t mailbox8;
  461. uint16_t mailbox9;
  462. uint16_t mailbox10;
  463. uint16_t mailbox11;
  464. uint16_t mailbox12;
  465. uint16_t mailbox13;
  466. uint16_t mailbox14;
  467. uint16_t mailbox15;
  468. uint16_t mailbox16;
  469. uint16_t mailbox17;
  470. uint16_t mailbox18;
  471. uint16_t mailbox19;
  472. uint16_t mailbox20;
  473. uint16_t mailbox21;
  474. uint16_t mailbox22;
  475. uint16_t mailbox23; /* Also probe reg. */
  476. } __attribute__((packed)) isp2200;
  477. } u_end;
  478. };
  479. struct device_reg_25xxmq {
  480. uint32_t req_q_in;
  481. uint32_t req_q_out;
  482. uint32_t rsp_q_in;
  483. uint32_t rsp_q_out;
  484. uint32_t atio_q_in;
  485. uint32_t atio_q_out;
  486. };
  487. typedef union {
  488. struct device_reg_2xxx isp;
  489. struct device_reg_24xx isp24;
  490. struct device_reg_25xxmq isp25mq;
  491. struct device_reg_82xx isp82;
  492. } device_reg_t;
  493. #define ISP_REQ_Q_IN(ha, reg) \
  494. (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
  495. &(reg)->u.isp2100.mailbox4 : \
  496. &(reg)->u.isp2300.req_q_in)
  497. #define ISP_REQ_Q_OUT(ha, reg) \
  498. (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
  499. &(reg)->u.isp2100.mailbox4 : \
  500. &(reg)->u.isp2300.req_q_out)
  501. #define ISP_RSP_Q_IN(ha, reg) \
  502. (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
  503. &(reg)->u.isp2100.mailbox5 : \
  504. &(reg)->u.isp2300.rsp_q_in)
  505. #define ISP_RSP_Q_OUT(ha, reg) \
  506. (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
  507. &(reg)->u.isp2100.mailbox5 : \
  508. &(reg)->u.isp2300.rsp_q_out)
  509. #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
  510. #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
  511. #define MAILBOX_REG(ha, reg, num) \
  512. (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
  513. (num < 8 ? \
  514. &(reg)->u.isp2100.mailbox0 + (num) : \
  515. &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
  516. &(reg)->u.isp2300.mailbox0 + (num))
  517. #define RD_MAILBOX_REG(ha, reg, num) \
  518. RD_REG_WORD(MAILBOX_REG(ha, reg, num))
  519. #define WRT_MAILBOX_REG(ha, reg, num, data) \
  520. WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
  521. #define FB_CMD_REG(ha, reg) \
  522. (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
  523. &(reg)->fb_cmd_2100 : \
  524. &(reg)->u.isp2300.fb_cmd)
  525. #define RD_FB_CMD_REG(ha, reg) \
  526. RD_REG_WORD(FB_CMD_REG(ha, reg))
  527. #define WRT_FB_CMD_REG(ha, reg, data) \
  528. WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
  529. typedef struct {
  530. uint32_t out_mb; /* outbound from driver */
  531. uint32_t in_mb; /* Incoming from RISC */
  532. uint16_t mb[MAILBOX_REGISTER_COUNT];
  533. long buf_size;
  534. void *bufp;
  535. uint32_t tov;
  536. uint8_t flags;
  537. #define MBX_DMA_IN BIT_0
  538. #define MBX_DMA_OUT BIT_1
  539. #define IOCTL_CMD BIT_2
  540. } mbx_cmd_t;
  541. #define MBX_TOV_SECONDS 30
  542. /*
  543. * ISP product identification definitions in mailboxes after reset.
  544. */
  545. #define PROD_ID_1 0x4953
  546. #define PROD_ID_2 0x0000
  547. #define PROD_ID_2a 0x5020
  548. #define PROD_ID_3 0x2020
  549. /*
  550. * ISP mailbox Self-Test status codes
  551. */
  552. #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
  553. #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
  554. #define MBS_BUSY 4 /* Busy. */
  555. /*
  556. * ISP mailbox command complete status codes
  557. */
  558. #define MBS_COMMAND_COMPLETE 0x4000
  559. #define MBS_INVALID_COMMAND 0x4001
  560. #define MBS_HOST_INTERFACE_ERROR 0x4002
  561. #define MBS_TEST_FAILED 0x4003
  562. #define MBS_COMMAND_ERROR 0x4005
  563. #define MBS_COMMAND_PARAMETER_ERROR 0x4006
  564. #define MBS_PORT_ID_USED 0x4007
  565. #define MBS_LOOP_ID_USED 0x4008
  566. #define MBS_ALL_IDS_IN_USE 0x4009
  567. #define MBS_NOT_LOGGED_IN 0x400A
  568. #define MBS_LINK_DOWN_ERROR 0x400B
  569. #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
  570. /*
  571. * ISP mailbox asynchronous event status codes
  572. */
  573. #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
  574. #define MBA_RESET 0x8001 /* Reset Detected. */
  575. #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
  576. #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
  577. #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
  578. #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
  579. #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
  580. /* occurred. */
  581. #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
  582. #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
  583. #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
  584. #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
  585. #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
  586. #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
  587. #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
  588. #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
  589. #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
  590. #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
  591. #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
  592. #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
  593. #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
  594. #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
  595. #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
  596. #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
  597. /* used. */
  598. #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
  599. #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
  600. #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
  601. #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
  602. #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
  603. #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
  604. #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
  605. #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
  606. #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
  607. #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
  608. #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
  609. #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
  610. #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
  611. #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
  612. /* 83XX FCoE specific */
  613. #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
  614. /* Interrupt type codes */
  615. #define INTR_ROM_MB_SUCCESS 0x1
  616. #define INTR_ROM_MB_FAILED 0x2
  617. #define INTR_MB_SUCCESS 0x10
  618. #define INTR_MB_FAILED 0x11
  619. #define INTR_ASYNC_EVENT 0x12
  620. #define INTR_RSP_QUE_UPDATE 0x13
  621. #define INTR_RSP_QUE_UPDATE_83XX 0x14
  622. #define INTR_ATIO_QUE_UPDATE 0x1C
  623. #define INTR_ATIO_RSP_QUE_UPDATE 0x1D
  624. /* ISP mailbox loopback echo diagnostic error code */
  625. #define MBS_LB_RESET 0x17
  626. /*
  627. * Firmware options 1, 2, 3.
  628. */
  629. #define FO1_AE_ON_LIPF8 BIT_0
  630. #define FO1_AE_ALL_LIP_RESET BIT_1
  631. #define FO1_CTIO_RETRY BIT_3
  632. #define FO1_DISABLE_LIP_F7_SW BIT_4
  633. #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
  634. #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
  635. #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
  636. #define FO1_SET_EMPHASIS_SWING BIT_8
  637. #define FO1_AE_AUTO_BYPASS BIT_9
  638. #define FO1_ENABLE_PURE_IOCB BIT_10
  639. #define FO1_AE_PLOGI_RJT BIT_11
  640. #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
  641. #define FO1_AE_QUEUE_FULL BIT_13
  642. #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
  643. #define FO2_REV_LOOPBACK BIT_1
  644. #define FO3_ENABLE_EMERG_IOCB BIT_0
  645. #define FO3_AE_RND_ERROR BIT_1
  646. /* 24XX additional firmware options */
  647. #define ADD_FO_COUNT 3
  648. #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
  649. #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
  650. #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
  651. #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
  652. /*
  653. * ISP mailbox commands
  654. */
  655. #define MBC_LOAD_RAM 1 /* Load RAM. */
  656. #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
  657. #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
  658. #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
  659. #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
  660. #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
  661. #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
  662. #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
  663. #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
  664. #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
  665. #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
  666. #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
  667. #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
  668. #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
  669. #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
  670. #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
  671. #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
  672. #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
  673. #define MBC_RESET 0x18 /* Reset. */
  674. #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
  675. #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
  676. #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
  677. #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
  678. #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
  679. #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
  680. #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
  681. #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
  682. #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
  683. #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
  684. #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
  685. #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
  686. #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
  687. #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
  688. #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
  689. #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
  690. #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
  691. #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
  692. #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
  693. #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
  694. #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */
  695. #define MBC_DATA_RATE 0x5d /* Data Rate */
  696. #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
  697. #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
  698. /* Initialization Procedure */
  699. #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
  700. #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
  701. #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
  702. #define MBC_TARGET_RESET 0x66 /* Target Reset. */
  703. #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
  704. #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
  705. #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
  706. #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
  707. #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
  708. #define MBC_LIP_RESET 0x6c /* LIP reset. */
  709. #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
  710. /* commandd. */
  711. #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
  712. #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
  713. #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
  714. #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
  715. #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
  716. #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
  717. #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
  718. #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
  719. #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
  720. #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
  721. #define MBC_LUN_RESET 0x7E /* Send LUN reset */
  722. /*
  723. * ISP24xx mailbox commands
  724. */
  725. #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
  726. #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
  727. #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
  728. #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
  729. #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
  730. #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
  731. #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
  732. #define MBC_READ_SFP 0x31 /* Read SFP Data. */
  733. #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
  734. #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
  735. #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
  736. #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
  737. #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
  738. #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
  739. #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
  740. #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */
  741. #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
  742. #define MBC_PORT_RESET 0x120 /* Port Reset */
  743. #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
  744. #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
  745. /*
  746. * ISP81xx mailbox commands
  747. */
  748. #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
  749. /* Firmware return data sizes */
  750. #define FCAL_MAP_SIZE 128
  751. /* Mailbox bit definitions for out_mb and in_mb */
  752. #define MBX_31 BIT_31
  753. #define MBX_30 BIT_30
  754. #define MBX_29 BIT_29
  755. #define MBX_28 BIT_28
  756. #define MBX_27 BIT_27
  757. #define MBX_26 BIT_26
  758. #define MBX_25 BIT_25
  759. #define MBX_24 BIT_24
  760. #define MBX_23 BIT_23
  761. #define MBX_22 BIT_22
  762. #define MBX_21 BIT_21
  763. #define MBX_20 BIT_20
  764. #define MBX_19 BIT_19
  765. #define MBX_18 BIT_18
  766. #define MBX_17 BIT_17
  767. #define MBX_16 BIT_16
  768. #define MBX_15 BIT_15
  769. #define MBX_14 BIT_14
  770. #define MBX_13 BIT_13
  771. #define MBX_12 BIT_12
  772. #define MBX_11 BIT_11
  773. #define MBX_10 BIT_10
  774. #define MBX_9 BIT_9
  775. #define MBX_8 BIT_8
  776. #define MBX_7 BIT_7
  777. #define MBX_6 BIT_6
  778. #define MBX_5 BIT_5
  779. #define MBX_4 BIT_4
  780. #define MBX_3 BIT_3
  781. #define MBX_2 BIT_2
  782. #define MBX_1 BIT_1
  783. #define MBX_0 BIT_0
  784. #define RNID_TYPE_SET_VERSION 0x9
  785. #define RNID_TYPE_ASIC_TEMP 0xC
  786. /*
  787. * Firmware state codes from get firmware state mailbox command
  788. */
  789. #define FSTATE_CONFIG_WAIT 0
  790. #define FSTATE_WAIT_AL_PA 1
  791. #define FSTATE_WAIT_LOGIN 2
  792. #define FSTATE_READY 3
  793. #define FSTATE_LOSS_OF_SYNC 4
  794. #define FSTATE_ERROR 5
  795. #define FSTATE_REINIT 6
  796. #define FSTATE_NON_PART 7
  797. #define FSTATE_CONFIG_CORRECT 0
  798. #define FSTATE_P2P_RCV_LIP 1
  799. #define FSTATE_P2P_CHOOSE_LOOP 2
  800. #define FSTATE_P2P_RCV_UNIDEN_LIP 3
  801. #define FSTATE_FATAL_ERROR 4
  802. #define FSTATE_LOOP_BACK_CONN 5
  803. /*
  804. * Port Database structure definition
  805. * Little endian except where noted.
  806. */
  807. #define PORT_DATABASE_SIZE 128 /* bytes */
  808. typedef struct {
  809. uint8_t options;
  810. uint8_t control;
  811. uint8_t master_state;
  812. uint8_t slave_state;
  813. uint8_t reserved[2];
  814. uint8_t hard_address;
  815. uint8_t reserved_1;
  816. uint8_t port_id[4];
  817. uint8_t node_name[WWN_SIZE];
  818. uint8_t port_name[WWN_SIZE];
  819. uint16_t execution_throttle;
  820. uint16_t execution_count;
  821. uint8_t reset_count;
  822. uint8_t reserved_2;
  823. uint16_t resource_allocation;
  824. uint16_t current_allocation;
  825. uint16_t queue_head;
  826. uint16_t queue_tail;
  827. uint16_t transmit_execution_list_next;
  828. uint16_t transmit_execution_list_previous;
  829. uint16_t common_features;
  830. uint16_t total_concurrent_sequences;
  831. uint16_t RO_by_information_category;
  832. uint8_t recipient;
  833. uint8_t initiator;
  834. uint16_t receive_data_size;
  835. uint16_t concurrent_sequences;
  836. uint16_t open_sequences_per_exchange;
  837. uint16_t lun_abort_flags;
  838. uint16_t lun_stop_flags;
  839. uint16_t stop_queue_head;
  840. uint16_t stop_queue_tail;
  841. uint16_t port_retry_timer;
  842. uint16_t next_sequence_id;
  843. uint16_t frame_count;
  844. uint16_t PRLI_payload_length;
  845. uint8_t prli_svc_param_word_0[2]; /* Big endian */
  846. /* Bits 15-0 of word 0 */
  847. uint8_t prli_svc_param_word_3[2]; /* Big endian */
  848. /* Bits 15-0 of word 3 */
  849. uint16_t loop_id;
  850. uint16_t extended_lun_info_list_pointer;
  851. uint16_t extended_lun_stop_list_pointer;
  852. } port_database_t;
  853. /*
  854. * Port database slave/master states
  855. */
  856. #define PD_STATE_DISCOVERY 0
  857. #define PD_STATE_WAIT_DISCOVERY_ACK 1
  858. #define PD_STATE_PORT_LOGIN 2
  859. #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
  860. #define PD_STATE_PROCESS_LOGIN 4
  861. #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
  862. #define PD_STATE_PORT_LOGGED_IN 6
  863. #define PD_STATE_PORT_UNAVAILABLE 7
  864. #define PD_STATE_PROCESS_LOGOUT 8
  865. #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
  866. #define PD_STATE_PORT_LOGOUT 10
  867. #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
  868. #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
  869. #define QLA_ZIO_DISABLED 0
  870. #define QLA_ZIO_DEFAULT_TIMER 2
  871. /*
  872. * ISP Initialization Control Block.
  873. * Little endian except where noted.
  874. */
  875. #define ICB_VERSION 1
  876. typedef struct {
  877. uint8_t version;
  878. uint8_t reserved_1;
  879. /*
  880. * LSB BIT 0 = Enable Hard Loop Id
  881. * LSB BIT 1 = Enable Fairness
  882. * LSB BIT 2 = Enable Full-Duplex
  883. * LSB BIT 3 = Enable Fast Posting
  884. * LSB BIT 4 = Enable Target Mode
  885. * LSB BIT 5 = Disable Initiator Mode
  886. * LSB BIT 6 = Enable ADISC
  887. * LSB BIT 7 = Enable Target Inquiry Data
  888. *
  889. * MSB BIT 0 = Enable PDBC Notify
  890. * MSB BIT 1 = Non Participating LIP
  891. * MSB BIT 2 = Descending Loop ID Search
  892. * MSB BIT 3 = Acquire Loop ID in LIPA
  893. * MSB BIT 4 = Stop PortQ on Full Status
  894. * MSB BIT 5 = Full Login after LIP
  895. * MSB BIT 6 = Node Name Option
  896. * MSB BIT 7 = Ext IFWCB enable bit
  897. */
  898. uint8_t firmware_options[2];
  899. uint16_t frame_payload_size;
  900. uint16_t max_iocb_allocation;
  901. uint16_t execution_throttle;
  902. uint8_t retry_count;
  903. uint8_t retry_delay; /* unused */
  904. uint8_t port_name[WWN_SIZE]; /* Big endian. */
  905. uint16_t hard_address;
  906. uint8_t inquiry_data;
  907. uint8_t login_timeout;
  908. uint8_t node_name[WWN_SIZE]; /* Big endian. */
  909. uint16_t request_q_outpointer;
  910. uint16_t response_q_inpointer;
  911. uint16_t request_q_length;
  912. uint16_t response_q_length;
  913. uint32_t request_q_address[2];
  914. uint32_t response_q_address[2];
  915. uint16_t lun_enables;
  916. uint8_t command_resource_count;
  917. uint8_t immediate_notify_resource_count;
  918. uint16_t timeout;
  919. uint8_t reserved_2[2];
  920. /*
  921. * LSB BIT 0 = Timer Operation mode bit 0
  922. * LSB BIT 1 = Timer Operation mode bit 1
  923. * LSB BIT 2 = Timer Operation mode bit 2
  924. * LSB BIT 3 = Timer Operation mode bit 3
  925. * LSB BIT 4 = Init Config Mode bit 0
  926. * LSB BIT 5 = Init Config Mode bit 1
  927. * LSB BIT 6 = Init Config Mode bit 2
  928. * LSB BIT 7 = Enable Non part on LIHA failure
  929. *
  930. * MSB BIT 0 = Enable class 2
  931. * MSB BIT 1 = Enable ACK0
  932. * MSB BIT 2 =
  933. * MSB BIT 3 =
  934. * MSB BIT 4 = FC Tape Enable
  935. * MSB BIT 5 = Enable FC Confirm
  936. * MSB BIT 6 = Enable command queuing in target mode
  937. * MSB BIT 7 = No Logo On Link Down
  938. */
  939. uint8_t add_firmware_options[2];
  940. uint8_t response_accumulation_timer;
  941. uint8_t interrupt_delay_timer;
  942. /*
  943. * LSB BIT 0 = Enable Read xfr_rdy
  944. * LSB BIT 1 = Soft ID only
  945. * LSB BIT 2 =
  946. * LSB BIT 3 =
  947. * LSB BIT 4 = FCP RSP Payload [0]
  948. * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
  949. * LSB BIT 6 = Enable Out-of-Order frame handling
  950. * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
  951. *
  952. * MSB BIT 0 = Sbus enable - 2300
  953. * MSB BIT 1 =
  954. * MSB BIT 2 =
  955. * MSB BIT 3 =
  956. * MSB BIT 4 = LED mode
  957. * MSB BIT 5 = enable 50 ohm termination
  958. * MSB BIT 6 = Data Rate (2300 only)
  959. * MSB BIT 7 = Data Rate (2300 only)
  960. */
  961. uint8_t special_options[2];
  962. uint8_t reserved_3[26];
  963. } init_cb_t;
  964. /*
  965. * Get Link Status mailbox command return buffer.
  966. */
  967. #define GLSO_SEND_RPS BIT_0
  968. #define GLSO_USE_DID BIT_3
  969. struct link_statistics {
  970. uint32_t link_fail_cnt;
  971. uint32_t loss_sync_cnt;
  972. uint32_t loss_sig_cnt;
  973. uint32_t prim_seq_err_cnt;
  974. uint32_t inval_xmit_word_cnt;
  975. uint32_t inval_crc_cnt;
  976. uint32_t lip_cnt;
  977. uint32_t unused1[0x1a];
  978. uint32_t tx_frames;
  979. uint32_t rx_frames;
  980. uint32_t dumped_frames;
  981. uint32_t unused2[2];
  982. uint32_t nos_rcvd;
  983. };
  984. /*
  985. * NVRAM Command values.
  986. */
  987. #define NV_START_BIT BIT_2
  988. #define NV_WRITE_OP (BIT_26+BIT_24)
  989. #define NV_READ_OP (BIT_26+BIT_25)
  990. #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
  991. #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
  992. #define NV_DELAY_COUNT 10
  993. /*
  994. * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
  995. */
  996. typedef struct {
  997. /*
  998. * NVRAM header
  999. */
  1000. uint8_t id[4];
  1001. uint8_t nvram_version;
  1002. uint8_t reserved_0;
  1003. /*
  1004. * NVRAM RISC parameter block
  1005. */
  1006. uint8_t parameter_block_version;
  1007. uint8_t reserved_1;
  1008. /*
  1009. * LSB BIT 0 = Enable Hard Loop Id
  1010. * LSB BIT 1 = Enable Fairness
  1011. * LSB BIT 2 = Enable Full-Duplex
  1012. * LSB BIT 3 = Enable Fast Posting
  1013. * LSB BIT 4 = Enable Target Mode
  1014. * LSB BIT 5 = Disable Initiator Mode
  1015. * LSB BIT 6 = Enable ADISC
  1016. * LSB BIT 7 = Enable Target Inquiry Data
  1017. *
  1018. * MSB BIT 0 = Enable PDBC Notify
  1019. * MSB BIT 1 = Non Participating LIP
  1020. * MSB BIT 2 = Descending Loop ID Search
  1021. * MSB BIT 3 = Acquire Loop ID in LIPA
  1022. * MSB BIT 4 = Stop PortQ on Full Status
  1023. * MSB BIT 5 = Full Login after LIP
  1024. * MSB BIT 6 = Node Name Option
  1025. * MSB BIT 7 = Ext IFWCB enable bit
  1026. */
  1027. uint8_t firmware_options[2];
  1028. uint16_t frame_payload_size;
  1029. uint16_t max_iocb_allocation;
  1030. uint16_t execution_throttle;
  1031. uint8_t retry_count;
  1032. uint8_t retry_delay; /* unused */
  1033. uint8_t port_name[WWN_SIZE]; /* Big endian. */
  1034. uint16_t hard_address;
  1035. uint8_t inquiry_data;
  1036. uint8_t login_timeout;
  1037. uint8_t node_name[WWN_SIZE]; /* Big endian. */
  1038. /*
  1039. * LSB BIT 0 = Timer Operation mode bit 0
  1040. * LSB BIT 1 = Timer Operation mode bit 1
  1041. * LSB BIT 2 = Timer Operation mode bit 2
  1042. * LSB BIT 3 = Timer Operation mode bit 3
  1043. * LSB BIT 4 = Init Config Mode bit 0
  1044. * LSB BIT 5 = Init Config Mode bit 1
  1045. * LSB BIT 6 = Init Config Mode bit 2
  1046. * LSB BIT 7 = Enable Non part on LIHA failure
  1047. *
  1048. * MSB BIT 0 = Enable class 2
  1049. * MSB BIT 1 = Enable ACK0
  1050. * MSB BIT 2 =
  1051. * MSB BIT 3 =
  1052. * MSB BIT 4 = FC Tape Enable
  1053. * MSB BIT 5 = Enable FC Confirm
  1054. * MSB BIT 6 = Enable command queuing in target mode
  1055. * MSB BIT 7 = No Logo On Link Down
  1056. */
  1057. uint8_t add_firmware_options[2];
  1058. uint8_t response_accumulation_timer;
  1059. uint8_t interrupt_delay_timer;
  1060. /*
  1061. * LSB BIT 0 = Enable Read xfr_rdy
  1062. * LSB BIT 1 = Soft ID only
  1063. * LSB BIT 2 =
  1064. * LSB BIT 3 =
  1065. * LSB BIT 4 = FCP RSP Payload [0]
  1066. * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
  1067. * LSB BIT 6 = Enable Out-of-Order frame handling
  1068. * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
  1069. *
  1070. * MSB BIT 0 = Sbus enable - 2300
  1071. * MSB BIT 1 =
  1072. * MSB BIT 2 =
  1073. * MSB BIT 3 =
  1074. * MSB BIT 4 = LED mode
  1075. * MSB BIT 5 = enable 50 ohm termination
  1076. * MSB BIT 6 = Data Rate (2300 only)
  1077. * MSB BIT 7 = Data Rate (2300 only)
  1078. */
  1079. uint8_t special_options[2];
  1080. /* Reserved for expanded RISC parameter block */
  1081. uint8_t reserved_2[22];
  1082. /*
  1083. * LSB BIT 0 = Tx Sensitivity 1G bit 0
  1084. * LSB BIT 1 = Tx Sensitivity 1G bit 1
  1085. * LSB BIT 2 = Tx Sensitivity 1G bit 2
  1086. * LSB BIT 3 = Tx Sensitivity 1G bit 3
  1087. * LSB BIT 4 = Rx Sensitivity 1G bit 0
  1088. * LSB BIT 5 = Rx Sensitivity 1G bit 1
  1089. * LSB BIT 6 = Rx Sensitivity 1G bit 2
  1090. * LSB BIT 7 = Rx Sensitivity 1G bit 3
  1091. *
  1092. * MSB BIT 0 = Tx Sensitivity 2G bit 0
  1093. * MSB BIT 1 = Tx Sensitivity 2G bit 1
  1094. * MSB BIT 2 = Tx Sensitivity 2G bit 2
  1095. * MSB BIT 3 = Tx Sensitivity 2G bit 3
  1096. * MSB BIT 4 = Rx Sensitivity 2G bit 0
  1097. * MSB BIT 5 = Rx Sensitivity 2G bit 1
  1098. * MSB BIT 6 = Rx Sensitivity 2G bit 2
  1099. * MSB BIT 7 = Rx Sensitivity 2G bit 3
  1100. *
  1101. * LSB BIT 0 = Output Swing 1G bit 0
  1102. * LSB BIT 1 = Output Swing 1G bit 1
  1103. * LSB BIT 2 = Output Swing 1G bit 2
  1104. * LSB BIT 3 = Output Emphasis 1G bit 0
  1105. * LSB BIT 4 = Output Emphasis 1G bit 1
  1106. * LSB BIT 5 = Output Swing 2G bit 0
  1107. * LSB BIT 6 = Output Swing 2G bit 1
  1108. * LSB BIT 7 = Output Swing 2G bit 2
  1109. *
  1110. * MSB BIT 0 = Output Emphasis 2G bit 0
  1111. * MSB BIT 1 = Output Emphasis 2G bit 1
  1112. * MSB BIT 2 = Output Enable
  1113. * MSB BIT 3 =
  1114. * MSB BIT 4 =
  1115. * MSB BIT 5 =
  1116. * MSB BIT 6 =
  1117. * MSB BIT 7 =
  1118. */
  1119. uint8_t seriallink_options[4];
  1120. /*
  1121. * NVRAM host parameter block
  1122. *
  1123. * LSB BIT 0 = Enable spinup delay
  1124. * LSB BIT 1 = Disable BIOS
  1125. * LSB BIT 2 = Enable Memory Map BIOS
  1126. * LSB BIT 3 = Enable Selectable Boot
  1127. * LSB BIT 4 = Disable RISC code load
  1128. * LSB BIT 5 = Set cache line size 1
  1129. * LSB BIT 6 = PCI Parity Disable
  1130. * LSB BIT 7 = Enable extended logging
  1131. *
  1132. * MSB BIT 0 = Enable 64bit addressing
  1133. * MSB BIT 1 = Enable lip reset
  1134. * MSB BIT 2 = Enable lip full login
  1135. * MSB BIT 3 = Enable target reset
  1136. * MSB BIT 4 = Enable database storage
  1137. * MSB BIT 5 = Enable cache flush read
  1138. * MSB BIT 6 = Enable database load
  1139. * MSB BIT 7 = Enable alternate WWN
  1140. */
  1141. uint8_t host_p[2];
  1142. uint8_t boot_node_name[WWN_SIZE];
  1143. uint8_t boot_lun_number;
  1144. uint8_t reset_delay;
  1145. uint8_t port_down_retry_count;
  1146. uint8_t boot_id_number;
  1147. uint16_t max_luns_per_target;
  1148. uint8_t fcode_boot_port_name[WWN_SIZE];
  1149. uint8_t alternate_port_name[WWN_SIZE];
  1150. uint8_t alternate_node_name[WWN_SIZE];
  1151. /*
  1152. * BIT 0 = Selective Login
  1153. * BIT 1 = Alt-Boot Enable
  1154. * BIT 2 =
  1155. * BIT 3 = Boot Order List
  1156. * BIT 4 =
  1157. * BIT 5 = Selective LUN
  1158. * BIT 6 =
  1159. * BIT 7 = unused
  1160. */
  1161. uint8_t efi_parameters;
  1162. uint8_t link_down_timeout;
  1163. uint8_t adapter_id[16];
  1164. uint8_t alt1_boot_node_name[WWN_SIZE];
  1165. uint16_t alt1_boot_lun_number;
  1166. uint8_t alt2_boot_node_name[WWN_SIZE];
  1167. uint16_t alt2_boot_lun_number;
  1168. uint8_t alt3_boot_node_name[WWN_SIZE];
  1169. uint16_t alt3_boot_lun_number;
  1170. uint8_t alt4_boot_node_name[WWN_SIZE];
  1171. uint16_t alt4_boot_lun_number;
  1172. uint8_t alt5_boot_node_name[WWN_SIZE];
  1173. uint16_t alt5_boot_lun_number;
  1174. uint8_t alt6_boot_node_name[WWN_SIZE];
  1175. uint16_t alt6_boot_lun_number;
  1176. uint8_t alt7_boot_node_name[WWN_SIZE];
  1177. uint16_t alt7_boot_lun_number;
  1178. uint8_t reserved_3[2];
  1179. /* Offset 200-215 : Model Number */
  1180. uint8_t model_number[16];
  1181. /* OEM related items */
  1182. uint8_t oem_specific[16];
  1183. /*
  1184. * NVRAM Adapter Features offset 232-239
  1185. *
  1186. * LSB BIT 0 = External GBIC
  1187. * LSB BIT 1 = Risc RAM parity
  1188. * LSB BIT 2 = Buffer Plus Module
  1189. * LSB BIT 3 = Multi Chip Adapter
  1190. * LSB BIT 4 = Internal connector
  1191. * LSB BIT 5 =
  1192. * LSB BIT 6 =
  1193. * LSB BIT 7 =
  1194. *
  1195. * MSB BIT 0 =
  1196. * MSB BIT 1 =
  1197. * MSB BIT 2 =
  1198. * MSB BIT 3 =
  1199. * MSB BIT 4 =
  1200. * MSB BIT 5 =
  1201. * MSB BIT 6 =
  1202. * MSB BIT 7 =
  1203. */
  1204. uint8_t adapter_features[2];
  1205. uint8_t reserved_4[16];
  1206. /* Subsystem vendor ID for ISP2200 */
  1207. uint16_t subsystem_vendor_id_2200;
  1208. /* Subsystem device ID for ISP2200 */
  1209. uint16_t subsystem_device_id_2200;
  1210. uint8_t reserved_5;
  1211. uint8_t checksum;
  1212. } nvram_t;
  1213. /*
  1214. * ISP queue - response queue entry definition.
  1215. */
  1216. typedef struct {
  1217. uint8_t entry_type; /* Entry type. */
  1218. uint8_t entry_count; /* Entry count. */
  1219. uint8_t sys_define; /* System defined. */
  1220. uint8_t entry_status; /* Entry Status. */
  1221. uint32_t handle; /* System defined handle */
  1222. uint8_t data[52];
  1223. uint32_t signature;
  1224. #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
  1225. } response_t;
  1226. /*
  1227. * ISP queue - ATIO queue entry definition.
  1228. */
  1229. struct atio {
  1230. uint8_t entry_type; /* Entry type. */
  1231. uint8_t entry_count; /* Entry count. */
  1232. uint8_t data[58];
  1233. uint32_t signature;
  1234. #define ATIO_PROCESSED 0xDEADDEAD /* Signature */
  1235. };
  1236. typedef union {
  1237. uint16_t extended;
  1238. struct {
  1239. uint8_t reserved;
  1240. uint8_t standard;
  1241. } id;
  1242. } target_id_t;
  1243. #define SET_TARGET_ID(ha, to, from) \
  1244. do { \
  1245. if (HAS_EXTENDED_IDS(ha)) \
  1246. to.extended = cpu_to_le16(from); \
  1247. else \
  1248. to.id.standard = (uint8_t)from; \
  1249. } while (0)
  1250. /*
  1251. * ISP queue - command entry structure definition.
  1252. */
  1253. #define COMMAND_TYPE 0x11 /* Command entry */
  1254. typedef struct {
  1255. uint8_t entry_type; /* Entry type. */
  1256. uint8_t entry_count; /* Entry count. */
  1257. uint8_t sys_define; /* System defined. */
  1258. uint8_t entry_status; /* Entry Status. */
  1259. uint32_t handle; /* System handle. */
  1260. target_id_t target; /* SCSI ID */
  1261. uint16_t lun; /* SCSI LUN */
  1262. uint16_t control_flags; /* Control flags. */
  1263. #define CF_WRITE BIT_6
  1264. #define CF_READ BIT_5
  1265. #define CF_SIMPLE_TAG BIT_3
  1266. #define CF_ORDERED_TAG BIT_2
  1267. #define CF_HEAD_TAG BIT_1
  1268. uint16_t reserved_1;
  1269. uint16_t timeout; /* Command timeout. */
  1270. uint16_t dseg_count; /* Data segment count. */
  1271. uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
  1272. uint32_t byte_count; /* Total byte count. */
  1273. uint32_t dseg_0_address; /* Data segment 0 address. */
  1274. uint32_t dseg_0_length; /* Data segment 0 length. */
  1275. uint32_t dseg_1_address; /* Data segment 1 address. */
  1276. uint32_t dseg_1_length; /* Data segment 1 length. */
  1277. uint32_t dseg_2_address; /* Data segment 2 address. */
  1278. uint32_t dseg_2_length; /* Data segment 2 length. */
  1279. } cmd_entry_t;
  1280. /*
  1281. * ISP queue - 64-Bit addressing, command entry structure definition.
  1282. */
  1283. #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
  1284. typedef struct {
  1285. uint8_t entry_type; /* Entry type. */
  1286. uint8_t entry_count; /* Entry count. */
  1287. uint8_t sys_define; /* System defined. */
  1288. uint8_t entry_status; /* Entry Status. */
  1289. uint32_t handle; /* System handle. */
  1290. target_id_t target; /* SCSI ID */
  1291. uint16_t lun; /* SCSI LUN */
  1292. uint16_t control_flags; /* Control flags. */
  1293. uint16_t reserved_1;
  1294. uint16_t timeout; /* Command timeout. */
  1295. uint16_t dseg_count; /* Data segment count. */
  1296. uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
  1297. uint32_t byte_count; /* Total byte count. */
  1298. uint32_t dseg_0_address[2]; /* Data segment 0 address. */
  1299. uint32_t dseg_0_length; /* Data segment 0 length. */
  1300. uint32_t dseg_1_address[2]; /* Data segment 1 address. */
  1301. uint32_t dseg_1_length; /* Data segment 1 length. */
  1302. } cmd_a64_entry_t, request_t;
  1303. /*
  1304. * ISP queue - continuation entry structure definition.
  1305. */
  1306. #define CONTINUE_TYPE 0x02 /* Continuation entry. */
  1307. typedef struct {
  1308. uint8_t entry_type; /* Entry type. */
  1309. uint8_t entry_count; /* Entry count. */
  1310. uint8_t sys_define; /* System defined. */
  1311. uint8_t entry_status; /* Entry Status. */
  1312. uint32_t reserved;
  1313. uint32_t dseg_0_address; /* Data segment 0 address. */
  1314. uint32_t dseg_0_length; /* Data segment 0 length. */
  1315. uint32_t dseg_1_address; /* Data segment 1 address. */
  1316. uint32_t dseg_1_length; /* Data segment 1 length. */
  1317. uint32_t dseg_2_address; /* Data segment 2 address. */
  1318. uint32_t dseg_2_length; /* Data segment 2 length. */
  1319. uint32_t dseg_3_address; /* Data segment 3 address. */
  1320. uint32_t dseg_3_length; /* Data segment 3 length. */
  1321. uint32_t dseg_4_address; /* Data segment 4 address. */
  1322. uint32_t dseg_4_length; /* Data segment 4 length. */
  1323. uint32_t dseg_5_address; /* Data segment 5 address. */
  1324. uint32_t dseg_5_length; /* Data segment 5 length. */
  1325. uint32_t dseg_6_address; /* Data segment 6 address. */
  1326. uint32_t dseg_6_length; /* Data segment 6 length. */
  1327. } cont_entry_t;
  1328. /*
  1329. * ISP queue - 64-Bit addressing, continuation entry structure definition.
  1330. */
  1331. #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
  1332. typedef struct {
  1333. uint8_t entry_type; /* Entry type. */
  1334. uint8_t entry_count; /* Entry count. */
  1335. uint8_t sys_define; /* System defined. */
  1336. uint8_t entry_status; /* Entry Status. */
  1337. uint32_t dseg_0_address[2]; /* Data segment 0 address. */
  1338. uint32_t dseg_0_length; /* Data segment 0 length. */
  1339. uint32_t dseg_1_address[2]; /* Data segment 1 address. */
  1340. uint32_t dseg_1_length; /* Data segment 1 length. */
  1341. uint32_t dseg_2_address [2]; /* Data segment 2 address. */
  1342. uint32_t dseg_2_length; /* Data segment 2 length. */
  1343. uint32_t dseg_3_address[2]; /* Data segment 3 address. */
  1344. uint32_t dseg_3_length; /* Data segment 3 length. */
  1345. uint32_t dseg_4_address[2]; /* Data segment 4 address. */
  1346. uint32_t dseg_4_length; /* Data segment 4 length. */
  1347. } cont_a64_entry_t;
  1348. #define PO_MODE_DIF_INSERT 0
  1349. #define PO_MODE_DIF_REMOVE 1
  1350. #define PO_MODE_DIF_PASS 2
  1351. #define PO_MODE_DIF_REPLACE 3
  1352. #define PO_MODE_DIF_TCP_CKSUM 6
  1353. #define PO_ENABLE_DIF_BUNDLING BIT_8
  1354. #define PO_ENABLE_INCR_GUARD_SEED BIT_3
  1355. #define PO_DISABLE_INCR_REF_TAG BIT_5
  1356. #define PO_DISABLE_GUARD_CHECK BIT_4
  1357. /*
  1358. * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
  1359. */
  1360. struct crc_context {
  1361. uint32_t handle; /* System handle. */
  1362. uint32_t ref_tag;
  1363. uint16_t app_tag;
  1364. uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
  1365. uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
  1366. uint16_t guard_seed; /* Initial Guard Seed */
  1367. uint16_t prot_opts; /* Requested Data Protection Mode */
  1368. uint16_t blk_size; /* Data size in bytes */
  1369. uint16_t runt_blk_guard; /* Guard value for runt block (tape
  1370. * only) */
  1371. uint32_t byte_count; /* Total byte count/ total data
  1372. * transfer count */
  1373. union {
  1374. struct {
  1375. uint32_t reserved_1;
  1376. uint16_t reserved_2;
  1377. uint16_t reserved_3;
  1378. uint32_t reserved_4;
  1379. uint32_t data_address[2];
  1380. uint32_t data_length;
  1381. uint32_t reserved_5[2];
  1382. uint32_t reserved_6;
  1383. } nobundling;
  1384. struct {
  1385. uint32_t dif_byte_count; /* Total DIF byte
  1386. * count */
  1387. uint16_t reserved_1;
  1388. uint16_t dseg_count; /* Data segment count */
  1389. uint32_t reserved_2;
  1390. uint32_t data_address[2];
  1391. uint32_t data_length;
  1392. uint32_t dif_address[2];
  1393. uint32_t dif_length; /* Data segment 0
  1394. * length */
  1395. } bundling;
  1396. } u;
  1397. struct fcp_cmnd fcp_cmnd;
  1398. dma_addr_t crc_ctx_dma;
  1399. /* List of DMA context transfers */
  1400. struct list_head dsd_list;
  1401. /* This structure should not exceed 512 bytes */
  1402. };
  1403. #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
  1404. #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
  1405. /*
  1406. * ISP queue - status entry structure definition.
  1407. */
  1408. #define STATUS_TYPE 0x03 /* Status entry. */
  1409. typedef struct {
  1410. uint8_t entry_type; /* Entry type. */
  1411. uint8_t entry_count; /* Entry count. */
  1412. uint8_t sys_define; /* System defined. */
  1413. uint8_t entry_status; /* Entry Status. */
  1414. uint32_t handle; /* System handle. */
  1415. uint16_t scsi_status; /* SCSI status. */
  1416. uint16_t comp_status; /* Completion status. */
  1417. uint16_t state_flags; /* State flags. */
  1418. uint16_t status_flags; /* Status flags. */
  1419. uint16_t rsp_info_len; /* Response Info Length. */
  1420. uint16_t req_sense_length; /* Request sense data length. */
  1421. uint32_t residual_length; /* Residual transfer length. */
  1422. uint8_t rsp_info[8]; /* FCP response information. */
  1423. uint8_t req_sense_data[32]; /* Request sense data. */
  1424. } sts_entry_t;
  1425. /*
  1426. * Status entry entry status
  1427. */
  1428. #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
  1429. #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
  1430. #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
  1431. #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
  1432. #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
  1433. #define RF_BUSY BIT_1 /* Busy */
  1434. #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
  1435. RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
  1436. #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
  1437. RF_INV_E_TYPE)
  1438. /*
  1439. * Status entry SCSI status bit definitions.
  1440. */
  1441. #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
  1442. #define SS_RESIDUAL_UNDER BIT_11
  1443. #define SS_RESIDUAL_OVER BIT_10
  1444. #define SS_SENSE_LEN_VALID BIT_9
  1445. #define SS_RESPONSE_INFO_LEN_VALID BIT_8
  1446. #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
  1447. #define SS_BUSY_CONDITION BIT_3
  1448. #define SS_CONDITION_MET BIT_2
  1449. #define SS_CHECK_CONDITION BIT_1
  1450. /*
  1451. * Status entry completion status
  1452. */
  1453. #define CS_COMPLETE 0x0 /* No errors */
  1454. #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
  1455. #define CS_DMA 0x2 /* A DMA direction error. */
  1456. #define CS_TRANSPORT 0x3 /* Transport error. */
  1457. #define CS_RESET 0x4 /* SCSI bus reset occurred */
  1458. #define CS_ABORTED 0x5 /* System aborted command. */
  1459. #define CS_TIMEOUT 0x6 /* Timeout error. */
  1460. #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
  1461. #define CS_DIF_ERROR 0xC /* DIF error detected */
  1462. #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
  1463. #define CS_QUEUE_FULL 0x1C /* Queue Full. */
  1464. #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
  1465. /* (selection timeout) */
  1466. #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
  1467. #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
  1468. #define CS_PORT_BUSY 0x2B /* Port Busy */
  1469. #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
  1470. #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
  1471. #define CS_UNKNOWN 0x81 /* Driver defined */
  1472. #define CS_RETRY 0x82 /* Driver defined */
  1473. #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
  1474. #define CS_BIDIR_RD_OVERRUN 0x700
  1475. #define CS_BIDIR_RD_WR_OVERRUN 0x707
  1476. #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
  1477. #define CS_BIDIR_RD_UNDERRUN 0x1500
  1478. #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
  1479. #define CS_BIDIR_RD_WR_UNDERRUN 0x1515
  1480. #define CS_BIDIR_DMA 0x200
  1481. /*
  1482. * Status entry status flags
  1483. */
  1484. #define SF_ABTS_TERMINATED BIT_10
  1485. #define SF_LOGOUT_SENT BIT_13
  1486. /*
  1487. * ISP queue - status continuation entry structure definition.
  1488. */
  1489. #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
  1490. typedef struct {
  1491. uint8_t entry_type; /* Entry type. */
  1492. uint8_t entry_count; /* Entry count. */
  1493. uint8_t sys_define; /* System defined. */
  1494. uint8_t entry_status; /* Entry Status. */
  1495. uint8_t data[60]; /* data */
  1496. } sts_cont_entry_t;
  1497. /*
  1498. * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
  1499. * structure definition.
  1500. */
  1501. #define STATUS_TYPE_21 0x21 /* Status entry. */
  1502. typedef struct {
  1503. uint8_t entry_type; /* Entry type. */
  1504. uint8_t entry_count; /* Entry count. */
  1505. uint8_t handle_count; /* Handle count. */
  1506. uint8_t entry_status; /* Entry Status. */
  1507. uint32_t handle[15]; /* System handles. */
  1508. } sts21_entry_t;
  1509. /*
  1510. * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
  1511. * structure definition.
  1512. */
  1513. #define STATUS_TYPE_22 0x22 /* Status entry. */
  1514. typedef struct {
  1515. uint8_t entry_type; /* Entry type. */
  1516. uint8_t entry_count; /* Entry count. */
  1517. uint8_t handle_count; /* Handle count. */
  1518. uint8_t entry_status; /* Entry Status. */
  1519. uint16_t handle[30]; /* System handles. */
  1520. } sts22_entry_t;
  1521. /*
  1522. * ISP queue - marker entry structure definition.
  1523. */
  1524. #define MARKER_TYPE 0x04 /* Marker entry. */
  1525. typedef struct {
  1526. uint8_t entry_type; /* Entry type. */
  1527. uint8_t entry_count; /* Entry count. */
  1528. uint8_t handle_count; /* Handle count. */
  1529. uint8_t entry_status; /* Entry Status. */
  1530. uint32_t sys_define_2; /* System defined. */
  1531. target_id_t target; /* SCSI ID */
  1532. uint8_t modifier; /* Modifier (7-0). */
  1533. #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
  1534. #define MK_SYNC_ID 1 /* Synchronize ID */
  1535. #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
  1536. #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
  1537. /* clear port changed, */
  1538. /* use sequence number. */
  1539. uint8_t reserved_1;
  1540. uint16_t sequence_number; /* Sequence number of event */
  1541. uint16_t lun; /* SCSI LUN */
  1542. uint8_t reserved_2[48];
  1543. } mrk_entry_t;
  1544. /*
  1545. * ISP queue - Management Server entry structure definition.
  1546. */
  1547. #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
  1548. typedef struct {
  1549. uint8_t entry_type; /* Entry type. */
  1550. uint8_t entry_count; /* Entry count. */
  1551. uint8_t handle_count; /* Handle count. */
  1552. uint8_t entry_status; /* Entry Status. */
  1553. uint32_t handle1; /* System handle. */
  1554. target_id_t loop_id;
  1555. uint16_t status;
  1556. uint16_t control_flags; /* Control flags. */
  1557. uint16_t reserved2;
  1558. uint16_t timeout;
  1559. uint16_t cmd_dsd_count;
  1560. uint16_t total_dsd_count;
  1561. uint8_t type;
  1562. uint8_t r_ctl;
  1563. uint16_t rx_id;
  1564. uint16_t reserved3;
  1565. uint32_t handle2;
  1566. uint32_t rsp_bytecount;
  1567. uint32_t req_bytecount;
  1568. uint32_t dseg_req_address[2]; /* Data segment 0 address. */
  1569. uint32_t dseg_req_length; /* Data segment 0 length. */
  1570. uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
  1571. uint32_t dseg_rsp_length; /* Data segment 1 length. */
  1572. } ms_iocb_entry_t;
  1573. /*
  1574. * ISP queue - Mailbox Command entry structure definition.
  1575. */
  1576. #define MBX_IOCB_TYPE 0x39
  1577. struct mbx_entry {
  1578. uint8_t entry_type;
  1579. uint8_t entry_count;
  1580. uint8_t sys_define1;
  1581. /* Use sys_define1 for source type */
  1582. #define SOURCE_SCSI 0x00
  1583. #define SOURCE_IP 0x01
  1584. #define SOURCE_VI 0x02
  1585. #define SOURCE_SCTP 0x03
  1586. #define SOURCE_MP 0x04
  1587. #define SOURCE_MPIOCTL 0x05
  1588. #define SOURCE_ASYNC_IOCB 0x07
  1589. uint8_t entry_status;
  1590. uint32_t handle;
  1591. target_id_t loop_id;
  1592. uint16_t status;
  1593. uint16_t state_flags;
  1594. uint16_t status_flags;
  1595. uint32_t sys_define2[2];
  1596. uint16_t mb0;
  1597. uint16_t mb1;
  1598. uint16_t mb2;
  1599. uint16_t mb3;
  1600. uint16_t mb6;
  1601. uint16_t mb7;
  1602. uint16_t mb9;
  1603. uint16_t mb10;
  1604. uint32_t reserved_2[2];
  1605. uint8_t node_name[WWN_SIZE];
  1606. uint8_t port_name[WWN_SIZE];
  1607. };
  1608. /*
  1609. * ISP request and response queue entry sizes
  1610. */
  1611. #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
  1612. #define REQUEST_ENTRY_SIZE (sizeof(request_t))
  1613. /*
  1614. * 24 bit port ID type definition.
  1615. */
  1616. typedef union {
  1617. uint32_t b24 : 24;
  1618. struct {
  1619. #ifdef __BIG_ENDIAN
  1620. uint8_t domain;
  1621. uint8_t area;
  1622. uint8_t al_pa;
  1623. #elif defined(__LITTLE_ENDIAN)
  1624. uint8_t al_pa;
  1625. uint8_t area;
  1626. uint8_t domain;
  1627. #else
  1628. #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
  1629. #endif
  1630. uint8_t rsvd_1;
  1631. } b;
  1632. } port_id_t;
  1633. #define INVALID_PORT_ID 0xFFFFFF
  1634. /*
  1635. * Switch info gathering structure.
  1636. */
  1637. typedef struct {
  1638. port_id_t d_id;
  1639. uint8_t node_name[WWN_SIZE];
  1640. uint8_t port_name[WWN_SIZE];
  1641. uint8_t fabric_port_name[WWN_SIZE];
  1642. uint16_t fp_speed;
  1643. uint8_t fc4_type;
  1644. } sw_info_t;
  1645. /* FCP-4 types */
  1646. #define FC4_TYPE_FCP_SCSI 0x08
  1647. #define FC4_TYPE_OTHER 0x0
  1648. #define FC4_TYPE_UNKNOWN 0xff
  1649. /*
  1650. * Fibre channel port type.
  1651. */
  1652. typedef enum {
  1653. FCT_UNKNOWN,
  1654. FCT_RSCN,
  1655. FCT_SWITCH,
  1656. FCT_BROADCAST,
  1657. FCT_INITIATOR,
  1658. FCT_TARGET
  1659. } fc_port_type_t;
  1660. /*
  1661. * Fibre channel port structure.
  1662. */
  1663. typedef struct fc_port {
  1664. struct list_head list;
  1665. struct scsi_qla_host *vha;
  1666. uint8_t node_name[WWN_SIZE];
  1667. uint8_t port_name[WWN_SIZE];
  1668. port_id_t d_id;
  1669. uint16_t loop_id;
  1670. uint16_t old_loop_id;
  1671. uint8_t fcp_prio;
  1672. uint8_t fabric_port_name[WWN_SIZE];
  1673. uint16_t fp_speed;
  1674. fc_port_type_t port_type;
  1675. atomic_t state;
  1676. uint32_t flags;
  1677. int login_retry;
  1678. struct fc_rport *rport, *drport;
  1679. u32 supported_classes;
  1680. uint8_t fc4_type;
  1681. uint8_t scan_state;
  1682. } fc_port_t;
  1683. /*
  1684. * Fibre channel port/lun states.
  1685. */
  1686. #define FCS_UNCONFIGURED 1
  1687. #define FCS_DEVICE_DEAD 2
  1688. #define FCS_DEVICE_LOST 3
  1689. #define FCS_ONLINE 4
  1690. static const char * const port_state_str[] = {
  1691. "Unknown",
  1692. "UNCONFIGURED",
  1693. "DEAD",
  1694. "LOST",
  1695. "ONLINE"
  1696. };
  1697. /*
  1698. * FC port flags.
  1699. */
  1700. #define FCF_FABRIC_DEVICE BIT_0
  1701. #define FCF_LOGIN_NEEDED BIT_1
  1702. #define FCF_FCP2_DEVICE BIT_2
  1703. #define FCF_ASYNC_SENT BIT_3
  1704. #define FCF_CONF_COMP_SUPPORTED BIT_4
  1705. /* No loop ID flag. */
  1706. #define FC_NO_LOOP_ID 0x1000
  1707. /*
  1708. * FC-CT interface
  1709. *
  1710. * NOTE: All structures are big-endian in form.
  1711. */
  1712. #define CT_REJECT_RESPONSE 0x8001
  1713. #define CT_ACCEPT_RESPONSE 0x8002
  1714. #define CT_REASON_INVALID_COMMAND_CODE 0x01
  1715. #define CT_REASON_CANNOT_PERFORM 0x09
  1716. #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
  1717. #define CT_EXPL_ALREADY_REGISTERED 0x10
  1718. #define NS_N_PORT_TYPE 0x01
  1719. #define NS_NL_PORT_TYPE 0x02
  1720. #define NS_NX_PORT_TYPE 0x7F
  1721. #define GA_NXT_CMD 0x100
  1722. #define GA_NXT_REQ_SIZE (16 + 4)
  1723. #define GA_NXT_RSP_SIZE (16 + 620)
  1724. #define GID_PT_CMD 0x1A1
  1725. #define GID_PT_REQ_SIZE (16 + 4)
  1726. #define GPN_ID_CMD 0x112
  1727. #define GPN_ID_REQ_SIZE (16 + 4)
  1728. #define GPN_ID_RSP_SIZE (16 + 8)
  1729. #define GNN_ID_CMD 0x113
  1730. #define GNN_ID_REQ_SIZE (16 + 4)
  1731. #define GNN_ID_RSP_SIZE (16 + 8)
  1732. #define GFT_ID_CMD 0x117
  1733. #define GFT_ID_REQ_SIZE (16 + 4)
  1734. #define GFT_ID_RSP_SIZE (16 + 32)
  1735. #define RFT_ID_CMD 0x217
  1736. #define RFT_ID_REQ_SIZE (16 + 4 + 32)
  1737. #define RFT_ID_RSP_SIZE 16
  1738. #define RFF_ID_CMD 0x21F
  1739. #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
  1740. #define RFF_ID_RSP_SIZE 16
  1741. #define RNN_ID_CMD 0x213
  1742. #define RNN_ID_REQ_SIZE (16 + 4 + 8)
  1743. #define RNN_ID_RSP_SIZE 16
  1744. #define RSNN_NN_CMD 0x239
  1745. #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
  1746. #define RSNN_NN_RSP_SIZE 16
  1747. #define GFPN_ID_CMD 0x11C
  1748. #define GFPN_ID_REQ_SIZE (16 + 4)
  1749. #define GFPN_ID_RSP_SIZE (16 + 8)
  1750. #define GPSC_CMD 0x127
  1751. #define GPSC_REQ_SIZE (16 + 8)
  1752. #define GPSC_RSP_SIZE (16 + 2 + 2)
  1753. #define GFF_ID_CMD 0x011F
  1754. #define GFF_ID_REQ_SIZE (16 + 4)
  1755. #define GFF_ID_RSP_SIZE (16 + 128)
  1756. /*
  1757. * HBA attribute types.
  1758. */
  1759. #define FDMI_HBA_ATTR_COUNT 9
  1760. #define FDMI_HBA_NODE_NAME 1
  1761. #define FDMI_HBA_MANUFACTURER 2
  1762. #define FDMI_HBA_SERIAL_NUMBER 3
  1763. #define FDMI_HBA_MODEL 4
  1764. #define FDMI_HBA_MODEL_DESCRIPTION 5
  1765. #define FDMI_HBA_HARDWARE_VERSION 6
  1766. #define FDMI_HBA_DRIVER_VERSION 7
  1767. #define FDMI_HBA_OPTION_ROM_VERSION 8
  1768. #define FDMI_HBA_FIRMWARE_VERSION 9
  1769. #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
  1770. #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
  1771. struct ct_fdmi_hba_attr {
  1772. uint16_t type;
  1773. uint16_t len;
  1774. union {
  1775. uint8_t node_name[WWN_SIZE];
  1776. uint8_t manufacturer[32];
  1777. uint8_t serial_num[8];
  1778. uint8_t model[16];
  1779. uint8_t model_desc[80];
  1780. uint8_t hw_version[16];
  1781. uint8_t driver_version[32];
  1782. uint8_t orom_version[16];
  1783. uint8_t fw_version[16];
  1784. uint8_t os_version[128];
  1785. uint8_t max_ct_len[4];
  1786. } a;
  1787. };
  1788. struct ct_fdmi_hba_attributes {
  1789. uint32_t count;
  1790. struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
  1791. };
  1792. /*
  1793. * Port attribute types.
  1794. */
  1795. #define FDMI_PORT_ATTR_COUNT 6
  1796. #define FDMI_PORT_FC4_TYPES 1
  1797. #define FDMI_PORT_SUPPORT_SPEED 2
  1798. #define FDMI_PORT_CURRENT_SPEED 3
  1799. #define FDMI_PORT_MAX_FRAME_SIZE 4
  1800. #define FDMI_PORT_OS_DEVICE_NAME 5
  1801. #define FDMI_PORT_HOST_NAME 6
  1802. #define FDMI_PORT_SPEED_1GB 0x1
  1803. #define FDMI_PORT_SPEED_2GB 0x2
  1804. #define FDMI_PORT_SPEED_10GB 0x4
  1805. #define FDMI_PORT_SPEED_4GB 0x8
  1806. #define FDMI_PORT_SPEED_8GB 0x10
  1807. #define FDMI_PORT_SPEED_16GB 0x20
  1808. #define FDMI_PORT_SPEED_UNKNOWN 0x8000
  1809. struct ct_fdmi_port_attr {
  1810. uint16_t type;
  1811. uint16_t len;
  1812. union {
  1813. uint8_t fc4_types[32];
  1814. uint32_t sup_speed;
  1815. uint32_t cur_speed;
  1816. uint32_t max_frame_size;
  1817. uint8_t os_dev_name[32];
  1818. uint8_t host_name[32];
  1819. } a;
  1820. };
  1821. /*
  1822. * Port Attribute Block.
  1823. */
  1824. struct ct_fdmi_port_attributes {
  1825. uint32_t count;
  1826. struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
  1827. };
  1828. /* FDMI definitions. */
  1829. #define GRHL_CMD 0x100
  1830. #define GHAT_CMD 0x101
  1831. #define GRPL_CMD 0x102
  1832. #define GPAT_CMD 0x110
  1833. #define RHBA_CMD 0x200
  1834. #define RHBA_RSP_SIZE 16
  1835. #define RHAT_CMD 0x201
  1836. #define RPRT_CMD 0x210
  1837. #define RPA_CMD 0x211
  1838. #define RPA_RSP_SIZE 16
  1839. #define DHBA_CMD 0x300
  1840. #define DHBA_REQ_SIZE (16 + 8)
  1841. #define DHBA_RSP_SIZE 16
  1842. #define DHAT_CMD 0x301
  1843. #define DPRT_CMD 0x310
  1844. #define DPA_CMD 0x311
  1845. /* CT command header -- request/response common fields */
  1846. struct ct_cmd_hdr {
  1847. uint8_t revision;
  1848. uint8_t in_id[3];
  1849. uint8_t gs_type;
  1850. uint8_t gs_subtype;
  1851. uint8_t options;
  1852. uint8_t reserved;
  1853. };
  1854. /* CT command request */
  1855. struct ct_sns_req {
  1856. struct ct_cmd_hdr header;
  1857. uint16_t command;
  1858. uint16_t max_rsp_size;
  1859. uint8_t fragment_id;
  1860. uint8_t reserved[3];
  1861. union {
  1862. /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
  1863. struct {
  1864. uint8_t reserved;
  1865. uint8_t port_id[3];
  1866. } port_id;
  1867. struct {
  1868. uint8_t port_type;
  1869. uint8_t domain;
  1870. uint8_t area;
  1871. uint8_t reserved;
  1872. } gid_pt;
  1873. struct {
  1874. uint8_t reserved;
  1875. uint8_t port_id[3];
  1876. uint8_t fc4_types[32];
  1877. } rft_id;
  1878. struct {
  1879. uint8_t reserved;
  1880. uint8_t port_id[3];
  1881. uint16_t reserved2;
  1882. uint8_t fc4_feature;
  1883. uint8_t fc4_type;
  1884. } rff_id;
  1885. struct {
  1886. uint8_t reserved;
  1887. uint8_t port_id[3];
  1888. uint8_t node_name[8];
  1889. } rnn_id;
  1890. struct {
  1891. uint8_t node_name[8];
  1892. uint8_t name_len;
  1893. uint8_t sym_node_name[255];
  1894. } rsnn_nn;
  1895. struct {
  1896. uint8_t hba_indentifier[8];
  1897. } ghat;
  1898. struct {
  1899. uint8_t hba_identifier[8];
  1900. uint32_t entry_count;
  1901. uint8_t port_name[8];
  1902. struct ct_fdmi_hba_attributes attrs;
  1903. } rhba;
  1904. struct {
  1905. uint8_t hba_identifier[8];
  1906. struct ct_fdmi_hba_attributes attrs;
  1907. } rhat;
  1908. struct {
  1909. uint8_t port_name[8];
  1910. struct ct_fdmi_port_attributes attrs;
  1911. } rpa;
  1912. struct {
  1913. uint8_t port_name[8];
  1914. } dhba;
  1915. struct {
  1916. uint8_t port_name[8];
  1917. } dhat;
  1918. struct {
  1919. uint8_t port_name[8];
  1920. } dprt;
  1921. struct {
  1922. uint8_t port_name[8];
  1923. } dpa;
  1924. struct {
  1925. uint8_t port_name[8];
  1926. } gpsc;
  1927. struct {
  1928. uint8_t reserved;
  1929. uint8_t port_name[3];
  1930. } gff_id;
  1931. } req;
  1932. };
  1933. /* CT command response header */
  1934. struct ct_rsp_hdr {
  1935. struct ct_cmd_hdr header;
  1936. uint16_t response;
  1937. uint16_t residual;
  1938. uint8_t fragment_id;
  1939. uint8_t reason_code;
  1940. uint8_t explanation_code;
  1941. uint8_t vendor_unique;
  1942. };
  1943. struct ct_sns_gid_pt_data {
  1944. uint8_t control_byte;
  1945. uint8_t port_id[3];
  1946. };
  1947. struct ct_sns_rsp {
  1948. struct ct_rsp_hdr header;
  1949. union {
  1950. struct {
  1951. uint8_t port_type;
  1952. uint8_t port_id[3];
  1953. uint8_t port_name[8];
  1954. uint8_t sym_port_name_len;
  1955. uint8_t sym_port_name[255];
  1956. uint8_t node_name[8];
  1957. uint8_t sym_node_name_len;
  1958. uint8_t sym_node_name[255];
  1959. uint8_t init_proc_assoc[8];
  1960. uint8_t node_ip_addr[16];
  1961. uint8_t class_of_service[4];
  1962. uint8_t fc4_types[32];
  1963. uint8_t ip_address[16];
  1964. uint8_t fabric_port_name[8];
  1965. uint8_t reserved;
  1966. uint8_t hard_address[3];
  1967. } ga_nxt;
  1968. struct {
  1969. /* Assume the largest number of targets for the union */
  1970. struct ct_sns_gid_pt_data
  1971. entries[MAX_FIBRE_DEVICES_MAX];
  1972. } gid_pt;
  1973. struct {
  1974. uint8_t port_name[8];
  1975. } gpn_id;
  1976. struct {
  1977. uint8_t node_name[8];
  1978. } gnn_id;
  1979. struct {
  1980. uint8_t fc4_types[32];
  1981. } gft_id;
  1982. struct {
  1983. uint32_t entry_count;
  1984. uint8_t port_name[8];
  1985. struct ct_fdmi_hba_attributes attrs;
  1986. } ghat;
  1987. struct {
  1988. uint8_t port_name[8];
  1989. } gfpn_id;
  1990. struct {
  1991. uint16_t speeds;
  1992. uint16_t speed;
  1993. } gpsc;
  1994. #define GFF_FCP_SCSI_OFFSET 7
  1995. struct {
  1996. uint8_t fc4_features[128];
  1997. } gff_id;
  1998. } rsp;
  1999. };
  2000. struct ct_sns_pkt {
  2001. union {
  2002. struct ct_sns_req req;
  2003. struct ct_sns_rsp rsp;
  2004. } p;
  2005. };
  2006. /*
  2007. * SNS command structures -- for 2200 compatibility.
  2008. */
  2009. #define RFT_ID_SNS_SCMD_LEN 22
  2010. #define RFT_ID_SNS_CMD_SIZE 60
  2011. #define RFT_ID_SNS_DATA_SIZE 16
  2012. #define RNN_ID_SNS_SCMD_LEN 10
  2013. #define RNN_ID_SNS_CMD_SIZE 36
  2014. #define RNN_ID_SNS_DATA_SIZE 16
  2015. #define GA_NXT_SNS_SCMD_LEN 6
  2016. #define GA_NXT_SNS_CMD_SIZE 28
  2017. #define GA_NXT_SNS_DATA_SIZE (620 + 16)
  2018. #define GID_PT_SNS_SCMD_LEN 6
  2019. #define GID_PT_SNS_CMD_SIZE 28
  2020. /*
  2021. * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
  2022. * adapters.
  2023. */
  2024. #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
  2025. #define GPN_ID_SNS_SCMD_LEN 6
  2026. #define GPN_ID_SNS_CMD_SIZE 28
  2027. #define GPN_ID_SNS_DATA_SIZE (8 + 16)
  2028. #define GNN_ID_SNS_SCMD_LEN 6
  2029. #define GNN_ID_SNS_CMD_SIZE 28
  2030. #define GNN_ID_SNS_DATA_SIZE (8 + 16)
  2031. struct sns_cmd_pkt {
  2032. union {
  2033. struct {
  2034. uint16_t buffer_length;
  2035. uint16_t reserved_1;
  2036. uint32_t buffer_address[2];
  2037. uint16_t subcommand_length;
  2038. uint16_t reserved_2;
  2039. uint16_t subcommand;
  2040. uint16_t size;
  2041. uint32_t reserved_3;
  2042. uint8_t param[36];
  2043. } cmd;
  2044. uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
  2045. uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
  2046. uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
  2047. uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
  2048. uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
  2049. uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
  2050. } p;
  2051. };
  2052. struct fw_blob {
  2053. char *name;
  2054. uint32_t segs[4];
  2055. const struct firmware *fw;
  2056. };
  2057. /* Return data from MBC_GET_ID_LIST call. */
  2058. struct gid_list_info {
  2059. uint8_t al_pa;
  2060. uint8_t area;
  2061. uint8_t domain;
  2062. uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
  2063. uint16_t loop_id; /* ISP23XX -- 6 bytes. */
  2064. uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
  2065. };
  2066. /* NPIV */
  2067. typedef struct vport_info {
  2068. uint8_t port_name[WWN_SIZE];
  2069. uint8_t node_name[WWN_SIZE];
  2070. int vp_id;
  2071. uint16_t loop_id;
  2072. unsigned long host_no;
  2073. uint8_t port_id[3];
  2074. int loop_state;
  2075. } vport_info_t;
  2076. typedef struct vport_params {
  2077. uint8_t port_name[WWN_SIZE];
  2078. uint8_t node_name[WWN_SIZE];
  2079. uint32_t options;
  2080. #define VP_OPTS_RETRY_ENABLE BIT_0
  2081. #define VP_OPTS_VP_DISABLE BIT_1
  2082. } vport_params_t;
  2083. /* NPIV - return codes of VP create and modify */
  2084. #define VP_RET_CODE_OK 0
  2085. #define VP_RET_CODE_FATAL 1
  2086. #define VP_RET_CODE_WRONG_ID 2
  2087. #define VP_RET_CODE_WWPN 3
  2088. #define VP_RET_CODE_RESOURCES 4
  2089. #define VP_RET_CODE_NO_MEM 5
  2090. #define VP_RET_CODE_NOT_FOUND 6
  2091. struct qla_hw_data;
  2092. struct rsp_que;
  2093. /*
  2094. * ISP operations
  2095. */
  2096. struct isp_operations {
  2097. int (*pci_config) (struct scsi_qla_host *);
  2098. void (*reset_chip) (struct scsi_qla_host *);
  2099. int (*chip_diag) (struct scsi_qla_host *);
  2100. void (*config_rings) (struct scsi_qla_host *);
  2101. void (*reset_adapter) (struct scsi_qla_host *);
  2102. int (*nvram_config) (struct scsi_qla_host *);
  2103. void (*update_fw_options) (struct scsi_qla_host *);
  2104. int (*load_risc) (struct scsi_qla_host *, uint32_t *);
  2105. char * (*pci_info_str) (struct scsi_qla_host *, char *);
  2106. char * (*fw_version_str) (struct scsi_qla_host *, char *);
  2107. irq_handler_t intr_handler;
  2108. void (*enable_intrs) (struct qla_hw_data *);
  2109. void (*disable_intrs) (struct qla_hw_data *);
  2110. int (*abort_command) (srb_t *);
  2111. int (*target_reset) (struct fc_port *, unsigned int, int);
  2112. int (*lun_reset) (struct fc_port *, unsigned int, int);
  2113. int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
  2114. uint8_t, uint8_t, uint16_t *, uint8_t);
  2115. int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
  2116. uint8_t, uint8_t);
  2117. uint16_t (*calc_req_entries) (uint16_t);
  2118. void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
  2119. void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
  2120. void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
  2121. uint32_t);
  2122. uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
  2123. uint32_t, uint32_t);
  2124. int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
  2125. uint32_t);
  2126. void (*fw_dump) (struct scsi_qla_host *, int);
  2127. int (*beacon_on) (struct scsi_qla_host *);
  2128. int (*beacon_off) (struct scsi_qla_host *);
  2129. void (*beacon_blink) (struct scsi_qla_host *);
  2130. uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
  2131. uint32_t, uint32_t);
  2132. int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
  2133. uint32_t);
  2134. int (*get_flash_version) (struct scsi_qla_host *, void *);
  2135. int (*start_scsi) (srb_t *);
  2136. int (*abort_isp) (struct scsi_qla_host *);
  2137. int (*iospace_config)(struct qla_hw_data*);
  2138. };
  2139. /* MSI-X Support *************************************************************/
  2140. #define QLA_MSIX_CHIP_REV_24XX 3
  2141. #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
  2142. #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
  2143. #define QLA_MSIX_DEFAULT 0x00
  2144. #define QLA_MSIX_RSP_Q 0x01
  2145. #define QLA_MIDX_DEFAULT 0
  2146. #define QLA_MIDX_RSP_Q 1
  2147. #define QLA_PCI_MSIX_CONTROL 0xa2
  2148. #define QLA_83XX_PCI_MSIX_CONTROL 0x92
  2149. struct scsi_qla_host;
  2150. struct qla_msix_entry {
  2151. int have_irq;
  2152. uint32_t vector;
  2153. uint16_t entry;
  2154. struct rsp_que *rsp;
  2155. };
  2156. #define WATCH_INTERVAL 1 /* number of seconds */
  2157. /* Work events. */
  2158. enum qla_work_type {
  2159. QLA_EVT_AEN,
  2160. QLA_EVT_IDC_ACK,
  2161. QLA_EVT_ASYNC_LOGIN,
  2162. QLA_EVT_ASYNC_LOGIN_DONE,
  2163. QLA_EVT_ASYNC_LOGOUT,
  2164. QLA_EVT_ASYNC_LOGOUT_DONE,
  2165. QLA_EVT_ASYNC_ADISC,
  2166. QLA_EVT_ASYNC_ADISC_DONE,
  2167. QLA_EVT_UEVENT,
  2168. };
  2169. struct qla_work_evt {
  2170. struct list_head list;
  2171. enum qla_work_type type;
  2172. u32 flags;
  2173. #define QLA_EVT_FLAG_FREE 0x1
  2174. union {
  2175. struct {
  2176. enum fc_host_event_code code;
  2177. u32 data;
  2178. } aen;
  2179. struct {
  2180. #define QLA_IDC_ACK_REGS 7
  2181. uint16_t mb[QLA_IDC_ACK_REGS];
  2182. } idc_ack;
  2183. struct {
  2184. struct fc_port *fcport;
  2185. #define QLA_LOGIO_LOGIN_RETRIED BIT_0
  2186. u16 data[2];
  2187. } logio;
  2188. struct {
  2189. u32 code;
  2190. #define QLA_UEVENT_CODE_FW_DUMP 0
  2191. } uevent;
  2192. } u;
  2193. };
  2194. struct qla_chip_state_84xx {
  2195. struct list_head list;
  2196. struct kref kref;
  2197. void *bus;
  2198. spinlock_t access_lock;
  2199. struct mutex fw_update_mutex;
  2200. uint32_t fw_update;
  2201. uint32_t op_fw_version;
  2202. uint32_t op_fw_size;
  2203. uint32_t op_fw_seq_size;
  2204. uint32_t diag_fw_version;
  2205. uint32_t gold_fw_version;
  2206. };
  2207. struct qla_statistics {
  2208. uint32_t total_isp_aborts;
  2209. uint64_t input_bytes;
  2210. uint64_t output_bytes;
  2211. };
  2212. struct bidi_statistics {
  2213. unsigned long long io_count;
  2214. unsigned long long transfer_bytes;
  2215. };
  2216. /* Multi queue support */
  2217. #define MBC_INITIALIZE_MULTIQ 0x1f
  2218. #define QLA_QUE_PAGE 0X1000
  2219. #define QLA_MQ_SIZE 32
  2220. #define QLA_MAX_QUEUES 256
  2221. #define ISP_QUE_REG(ha, id) \
  2222. ((ha->mqenable || IS_QLA83XX(ha)) ? \
  2223. ((device_reg_t __iomem *)(ha->mqiobase) +\
  2224. (QLA_QUE_PAGE * id)) :\
  2225. ((device_reg_t __iomem *)(ha->iobase)))
  2226. #define QLA_REQ_QUE_ID(tag) \
  2227. ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
  2228. #define QLA_DEFAULT_QUE_QOS 5
  2229. #define QLA_PRECONFIG_VPORTS 32
  2230. #define QLA_MAX_VPORTS_QLA24XX 128
  2231. #define QLA_MAX_VPORTS_QLA25XX 256
  2232. /* Response queue data structure */
  2233. struct rsp_que {
  2234. dma_addr_t dma;
  2235. response_t *ring;
  2236. response_t *ring_ptr;
  2237. uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
  2238. uint32_t __iomem *rsp_q_out;
  2239. uint16_t ring_index;
  2240. uint16_t out_ptr;
  2241. uint16_t length;
  2242. uint16_t options;
  2243. uint16_t rid;
  2244. uint16_t id;
  2245. uint16_t vp_idx;
  2246. struct qla_hw_data *hw;
  2247. struct qla_msix_entry *msix;
  2248. struct req_que *req;
  2249. srb_t *status_srb; /* status continuation entry */
  2250. struct work_struct q_work;
  2251. };
  2252. /* Request queue data structure */
  2253. struct req_que {
  2254. dma_addr_t dma;
  2255. request_t *ring;
  2256. request_t *ring_ptr;
  2257. uint32_t __iomem *req_q_in; /* FWI2-capable only. */
  2258. uint32_t __iomem *req_q_out;
  2259. uint16_t ring_index;
  2260. uint16_t in_ptr;
  2261. uint16_t cnt;
  2262. uint16_t length;
  2263. uint16_t options;
  2264. uint16_t rid;
  2265. uint16_t id;
  2266. uint16_t qos;
  2267. uint16_t vp_idx;
  2268. struct rsp_que *rsp;
  2269. srb_t **outstanding_cmds;
  2270. uint32_t current_outstanding_cmd;
  2271. uint16_t num_outstanding_cmds;
  2272. #define MAX_Q_DEPTH 32
  2273. int max_q_depth;
  2274. };
  2275. /* Place holder for FW buffer parameters */
  2276. struct qlfc_fw {
  2277. void *fw_buf;
  2278. dma_addr_t fw_dma;
  2279. uint32_t len;
  2280. };
  2281. struct qlt_hw_data {
  2282. /* Protected by hw lock */
  2283. uint32_t enable_class_2:1;
  2284. uint32_t enable_explicit_conf:1;
  2285. uint32_t ini_mode_force_reverse:1;
  2286. uint32_t node_name_set:1;
  2287. dma_addr_t atio_dma; /* Physical address. */
  2288. struct atio *atio_ring; /* Base virtual address */
  2289. struct atio *atio_ring_ptr; /* Current address. */
  2290. uint16_t atio_ring_index; /* Current index. */
  2291. uint16_t atio_q_length;
  2292. uint32_t __iomem *atio_q_in;
  2293. uint32_t __iomem *atio_q_out;
  2294. void *target_lport_ptr;
  2295. struct qla_tgt_func_tmpl *tgt_ops;
  2296. struct qla_tgt *qla_tgt;
  2297. struct qla_tgt_cmd *cmds[DEFAULT_OUTSTANDING_COMMANDS];
  2298. uint16_t current_handle;
  2299. struct qla_tgt_vp_map *tgt_vp_map;
  2300. struct mutex tgt_mutex;
  2301. struct mutex tgt_host_action_mutex;
  2302. int saved_set;
  2303. uint16_t saved_exchange_count;
  2304. uint32_t saved_firmware_options_1;
  2305. uint32_t saved_firmware_options_2;
  2306. uint32_t saved_firmware_options_3;
  2307. uint8_t saved_firmware_options[2];
  2308. uint8_t saved_add_firmware_options[2];
  2309. uint8_t tgt_node_name[WWN_SIZE];
  2310. };
  2311. /*
  2312. * Qlogic host adapter specific data structure.
  2313. */
  2314. struct qla_hw_data {
  2315. struct pci_dev *pdev;
  2316. /* SRB cache. */
  2317. #define SRB_MIN_REQ 128
  2318. mempool_t *srb_mempool;
  2319. volatile struct {
  2320. uint32_t mbox_int :1;
  2321. uint32_t mbox_busy :1;
  2322. uint32_t disable_risc_code_load :1;
  2323. uint32_t enable_64bit_addressing :1;
  2324. uint32_t enable_lip_reset :1;
  2325. uint32_t enable_target_reset :1;
  2326. uint32_t enable_lip_full_login :1;
  2327. uint32_t enable_led_scheme :1;
  2328. uint32_t msi_enabled :1;
  2329. uint32_t msix_enabled :1;
  2330. uint32_t disable_serdes :1;
  2331. uint32_t gpsc_supported :1;
  2332. uint32_t npiv_supported :1;
  2333. uint32_t pci_channel_io_perm_failure :1;
  2334. uint32_t fce_enabled :1;
  2335. uint32_t fac_supported :1;
  2336. uint32_t chip_reset_done :1;
  2337. uint32_t port0 :1;
  2338. uint32_t running_gold_fw :1;
  2339. uint32_t eeh_busy :1;
  2340. uint32_t cpu_affinity_enabled :1;
  2341. uint32_t disable_msix_handshake :1;
  2342. uint32_t fcp_prio_enabled :1;
  2343. uint32_t isp82xx_fw_hung:1;
  2344. uint32_t nic_core_hung:1;
  2345. uint32_t quiesce_owner:1;
  2346. uint32_t nic_core_reset_hdlr_active:1;
  2347. uint32_t nic_core_reset_owner:1;
  2348. uint32_t isp82xx_no_md_cap:1;
  2349. uint32_t host_shutting_down:1;
  2350. uint32_t idc_compl_status:1;
  2351. /* 32 bits */
  2352. } flags;
  2353. /* This spinlock is used to protect "io transactions", you must
  2354. * acquire it before doing any IO to the card, eg with RD_REG*() and
  2355. * WRT_REG*() for the duration of your entire commandtransaction.
  2356. *
  2357. * This spinlock is of lower priority than the io request lock.
  2358. */
  2359. spinlock_t hardware_lock ____cacheline_aligned;
  2360. int bars;
  2361. int mem_only;
  2362. device_reg_t __iomem *iobase; /* Base I/O address */
  2363. resource_size_t pio_address;
  2364. #define MIN_IOBASE_LEN 0x100
  2365. /* Multi queue data structs */
  2366. device_reg_t __iomem *mqiobase;
  2367. device_reg_t __iomem *msixbase;
  2368. uint16_t msix_count;
  2369. uint8_t mqenable;
  2370. struct req_que **req_q_map;
  2371. struct rsp_que **rsp_q_map;
  2372. unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
  2373. unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
  2374. uint8_t max_req_queues;
  2375. uint8_t max_rsp_queues;
  2376. struct qla_npiv_entry *npiv_info;
  2377. uint16_t nvram_npiv_size;
  2378. uint16_t switch_cap;
  2379. #define FLOGI_SEQ_DEL BIT_8
  2380. #define FLOGI_MID_SUPPORT BIT_10
  2381. #define FLOGI_VSAN_SUPPORT BIT_12
  2382. #define FLOGI_SP_SUPPORT BIT_13
  2383. uint8_t port_no; /* Physical port of adapter */
  2384. /* Timeout timers. */
  2385. uint8_t loop_down_abort_time; /* port down timer */
  2386. atomic_t loop_down_timer; /* loop down timer */
  2387. uint8_t link_down_timeout; /* link down timeout */
  2388. uint16_t max_loop_id;
  2389. uint16_t max_fibre_devices; /* Maximum number of targets */
  2390. uint16_t fb_rev;
  2391. uint16_t min_external_loopid; /* First external loop Id */
  2392. #define PORT_SPEED_UNKNOWN 0xFFFF
  2393. #define PORT_SPEED_1GB 0x00
  2394. #define PORT_SPEED_2GB 0x01
  2395. #define PORT_SPEED_4GB 0x03
  2396. #define PORT_SPEED_8GB 0x04
  2397. #define PORT_SPEED_16GB 0x05
  2398. #define PORT_SPEED_10GB 0x13
  2399. uint16_t link_data_rate; /* F/W operating speed */
  2400. uint8_t current_topology;
  2401. uint8_t prev_topology;
  2402. #define ISP_CFG_NL 1
  2403. #define ISP_CFG_N 2
  2404. #define ISP_CFG_FL 4
  2405. #define ISP_CFG_F 8
  2406. uint8_t operating_mode; /* F/W operating mode */
  2407. #define LOOP 0
  2408. #define P2P 1
  2409. #define LOOP_P2P 2
  2410. #define P2P_LOOP 3
  2411. uint8_t interrupts_on;
  2412. uint32_t isp_abort_cnt;
  2413. #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
  2414. #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
  2415. #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
  2416. #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
  2417. #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
  2418. uint32_t device_type;
  2419. #define DT_ISP2100 BIT_0
  2420. #define DT_ISP2200 BIT_1
  2421. #define DT_ISP2300 BIT_2
  2422. #define DT_ISP2312 BIT_3
  2423. #define DT_ISP2322 BIT_4
  2424. #define DT_ISP6312 BIT_5
  2425. #define DT_ISP6322 BIT_6
  2426. #define DT_ISP2422 BIT_7
  2427. #define DT_ISP2432 BIT_8
  2428. #define DT_ISP5422 BIT_9
  2429. #define DT_ISP5432 BIT_10
  2430. #define DT_ISP2532 BIT_11
  2431. #define DT_ISP8432 BIT_12
  2432. #define DT_ISP8001 BIT_13
  2433. #define DT_ISP8021 BIT_14
  2434. #define DT_ISP2031 BIT_15
  2435. #define DT_ISP8031 BIT_16
  2436. #define DT_ISP_LAST (DT_ISP8031 << 1)
  2437. #define DT_T10_PI BIT_25
  2438. #define DT_IIDMA BIT_26
  2439. #define DT_FWI2 BIT_27
  2440. #define DT_ZIO_SUPPORTED BIT_28
  2441. #define DT_OEM_001 BIT_29
  2442. #define DT_ISP2200A BIT_30
  2443. #define DT_EXTENDED_IDS BIT_31
  2444. #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
  2445. #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
  2446. #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
  2447. #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
  2448. #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
  2449. #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
  2450. #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
  2451. #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
  2452. #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
  2453. #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
  2454. #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
  2455. #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
  2456. #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
  2457. #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
  2458. #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
  2459. #define IS_QLA81XX(ha) (IS_QLA8001(ha))
  2460. #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
  2461. #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
  2462. #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
  2463. #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
  2464. IS_QLA6312(ha) || IS_QLA6322(ha))
  2465. #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
  2466. #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
  2467. #define IS_QLA25XX(ha) (IS_QLA2532(ha))
  2468. #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
  2469. #define IS_QLA84XX(ha) (IS_QLA8432(ha))
  2470. #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
  2471. IS_QLA84XX(ha))
  2472. #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
  2473. IS_QLA8031(ha))
  2474. #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
  2475. IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
  2476. IS_QLA82XX(ha) || IS_QLA83XX(ha))
  2477. #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
  2478. #define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
  2479. IS_QLA83XX(ha)) && (ha)->flags.msix_enabled)
  2480. #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
  2481. #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
  2482. #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
  2483. #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
  2484. #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
  2485. #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
  2486. #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
  2487. #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
  2488. #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
  2489. #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
  2490. #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha))
  2491. #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha)))
  2492. /* Bit 21 of fw_attributes decides the MCTP capabilities */
  2493. #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
  2494. ((ha)->fw_attributes_ext[0] & BIT_0))
  2495. #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha))
  2496. #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha))
  2497. #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
  2498. #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha))
  2499. #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
  2500. (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
  2501. #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha))
  2502. #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
  2503. /* HBA serial number */
  2504. uint8_t serial0;
  2505. uint8_t serial1;
  2506. uint8_t serial2;
  2507. /* NVRAM configuration data */
  2508. #define MAX_NVRAM_SIZE 4096
  2509. #define VPD_OFFSET MAX_NVRAM_SIZE / 2
  2510. uint16_t nvram_size;
  2511. uint16_t nvram_base;
  2512. void *nvram;
  2513. uint16_t vpd_size;
  2514. uint16_t vpd_base;
  2515. void *vpd;
  2516. uint16_t loop_reset_delay;
  2517. uint8_t retry_count;
  2518. uint8_t login_timeout;
  2519. uint16_t r_a_tov;
  2520. int port_down_retry_count;
  2521. uint8_t mbx_count;
  2522. uint32_t login_retry_count;
  2523. /* SNS command interfaces. */
  2524. ms_iocb_entry_t *ms_iocb;
  2525. dma_addr_t ms_iocb_dma;
  2526. struct ct_sns_pkt *ct_sns;
  2527. dma_addr_t ct_sns_dma;
  2528. /* SNS command interfaces for 2200. */
  2529. struct sns_cmd_pkt *sns_cmd;
  2530. dma_addr_t sns_cmd_dma;
  2531. #define SFP_DEV_SIZE 256
  2532. #define SFP_BLOCK_SIZE 64
  2533. void *sfp_data;
  2534. dma_addr_t sfp_data_dma;
  2535. #define XGMAC_DATA_SIZE 4096
  2536. void *xgmac_data;
  2537. dma_addr_t xgmac_data_dma;
  2538. #define DCBX_TLV_DATA_SIZE 4096
  2539. void *dcbx_tlv;
  2540. dma_addr_t dcbx_tlv_dma;
  2541. struct task_struct *dpc_thread;
  2542. uint8_t dpc_active; /* DPC routine is active */
  2543. dma_addr_t gid_list_dma;
  2544. struct gid_list_info *gid_list;
  2545. int gid_list_info_size;
  2546. /* Small DMA pool allocations -- maximum 256 bytes in length. */
  2547. #define DMA_POOL_SIZE 256
  2548. struct dma_pool *s_dma_pool;
  2549. dma_addr_t init_cb_dma;
  2550. init_cb_t *init_cb;
  2551. int init_cb_size;
  2552. dma_addr_t ex_init_cb_dma;
  2553. struct ex_init_cb_81xx *ex_init_cb;
  2554. void *async_pd;
  2555. dma_addr_t async_pd_dma;
  2556. void *swl;
  2557. /* These are used by mailbox operations. */
  2558. volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
  2559. mbx_cmd_t *mcp;
  2560. unsigned long mbx_cmd_flags;
  2561. #define MBX_INTERRUPT 1
  2562. #define MBX_INTR_WAIT 2
  2563. #define MBX_UPDATE_FLASH_ACTIVE 3
  2564. struct mutex vport_lock; /* Virtual port synchronization */
  2565. spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
  2566. struct completion mbx_cmd_comp; /* Serialize mbx access */
  2567. struct completion mbx_intr_comp; /* Used for completion notification */
  2568. struct completion dcbx_comp; /* For set port config notification */
  2569. struct completion lb_portup_comp; /* Used to wait for link up during
  2570. * loopback */
  2571. #define DCBX_COMP_TIMEOUT 20
  2572. #define LB_PORTUP_COMP_TIMEOUT 10
  2573. int notify_dcbx_comp;
  2574. int notify_lb_portup_comp;
  2575. struct mutex selflogin_lock;
  2576. /* Basic firmware related information. */
  2577. uint16_t fw_major_version;
  2578. uint16_t fw_minor_version;
  2579. uint16_t fw_subminor_version;
  2580. uint16_t fw_attributes;
  2581. uint16_t fw_attributes_h;
  2582. uint16_t fw_attributes_ext[2];
  2583. uint32_t fw_memory_size;
  2584. uint32_t fw_transfer_size;
  2585. uint32_t fw_srisc_address;
  2586. #define RISC_START_ADDRESS_2100 0x1000
  2587. #define RISC_START_ADDRESS_2300 0x800
  2588. #define RISC_START_ADDRESS_2400 0x100000
  2589. uint16_t fw_xcb_count;
  2590. uint16_t fw_iocb_count;
  2591. uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
  2592. uint8_t fw_seriallink_options[4];
  2593. uint16_t fw_seriallink_options24[4];
  2594. uint8_t mpi_version[3];
  2595. uint32_t mpi_capabilities;
  2596. uint8_t phy_version[3];
  2597. /* Firmware dump information. */
  2598. struct qla2xxx_fw_dump *fw_dump;
  2599. uint32_t fw_dump_len;
  2600. int fw_dumped;
  2601. int fw_dump_reading;
  2602. dma_addr_t eft_dma;
  2603. void *eft;
  2604. /* Current size of mctp dump is 0x086064 bytes */
  2605. #define MCTP_DUMP_SIZE 0x086064
  2606. dma_addr_t mctp_dump_dma;
  2607. void *mctp_dump;
  2608. int mctp_dumped;
  2609. int mctp_dump_reading;
  2610. uint32_t chain_offset;
  2611. struct dentry *dfs_dir;
  2612. struct dentry *dfs_fce;
  2613. dma_addr_t fce_dma;
  2614. void *fce;
  2615. uint32_t fce_bufs;
  2616. uint16_t fce_mb[8];
  2617. uint64_t fce_wr, fce_rd;
  2618. struct mutex fce_mutex;
  2619. uint32_t pci_attr;
  2620. uint16_t chip_revision;
  2621. uint16_t product_id[4];
  2622. uint8_t model_number[16+1];
  2623. #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
  2624. char model_desc[80];
  2625. uint8_t adapter_id[16+1];
  2626. /* Option ROM information. */
  2627. char *optrom_buffer;
  2628. uint32_t optrom_size;
  2629. int optrom_state;
  2630. #define QLA_SWAITING 0
  2631. #define QLA_SREADING 1
  2632. #define QLA_SWRITING 2
  2633. uint32_t optrom_region_start;
  2634. uint32_t optrom_region_size;
  2635. /* PCI expansion ROM image information. */
  2636. #define ROM_CODE_TYPE_BIOS 0
  2637. #define ROM_CODE_TYPE_FCODE 1
  2638. #define ROM_CODE_TYPE_EFI 3
  2639. uint8_t bios_revision[2];
  2640. uint8_t efi_revision[2];
  2641. uint8_t fcode_revision[16];
  2642. uint32_t fw_revision[4];
  2643. uint32_t gold_fw_version[4];
  2644. /* Offsets for flash/nvram access (set to ~0 if not used). */
  2645. uint32_t flash_conf_off;
  2646. uint32_t flash_data_off;
  2647. uint32_t nvram_conf_off;
  2648. uint32_t nvram_data_off;
  2649. uint32_t fdt_wrt_disable;
  2650. uint32_t fdt_erase_cmd;
  2651. uint32_t fdt_block_size;
  2652. uint32_t fdt_unprotect_sec_cmd;
  2653. uint32_t fdt_protect_sec_cmd;
  2654. uint32_t flt_region_flt;
  2655. uint32_t flt_region_fdt;
  2656. uint32_t flt_region_boot;
  2657. uint32_t flt_region_fw;
  2658. uint32_t flt_region_vpd_nvram;
  2659. uint32_t flt_region_vpd;
  2660. uint32_t flt_region_nvram;
  2661. uint32_t flt_region_npiv_conf;
  2662. uint32_t flt_region_gold_fw;
  2663. uint32_t flt_region_fcp_prio;
  2664. uint32_t flt_region_bootload;
  2665. /* Needed for BEACON */
  2666. uint16_t beacon_blink_led;
  2667. uint8_t beacon_color_state;
  2668. #define QLA_LED_GRN_ON 0x01
  2669. #define QLA_LED_YLW_ON 0x02
  2670. #define QLA_LED_ABR_ON 0x04
  2671. #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
  2672. /* ISP2322: red, green, amber. */
  2673. uint16_t zio_mode;
  2674. uint16_t zio_timer;
  2675. struct qla_msix_entry *msix_entries;
  2676. struct list_head vp_list; /* list of VP */
  2677. unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
  2678. sizeof(unsigned long)];
  2679. uint16_t num_vhosts; /* number of vports created */
  2680. uint16_t num_vsans; /* number of vsan created */
  2681. uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
  2682. int cur_vport_count;
  2683. struct qla_chip_state_84xx *cs84xx;
  2684. struct isp_operations *isp_ops;
  2685. struct workqueue_struct *wq;
  2686. struct qlfc_fw fw_buf;
  2687. /* FCP_CMND priority support */
  2688. struct qla_fcp_prio_cfg *fcp_prio_cfg;
  2689. struct dma_pool *dl_dma_pool;
  2690. #define DSD_LIST_DMA_POOL_SIZE 512
  2691. struct dma_pool *fcp_cmnd_dma_pool;
  2692. mempool_t *ctx_mempool;
  2693. #define FCP_CMND_DMA_POOL_SIZE 512
  2694. unsigned long nx_pcibase; /* Base I/O address */
  2695. uint8_t *nxdb_rd_ptr; /* Doorbell read pointer */
  2696. unsigned long nxdb_wr_ptr; /* Door bell write pointer */
  2697. uint32_t crb_win;
  2698. uint32_t curr_window;
  2699. uint32_t ddr_mn_window;
  2700. unsigned long mn_win_crb;
  2701. unsigned long ms_win_crb;
  2702. int qdr_sn_window;
  2703. uint32_t fcoe_dev_init_timeout;
  2704. uint32_t fcoe_reset_timeout;
  2705. rwlock_t hw_lock;
  2706. uint16_t portnum; /* port number */
  2707. int link_width;
  2708. struct fw_blob *hablob;
  2709. struct qla82xx_legacy_intr_set nx_legacy_intr;
  2710. uint16_t gbl_dsd_inuse;
  2711. uint16_t gbl_dsd_avail;
  2712. struct list_head gbl_dsd_list;
  2713. #define NUM_DSD_CHAIN 4096
  2714. uint8_t fw_type;
  2715. __le32 file_prd_off; /* File firmware product offset */
  2716. uint32_t md_template_size;
  2717. void *md_tmplt_hdr;
  2718. dma_addr_t md_tmplt_hdr_dma;
  2719. void *md_dump;
  2720. uint32_t md_dump_size;
  2721. void *loop_id_map;
  2722. /* QLA83XX IDC specific fields */
  2723. uint32_t idc_audit_ts;
  2724. /* DPC low-priority workqueue */
  2725. struct workqueue_struct *dpc_lp_wq;
  2726. struct work_struct idc_aen;
  2727. /* DPC high-priority workqueue */
  2728. struct workqueue_struct *dpc_hp_wq;
  2729. struct work_struct nic_core_reset;
  2730. struct work_struct idc_state_handler;
  2731. struct work_struct nic_core_unrecoverable;
  2732. #define HOST_QUEUE_RAMPDOWN_INTERVAL (60 * HZ)
  2733. #define HOST_QUEUE_RAMPUP_INTERVAL (30 * HZ)
  2734. unsigned long host_last_rampdown_time;
  2735. unsigned long host_last_rampup_time;
  2736. int cfg_lun_q_depth;
  2737. struct qlt_hw_data tgt;
  2738. uint16_t thermal_support;
  2739. #define THERMAL_SUPPORT_I2C BIT_0
  2740. #define THERMAL_SUPPORT_ISP BIT_1
  2741. };
  2742. /*
  2743. * Qlogic scsi host structure
  2744. */
  2745. typedef struct scsi_qla_host {
  2746. struct list_head list;
  2747. struct list_head vp_fcports; /* list of fcports */
  2748. struct list_head work_list;
  2749. spinlock_t work_lock;
  2750. /* Commonly used flags and state information. */
  2751. struct Scsi_Host *host;
  2752. unsigned long host_no;
  2753. uint8_t host_str[16];
  2754. volatile struct {
  2755. uint32_t init_done :1;
  2756. uint32_t online :1;
  2757. uint32_t reset_active :1;
  2758. uint32_t management_server_logged_in :1;
  2759. uint32_t process_response_queue :1;
  2760. uint32_t difdix_supported:1;
  2761. uint32_t delete_progress:1;
  2762. } flags;
  2763. atomic_t loop_state;
  2764. #define LOOP_TIMEOUT 1
  2765. #define LOOP_DOWN 2
  2766. #define LOOP_UP 3
  2767. #define LOOP_UPDATE 4
  2768. #define LOOP_READY 5
  2769. #define LOOP_DEAD 6
  2770. unsigned long dpc_flags;
  2771. #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
  2772. #define RESET_ACTIVE 1
  2773. #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
  2774. #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
  2775. #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
  2776. #define LOOP_RESYNC_ACTIVE 5
  2777. #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
  2778. #define RSCN_UPDATE 7 /* Perform an RSCN update. */
  2779. #define RELOGIN_NEEDED 8
  2780. #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
  2781. #define ISP_ABORT_RETRY 10 /* ISP aborted. */
  2782. #define BEACON_BLINK_NEEDED 11
  2783. #define REGISTER_FDMI_NEEDED 12
  2784. #define FCPORT_UPDATE_NEEDED 13
  2785. #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
  2786. #define UNLOADING 15
  2787. #define NPIV_CONFIG_NEEDED 16
  2788. #define ISP_UNRECOVERABLE 17
  2789. #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
  2790. #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
  2791. #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
  2792. #define SCR_PENDING 21 /* SCR in target mode */
  2793. #define HOST_RAMP_DOWN_QUEUE_DEPTH 22
  2794. #define HOST_RAMP_UP_QUEUE_DEPTH 23
  2795. uint32_t device_flags;
  2796. #define SWITCH_FOUND BIT_0
  2797. #define DFLG_NO_CABLE BIT_1
  2798. #define DFLG_DEV_FAILED BIT_5
  2799. /* ISP configuration data. */
  2800. uint16_t loop_id; /* Host adapter loop id */
  2801. uint16_t self_login_loop_id; /* host adapter loop id
  2802. * get it on self login
  2803. */
  2804. fc_port_t bidir_fcport; /* fcport used for bidir cmnds
  2805. * no need of allocating it for
  2806. * each command
  2807. */
  2808. port_id_t d_id; /* Host adapter port id */
  2809. uint8_t marker_needed;
  2810. uint16_t mgmt_svr_loop_id;
  2811. /* Timeout timers. */
  2812. uint8_t loop_down_abort_time; /* port down timer */
  2813. atomic_t loop_down_timer; /* loop down timer */
  2814. uint8_t link_down_timeout; /* link down timeout */
  2815. uint32_t timer_active;
  2816. struct timer_list timer;
  2817. uint8_t node_name[WWN_SIZE];
  2818. uint8_t port_name[WWN_SIZE];
  2819. uint8_t fabric_node_name[WWN_SIZE];
  2820. uint16_t fcoe_vlan_id;
  2821. uint16_t fcoe_fcf_idx;
  2822. uint8_t fcoe_vn_port_mac[6];
  2823. uint32_t vp_abort_cnt;
  2824. struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
  2825. uint16_t vp_idx; /* vport ID */
  2826. unsigned long vp_flags;
  2827. #define VP_IDX_ACQUIRED 0 /* bit no 0 */
  2828. #define VP_CREATE_NEEDED 1
  2829. #define VP_BIND_NEEDED 2
  2830. #define VP_DELETE_NEEDED 3
  2831. #define VP_SCR_NEEDED 4 /* State Change Request registration */
  2832. atomic_t vp_state;
  2833. #define VP_OFFLINE 0
  2834. #define VP_ACTIVE 1
  2835. #define VP_FAILED 2
  2836. // #define VP_DISABLE 3
  2837. uint16_t vp_err_state;
  2838. uint16_t vp_prev_err_state;
  2839. #define VP_ERR_UNKWN 0
  2840. #define VP_ERR_PORTDWN 1
  2841. #define VP_ERR_FAB_UNSUPPORTED 2
  2842. #define VP_ERR_FAB_NORESOURCES 3
  2843. #define VP_ERR_FAB_LOGOUT 4
  2844. #define VP_ERR_ADAP_NORESOURCES 5
  2845. struct qla_hw_data *hw;
  2846. struct req_que *req;
  2847. int fw_heartbeat_counter;
  2848. int seconds_since_last_heartbeat;
  2849. struct fc_host_statistics fc_host_stat;
  2850. struct qla_statistics qla_stats;
  2851. struct bidi_statistics bidi_stats;
  2852. atomic_t vref_count;
  2853. } scsi_qla_host_t;
  2854. #define SET_VP_IDX 1
  2855. #define SET_AL_PA 2
  2856. #define RESET_VP_IDX 3
  2857. #define RESET_AL_PA 4
  2858. struct qla_tgt_vp_map {
  2859. uint8_t idx;
  2860. scsi_qla_host_t *vha;
  2861. };
  2862. /*
  2863. * Macros to help code, maintain, etc.
  2864. */
  2865. #define LOOP_TRANSITION(ha) \
  2866. (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
  2867. test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
  2868. atomic_read(&ha->loop_state) == LOOP_DOWN)
  2869. #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
  2870. atomic_inc(&__vha->vref_count); \
  2871. mb(); \
  2872. if (__vha->flags.delete_progress) { \
  2873. atomic_dec(&__vha->vref_count); \
  2874. __bail = 1; \
  2875. } else { \
  2876. __bail = 0; \
  2877. } \
  2878. } while (0)
  2879. #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
  2880. atomic_dec(&__vha->vref_count); \
  2881. } while (0)
  2882. /*
  2883. * qla2x00 local function return status codes
  2884. */
  2885. #define MBS_MASK 0x3fff
  2886. #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
  2887. #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
  2888. #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
  2889. #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
  2890. #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
  2891. #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
  2892. #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
  2893. #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
  2894. #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
  2895. #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
  2896. #define QLA_FUNCTION_TIMEOUT 0x100
  2897. #define QLA_FUNCTION_PARAMETER_ERROR 0x101
  2898. #define QLA_FUNCTION_FAILED 0x102
  2899. #define QLA_MEMORY_ALLOC_FAILED 0x103
  2900. #define QLA_LOCK_TIMEOUT 0x104
  2901. #define QLA_ABORTED 0x105
  2902. #define QLA_SUSPENDED 0x106
  2903. #define QLA_BUSY 0x107
  2904. #define QLA_ALREADY_REGISTERED 0x109
  2905. #define NVRAM_DELAY() udelay(10)
  2906. /*
  2907. * Flash support definitions
  2908. */
  2909. #define OPTROM_SIZE_2300 0x20000
  2910. #define OPTROM_SIZE_2322 0x100000
  2911. #define OPTROM_SIZE_24XX 0x100000
  2912. #define OPTROM_SIZE_25XX 0x200000
  2913. #define OPTROM_SIZE_81XX 0x400000
  2914. #define OPTROM_SIZE_82XX 0x800000
  2915. #define OPTROM_SIZE_83XX 0x1000000
  2916. #define OPTROM_BURST_SIZE 0x1000
  2917. #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
  2918. #define QLA_DSDS_PER_IOCB 37
  2919. #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
  2920. #define QLA_SG_ALL 1024
  2921. enum nexus_wait_type {
  2922. WAIT_HOST = 0,
  2923. WAIT_TARGET,
  2924. WAIT_LUN,
  2925. };
  2926. #include "qla_gbl.h"
  2927. #include "qla_dbg.h"
  2928. #include "qla_inline.h"
  2929. #endif