bnx2fc_hwi.c 62 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177
  1. /* bnx2fc_hwi.c: Broadcom NetXtreme II Linux FCoE offload driver.
  2. * This file contains the code that low level functions that interact
  3. * with 57712 FCoE firmware.
  4. *
  5. * Copyright (c) 2008 - 2011 Broadcom Corporation
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation.
  10. *
  11. * Written by: Bhanu Prakash Gollapudi (bprakash@broadcom.com)
  12. */
  13. #include "bnx2fc.h"
  14. DECLARE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu);
  15. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  16. struct fcoe_kcqe *new_cqe_kcqe);
  17. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  18. struct fcoe_kcqe *ofld_kcqe);
  19. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  20. struct fcoe_kcqe *ofld_kcqe);
  21. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code);
  22. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  23. struct fcoe_kcqe *destroy_kcqe);
  24. int bnx2fc_send_stat_req(struct bnx2fc_hba *hba)
  25. {
  26. struct fcoe_kwqe_stat stat_req;
  27. struct kwqe *kwqe_arr[2];
  28. int num_kwqes = 1;
  29. int rc = 0;
  30. memset(&stat_req, 0x00, sizeof(struct fcoe_kwqe_stat));
  31. stat_req.hdr.op_code = FCOE_KWQE_OPCODE_STAT;
  32. stat_req.hdr.flags =
  33. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  34. stat_req.stat_params_addr_lo = (u32) hba->stats_buf_dma;
  35. stat_req.stat_params_addr_hi = (u32) ((u64)hba->stats_buf_dma >> 32);
  36. kwqe_arr[0] = (struct kwqe *) &stat_req;
  37. if (hba->cnic && hba->cnic->submit_kwqes)
  38. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  39. return rc;
  40. }
  41. /**
  42. * bnx2fc_send_fw_fcoe_init_msg - initiates initial handshake with FCoE f/w
  43. *
  44. * @hba: adapter structure pointer
  45. *
  46. * Send down FCoE firmware init KWQEs which initiates the initial handshake
  47. * with the f/w.
  48. *
  49. */
  50. int bnx2fc_send_fw_fcoe_init_msg(struct bnx2fc_hba *hba)
  51. {
  52. struct fcoe_kwqe_init1 fcoe_init1;
  53. struct fcoe_kwqe_init2 fcoe_init2;
  54. struct fcoe_kwqe_init3 fcoe_init3;
  55. struct kwqe *kwqe_arr[3];
  56. int num_kwqes = 3;
  57. int rc = 0;
  58. if (!hba->cnic) {
  59. printk(KERN_ERR PFX "hba->cnic NULL during fcoe fw init\n");
  60. return -ENODEV;
  61. }
  62. /* fill init1 KWQE */
  63. memset(&fcoe_init1, 0x00, sizeof(struct fcoe_kwqe_init1));
  64. fcoe_init1.hdr.op_code = FCOE_KWQE_OPCODE_INIT1;
  65. fcoe_init1.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  66. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  67. fcoe_init1.num_tasks = BNX2FC_MAX_TASKS;
  68. fcoe_init1.sq_num_wqes = BNX2FC_SQ_WQES_MAX;
  69. fcoe_init1.rq_num_wqes = BNX2FC_RQ_WQES_MAX;
  70. fcoe_init1.rq_buffer_log_size = BNX2FC_RQ_BUF_LOG_SZ;
  71. fcoe_init1.cq_num_wqes = BNX2FC_CQ_WQES_MAX;
  72. fcoe_init1.dummy_buffer_addr_lo = (u32) hba->dummy_buf_dma;
  73. fcoe_init1.dummy_buffer_addr_hi = (u32) ((u64)hba->dummy_buf_dma >> 32);
  74. fcoe_init1.task_list_pbl_addr_lo = (u32) hba->task_ctx_bd_dma;
  75. fcoe_init1.task_list_pbl_addr_hi =
  76. (u32) ((u64) hba->task_ctx_bd_dma >> 32);
  77. fcoe_init1.mtu = BNX2FC_MINI_JUMBO_MTU;
  78. fcoe_init1.flags = (PAGE_SHIFT <<
  79. FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT);
  80. fcoe_init1.num_sessions_log = BNX2FC_NUM_MAX_SESS_LOG;
  81. /* fill init2 KWQE */
  82. memset(&fcoe_init2, 0x00, sizeof(struct fcoe_kwqe_init2));
  83. fcoe_init2.hdr.op_code = FCOE_KWQE_OPCODE_INIT2;
  84. fcoe_init2.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  85. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  86. fcoe_init2.hsi_major_version = FCOE_HSI_MAJOR_VERSION;
  87. fcoe_init2.hsi_minor_version = FCOE_HSI_MINOR_VERSION;
  88. fcoe_init2.hash_tbl_pbl_addr_lo = (u32) hba->hash_tbl_pbl_dma;
  89. fcoe_init2.hash_tbl_pbl_addr_hi = (u32)
  90. ((u64) hba->hash_tbl_pbl_dma >> 32);
  91. fcoe_init2.t2_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_dma;
  92. fcoe_init2.t2_hash_tbl_addr_hi = (u32)
  93. ((u64) hba->t2_hash_tbl_dma >> 32);
  94. fcoe_init2.t2_ptr_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_ptr_dma;
  95. fcoe_init2.t2_ptr_hash_tbl_addr_hi = (u32)
  96. ((u64) hba->t2_hash_tbl_ptr_dma >> 32);
  97. fcoe_init2.free_list_count = BNX2FC_NUM_MAX_SESS;
  98. /* fill init3 KWQE */
  99. memset(&fcoe_init3, 0x00, sizeof(struct fcoe_kwqe_init3));
  100. fcoe_init3.hdr.op_code = FCOE_KWQE_OPCODE_INIT3;
  101. fcoe_init3.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  102. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  103. fcoe_init3.error_bit_map_lo = 0xffffffff;
  104. fcoe_init3.error_bit_map_hi = 0xffffffff;
  105. fcoe_init3.perf_config = 1;
  106. kwqe_arr[0] = (struct kwqe *) &fcoe_init1;
  107. kwqe_arr[1] = (struct kwqe *) &fcoe_init2;
  108. kwqe_arr[2] = (struct kwqe *) &fcoe_init3;
  109. if (hba->cnic && hba->cnic->submit_kwqes)
  110. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  111. return rc;
  112. }
  113. int bnx2fc_send_fw_fcoe_destroy_msg(struct bnx2fc_hba *hba)
  114. {
  115. struct fcoe_kwqe_destroy fcoe_destroy;
  116. struct kwqe *kwqe_arr[2];
  117. int num_kwqes = 1;
  118. int rc = -1;
  119. /* fill destroy KWQE */
  120. memset(&fcoe_destroy, 0x00, sizeof(struct fcoe_kwqe_destroy));
  121. fcoe_destroy.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY;
  122. fcoe_destroy.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  123. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  124. kwqe_arr[0] = (struct kwqe *) &fcoe_destroy;
  125. if (hba->cnic && hba->cnic->submit_kwqes)
  126. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  127. return rc;
  128. }
  129. /**
  130. * bnx2fc_send_session_ofld_req - initiates FCoE Session offload process
  131. *
  132. * @port: port structure pointer
  133. * @tgt: bnx2fc_rport structure pointer
  134. */
  135. int bnx2fc_send_session_ofld_req(struct fcoe_port *port,
  136. struct bnx2fc_rport *tgt)
  137. {
  138. struct fc_lport *lport = port->lport;
  139. struct bnx2fc_interface *interface = port->priv;
  140. struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
  141. struct bnx2fc_hba *hba = interface->hba;
  142. struct kwqe *kwqe_arr[4];
  143. struct fcoe_kwqe_conn_offload1 ofld_req1;
  144. struct fcoe_kwqe_conn_offload2 ofld_req2;
  145. struct fcoe_kwqe_conn_offload3 ofld_req3;
  146. struct fcoe_kwqe_conn_offload4 ofld_req4;
  147. struct fc_rport_priv *rdata = tgt->rdata;
  148. struct fc_rport *rport = tgt->rport;
  149. int num_kwqes = 4;
  150. u32 port_id;
  151. int rc = 0;
  152. u16 conn_id;
  153. /* Initialize offload request 1 structure */
  154. memset(&ofld_req1, 0x00, sizeof(struct fcoe_kwqe_conn_offload1));
  155. ofld_req1.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN1;
  156. ofld_req1.hdr.flags =
  157. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  158. conn_id = (u16)tgt->fcoe_conn_id;
  159. ofld_req1.fcoe_conn_id = conn_id;
  160. ofld_req1.sq_addr_lo = (u32) tgt->sq_dma;
  161. ofld_req1.sq_addr_hi = (u32)((u64) tgt->sq_dma >> 32);
  162. ofld_req1.rq_pbl_addr_lo = (u32) tgt->rq_pbl_dma;
  163. ofld_req1.rq_pbl_addr_hi = (u32)((u64) tgt->rq_pbl_dma >> 32);
  164. ofld_req1.rq_first_pbe_addr_lo = (u32) tgt->rq_dma;
  165. ofld_req1.rq_first_pbe_addr_hi =
  166. (u32)((u64) tgt->rq_dma >> 32);
  167. ofld_req1.rq_prod = 0x8000;
  168. /* Initialize offload request 2 structure */
  169. memset(&ofld_req2, 0x00, sizeof(struct fcoe_kwqe_conn_offload2));
  170. ofld_req2.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN2;
  171. ofld_req2.hdr.flags =
  172. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  173. ofld_req2.tx_max_fc_pay_len = rdata->maxframe_size;
  174. ofld_req2.cq_addr_lo = (u32) tgt->cq_dma;
  175. ofld_req2.cq_addr_hi = (u32)((u64)tgt->cq_dma >> 32);
  176. ofld_req2.xferq_addr_lo = (u32) tgt->xferq_dma;
  177. ofld_req2.xferq_addr_hi = (u32)((u64)tgt->xferq_dma >> 32);
  178. ofld_req2.conn_db_addr_lo = (u32)tgt->conn_db_dma;
  179. ofld_req2.conn_db_addr_hi = (u32)((u64)tgt->conn_db_dma >> 32);
  180. /* Initialize offload request 3 structure */
  181. memset(&ofld_req3, 0x00, sizeof(struct fcoe_kwqe_conn_offload3));
  182. ofld_req3.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN3;
  183. ofld_req3.hdr.flags =
  184. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  185. ofld_req3.vlan_tag = interface->vlan_id <<
  186. FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT;
  187. ofld_req3.vlan_tag |= 3 << FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT;
  188. port_id = fc_host_port_id(lport->host);
  189. if (port_id == 0) {
  190. BNX2FC_HBA_DBG(lport, "ofld_req: port_id = 0, link down?\n");
  191. return -EINVAL;
  192. }
  193. /*
  194. * Store s_id of the initiator for further reference. This will
  195. * be used during disable/destroy during linkdown processing as
  196. * when the lport is reset, the port_id also is reset to 0
  197. */
  198. tgt->sid = port_id;
  199. ofld_req3.s_id[0] = (port_id & 0x000000FF);
  200. ofld_req3.s_id[1] = (port_id & 0x0000FF00) >> 8;
  201. ofld_req3.s_id[2] = (port_id & 0x00FF0000) >> 16;
  202. port_id = rport->port_id;
  203. ofld_req3.d_id[0] = (port_id & 0x000000FF);
  204. ofld_req3.d_id[1] = (port_id & 0x0000FF00) >> 8;
  205. ofld_req3.d_id[2] = (port_id & 0x00FF0000) >> 16;
  206. ofld_req3.tx_total_conc_seqs = rdata->max_seq;
  207. ofld_req3.tx_max_conc_seqs_c3 = rdata->max_seq;
  208. ofld_req3.rx_max_fc_pay_len = lport->mfs;
  209. ofld_req3.rx_total_conc_seqs = BNX2FC_MAX_SEQS;
  210. ofld_req3.rx_max_conc_seqs_c3 = BNX2FC_MAX_SEQS;
  211. ofld_req3.rx_open_seqs_exch_c3 = 1;
  212. ofld_req3.confq_first_pbe_addr_lo = tgt->confq_dma;
  213. ofld_req3.confq_first_pbe_addr_hi = (u32)((u64) tgt->confq_dma >> 32);
  214. /* set mul_n_port_ids supported flag to 0, until it is supported */
  215. ofld_req3.flags = 0;
  216. /*
  217. ofld_req3.flags |= (((lport->send_sp_features & FC_SP_FT_MNA) ? 1:0) <<
  218. FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT);
  219. */
  220. /* Info from PLOGI response */
  221. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_EDTR) ? 1 : 0) <<
  222. FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT);
  223. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_SEQC) ? 1 : 0) <<
  224. FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT);
  225. /*
  226. * Info from PRLI response, this info is used for sequence level error
  227. * recovery support
  228. */
  229. if (tgt->dev_type == TYPE_TAPE) {
  230. ofld_req3.flags |= 1 <<
  231. FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT;
  232. ofld_req3.flags |= (((rdata->flags & FC_RP_FLAGS_REC_SUPPORTED)
  233. ? 1 : 0) <<
  234. FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT);
  235. }
  236. /* vlan flag */
  237. ofld_req3.flags |= (interface->vlan_enabled <<
  238. FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT);
  239. /* C2_VALID and ACK flags are not set as they are not supported */
  240. /* Initialize offload request 4 structure */
  241. memset(&ofld_req4, 0x00, sizeof(struct fcoe_kwqe_conn_offload4));
  242. ofld_req4.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN4;
  243. ofld_req4.hdr.flags =
  244. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  245. ofld_req4.e_d_tov_timer_val = lport->e_d_tov / 20;
  246. ofld_req4.src_mac_addr_lo[0] = port->data_src_addr[5];
  247. /* local mac */
  248. ofld_req4.src_mac_addr_lo[1] = port->data_src_addr[4];
  249. ofld_req4.src_mac_addr_mid[0] = port->data_src_addr[3];
  250. ofld_req4.src_mac_addr_mid[1] = port->data_src_addr[2];
  251. ofld_req4.src_mac_addr_hi[0] = port->data_src_addr[1];
  252. ofld_req4.src_mac_addr_hi[1] = port->data_src_addr[0];
  253. ofld_req4.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
  254. /* fcf mac */
  255. ofld_req4.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
  256. ofld_req4.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
  257. ofld_req4.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
  258. ofld_req4.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
  259. ofld_req4.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
  260. ofld_req4.lcq_addr_lo = (u32) tgt->lcq_dma;
  261. ofld_req4.lcq_addr_hi = (u32)((u64) tgt->lcq_dma >> 32);
  262. ofld_req4.confq_pbl_base_addr_lo = (u32) tgt->confq_pbl_dma;
  263. ofld_req4.confq_pbl_base_addr_hi =
  264. (u32)((u64) tgt->confq_pbl_dma >> 32);
  265. kwqe_arr[0] = (struct kwqe *) &ofld_req1;
  266. kwqe_arr[1] = (struct kwqe *) &ofld_req2;
  267. kwqe_arr[2] = (struct kwqe *) &ofld_req3;
  268. kwqe_arr[3] = (struct kwqe *) &ofld_req4;
  269. if (hba->cnic && hba->cnic->submit_kwqes)
  270. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  271. return rc;
  272. }
  273. /**
  274. * bnx2fc_send_session_enable_req - initiates FCoE Session enablement
  275. *
  276. * @port: port structure pointer
  277. * @tgt: bnx2fc_rport structure pointer
  278. */
  279. int bnx2fc_send_session_enable_req(struct fcoe_port *port,
  280. struct bnx2fc_rport *tgt)
  281. {
  282. struct kwqe *kwqe_arr[2];
  283. struct bnx2fc_interface *interface = port->priv;
  284. struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
  285. struct bnx2fc_hba *hba = interface->hba;
  286. struct fcoe_kwqe_conn_enable_disable enbl_req;
  287. struct fc_lport *lport = port->lport;
  288. struct fc_rport *rport = tgt->rport;
  289. int num_kwqes = 1;
  290. int rc = 0;
  291. u32 port_id;
  292. memset(&enbl_req, 0x00,
  293. sizeof(struct fcoe_kwqe_conn_enable_disable));
  294. enbl_req.hdr.op_code = FCOE_KWQE_OPCODE_ENABLE_CONN;
  295. enbl_req.hdr.flags =
  296. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  297. enbl_req.src_mac_addr_lo[0] = port->data_src_addr[5];
  298. /* local mac */
  299. enbl_req.src_mac_addr_lo[1] = port->data_src_addr[4];
  300. enbl_req.src_mac_addr_mid[0] = port->data_src_addr[3];
  301. enbl_req.src_mac_addr_mid[1] = port->data_src_addr[2];
  302. enbl_req.src_mac_addr_hi[0] = port->data_src_addr[1];
  303. enbl_req.src_mac_addr_hi[1] = port->data_src_addr[0];
  304. memcpy(tgt->src_addr, port->data_src_addr, ETH_ALEN);
  305. enbl_req.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
  306. enbl_req.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
  307. enbl_req.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
  308. enbl_req.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
  309. enbl_req.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
  310. enbl_req.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
  311. port_id = fc_host_port_id(lport->host);
  312. if (port_id != tgt->sid) {
  313. printk(KERN_ERR PFX "WARN: enable_req port_id = 0x%x,"
  314. "sid = 0x%x\n", port_id, tgt->sid);
  315. port_id = tgt->sid;
  316. }
  317. enbl_req.s_id[0] = (port_id & 0x000000FF);
  318. enbl_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  319. enbl_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  320. port_id = rport->port_id;
  321. enbl_req.d_id[0] = (port_id & 0x000000FF);
  322. enbl_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  323. enbl_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  324. enbl_req.vlan_tag = interface->vlan_id <<
  325. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  326. enbl_req.vlan_tag |= 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  327. enbl_req.vlan_flag = interface->vlan_enabled;
  328. enbl_req.context_id = tgt->context_id;
  329. enbl_req.conn_id = tgt->fcoe_conn_id;
  330. kwqe_arr[0] = (struct kwqe *) &enbl_req;
  331. if (hba->cnic && hba->cnic->submit_kwqes)
  332. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  333. return rc;
  334. }
  335. /**
  336. * bnx2fc_send_session_disable_req - initiates FCoE Session disable
  337. *
  338. * @port: port structure pointer
  339. * @tgt: bnx2fc_rport structure pointer
  340. */
  341. int bnx2fc_send_session_disable_req(struct fcoe_port *port,
  342. struct bnx2fc_rport *tgt)
  343. {
  344. struct bnx2fc_interface *interface = port->priv;
  345. struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
  346. struct bnx2fc_hba *hba = interface->hba;
  347. struct fcoe_kwqe_conn_enable_disable disable_req;
  348. struct kwqe *kwqe_arr[2];
  349. struct fc_rport *rport = tgt->rport;
  350. int num_kwqes = 1;
  351. int rc = 0;
  352. u32 port_id;
  353. memset(&disable_req, 0x00,
  354. sizeof(struct fcoe_kwqe_conn_enable_disable));
  355. disable_req.hdr.op_code = FCOE_KWQE_OPCODE_DISABLE_CONN;
  356. disable_req.hdr.flags =
  357. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  358. disable_req.src_mac_addr_lo[0] = tgt->src_addr[5];
  359. disable_req.src_mac_addr_lo[1] = tgt->src_addr[4];
  360. disable_req.src_mac_addr_mid[0] = tgt->src_addr[3];
  361. disable_req.src_mac_addr_mid[1] = tgt->src_addr[2];
  362. disable_req.src_mac_addr_hi[0] = tgt->src_addr[1];
  363. disable_req.src_mac_addr_hi[1] = tgt->src_addr[0];
  364. disable_req.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
  365. disable_req.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
  366. disable_req.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
  367. disable_req.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
  368. disable_req.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
  369. disable_req.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
  370. port_id = tgt->sid;
  371. disable_req.s_id[0] = (port_id & 0x000000FF);
  372. disable_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  373. disable_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  374. port_id = rport->port_id;
  375. disable_req.d_id[0] = (port_id & 0x000000FF);
  376. disable_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  377. disable_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  378. disable_req.context_id = tgt->context_id;
  379. disable_req.conn_id = tgt->fcoe_conn_id;
  380. disable_req.vlan_tag = interface->vlan_id <<
  381. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  382. disable_req.vlan_tag |=
  383. 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  384. disable_req.vlan_flag = interface->vlan_enabled;
  385. kwqe_arr[0] = (struct kwqe *) &disable_req;
  386. if (hba->cnic && hba->cnic->submit_kwqes)
  387. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  388. return rc;
  389. }
  390. /**
  391. * bnx2fc_send_session_destroy_req - initiates FCoE Session destroy
  392. *
  393. * @port: port structure pointer
  394. * @tgt: bnx2fc_rport structure pointer
  395. */
  396. int bnx2fc_send_session_destroy_req(struct bnx2fc_hba *hba,
  397. struct bnx2fc_rport *tgt)
  398. {
  399. struct fcoe_kwqe_conn_destroy destroy_req;
  400. struct kwqe *kwqe_arr[2];
  401. int num_kwqes = 1;
  402. int rc = 0;
  403. memset(&destroy_req, 0x00, sizeof(struct fcoe_kwqe_conn_destroy));
  404. destroy_req.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY_CONN;
  405. destroy_req.hdr.flags =
  406. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  407. destroy_req.context_id = tgt->context_id;
  408. destroy_req.conn_id = tgt->fcoe_conn_id;
  409. kwqe_arr[0] = (struct kwqe *) &destroy_req;
  410. if (hba->cnic && hba->cnic->submit_kwqes)
  411. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  412. return rc;
  413. }
  414. static bool is_valid_lport(struct bnx2fc_hba *hba, struct fc_lport *lport)
  415. {
  416. struct bnx2fc_lport *blport;
  417. spin_lock_bh(&hba->hba_lock);
  418. list_for_each_entry(blport, &hba->vports, list) {
  419. if (blport->lport == lport) {
  420. spin_unlock_bh(&hba->hba_lock);
  421. return true;
  422. }
  423. }
  424. spin_unlock_bh(&hba->hba_lock);
  425. return false;
  426. }
  427. static void bnx2fc_unsol_els_work(struct work_struct *work)
  428. {
  429. struct bnx2fc_unsol_els *unsol_els;
  430. struct fc_lport *lport;
  431. struct bnx2fc_hba *hba;
  432. struct fc_frame *fp;
  433. unsol_els = container_of(work, struct bnx2fc_unsol_els, unsol_els_work);
  434. lport = unsol_els->lport;
  435. fp = unsol_els->fp;
  436. hba = unsol_els->hba;
  437. if (is_valid_lport(hba, lport))
  438. fc_exch_recv(lport, fp);
  439. kfree(unsol_els);
  440. }
  441. void bnx2fc_process_l2_frame_compl(struct bnx2fc_rport *tgt,
  442. unsigned char *buf,
  443. u32 frame_len, u16 l2_oxid)
  444. {
  445. struct fcoe_port *port = tgt->port;
  446. struct fc_lport *lport = port->lport;
  447. struct bnx2fc_interface *interface = port->priv;
  448. struct bnx2fc_unsol_els *unsol_els;
  449. struct fc_frame_header *fh;
  450. struct fc_frame *fp;
  451. struct sk_buff *skb;
  452. u32 payload_len;
  453. u32 crc;
  454. u8 op;
  455. unsol_els = kzalloc(sizeof(*unsol_els), GFP_ATOMIC);
  456. if (!unsol_els) {
  457. BNX2FC_TGT_DBG(tgt, "Unable to allocate unsol_work\n");
  458. return;
  459. }
  460. BNX2FC_TGT_DBG(tgt, "l2_frame_compl l2_oxid = 0x%x, frame_len = %d\n",
  461. l2_oxid, frame_len);
  462. payload_len = frame_len - sizeof(struct fc_frame_header);
  463. fp = fc_frame_alloc(lport, payload_len);
  464. if (!fp) {
  465. printk(KERN_ERR PFX "fc_frame_alloc failure\n");
  466. kfree(unsol_els);
  467. return;
  468. }
  469. fh = (struct fc_frame_header *) fc_frame_header_get(fp);
  470. /* Copy FC Frame header and payload into the frame */
  471. memcpy(fh, buf, frame_len);
  472. if (l2_oxid != FC_XID_UNKNOWN)
  473. fh->fh_ox_id = htons(l2_oxid);
  474. skb = fp_skb(fp);
  475. if ((fh->fh_r_ctl == FC_RCTL_ELS_REQ) ||
  476. (fh->fh_r_ctl == FC_RCTL_ELS_REP)) {
  477. if (fh->fh_type == FC_TYPE_ELS) {
  478. op = fc_frame_payload_op(fp);
  479. if ((op == ELS_TEST) || (op == ELS_ESTC) ||
  480. (op == ELS_FAN) || (op == ELS_CSU)) {
  481. /*
  482. * No need to reply for these
  483. * ELS requests
  484. */
  485. printk(KERN_ERR PFX "dropping ELS 0x%x\n", op);
  486. kfree_skb(skb);
  487. kfree(unsol_els);
  488. return;
  489. }
  490. }
  491. crc = fcoe_fc_crc(fp);
  492. fc_frame_init(fp);
  493. fr_dev(fp) = lport;
  494. fr_sof(fp) = FC_SOF_I3;
  495. fr_eof(fp) = FC_EOF_T;
  496. fr_crc(fp) = cpu_to_le32(~crc);
  497. unsol_els->lport = lport;
  498. unsol_els->hba = interface->hba;
  499. unsol_els->fp = fp;
  500. INIT_WORK(&unsol_els->unsol_els_work, bnx2fc_unsol_els_work);
  501. queue_work(bnx2fc_wq, &unsol_els->unsol_els_work);
  502. } else {
  503. BNX2FC_HBA_DBG(lport, "fh_r_ctl = 0x%x\n", fh->fh_r_ctl);
  504. kfree_skb(skb);
  505. kfree(unsol_els);
  506. }
  507. }
  508. static void bnx2fc_process_unsol_compl(struct bnx2fc_rport *tgt, u16 wqe)
  509. {
  510. u8 num_rq;
  511. struct fcoe_err_report_entry *err_entry;
  512. unsigned char *rq_data;
  513. unsigned char *buf = NULL, *buf1;
  514. int i;
  515. u16 xid;
  516. u32 frame_len, len;
  517. struct bnx2fc_cmd *io_req = NULL;
  518. struct fcoe_task_ctx_entry *task, *task_page;
  519. struct bnx2fc_interface *interface = tgt->port->priv;
  520. struct bnx2fc_hba *hba = interface->hba;
  521. int task_idx, index;
  522. int rc = 0;
  523. u64 err_warn_bit_map;
  524. u8 err_warn = 0xff;
  525. BNX2FC_TGT_DBG(tgt, "Entered UNSOL COMPLETION wqe = 0x%x\n", wqe);
  526. switch (wqe & FCOE_UNSOLICITED_CQE_SUBTYPE) {
  527. case FCOE_UNSOLICITED_FRAME_CQE_TYPE:
  528. frame_len = (wqe & FCOE_UNSOLICITED_CQE_PKT_LEN) >>
  529. FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT;
  530. num_rq = (frame_len + BNX2FC_RQ_BUF_SZ - 1) / BNX2FC_RQ_BUF_SZ;
  531. spin_lock_bh(&tgt->tgt_lock);
  532. rq_data = (unsigned char *)bnx2fc_get_next_rqe(tgt, num_rq);
  533. spin_unlock_bh(&tgt->tgt_lock);
  534. if (rq_data) {
  535. buf = rq_data;
  536. } else {
  537. buf1 = buf = kmalloc((num_rq * BNX2FC_RQ_BUF_SZ),
  538. GFP_ATOMIC);
  539. if (!buf1) {
  540. BNX2FC_TGT_DBG(tgt, "Memory alloc failure\n");
  541. break;
  542. }
  543. for (i = 0; i < num_rq; i++) {
  544. spin_lock_bh(&tgt->tgt_lock);
  545. rq_data = (unsigned char *)
  546. bnx2fc_get_next_rqe(tgt, 1);
  547. spin_unlock_bh(&tgt->tgt_lock);
  548. len = BNX2FC_RQ_BUF_SZ;
  549. memcpy(buf1, rq_data, len);
  550. buf1 += len;
  551. }
  552. }
  553. bnx2fc_process_l2_frame_compl(tgt, buf, frame_len,
  554. FC_XID_UNKNOWN);
  555. if (buf != rq_data)
  556. kfree(buf);
  557. spin_lock_bh(&tgt->tgt_lock);
  558. bnx2fc_return_rqe(tgt, num_rq);
  559. spin_unlock_bh(&tgt->tgt_lock);
  560. break;
  561. case FCOE_ERROR_DETECTION_CQE_TYPE:
  562. /*
  563. * In case of error reporting CQE a single RQ entry
  564. * is consumed.
  565. */
  566. spin_lock_bh(&tgt->tgt_lock);
  567. num_rq = 1;
  568. err_entry = (struct fcoe_err_report_entry *)
  569. bnx2fc_get_next_rqe(tgt, 1);
  570. xid = err_entry->fc_hdr.ox_id;
  571. BNX2FC_TGT_DBG(tgt, "Unsol Error Frame OX_ID = 0x%x\n", xid);
  572. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x\n",
  573. err_entry->data.err_warn_bitmap_hi,
  574. err_entry->data.err_warn_bitmap_lo);
  575. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x\n",
  576. err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
  577. if (xid > BNX2FC_MAX_XID) {
  578. BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n",
  579. xid);
  580. goto ret_err_rqe;
  581. }
  582. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  583. index = xid % BNX2FC_TASKS_PER_PAGE;
  584. task_page = (struct fcoe_task_ctx_entry *)
  585. hba->task_ctx[task_idx];
  586. task = &(task_page[index]);
  587. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  588. if (!io_req)
  589. goto ret_err_rqe;
  590. if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
  591. printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
  592. goto ret_err_rqe;
  593. }
  594. if (test_and_clear_bit(BNX2FC_FLAG_IO_CLEANUP,
  595. &io_req->req_flags)) {
  596. BNX2FC_IO_DBG(io_req, "unsol_err: cleanup in "
  597. "progress.. ignore unsol err\n");
  598. goto ret_err_rqe;
  599. }
  600. err_warn_bit_map = (u64)
  601. ((u64)err_entry->data.err_warn_bitmap_hi << 32) |
  602. (u64)err_entry->data.err_warn_bitmap_lo;
  603. for (i = 0; i < BNX2FC_NUM_ERR_BITS; i++) {
  604. if (err_warn_bit_map & (u64)((u64)1 << i)) {
  605. err_warn = i;
  606. break;
  607. }
  608. }
  609. /*
  610. * If ABTS is already in progress, and FW error is
  611. * received after that, do not cancel the timeout_work
  612. * and let the error recovery continue by explicitly
  613. * logging out the target, when the ABTS eventually
  614. * times out.
  615. */
  616. if (test_bit(BNX2FC_FLAG_ISSUE_ABTS, &io_req->req_flags)) {
  617. printk(KERN_ERR PFX "err_warn: io_req (0x%x) already "
  618. "in ABTS processing\n", xid);
  619. goto ret_err_rqe;
  620. }
  621. BNX2FC_TGT_DBG(tgt, "err = 0x%x\n", err_warn);
  622. if (tgt->dev_type != TYPE_TAPE)
  623. goto skip_rec;
  624. switch (err_warn) {
  625. case FCOE_ERROR_CODE_REC_TOV_TIMER_EXPIRATION:
  626. case FCOE_ERROR_CODE_DATA_OOO_RO:
  627. case FCOE_ERROR_CODE_COMMON_INCORRECT_SEQ_CNT:
  628. case FCOE_ERROR_CODE_DATA_SOFI3_SEQ_ACTIVE_SET:
  629. case FCOE_ERROR_CODE_FCP_RSP_OPENED_SEQ:
  630. case FCOE_ERROR_CODE_DATA_SOFN_SEQ_ACTIVE_RESET:
  631. BNX2FC_TGT_DBG(tgt, "REC TOV popped for xid - 0x%x\n",
  632. xid);
  633. memcpy(&io_req->err_entry, err_entry,
  634. sizeof(struct fcoe_err_report_entry));
  635. if (!test_bit(BNX2FC_FLAG_SRR_SENT,
  636. &io_req->req_flags)) {
  637. spin_unlock_bh(&tgt->tgt_lock);
  638. rc = bnx2fc_send_rec(io_req);
  639. spin_lock_bh(&tgt->tgt_lock);
  640. if (rc)
  641. goto skip_rec;
  642. } else
  643. printk(KERN_ERR PFX "SRR in progress\n");
  644. goto ret_err_rqe;
  645. break;
  646. default:
  647. break;
  648. }
  649. skip_rec:
  650. set_bit(BNX2FC_FLAG_ISSUE_ABTS, &io_req->req_flags);
  651. /*
  652. * Cancel the timeout_work, as we received IO
  653. * completion with FW error.
  654. */
  655. if (cancel_delayed_work(&io_req->timeout_work))
  656. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  657. rc = bnx2fc_initiate_abts(io_req);
  658. if (rc != SUCCESS) {
  659. printk(KERN_ERR PFX "err_warn: initiate_abts "
  660. "failed xid = 0x%x. issue cleanup\n",
  661. io_req->xid);
  662. bnx2fc_initiate_cleanup(io_req);
  663. }
  664. ret_err_rqe:
  665. bnx2fc_return_rqe(tgt, 1);
  666. spin_unlock_bh(&tgt->tgt_lock);
  667. break;
  668. case FCOE_WARNING_DETECTION_CQE_TYPE:
  669. /*
  670. *In case of warning reporting CQE a single RQ entry
  671. * is consumes.
  672. */
  673. spin_lock_bh(&tgt->tgt_lock);
  674. num_rq = 1;
  675. err_entry = (struct fcoe_err_report_entry *)
  676. bnx2fc_get_next_rqe(tgt, 1);
  677. xid = cpu_to_be16(err_entry->fc_hdr.ox_id);
  678. BNX2FC_TGT_DBG(tgt, "Unsol Warning Frame OX_ID = 0x%x\n", xid);
  679. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x",
  680. err_entry->data.err_warn_bitmap_hi,
  681. err_entry->data.err_warn_bitmap_lo);
  682. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x",
  683. err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
  684. if (xid > BNX2FC_MAX_XID) {
  685. BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n", xid);
  686. goto ret_warn_rqe;
  687. }
  688. err_warn_bit_map = (u64)
  689. ((u64)err_entry->data.err_warn_bitmap_hi << 32) |
  690. (u64)err_entry->data.err_warn_bitmap_lo;
  691. for (i = 0; i < BNX2FC_NUM_ERR_BITS; i++) {
  692. if (err_warn_bit_map & (u64) (1 << i)) {
  693. err_warn = i;
  694. break;
  695. }
  696. }
  697. BNX2FC_TGT_DBG(tgt, "warn = 0x%x\n", err_warn);
  698. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  699. index = xid % BNX2FC_TASKS_PER_PAGE;
  700. task_page = (struct fcoe_task_ctx_entry *)
  701. interface->hba->task_ctx[task_idx];
  702. task = &(task_page[index]);
  703. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  704. if (!io_req)
  705. goto ret_warn_rqe;
  706. if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
  707. printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
  708. goto ret_warn_rqe;
  709. }
  710. memcpy(&io_req->err_entry, err_entry,
  711. sizeof(struct fcoe_err_report_entry));
  712. if (err_warn == FCOE_ERROR_CODE_REC_TOV_TIMER_EXPIRATION)
  713. /* REC_TOV is not a warning code */
  714. BUG_ON(1);
  715. else
  716. BNX2FC_TGT_DBG(tgt, "Unsolicited warning\n");
  717. ret_warn_rqe:
  718. bnx2fc_return_rqe(tgt, 1);
  719. spin_unlock_bh(&tgt->tgt_lock);
  720. break;
  721. default:
  722. printk(KERN_ERR PFX "Unsol Compl: Invalid CQE Subtype\n");
  723. break;
  724. }
  725. }
  726. void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe)
  727. {
  728. struct fcoe_task_ctx_entry *task;
  729. struct fcoe_task_ctx_entry *task_page;
  730. struct fcoe_port *port = tgt->port;
  731. struct bnx2fc_interface *interface = port->priv;
  732. struct bnx2fc_hba *hba = interface->hba;
  733. struct bnx2fc_cmd *io_req;
  734. int task_idx, index;
  735. u16 xid;
  736. u8 cmd_type;
  737. u8 rx_state = 0;
  738. u8 num_rq;
  739. spin_lock_bh(&tgt->tgt_lock);
  740. xid = wqe & FCOE_PEND_WQ_CQE_TASK_ID;
  741. if (xid >= BNX2FC_MAX_TASKS) {
  742. printk(KERN_ERR PFX "ERROR:xid out of range\n");
  743. spin_unlock_bh(&tgt->tgt_lock);
  744. return;
  745. }
  746. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  747. index = xid % BNX2FC_TASKS_PER_PAGE;
  748. task_page = (struct fcoe_task_ctx_entry *)hba->task_ctx[task_idx];
  749. task = &(task_page[index]);
  750. num_rq = ((task->rxwr_txrd.var_ctx.rx_flags &
  751. FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE) >>
  752. FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT);
  753. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  754. if (io_req == NULL) {
  755. printk(KERN_ERR PFX "ERROR? cq_compl - io_req is NULL\n");
  756. spin_unlock_bh(&tgt->tgt_lock);
  757. return;
  758. }
  759. /* Timestamp IO completion time */
  760. cmd_type = io_req->cmd_type;
  761. rx_state = ((task->rxwr_txrd.var_ctx.rx_flags &
  762. FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE) >>
  763. FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT);
  764. /* Process other IO completion types */
  765. switch (cmd_type) {
  766. case BNX2FC_SCSI_CMD:
  767. if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) {
  768. bnx2fc_process_scsi_cmd_compl(io_req, task, num_rq);
  769. spin_unlock_bh(&tgt->tgt_lock);
  770. return;
  771. }
  772. if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
  773. bnx2fc_process_abts_compl(io_req, task, num_rq);
  774. else if (rx_state ==
  775. FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
  776. bnx2fc_process_cleanup_compl(io_req, task, num_rq);
  777. else
  778. printk(KERN_ERR PFX "Invalid rx state - %d\n",
  779. rx_state);
  780. break;
  781. case BNX2FC_TASK_MGMT_CMD:
  782. BNX2FC_IO_DBG(io_req, "Processing TM complete\n");
  783. bnx2fc_process_tm_compl(io_req, task, num_rq);
  784. break;
  785. case BNX2FC_ABTS:
  786. /*
  787. * ABTS request received by firmware. ABTS response
  788. * will be delivered to the task belonging to the IO
  789. * that was aborted
  790. */
  791. BNX2FC_IO_DBG(io_req, "cq_compl- ABTS sent out by fw\n");
  792. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  793. break;
  794. case BNX2FC_ELS:
  795. if (rx_state == FCOE_TASK_RX_STATE_COMPLETED)
  796. bnx2fc_process_els_compl(io_req, task, num_rq);
  797. else if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
  798. bnx2fc_process_abts_compl(io_req, task, num_rq);
  799. else if (rx_state ==
  800. FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
  801. bnx2fc_process_cleanup_compl(io_req, task, num_rq);
  802. else
  803. printk(KERN_ERR PFX "Invalid rx state = %d\n",
  804. rx_state);
  805. break;
  806. case BNX2FC_CLEANUP:
  807. BNX2FC_IO_DBG(io_req, "cq_compl- cleanup resp rcvd\n");
  808. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  809. break;
  810. case BNX2FC_SEQ_CLEANUP:
  811. BNX2FC_IO_DBG(io_req, "cq_compl(0x%x) - seq cleanup resp\n",
  812. io_req->xid);
  813. bnx2fc_process_seq_cleanup_compl(io_req, task, rx_state);
  814. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  815. break;
  816. default:
  817. printk(KERN_ERR PFX "Invalid cmd_type %d\n", cmd_type);
  818. break;
  819. }
  820. spin_unlock_bh(&tgt->tgt_lock);
  821. }
  822. void bnx2fc_arm_cq(struct bnx2fc_rport *tgt)
  823. {
  824. struct b577xx_fcoe_rx_doorbell *rx_db = &tgt->rx_db;
  825. u32 msg;
  826. wmb();
  827. rx_db->doorbell_cq_cons = tgt->cq_cons_idx | (tgt->cq_curr_toggle_bit <<
  828. FCOE_CQE_TOGGLE_BIT_SHIFT);
  829. msg = *((u32 *)rx_db);
  830. writel(cpu_to_le32(msg), tgt->ctx_base);
  831. mmiowb();
  832. }
  833. struct bnx2fc_work *bnx2fc_alloc_work(struct bnx2fc_rport *tgt, u16 wqe)
  834. {
  835. struct bnx2fc_work *work;
  836. work = kzalloc(sizeof(struct bnx2fc_work), GFP_ATOMIC);
  837. if (!work)
  838. return NULL;
  839. INIT_LIST_HEAD(&work->list);
  840. work->tgt = tgt;
  841. work->wqe = wqe;
  842. return work;
  843. }
  844. int bnx2fc_process_new_cqes(struct bnx2fc_rport *tgt)
  845. {
  846. struct fcoe_cqe *cq;
  847. u32 cq_cons;
  848. struct fcoe_cqe *cqe;
  849. u32 num_free_sqes = 0;
  850. u32 num_cqes = 0;
  851. u16 wqe;
  852. /*
  853. * cq_lock is a low contention lock used to protect
  854. * the CQ data structure from being freed up during
  855. * the upload operation
  856. */
  857. spin_lock_bh(&tgt->cq_lock);
  858. if (!tgt->cq) {
  859. printk(KERN_ERR PFX "process_new_cqes: cq is NULL\n");
  860. spin_unlock_bh(&tgt->cq_lock);
  861. return 0;
  862. }
  863. cq = tgt->cq;
  864. cq_cons = tgt->cq_cons_idx;
  865. cqe = &cq[cq_cons];
  866. while (((wqe = cqe->wqe) & FCOE_CQE_TOGGLE_BIT) ==
  867. (tgt->cq_curr_toggle_bit <<
  868. FCOE_CQE_TOGGLE_BIT_SHIFT)) {
  869. /* new entry on the cq */
  870. if (wqe & FCOE_CQE_CQE_TYPE) {
  871. /* Unsolicited event notification */
  872. bnx2fc_process_unsol_compl(tgt, wqe);
  873. } else {
  874. /* Pending work request completion */
  875. struct bnx2fc_work *work = NULL;
  876. struct bnx2fc_percpu_s *fps = NULL;
  877. unsigned int cpu = wqe % num_possible_cpus();
  878. fps = &per_cpu(bnx2fc_percpu, cpu);
  879. spin_lock_bh(&fps->fp_work_lock);
  880. if (unlikely(!fps->iothread))
  881. goto unlock;
  882. work = bnx2fc_alloc_work(tgt, wqe);
  883. if (work)
  884. list_add_tail(&work->list,
  885. &fps->work_list);
  886. unlock:
  887. spin_unlock_bh(&fps->fp_work_lock);
  888. /* Pending work request completion */
  889. if (fps->iothread && work)
  890. wake_up_process(fps->iothread);
  891. else
  892. bnx2fc_process_cq_compl(tgt, wqe);
  893. num_free_sqes++;
  894. }
  895. cqe++;
  896. tgt->cq_cons_idx++;
  897. num_cqes++;
  898. if (tgt->cq_cons_idx == BNX2FC_CQ_WQES_MAX) {
  899. tgt->cq_cons_idx = 0;
  900. cqe = cq;
  901. tgt->cq_curr_toggle_bit =
  902. 1 - tgt->cq_curr_toggle_bit;
  903. }
  904. }
  905. if (num_cqes) {
  906. /* Arm CQ only if doorbell is mapped */
  907. if (tgt->ctx_base)
  908. bnx2fc_arm_cq(tgt);
  909. atomic_add(num_free_sqes, &tgt->free_sqes);
  910. }
  911. spin_unlock_bh(&tgt->cq_lock);
  912. return 0;
  913. }
  914. /**
  915. * bnx2fc_fastpath_notification - process global event queue (KCQ)
  916. *
  917. * @hba: adapter structure pointer
  918. * @new_cqe_kcqe: pointer to newly DMA'd KCQ entry
  919. *
  920. * Fast path event notification handler
  921. */
  922. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  923. struct fcoe_kcqe *new_cqe_kcqe)
  924. {
  925. u32 conn_id = new_cqe_kcqe->fcoe_conn_id;
  926. struct bnx2fc_rport *tgt = hba->tgt_ofld_list[conn_id];
  927. if (!tgt) {
  928. printk(KERN_ERR PFX "conn_id 0x%x not valid\n", conn_id);
  929. return;
  930. }
  931. bnx2fc_process_new_cqes(tgt);
  932. }
  933. /**
  934. * bnx2fc_process_ofld_cmpl - process FCoE session offload completion
  935. *
  936. * @hba: adapter structure pointer
  937. * @ofld_kcqe: connection offload kcqe pointer
  938. *
  939. * handle session offload completion, enable the session if offload is
  940. * successful.
  941. */
  942. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  943. struct fcoe_kcqe *ofld_kcqe)
  944. {
  945. struct bnx2fc_rport *tgt;
  946. struct fcoe_port *port;
  947. struct bnx2fc_interface *interface;
  948. u32 conn_id;
  949. u32 context_id;
  950. conn_id = ofld_kcqe->fcoe_conn_id;
  951. context_id = ofld_kcqe->fcoe_conn_context_id;
  952. tgt = hba->tgt_ofld_list[conn_id];
  953. if (!tgt) {
  954. printk(KERN_ALERT PFX "ERROR:ofld_cmpl: No pending ofld req\n");
  955. return;
  956. }
  957. BNX2FC_TGT_DBG(tgt, "Entered ofld compl - context_id = 0x%x\n",
  958. ofld_kcqe->fcoe_conn_context_id);
  959. port = tgt->port;
  960. interface = tgt->port->priv;
  961. if (hba != interface->hba) {
  962. printk(KERN_ERR PFX "ERROR:ofld_cmpl: HBA mis-match\n");
  963. goto ofld_cmpl_err;
  964. }
  965. /*
  966. * cnic has allocated a context_id for this session; use this
  967. * while enabling the session.
  968. */
  969. tgt->context_id = context_id;
  970. if (ofld_kcqe->completion_status) {
  971. if (ofld_kcqe->completion_status ==
  972. FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE) {
  973. printk(KERN_ERR PFX "unable to allocate FCoE context "
  974. "resources\n");
  975. set_bit(BNX2FC_FLAG_CTX_ALLOC_FAILURE, &tgt->flags);
  976. }
  977. } else {
  978. /* FW offload request successfully completed */
  979. set_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  980. }
  981. ofld_cmpl_err:
  982. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  983. wake_up_interruptible(&tgt->ofld_wait);
  984. }
  985. /**
  986. * bnx2fc_process_enable_conn_cmpl - process FCoE session enable completion
  987. *
  988. * @hba: adapter structure pointer
  989. * @ofld_kcqe: connection offload kcqe pointer
  990. *
  991. * handle session enable completion, mark the rport as ready
  992. */
  993. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  994. struct fcoe_kcqe *ofld_kcqe)
  995. {
  996. struct bnx2fc_rport *tgt;
  997. struct bnx2fc_interface *interface;
  998. u32 conn_id;
  999. u32 context_id;
  1000. context_id = ofld_kcqe->fcoe_conn_context_id;
  1001. conn_id = ofld_kcqe->fcoe_conn_id;
  1002. tgt = hba->tgt_ofld_list[conn_id];
  1003. if (!tgt) {
  1004. printk(KERN_ERR PFX "ERROR:enbl_cmpl: No pending ofld req\n");
  1005. return;
  1006. }
  1007. BNX2FC_TGT_DBG(tgt, "Enable compl - context_id = 0x%x\n",
  1008. ofld_kcqe->fcoe_conn_context_id);
  1009. /*
  1010. * context_id should be the same for this target during offload
  1011. * and enable
  1012. */
  1013. if (tgt->context_id != context_id) {
  1014. printk(KERN_ERR PFX "context id mis-match\n");
  1015. return;
  1016. }
  1017. interface = tgt->port->priv;
  1018. if (hba != interface->hba) {
  1019. printk(KERN_ERR PFX "bnx2fc-enbl_cmpl: HBA mis-match\n");
  1020. goto enbl_cmpl_err;
  1021. }
  1022. if (!ofld_kcqe->completion_status)
  1023. /* enable successful - rport ready for issuing IOs */
  1024. set_bit(BNX2FC_FLAG_ENABLED, &tgt->flags);
  1025. enbl_cmpl_err:
  1026. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  1027. wake_up_interruptible(&tgt->ofld_wait);
  1028. }
  1029. static void bnx2fc_process_conn_disable_cmpl(struct bnx2fc_hba *hba,
  1030. struct fcoe_kcqe *disable_kcqe)
  1031. {
  1032. struct bnx2fc_rport *tgt;
  1033. u32 conn_id;
  1034. conn_id = disable_kcqe->fcoe_conn_id;
  1035. tgt = hba->tgt_ofld_list[conn_id];
  1036. if (!tgt) {
  1037. printk(KERN_ERR PFX "ERROR: disable_cmpl: No disable req\n");
  1038. return;
  1039. }
  1040. BNX2FC_TGT_DBG(tgt, PFX "disable_cmpl: conn_id %d\n", conn_id);
  1041. if (disable_kcqe->completion_status) {
  1042. printk(KERN_ERR PFX "Disable failed with cmpl status %d\n",
  1043. disable_kcqe->completion_status);
  1044. set_bit(BNX2FC_FLAG_DISABLE_FAILED, &tgt->flags);
  1045. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  1046. wake_up_interruptible(&tgt->upld_wait);
  1047. } else {
  1048. /* disable successful */
  1049. BNX2FC_TGT_DBG(tgt, "disable successful\n");
  1050. clear_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  1051. clear_bit(BNX2FC_FLAG_ENABLED, &tgt->flags);
  1052. set_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  1053. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  1054. wake_up_interruptible(&tgt->upld_wait);
  1055. }
  1056. }
  1057. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  1058. struct fcoe_kcqe *destroy_kcqe)
  1059. {
  1060. struct bnx2fc_rport *tgt;
  1061. u32 conn_id;
  1062. conn_id = destroy_kcqe->fcoe_conn_id;
  1063. tgt = hba->tgt_ofld_list[conn_id];
  1064. if (!tgt) {
  1065. printk(KERN_ERR PFX "destroy_cmpl: No destroy req\n");
  1066. return;
  1067. }
  1068. BNX2FC_TGT_DBG(tgt, "destroy_cmpl: conn_id %d\n", conn_id);
  1069. if (destroy_kcqe->completion_status) {
  1070. printk(KERN_ERR PFX "Destroy conn failed, cmpl status %d\n",
  1071. destroy_kcqe->completion_status);
  1072. return;
  1073. } else {
  1074. /* destroy successful */
  1075. BNX2FC_TGT_DBG(tgt, "upload successful\n");
  1076. clear_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  1077. set_bit(BNX2FC_FLAG_DESTROYED, &tgt->flags);
  1078. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  1079. wake_up_interruptible(&tgt->upld_wait);
  1080. }
  1081. }
  1082. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code)
  1083. {
  1084. switch (err_code) {
  1085. case FCOE_KCQE_COMPLETION_STATUS_INVALID_OPCODE:
  1086. printk(KERN_ERR PFX "init_failure due to invalid opcode\n");
  1087. break;
  1088. case FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE:
  1089. printk(KERN_ERR PFX "init failed due to ctx alloc failure\n");
  1090. break;
  1091. case FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR:
  1092. printk(KERN_ERR PFX "init_failure due to NIC error\n");
  1093. break;
  1094. case FCOE_KCQE_COMPLETION_STATUS_ERROR:
  1095. printk(KERN_ERR PFX "init failure due to compl status err\n");
  1096. break;
  1097. case FCOE_KCQE_COMPLETION_STATUS_WRONG_HSI_VERSION:
  1098. printk(KERN_ERR PFX "init failure due to HSI mismatch\n");
  1099. break;
  1100. default:
  1101. printk(KERN_ERR PFX "Unknown Error code %d\n", err_code);
  1102. }
  1103. }
  1104. /**
  1105. * bnx2fc_indicae_kcqe - process KCQE
  1106. *
  1107. * @hba: adapter structure pointer
  1108. * @kcqe: kcqe pointer
  1109. * @num_cqe: Number of completion queue elements
  1110. *
  1111. * Generic KCQ event handler
  1112. */
  1113. void bnx2fc_indicate_kcqe(void *context, struct kcqe *kcq[],
  1114. u32 num_cqe)
  1115. {
  1116. struct bnx2fc_hba *hba = (struct bnx2fc_hba *)context;
  1117. int i = 0;
  1118. struct fcoe_kcqe *kcqe = NULL;
  1119. while (i < num_cqe) {
  1120. kcqe = (struct fcoe_kcqe *) kcq[i++];
  1121. switch (kcqe->op_code) {
  1122. case FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION:
  1123. bnx2fc_fastpath_notification(hba, kcqe);
  1124. break;
  1125. case FCOE_KCQE_OPCODE_OFFLOAD_CONN:
  1126. bnx2fc_process_ofld_cmpl(hba, kcqe);
  1127. break;
  1128. case FCOE_KCQE_OPCODE_ENABLE_CONN:
  1129. bnx2fc_process_enable_conn_cmpl(hba, kcqe);
  1130. break;
  1131. case FCOE_KCQE_OPCODE_INIT_FUNC:
  1132. if (kcqe->completion_status !=
  1133. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  1134. bnx2fc_init_failure(hba,
  1135. kcqe->completion_status);
  1136. } else {
  1137. set_bit(ADAPTER_STATE_UP, &hba->adapter_state);
  1138. bnx2fc_get_link_state(hba);
  1139. printk(KERN_INFO PFX "[%.2x]: FCOE_INIT passed\n",
  1140. (u8)hba->pcidev->bus->number);
  1141. }
  1142. break;
  1143. case FCOE_KCQE_OPCODE_DESTROY_FUNC:
  1144. if (kcqe->completion_status !=
  1145. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  1146. printk(KERN_ERR PFX "DESTROY failed\n");
  1147. } else {
  1148. printk(KERN_ERR PFX "DESTROY success\n");
  1149. }
  1150. set_bit(BNX2FC_FLAG_DESTROY_CMPL, &hba->flags);
  1151. wake_up_interruptible(&hba->destroy_wait);
  1152. break;
  1153. case FCOE_KCQE_OPCODE_DISABLE_CONN:
  1154. bnx2fc_process_conn_disable_cmpl(hba, kcqe);
  1155. break;
  1156. case FCOE_KCQE_OPCODE_DESTROY_CONN:
  1157. bnx2fc_process_conn_destroy_cmpl(hba, kcqe);
  1158. break;
  1159. case FCOE_KCQE_OPCODE_STAT_FUNC:
  1160. if (kcqe->completion_status !=
  1161. FCOE_KCQE_COMPLETION_STATUS_SUCCESS)
  1162. printk(KERN_ERR PFX "STAT failed\n");
  1163. complete(&hba->stat_req_done);
  1164. break;
  1165. case FCOE_KCQE_OPCODE_FCOE_ERROR:
  1166. /* fall thru */
  1167. default:
  1168. printk(KERN_ERR PFX "unknown opcode 0x%x\n",
  1169. kcqe->op_code);
  1170. }
  1171. }
  1172. }
  1173. void bnx2fc_add_2_sq(struct bnx2fc_rport *tgt, u16 xid)
  1174. {
  1175. struct fcoe_sqe *sqe;
  1176. sqe = &tgt->sq[tgt->sq_prod_idx];
  1177. /* Fill SQ WQE */
  1178. sqe->wqe = xid << FCOE_SQE_TASK_ID_SHIFT;
  1179. sqe->wqe |= tgt->sq_curr_toggle_bit << FCOE_SQE_TOGGLE_BIT_SHIFT;
  1180. /* Advance SQ Prod Idx */
  1181. if (++tgt->sq_prod_idx == BNX2FC_SQ_WQES_MAX) {
  1182. tgt->sq_prod_idx = 0;
  1183. tgt->sq_curr_toggle_bit = 1 - tgt->sq_curr_toggle_bit;
  1184. }
  1185. }
  1186. void bnx2fc_ring_doorbell(struct bnx2fc_rport *tgt)
  1187. {
  1188. struct b577xx_doorbell_set_prod *sq_db = &tgt->sq_db;
  1189. u32 msg;
  1190. wmb();
  1191. sq_db->prod = tgt->sq_prod_idx |
  1192. (tgt->sq_curr_toggle_bit << 15);
  1193. msg = *((u32 *)sq_db);
  1194. writel(cpu_to_le32(msg), tgt->ctx_base);
  1195. mmiowb();
  1196. }
  1197. int bnx2fc_map_doorbell(struct bnx2fc_rport *tgt)
  1198. {
  1199. u32 context_id = tgt->context_id;
  1200. struct fcoe_port *port = tgt->port;
  1201. u32 reg_off;
  1202. resource_size_t reg_base;
  1203. struct bnx2fc_interface *interface = port->priv;
  1204. struct bnx2fc_hba *hba = interface->hba;
  1205. reg_base = pci_resource_start(hba->pcidev,
  1206. BNX2X_DOORBELL_PCI_BAR);
  1207. reg_off = BNX2FC_5771X_DB_PAGE_SIZE *
  1208. (context_id & 0x1FFFF) + DPM_TRIGER_TYPE;
  1209. tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4);
  1210. if (!tgt->ctx_base)
  1211. return -ENOMEM;
  1212. return 0;
  1213. }
  1214. char *bnx2fc_get_next_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1215. {
  1216. char *buf = (char *)tgt->rq + (tgt->rq_cons_idx * BNX2FC_RQ_BUF_SZ);
  1217. if (tgt->rq_cons_idx + num_items > BNX2FC_RQ_WQES_MAX)
  1218. return NULL;
  1219. tgt->rq_cons_idx += num_items;
  1220. if (tgt->rq_cons_idx >= BNX2FC_RQ_WQES_MAX)
  1221. tgt->rq_cons_idx -= BNX2FC_RQ_WQES_MAX;
  1222. return buf;
  1223. }
  1224. void bnx2fc_return_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1225. {
  1226. /* return the rq buffer */
  1227. u32 next_prod_idx = tgt->rq_prod_idx + num_items;
  1228. if ((next_prod_idx & 0x7fff) == BNX2FC_RQ_WQES_MAX) {
  1229. /* Wrap around RQ */
  1230. next_prod_idx += 0x8000 - BNX2FC_RQ_WQES_MAX;
  1231. }
  1232. tgt->rq_prod_idx = next_prod_idx;
  1233. tgt->conn_db->rq_prod = tgt->rq_prod_idx;
  1234. }
  1235. void bnx2fc_init_seq_cleanup_task(struct bnx2fc_cmd *seq_clnp_req,
  1236. struct fcoe_task_ctx_entry *task,
  1237. struct bnx2fc_cmd *orig_io_req,
  1238. u32 offset)
  1239. {
  1240. struct scsi_cmnd *sc_cmd = orig_io_req->sc_cmd;
  1241. struct bnx2fc_rport *tgt = seq_clnp_req->tgt;
  1242. struct bnx2fc_interface *interface = tgt->port->priv;
  1243. struct fcoe_bd_ctx *bd = orig_io_req->bd_tbl->bd_tbl;
  1244. struct fcoe_task_ctx_entry *orig_task;
  1245. struct fcoe_task_ctx_entry *task_page;
  1246. struct fcoe_ext_mul_sges_ctx *sgl;
  1247. u8 task_type = FCOE_TASK_TYPE_SEQUENCE_CLEANUP;
  1248. u8 orig_task_type;
  1249. u16 orig_xid = orig_io_req->xid;
  1250. u32 context_id = tgt->context_id;
  1251. u64 phys_addr = (u64)orig_io_req->bd_tbl->bd_tbl_dma;
  1252. u32 orig_offset = offset;
  1253. int bd_count;
  1254. int orig_task_idx, index;
  1255. int i;
  1256. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1257. if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
  1258. orig_task_type = FCOE_TASK_TYPE_WRITE;
  1259. else
  1260. orig_task_type = FCOE_TASK_TYPE_READ;
  1261. /* Tx flags */
  1262. task->txwr_rxrd.const_ctx.tx_flags =
  1263. FCOE_TASK_TX_STATE_SEQUENCE_CLEANUP <<
  1264. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1265. /* init flags */
  1266. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1267. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1268. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1269. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1270. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1271. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1272. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1273. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1274. task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid;
  1275. task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_seq_cnt = 0;
  1276. task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_data_offset = offset;
  1277. bd_count = orig_io_req->bd_tbl->bd_valid;
  1278. /* obtain the appropriate bd entry from relative offset */
  1279. for (i = 0; i < bd_count; i++) {
  1280. if (offset < bd[i].buf_len)
  1281. break;
  1282. offset -= bd[i].buf_len;
  1283. }
  1284. phys_addr += (i * sizeof(struct fcoe_bd_ctx));
  1285. if (orig_task_type == FCOE_TASK_TYPE_WRITE) {
  1286. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1287. (u32)phys_addr;
  1288. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1289. (u32)((u64)phys_addr >> 32);
  1290. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size =
  1291. bd_count;
  1292. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_off =
  1293. offset; /* adjusted offset */
  1294. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_idx = i;
  1295. } else {
  1296. orig_task_idx = orig_xid / BNX2FC_TASKS_PER_PAGE;
  1297. index = orig_xid % BNX2FC_TASKS_PER_PAGE;
  1298. task_page = (struct fcoe_task_ctx_entry *)
  1299. interface->hba->task_ctx[orig_task_idx];
  1300. orig_task = &(task_page[index]);
  1301. /* Multiple SGEs were used for this IO */
  1302. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1303. sgl->mul_sgl.cur_sge_addr.lo = (u32)phys_addr;
  1304. sgl->mul_sgl.cur_sge_addr.hi = (u32)((u64)phys_addr >> 32);
  1305. sgl->mul_sgl.sgl_size = bd_count;
  1306. sgl->mul_sgl.cur_sge_off = offset; /*adjusted offset */
  1307. sgl->mul_sgl.cur_sge_idx = i;
  1308. memset(&task->rxwr_only.rx_seq_ctx, 0,
  1309. sizeof(struct fcoe_rx_seq_ctx));
  1310. task->rxwr_only.rx_seq_ctx.low_exp_ro = orig_offset;
  1311. task->rxwr_only.rx_seq_ctx.high_exp_ro = orig_offset;
  1312. }
  1313. }
  1314. void bnx2fc_init_cleanup_task(struct bnx2fc_cmd *io_req,
  1315. struct fcoe_task_ctx_entry *task,
  1316. u16 orig_xid)
  1317. {
  1318. u8 task_type = FCOE_TASK_TYPE_EXCHANGE_CLEANUP;
  1319. struct bnx2fc_rport *tgt = io_req->tgt;
  1320. u32 context_id = tgt->context_id;
  1321. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1322. /* Tx Write Rx Read */
  1323. /* init flags */
  1324. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1325. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1326. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1327. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1328. if (tgt->dev_type == TYPE_TAPE)
  1329. task->txwr_rxrd.const_ctx.init_flags |=
  1330. FCOE_TASK_DEV_TYPE_TAPE <<
  1331. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1332. else
  1333. task->txwr_rxrd.const_ctx.init_flags |=
  1334. FCOE_TASK_DEV_TYPE_DISK <<
  1335. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1336. task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid;
  1337. /* Tx flags */
  1338. task->txwr_rxrd.const_ctx.tx_flags =
  1339. FCOE_TASK_TX_STATE_EXCHANGE_CLEANUP <<
  1340. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1341. /* Rx Read Tx Write */
  1342. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1343. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1344. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1345. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1346. }
  1347. void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req,
  1348. struct fcoe_task_ctx_entry *task)
  1349. {
  1350. struct bnx2fc_mp_req *mp_req = &(io_req->mp_req);
  1351. struct bnx2fc_rport *tgt = io_req->tgt;
  1352. struct fc_frame_header *fc_hdr;
  1353. struct fcoe_ext_mul_sges_ctx *sgl;
  1354. u8 task_type = 0;
  1355. u64 *hdr;
  1356. u64 temp_hdr[3];
  1357. u32 context_id;
  1358. /* Obtain task_type */
  1359. if ((io_req->cmd_type == BNX2FC_TASK_MGMT_CMD) ||
  1360. (io_req->cmd_type == BNX2FC_ELS)) {
  1361. task_type = FCOE_TASK_TYPE_MIDPATH;
  1362. } else if (io_req->cmd_type == BNX2FC_ABTS) {
  1363. task_type = FCOE_TASK_TYPE_ABTS;
  1364. }
  1365. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1366. /* Setup the task from io_req for easy reference */
  1367. io_req->task = task;
  1368. BNX2FC_IO_DBG(io_req, "Init MP task for cmd_type = %d task_type = %d\n",
  1369. io_req->cmd_type, task_type);
  1370. /* Tx only */
  1371. if ((task_type == FCOE_TASK_TYPE_MIDPATH) ||
  1372. (task_type == FCOE_TASK_TYPE_UNSOLICITED)) {
  1373. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1374. (u32)mp_req->mp_req_bd_dma;
  1375. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1376. (u32)((u64)mp_req->mp_req_bd_dma >> 32);
  1377. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size = 1;
  1378. }
  1379. /* Tx Write Rx Read */
  1380. /* init flags */
  1381. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1382. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1383. if (tgt->dev_type == TYPE_TAPE)
  1384. task->txwr_rxrd.const_ctx.init_flags |=
  1385. FCOE_TASK_DEV_TYPE_TAPE <<
  1386. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1387. else
  1388. task->txwr_rxrd.const_ctx.init_flags |=
  1389. FCOE_TASK_DEV_TYPE_DISK <<
  1390. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1391. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1392. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1393. /* tx flags */
  1394. task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_INIT <<
  1395. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1396. /* Rx Write Tx Read */
  1397. task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
  1398. /* rx flags */
  1399. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1400. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1401. context_id = tgt->context_id;
  1402. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1403. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1404. fc_hdr = &(mp_req->req_fc_hdr);
  1405. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1406. fc_hdr->fh_ox_id = cpu_to_be16(io_req->xid);
  1407. fc_hdr->fh_rx_id = htons(0xffff);
  1408. task->rxwr_txrd.var_ctx.rx_id = 0xffff;
  1409. } else if (task_type == FCOE_TASK_TYPE_UNSOLICITED) {
  1410. fc_hdr->fh_rx_id = cpu_to_be16(io_req->xid);
  1411. }
  1412. /* Fill FC Header into middle path buffer */
  1413. hdr = (u64 *) &task->txwr_rxrd.union_ctx.tx_frame.fc_hdr;
  1414. memcpy(temp_hdr, fc_hdr, sizeof(temp_hdr));
  1415. hdr[0] = cpu_to_be64(temp_hdr[0]);
  1416. hdr[1] = cpu_to_be64(temp_hdr[1]);
  1417. hdr[2] = cpu_to_be64(temp_hdr[2]);
  1418. /* Rx Only */
  1419. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1420. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1421. sgl->mul_sgl.cur_sge_addr.lo = (u32)mp_req->mp_resp_bd_dma;
  1422. sgl->mul_sgl.cur_sge_addr.hi =
  1423. (u32)((u64)mp_req->mp_resp_bd_dma >> 32);
  1424. sgl->mul_sgl.sgl_size = 1;
  1425. }
  1426. }
  1427. void bnx2fc_init_task(struct bnx2fc_cmd *io_req,
  1428. struct fcoe_task_ctx_entry *task)
  1429. {
  1430. u8 task_type;
  1431. struct scsi_cmnd *sc_cmd = io_req->sc_cmd;
  1432. struct io_bdt *bd_tbl = io_req->bd_tbl;
  1433. struct bnx2fc_rport *tgt = io_req->tgt;
  1434. struct fcoe_cached_sge_ctx *cached_sge;
  1435. struct fcoe_ext_mul_sges_ctx *sgl;
  1436. int dev_type = tgt->dev_type;
  1437. u64 *fcp_cmnd;
  1438. u64 tmp_fcp_cmnd[4];
  1439. u32 context_id;
  1440. int cnt, i;
  1441. int bd_count;
  1442. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1443. /* Setup the task from io_req for easy reference */
  1444. io_req->task = task;
  1445. if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
  1446. task_type = FCOE_TASK_TYPE_WRITE;
  1447. else
  1448. task_type = FCOE_TASK_TYPE_READ;
  1449. /* Tx only */
  1450. bd_count = bd_tbl->bd_valid;
  1451. cached_sge = &task->rxwr_only.union_ctx.read_info.sgl_ctx.cached_sge;
  1452. if (task_type == FCOE_TASK_TYPE_WRITE) {
  1453. if ((dev_type == TYPE_DISK) && (bd_count == 1)) {
  1454. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1455. task->txwr_only.sgl_ctx.cached_sge.cur_buf_addr.lo =
  1456. cached_sge->cur_buf_addr.lo =
  1457. fcoe_bd_tbl->buf_addr_lo;
  1458. task->txwr_only.sgl_ctx.cached_sge.cur_buf_addr.hi =
  1459. cached_sge->cur_buf_addr.hi =
  1460. fcoe_bd_tbl->buf_addr_hi;
  1461. task->txwr_only.sgl_ctx.cached_sge.cur_buf_rem =
  1462. cached_sge->cur_buf_rem =
  1463. fcoe_bd_tbl->buf_len;
  1464. task->txwr_rxrd.const_ctx.init_flags |= 1 <<
  1465. FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
  1466. } else {
  1467. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1468. (u32)bd_tbl->bd_tbl_dma;
  1469. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1470. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1471. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size =
  1472. bd_tbl->bd_valid;
  1473. }
  1474. }
  1475. /*Tx Write Rx Read */
  1476. /* Init state to NORMAL */
  1477. task->txwr_rxrd.const_ctx.init_flags |= task_type <<
  1478. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1479. if (dev_type == TYPE_TAPE) {
  1480. task->txwr_rxrd.const_ctx.init_flags |=
  1481. FCOE_TASK_DEV_TYPE_TAPE <<
  1482. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1483. io_req->rec_retry = 0;
  1484. io_req->rec_retry = 0;
  1485. } else
  1486. task->txwr_rxrd.const_ctx.init_flags |=
  1487. FCOE_TASK_DEV_TYPE_DISK <<
  1488. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1489. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1490. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1491. /* tx flags */
  1492. task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_NORMAL <<
  1493. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1494. /* Set initial seq counter */
  1495. task->txwr_rxrd.union_ctx.tx_seq.ctx.seq_cnt = 1;
  1496. /* Fill FCP_CMND IU */
  1497. fcp_cmnd = (u64 *)
  1498. task->txwr_rxrd.union_ctx.fcp_cmd.opaque;
  1499. bnx2fc_build_fcp_cmnd(io_req, (struct fcp_cmnd *)&tmp_fcp_cmnd);
  1500. /* swap fcp_cmnd */
  1501. cnt = sizeof(struct fcp_cmnd) / sizeof(u64);
  1502. for (i = 0; i < cnt; i++) {
  1503. *fcp_cmnd = cpu_to_be64(tmp_fcp_cmnd[i]);
  1504. fcp_cmnd++;
  1505. }
  1506. /* Rx Write Tx Read */
  1507. task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
  1508. context_id = tgt->context_id;
  1509. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1510. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1511. /* rx flags */
  1512. /* Set state to "waiting for the first packet" */
  1513. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1514. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1515. task->rxwr_txrd.var_ctx.rx_id = 0xffff;
  1516. /* Rx Only */
  1517. if (task_type != FCOE_TASK_TYPE_READ)
  1518. return;
  1519. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1520. bd_count = bd_tbl->bd_valid;
  1521. if (dev_type == TYPE_DISK) {
  1522. if (bd_count == 1) {
  1523. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1524. cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
  1525. cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
  1526. cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
  1527. task->txwr_rxrd.const_ctx.init_flags |= 1 <<
  1528. FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
  1529. } else if (bd_count == 2) {
  1530. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1531. cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
  1532. cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
  1533. cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
  1534. fcoe_bd_tbl++;
  1535. cached_sge->second_buf_addr.lo =
  1536. fcoe_bd_tbl->buf_addr_lo;
  1537. cached_sge->second_buf_addr.hi =
  1538. fcoe_bd_tbl->buf_addr_hi;
  1539. cached_sge->second_buf_rem = fcoe_bd_tbl->buf_len;
  1540. task->txwr_rxrd.const_ctx.init_flags |= 1 <<
  1541. FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
  1542. } else {
  1543. sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma;
  1544. sgl->mul_sgl.cur_sge_addr.hi =
  1545. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1546. sgl->mul_sgl.sgl_size = bd_count;
  1547. }
  1548. } else {
  1549. sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma;
  1550. sgl->mul_sgl.cur_sge_addr.hi =
  1551. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1552. sgl->mul_sgl.sgl_size = bd_count;
  1553. }
  1554. }
  1555. /**
  1556. * bnx2fc_setup_task_ctx - allocate and map task context
  1557. *
  1558. * @hba: pointer to adapter structure
  1559. *
  1560. * allocate memory for task context, and associated BD table to be used
  1561. * by firmware
  1562. *
  1563. */
  1564. int bnx2fc_setup_task_ctx(struct bnx2fc_hba *hba)
  1565. {
  1566. int rc = 0;
  1567. struct regpair *task_ctx_bdt;
  1568. dma_addr_t addr;
  1569. int i;
  1570. /*
  1571. * Allocate task context bd table. A page size of bd table
  1572. * can map 256 buffers. Each buffer contains 32 task context
  1573. * entries. Hence the limit with one page is 8192 task context
  1574. * entries.
  1575. */
  1576. hba->task_ctx_bd_tbl = dma_alloc_coherent(&hba->pcidev->dev,
  1577. PAGE_SIZE,
  1578. &hba->task_ctx_bd_dma,
  1579. GFP_KERNEL);
  1580. if (!hba->task_ctx_bd_tbl) {
  1581. printk(KERN_ERR PFX "unable to allocate task context BDT\n");
  1582. rc = -1;
  1583. goto out;
  1584. }
  1585. memset(hba->task_ctx_bd_tbl, 0, PAGE_SIZE);
  1586. /*
  1587. * Allocate task_ctx which is an array of pointers pointing to
  1588. * a page containing 32 task contexts
  1589. */
  1590. hba->task_ctx = kzalloc((BNX2FC_TASK_CTX_ARR_SZ * sizeof(void *)),
  1591. GFP_KERNEL);
  1592. if (!hba->task_ctx) {
  1593. printk(KERN_ERR PFX "unable to allocate task context array\n");
  1594. rc = -1;
  1595. goto out1;
  1596. }
  1597. /*
  1598. * Allocate task_ctx_dma which is an array of dma addresses
  1599. */
  1600. hba->task_ctx_dma = kmalloc((BNX2FC_TASK_CTX_ARR_SZ *
  1601. sizeof(dma_addr_t)), GFP_KERNEL);
  1602. if (!hba->task_ctx_dma) {
  1603. printk(KERN_ERR PFX "unable to alloc context mapping array\n");
  1604. rc = -1;
  1605. goto out2;
  1606. }
  1607. task_ctx_bdt = (struct regpair *)hba->task_ctx_bd_tbl;
  1608. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1609. hba->task_ctx[i] = dma_alloc_coherent(&hba->pcidev->dev,
  1610. PAGE_SIZE,
  1611. &hba->task_ctx_dma[i],
  1612. GFP_KERNEL);
  1613. if (!hba->task_ctx[i]) {
  1614. printk(KERN_ERR PFX "unable to alloc task context\n");
  1615. rc = -1;
  1616. goto out3;
  1617. }
  1618. memset(hba->task_ctx[i], 0, PAGE_SIZE);
  1619. addr = (u64)hba->task_ctx_dma[i];
  1620. task_ctx_bdt->hi = cpu_to_le32((u64)addr >> 32);
  1621. task_ctx_bdt->lo = cpu_to_le32((u32)addr);
  1622. task_ctx_bdt++;
  1623. }
  1624. return 0;
  1625. out3:
  1626. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1627. if (hba->task_ctx[i]) {
  1628. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1629. hba->task_ctx[i], hba->task_ctx_dma[i]);
  1630. hba->task_ctx[i] = NULL;
  1631. }
  1632. }
  1633. kfree(hba->task_ctx_dma);
  1634. hba->task_ctx_dma = NULL;
  1635. out2:
  1636. kfree(hba->task_ctx);
  1637. hba->task_ctx = NULL;
  1638. out1:
  1639. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1640. hba->task_ctx_bd_tbl, hba->task_ctx_bd_dma);
  1641. hba->task_ctx_bd_tbl = NULL;
  1642. out:
  1643. return rc;
  1644. }
  1645. void bnx2fc_free_task_ctx(struct bnx2fc_hba *hba)
  1646. {
  1647. int i;
  1648. if (hba->task_ctx_bd_tbl) {
  1649. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1650. hba->task_ctx_bd_tbl,
  1651. hba->task_ctx_bd_dma);
  1652. hba->task_ctx_bd_tbl = NULL;
  1653. }
  1654. if (hba->task_ctx) {
  1655. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1656. if (hba->task_ctx[i]) {
  1657. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1658. hba->task_ctx[i],
  1659. hba->task_ctx_dma[i]);
  1660. hba->task_ctx[i] = NULL;
  1661. }
  1662. }
  1663. kfree(hba->task_ctx);
  1664. hba->task_ctx = NULL;
  1665. }
  1666. kfree(hba->task_ctx_dma);
  1667. hba->task_ctx_dma = NULL;
  1668. }
  1669. static void bnx2fc_free_hash_table(struct bnx2fc_hba *hba)
  1670. {
  1671. int i;
  1672. int segment_count;
  1673. int hash_table_size;
  1674. u32 *pbl;
  1675. segment_count = hba->hash_tbl_segment_count;
  1676. hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
  1677. sizeof(struct fcoe_hash_table_entry);
  1678. pbl = hba->hash_tbl_pbl;
  1679. for (i = 0; i < segment_count; ++i) {
  1680. dma_addr_t dma_address;
  1681. dma_address = le32_to_cpu(*pbl);
  1682. ++pbl;
  1683. dma_address += ((u64)le32_to_cpu(*pbl)) << 32;
  1684. ++pbl;
  1685. dma_free_coherent(&hba->pcidev->dev,
  1686. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1687. hba->hash_tbl_segments[i],
  1688. dma_address);
  1689. }
  1690. if (hba->hash_tbl_pbl) {
  1691. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1692. hba->hash_tbl_pbl,
  1693. hba->hash_tbl_pbl_dma);
  1694. hba->hash_tbl_pbl = NULL;
  1695. }
  1696. }
  1697. static int bnx2fc_allocate_hash_table(struct bnx2fc_hba *hba)
  1698. {
  1699. int i;
  1700. int hash_table_size;
  1701. int segment_count;
  1702. int segment_array_size;
  1703. int dma_segment_array_size;
  1704. dma_addr_t *dma_segment_array;
  1705. u32 *pbl;
  1706. hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
  1707. sizeof(struct fcoe_hash_table_entry);
  1708. segment_count = hash_table_size + BNX2FC_HASH_TBL_CHUNK_SIZE - 1;
  1709. segment_count /= BNX2FC_HASH_TBL_CHUNK_SIZE;
  1710. hba->hash_tbl_segment_count = segment_count;
  1711. segment_array_size = segment_count * sizeof(*hba->hash_tbl_segments);
  1712. hba->hash_tbl_segments = kzalloc(segment_array_size, GFP_KERNEL);
  1713. if (!hba->hash_tbl_segments) {
  1714. printk(KERN_ERR PFX "hash table pointers alloc failed\n");
  1715. return -ENOMEM;
  1716. }
  1717. dma_segment_array_size = segment_count * sizeof(*dma_segment_array);
  1718. dma_segment_array = kzalloc(dma_segment_array_size, GFP_KERNEL);
  1719. if (!dma_segment_array) {
  1720. printk(KERN_ERR PFX "hash table pointers (dma) alloc failed\n");
  1721. return -ENOMEM;
  1722. }
  1723. for (i = 0; i < segment_count; ++i) {
  1724. hba->hash_tbl_segments[i] =
  1725. dma_alloc_coherent(&hba->pcidev->dev,
  1726. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1727. &dma_segment_array[i],
  1728. GFP_KERNEL);
  1729. if (!hba->hash_tbl_segments[i]) {
  1730. printk(KERN_ERR PFX "hash segment alloc failed\n");
  1731. while (--i >= 0) {
  1732. dma_free_coherent(&hba->pcidev->dev,
  1733. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1734. hba->hash_tbl_segments[i],
  1735. dma_segment_array[i]);
  1736. hba->hash_tbl_segments[i] = NULL;
  1737. }
  1738. kfree(dma_segment_array);
  1739. return -ENOMEM;
  1740. }
  1741. memset(hba->hash_tbl_segments[i], 0,
  1742. BNX2FC_HASH_TBL_CHUNK_SIZE);
  1743. }
  1744. hba->hash_tbl_pbl = dma_alloc_coherent(&hba->pcidev->dev,
  1745. PAGE_SIZE,
  1746. &hba->hash_tbl_pbl_dma,
  1747. GFP_KERNEL);
  1748. if (!hba->hash_tbl_pbl) {
  1749. printk(KERN_ERR PFX "hash table pbl alloc failed\n");
  1750. kfree(dma_segment_array);
  1751. return -ENOMEM;
  1752. }
  1753. memset(hba->hash_tbl_pbl, 0, PAGE_SIZE);
  1754. pbl = hba->hash_tbl_pbl;
  1755. for (i = 0; i < segment_count; ++i) {
  1756. u64 paddr = dma_segment_array[i];
  1757. *pbl = cpu_to_le32((u32) paddr);
  1758. ++pbl;
  1759. *pbl = cpu_to_le32((u32) (paddr >> 32));
  1760. ++pbl;
  1761. }
  1762. pbl = hba->hash_tbl_pbl;
  1763. i = 0;
  1764. while (*pbl && *(pbl + 1)) {
  1765. u32 lo;
  1766. u32 hi;
  1767. lo = *pbl;
  1768. ++pbl;
  1769. hi = *pbl;
  1770. ++pbl;
  1771. ++i;
  1772. }
  1773. kfree(dma_segment_array);
  1774. return 0;
  1775. }
  1776. /**
  1777. * bnx2fc_setup_fw_resc - Allocate and map hash table and dummy buffer
  1778. *
  1779. * @hba: Pointer to adapter structure
  1780. *
  1781. */
  1782. int bnx2fc_setup_fw_resc(struct bnx2fc_hba *hba)
  1783. {
  1784. u64 addr;
  1785. u32 mem_size;
  1786. int i;
  1787. if (bnx2fc_allocate_hash_table(hba))
  1788. return -ENOMEM;
  1789. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1790. hba->t2_hash_tbl_ptr = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
  1791. &hba->t2_hash_tbl_ptr_dma,
  1792. GFP_KERNEL);
  1793. if (!hba->t2_hash_tbl_ptr) {
  1794. printk(KERN_ERR PFX "unable to allocate t2 hash table ptr\n");
  1795. bnx2fc_free_fw_resc(hba);
  1796. return -ENOMEM;
  1797. }
  1798. memset(hba->t2_hash_tbl_ptr, 0x00, mem_size);
  1799. mem_size = BNX2FC_NUM_MAX_SESS *
  1800. sizeof(struct fcoe_t2_hash_table_entry);
  1801. hba->t2_hash_tbl = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
  1802. &hba->t2_hash_tbl_dma,
  1803. GFP_KERNEL);
  1804. if (!hba->t2_hash_tbl) {
  1805. printk(KERN_ERR PFX "unable to allocate t2 hash table\n");
  1806. bnx2fc_free_fw_resc(hba);
  1807. return -ENOMEM;
  1808. }
  1809. memset(hba->t2_hash_tbl, 0x00, mem_size);
  1810. for (i = 0; i < BNX2FC_NUM_MAX_SESS; i++) {
  1811. addr = (unsigned long) hba->t2_hash_tbl_dma +
  1812. ((i+1) * sizeof(struct fcoe_t2_hash_table_entry));
  1813. hba->t2_hash_tbl[i].next.lo = addr & 0xffffffff;
  1814. hba->t2_hash_tbl[i].next.hi = addr >> 32;
  1815. }
  1816. hba->dummy_buffer = dma_alloc_coherent(&hba->pcidev->dev,
  1817. PAGE_SIZE, &hba->dummy_buf_dma,
  1818. GFP_KERNEL);
  1819. if (!hba->dummy_buffer) {
  1820. printk(KERN_ERR PFX "unable to alloc MP Dummy Buffer\n");
  1821. bnx2fc_free_fw_resc(hba);
  1822. return -ENOMEM;
  1823. }
  1824. hba->stats_buffer = dma_alloc_coherent(&hba->pcidev->dev,
  1825. PAGE_SIZE,
  1826. &hba->stats_buf_dma,
  1827. GFP_KERNEL);
  1828. if (!hba->stats_buffer) {
  1829. printk(KERN_ERR PFX "unable to alloc Stats Buffer\n");
  1830. bnx2fc_free_fw_resc(hba);
  1831. return -ENOMEM;
  1832. }
  1833. memset(hba->stats_buffer, 0x00, PAGE_SIZE);
  1834. return 0;
  1835. }
  1836. void bnx2fc_free_fw_resc(struct bnx2fc_hba *hba)
  1837. {
  1838. u32 mem_size;
  1839. if (hba->stats_buffer) {
  1840. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1841. hba->stats_buffer, hba->stats_buf_dma);
  1842. hba->stats_buffer = NULL;
  1843. }
  1844. if (hba->dummy_buffer) {
  1845. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1846. hba->dummy_buffer, hba->dummy_buf_dma);
  1847. hba->dummy_buffer = NULL;
  1848. }
  1849. if (hba->t2_hash_tbl_ptr) {
  1850. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1851. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1852. hba->t2_hash_tbl_ptr,
  1853. hba->t2_hash_tbl_ptr_dma);
  1854. hba->t2_hash_tbl_ptr = NULL;
  1855. }
  1856. if (hba->t2_hash_tbl) {
  1857. mem_size = BNX2FC_NUM_MAX_SESS *
  1858. sizeof(struct fcoe_t2_hash_table_entry);
  1859. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1860. hba->t2_hash_tbl, hba->t2_hash_tbl_dma);
  1861. hba->t2_hash_tbl = NULL;
  1862. }
  1863. bnx2fc_free_hash_table(hba);
  1864. }