qeth_core_main.c 155 KB

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  1. /*
  2. * Copyright IBM Corp. 2007, 2009
  3. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  4. * Frank Pavlic <fpavlic@de.ibm.com>,
  5. * Thomas Spatzier <tspat@de.ibm.com>,
  6. * Frank Blaschka <frank.blaschka@de.ibm.com>
  7. */
  8. #define KMSG_COMPONENT "qeth"
  9. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/string.h>
  13. #include <linux/errno.h>
  14. #include <linux/kernel.h>
  15. #include <linux/ip.h>
  16. #include <linux/tcp.h>
  17. #include <linux/mii.h>
  18. #include <linux/kthread.h>
  19. #include <linux/slab.h>
  20. #include <net/iucv/af_iucv.h>
  21. #include <asm/ebcdic.h>
  22. #include <asm/io.h>
  23. #include <asm/sysinfo.h>
  24. #include <asm/compat.h>
  25. #include "qeth_core.h"
  26. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  27. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  28. /* N P A M L V H */
  29. [QETH_DBF_SETUP] = {"qeth_setup",
  30. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  31. [QETH_DBF_MSG] = {"qeth_msg",
  32. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  33. [QETH_DBF_CTRL] = {"qeth_control",
  34. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  35. };
  36. EXPORT_SYMBOL_GPL(qeth_dbf);
  37. struct qeth_card_list_struct qeth_core_card_list;
  38. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  39. struct kmem_cache *qeth_core_header_cache;
  40. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  41. static struct kmem_cache *qeth_qdio_outbuf_cache;
  42. static struct device *qeth_core_root_dev;
  43. static unsigned int known_devices[][6] = QETH_MODELLIST_ARRAY;
  44. static struct lock_class_key qdio_out_skb_queue_key;
  45. static struct mutex qeth_mod_mutex;
  46. static void qeth_send_control_data_cb(struct qeth_channel *,
  47. struct qeth_cmd_buffer *);
  48. static int qeth_issue_next_read(struct qeth_card *);
  49. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  50. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  51. static void qeth_free_buffer_pool(struct qeth_card *);
  52. static int qeth_qdio_establish(struct qeth_card *);
  53. static void qeth_free_qdio_buffers(struct qeth_card *);
  54. static void qeth_notify_skbs(struct qeth_qdio_out_q *queue,
  55. struct qeth_qdio_out_buffer *buf,
  56. enum iucv_tx_notify notification);
  57. static void qeth_release_skbs(struct qeth_qdio_out_buffer *buf);
  58. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  59. struct qeth_qdio_out_buffer *buf,
  60. enum qeth_qdio_buffer_states newbufstate);
  61. static int qeth_init_qdio_out_buf(struct qeth_qdio_out_q *, int);
  62. static struct workqueue_struct *qeth_wq;
  63. static void qeth_close_dev_handler(struct work_struct *work)
  64. {
  65. struct qeth_card *card;
  66. card = container_of(work, struct qeth_card, close_dev_work);
  67. QETH_CARD_TEXT(card, 2, "cldevhdl");
  68. rtnl_lock();
  69. dev_close(card->dev);
  70. rtnl_unlock();
  71. ccwgroup_set_offline(card->gdev);
  72. }
  73. void qeth_close_dev(struct qeth_card *card)
  74. {
  75. QETH_CARD_TEXT(card, 2, "cldevsubm");
  76. queue_work(qeth_wq, &card->close_dev_work);
  77. }
  78. EXPORT_SYMBOL_GPL(qeth_close_dev);
  79. static inline const char *qeth_get_cardname(struct qeth_card *card)
  80. {
  81. if (card->info.guestlan) {
  82. switch (card->info.type) {
  83. case QETH_CARD_TYPE_OSD:
  84. return " Virtual NIC QDIO";
  85. case QETH_CARD_TYPE_IQD:
  86. return " Virtual NIC Hiper";
  87. case QETH_CARD_TYPE_OSM:
  88. return " Virtual NIC QDIO - OSM";
  89. case QETH_CARD_TYPE_OSX:
  90. return " Virtual NIC QDIO - OSX";
  91. default:
  92. return " unknown";
  93. }
  94. } else {
  95. switch (card->info.type) {
  96. case QETH_CARD_TYPE_OSD:
  97. return " OSD Express";
  98. case QETH_CARD_TYPE_IQD:
  99. return " HiperSockets";
  100. case QETH_CARD_TYPE_OSN:
  101. return " OSN QDIO";
  102. case QETH_CARD_TYPE_OSM:
  103. return " OSM QDIO";
  104. case QETH_CARD_TYPE_OSX:
  105. return " OSX QDIO";
  106. default:
  107. return " unknown";
  108. }
  109. }
  110. return " n/a";
  111. }
  112. /* max length to be returned: 14 */
  113. const char *qeth_get_cardname_short(struct qeth_card *card)
  114. {
  115. if (card->info.guestlan) {
  116. switch (card->info.type) {
  117. case QETH_CARD_TYPE_OSD:
  118. return "Virt.NIC QDIO";
  119. case QETH_CARD_TYPE_IQD:
  120. return "Virt.NIC Hiper";
  121. case QETH_CARD_TYPE_OSM:
  122. return "Virt.NIC OSM";
  123. case QETH_CARD_TYPE_OSX:
  124. return "Virt.NIC OSX";
  125. default:
  126. return "unknown";
  127. }
  128. } else {
  129. switch (card->info.type) {
  130. case QETH_CARD_TYPE_OSD:
  131. switch (card->info.link_type) {
  132. case QETH_LINK_TYPE_FAST_ETH:
  133. return "OSD_100";
  134. case QETH_LINK_TYPE_HSTR:
  135. return "HSTR";
  136. case QETH_LINK_TYPE_GBIT_ETH:
  137. return "OSD_1000";
  138. case QETH_LINK_TYPE_10GBIT_ETH:
  139. return "OSD_10GIG";
  140. case QETH_LINK_TYPE_LANE_ETH100:
  141. return "OSD_FE_LANE";
  142. case QETH_LINK_TYPE_LANE_TR:
  143. return "OSD_TR_LANE";
  144. case QETH_LINK_TYPE_LANE_ETH1000:
  145. return "OSD_GbE_LANE";
  146. case QETH_LINK_TYPE_LANE:
  147. return "OSD_ATM_LANE";
  148. default:
  149. return "OSD_Express";
  150. }
  151. case QETH_CARD_TYPE_IQD:
  152. return "HiperSockets";
  153. case QETH_CARD_TYPE_OSN:
  154. return "OSN";
  155. case QETH_CARD_TYPE_OSM:
  156. return "OSM_1000";
  157. case QETH_CARD_TYPE_OSX:
  158. return "OSX_10GIG";
  159. default:
  160. return "unknown";
  161. }
  162. }
  163. return "n/a";
  164. }
  165. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  166. int clear_start_mask)
  167. {
  168. unsigned long flags;
  169. spin_lock_irqsave(&card->thread_mask_lock, flags);
  170. card->thread_allowed_mask = threads;
  171. if (clear_start_mask)
  172. card->thread_start_mask &= threads;
  173. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  174. wake_up(&card->wait_q);
  175. }
  176. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  177. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  178. {
  179. unsigned long flags;
  180. int rc = 0;
  181. spin_lock_irqsave(&card->thread_mask_lock, flags);
  182. rc = (card->thread_running_mask & threads);
  183. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  184. return rc;
  185. }
  186. EXPORT_SYMBOL_GPL(qeth_threads_running);
  187. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  188. {
  189. return wait_event_interruptible(card->wait_q,
  190. qeth_threads_running(card, threads) == 0);
  191. }
  192. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  193. void qeth_clear_working_pool_list(struct qeth_card *card)
  194. {
  195. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  196. QETH_CARD_TEXT(card, 5, "clwrklst");
  197. list_for_each_entry_safe(pool_entry, tmp,
  198. &card->qdio.in_buf_pool.entry_list, list){
  199. list_del(&pool_entry->list);
  200. }
  201. }
  202. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  203. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  204. {
  205. struct qeth_buffer_pool_entry *pool_entry;
  206. void *ptr;
  207. int i, j;
  208. QETH_CARD_TEXT(card, 5, "alocpool");
  209. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  210. pool_entry = kzalloc(sizeof(*pool_entry), GFP_KERNEL);
  211. if (!pool_entry) {
  212. qeth_free_buffer_pool(card);
  213. return -ENOMEM;
  214. }
  215. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  216. ptr = (void *) __get_free_page(GFP_KERNEL);
  217. if (!ptr) {
  218. while (j > 0)
  219. free_page((unsigned long)
  220. pool_entry->elements[--j]);
  221. kfree(pool_entry);
  222. qeth_free_buffer_pool(card);
  223. return -ENOMEM;
  224. }
  225. pool_entry->elements[j] = ptr;
  226. }
  227. list_add(&pool_entry->init_list,
  228. &card->qdio.init_pool.entry_list);
  229. }
  230. return 0;
  231. }
  232. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  233. {
  234. QETH_CARD_TEXT(card, 2, "realcbp");
  235. if ((card->state != CARD_STATE_DOWN) &&
  236. (card->state != CARD_STATE_RECOVER))
  237. return -EPERM;
  238. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  239. qeth_clear_working_pool_list(card);
  240. qeth_free_buffer_pool(card);
  241. card->qdio.in_buf_pool.buf_count = bufcnt;
  242. card->qdio.init_pool.buf_count = bufcnt;
  243. return qeth_alloc_buffer_pool(card);
  244. }
  245. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  246. static inline int qeth_cq_init(struct qeth_card *card)
  247. {
  248. int rc;
  249. if (card->options.cq == QETH_CQ_ENABLED) {
  250. QETH_DBF_TEXT(SETUP, 2, "cqinit");
  251. memset(card->qdio.c_q->qdio_bufs, 0,
  252. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  253. card->qdio.c_q->next_buf_to_init = 127;
  254. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT,
  255. card->qdio.no_in_queues - 1, 0,
  256. 127);
  257. if (rc) {
  258. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  259. goto out;
  260. }
  261. }
  262. rc = 0;
  263. out:
  264. return rc;
  265. }
  266. static inline int qeth_alloc_cq(struct qeth_card *card)
  267. {
  268. int rc;
  269. if (card->options.cq == QETH_CQ_ENABLED) {
  270. int i;
  271. struct qdio_outbuf_state *outbuf_states;
  272. QETH_DBF_TEXT(SETUP, 2, "cqon");
  273. card->qdio.c_q = kzalloc(sizeof(struct qeth_qdio_q),
  274. GFP_KERNEL);
  275. if (!card->qdio.c_q) {
  276. rc = -1;
  277. goto kmsg_out;
  278. }
  279. QETH_DBF_HEX(SETUP, 2, &card->qdio.c_q, sizeof(void *));
  280. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  281. card->qdio.c_q->bufs[i].buffer =
  282. &card->qdio.c_q->qdio_bufs[i];
  283. }
  284. card->qdio.no_in_queues = 2;
  285. card->qdio.out_bufstates = (struct qdio_outbuf_state *)
  286. kzalloc(card->qdio.no_out_queues *
  287. QDIO_MAX_BUFFERS_PER_Q *
  288. sizeof(struct qdio_outbuf_state), GFP_KERNEL);
  289. outbuf_states = card->qdio.out_bufstates;
  290. if (outbuf_states == NULL) {
  291. rc = -1;
  292. goto free_cq_out;
  293. }
  294. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  295. card->qdio.out_qs[i]->bufstates = outbuf_states;
  296. outbuf_states += QDIO_MAX_BUFFERS_PER_Q;
  297. }
  298. } else {
  299. QETH_DBF_TEXT(SETUP, 2, "nocq");
  300. card->qdio.c_q = NULL;
  301. card->qdio.no_in_queues = 1;
  302. }
  303. QETH_DBF_TEXT_(SETUP, 2, "iqc%d", card->qdio.no_in_queues);
  304. rc = 0;
  305. out:
  306. return rc;
  307. free_cq_out:
  308. kfree(card->qdio.c_q);
  309. card->qdio.c_q = NULL;
  310. kmsg_out:
  311. dev_err(&card->gdev->dev, "Failed to create completion queue\n");
  312. goto out;
  313. }
  314. static inline void qeth_free_cq(struct qeth_card *card)
  315. {
  316. if (card->qdio.c_q) {
  317. --card->qdio.no_in_queues;
  318. kfree(card->qdio.c_q);
  319. card->qdio.c_q = NULL;
  320. }
  321. kfree(card->qdio.out_bufstates);
  322. card->qdio.out_bufstates = NULL;
  323. }
  324. static inline enum iucv_tx_notify qeth_compute_cq_notification(int sbalf15,
  325. int delayed) {
  326. enum iucv_tx_notify n;
  327. switch (sbalf15) {
  328. case 0:
  329. n = delayed ? TX_NOTIFY_DELAYED_OK : TX_NOTIFY_OK;
  330. break;
  331. case 4:
  332. case 16:
  333. case 17:
  334. case 18:
  335. n = delayed ? TX_NOTIFY_DELAYED_UNREACHABLE :
  336. TX_NOTIFY_UNREACHABLE;
  337. break;
  338. default:
  339. n = delayed ? TX_NOTIFY_DELAYED_GENERALERROR :
  340. TX_NOTIFY_GENERALERROR;
  341. break;
  342. }
  343. return n;
  344. }
  345. static inline void qeth_cleanup_handled_pending(struct qeth_qdio_out_q *q,
  346. int bidx, int forced_cleanup)
  347. {
  348. if (q->card->options.cq != QETH_CQ_ENABLED)
  349. return;
  350. if (q->bufs[bidx]->next_pending != NULL) {
  351. struct qeth_qdio_out_buffer *head = q->bufs[bidx];
  352. struct qeth_qdio_out_buffer *c = q->bufs[bidx]->next_pending;
  353. while (c) {
  354. if (forced_cleanup ||
  355. atomic_read(&c->state) ==
  356. QETH_QDIO_BUF_HANDLED_DELAYED) {
  357. struct qeth_qdio_out_buffer *f = c;
  358. QETH_CARD_TEXT(f->q->card, 5, "fp");
  359. QETH_CARD_TEXT_(f->q->card, 5, "%lx", (long) f);
  360. /* release here to avoid interleaving between
  361. outbound tasklet and inbound tasklet
  362. regarding notifications and lifecycle */
  363. qeth_release_skbs(c);
  364. c = f->next_pending;
  365. WARN_ON_ONCE(head->next_pending != f);
  366. head->next_pending = c;
  367. kmem_cache_free(qeth_qdio_outbuf_cache, f);
  368. } else {
  369. head = c;
  370. c = c->next_pending;
  371. }
  372. }
  373. }
  374. if (forced_cleanup && (atomic_read(&(q->bufs[bidx]->state)) ==
  375. QETH_QDIO_BUF_HANDLED_DELAYED)) {
  376. /* for recovery situations */
  377. q->bufs[bidx]->aob = q->bufstates[bidx].aob;
  378. qeth_init_qdio_out_buf(q, bidx);
  379. QETH_CARD_TEXT(q->card, 2, "clprecov");
  380. }
  381. }
  382. static inline void qeth_qdio_handle_aob(struct qeth_card *card,
  383. unsigned long phys_aob_addr) {
  384. struct qaob *aob;
  385. struct qeth_qdio_out_buffer *buffer;
  386. enum iucv_tx_notify notification;
  387. aob = (struct qaob *) phys_to_virt(phys_aob_addr);
  388. QETH_CARD_TEXT(card, 5, "haob");
  389. QETH_CARD_TEXT_(card, 5, "%lx", phys_aob_addr);
  390. buffer = (struct qeth_qdio_out_buffer *) aob->user1;
  391. QETH_CARD_TEXT_(card, 5, "%lx", aob->user1);
  392. if (atomic_cmpxchg(&buffer->state, QETH_QDIO_BUF_PRIMED,
  393. QETH_QDIO_BUF_IN_CQ) == QETH_QDIO_BUF_PRIMED) {
  394. notification = TX_NOTIFY_OK;
  395. } else {
  396. WARN_ON_ONCE(atomic_read(&buffer->state) !=
  397. QETH_QDIO_BUF_PENDING);
  398. atomic_set(&buffer->state, QETH_QDIO_BUF_IN_CQ);
  399. notification = TX_NOTIFY_DELAYED_OK;
  400. }
  401. if (aob->aorc != 0) {
  402. QETH_CARD_TEXT_(card, 2, "aorc%02X", aob->aorc);
  403. notification = qeth_compute_cq_notification(aob->aorc, 1);
  404. }
  405. qeth_notify_skbs(buffer->q, buffer, notification);
  406. buffer->aob = NULL;
  407. qeth_clear_output_buffer(buffer->q, buffer,
  408. QETH_QDIO_BUF_HANDLED_DELAYED);
  409. /* from here on: do not touch buffer anymore */
  410. qdio_release_aob(aob);
  411. }
  412. static inline int qeth_is_cq(struct qeth_card *card, unsigned int queue)
  413. {
  414. return card->options.cq == QETH_CQ_ENABLED &&
  415. card->qdio.c_q != NULL &&
  416. queue != 0 &&
  417. queue == card->qdio.no_in_queues - 1;
  418. }
  419. static int qeth_issue_next_read(struct qeth_card *card)
  420. {
  421. int rc;
  422. struct qeth_cmd_buffer *iob;
  423. QETH_CARD_TEXT(card, 5, "issnxrd");
  424. if (card->read.state != CH_STATE_UP)
  425. return -EIO;
  426. iob = qeth_get_buffer(&card->read);
  427. if (!iob) {
  428. dev_warn(&card->gdev->dev, "The qeth device driver "
  429. "failed to recover an error on the device\n");
  430. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  431. "available\n", dev_name(&card->gdev->dev));
  432. return -ENOMEM;
  433. }
  434. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  435. QETH_CARD_TEXT(card, 6, "noirqpnd");
  436. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  437. (addr_t) iob, 0, 0);
  438. if (rc) {
  439. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  440. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  441. atomic_set(&card->read.irq_pending, 0);
  442. card->read_or_write_problem = 1;
  443. qeth_schedule_recovery(card);
  444. wake_up(&card->wait_q);
  445. }
  446. return rc;
  447. }
  448. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  449. {
  450. struct qeth_reply *reply;
  451. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  452. if (reply) {
  453. atomic_set(&reply->refcnt, 1);
  454. atomic_set(&reply->received, 0);
  455. reply->card = card;
  456. }
  457. return reply;
  458. }
  459. static void qeth_get_reply(struct qeth_reply *reply)
  460. {
  461. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  462. atomic_inc(&reply->refcnt);
  463. }
  464. static void qeth_put_reply(struct qeth_reply *reply)
  465. {
  466. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  467. if (atomic_dec_and_test(&reply->refcnt))
  468. kfree(reply);
  469. }
  470. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  471. struct qeth_card *card)
  472. {
  473. char *ipa_name;
  474. int com = cmd->hdr.command;
  475. ipa_name = qeth_get_ipa_cmd_name(com);
  476. if (rc)
  477. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s/%s returned "
  478. "x%X \"%s\"\n",
  479. ipa_name, com, dev_name(&card->gdev->dev),
  480. QETH_CARD_IFNAME(card), rc,
  481. qeth_get_ipa_msg(rc));
  482. else
  483. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s/%s succeeded\n",
  484. ipa_name, com, dev_name(&card->gdev->dev),
  485. QETH_CARD_IFNAME(card));
  486. }
  487. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  488. struct qeth_cmd_buffer *iob)
  489. {
  490. struct qeth_ipa_cmd *cmd = NULL;
  491. QETH_CARD_TEXT(card, 5, "chkipad");
  492. if (IS_IPA(iob->data)) {
  493. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  494. if (IS_IPA_REPLY(cmd)) {
  495. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  496. cmd->hdr.command != IPA_CMD_DELCCID &&
  497. cmd->hdr.command != IPA_CMD_MODCCID &&
  498. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  499. qeth_issue_ipa_msg(cmd,
  500. cmd->hdr.return_code, card);
  501. return cmd;
  502. } else {
  503. switch (cmd->hdr.command) {
  504. case IPA_CMD_STOPLAN:
  505. if (cmd->hdr.return_code ==
  506. IPA_RC_VEPA_TO_VEB_TRANSITION) {
  507. dev_err(&card->gdev->dev,
  508. "Interface %s is down because the "
  509. "adjacent port is no longer in "
  510. "reflective relay mode\n",
  511. QETH_CARD_IFNAME(card));
  512. qeth_close_dev(card);
  513. } else {
  514. dev_warn(&card->gdev->dev,
  515. "The link for interface %s on CHPID"
  516. " 0x%X failed\n",
  517. QETH_CARD_IFNAME(card),
  518. card->info.chpid);
  519. qeth_issue_ipa_msg(cmd,
  520. cmd->hdr.return_code, card);
  521. }
  522. card->lan_online = 0;
  523. if (card->dev && netif_carrier_ok(card->dev))
  524. netif_carrier_off(card->dev);
  525. return NULL;
  526. case IPA_CMD_STARTLAN:
  527. dev_info(&card->gdev->dev,
  528. "The link for %s on CHPID 0x%X has"
  529. " been restored\n",
  530. QETH_CARD_IFNAME(card),
  531. card->info.chpid);
  532. netif_carrier_on(card->dev);
  533. card->lan_online = 1;
  534. if (card->info.hwtrap)
  535. card->info.hwtrap = 2;
  536. qeth_schedule_recovery(card);
  537. return NULL;
  538. case IPA_CMD_MODCCID:
  539. return cmd;
  540. case IPA_CMD_REGISTER_LOCAL_ADDR:
  541. QETH_CARD_TEXT(card, 3, "irla");
  542. break;
  543. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  544. QETH_CARD_TEXT(card, 3, "urla");
  545. break;
  546. default:
  547. QETH_DBF_MESSAGE(2, "Received data is IPA "
  548. "but not a reply!\n");
  549. break;
  550. }
  551. }
  552. }
  553. return cmd;
  554. }
  555. void qeth_clear_ipacmd_list(struct qeth_card *card)
  556. {
  557. struct qeth_reply *reply, *r;
  558. unsigned long flags;
  559. QETH_CARD_TEXT(card, 4, "clipalst");
  560. spin_lock_irqsave(&card->lock, flags);
  561. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  562. qeth_get_reply(reply);
  563. reply->rc = -EIO;
  564. atomic_inc(&reply->received);
  565. list_del_init(&reply->list);
  566. wake_up(&reply->wait_q);
  567. qeth_put_reply(reply);
  568. }
  569. spin_unlock_irqrestore(&card->lock, flags);
  570. atomic_set(&card->write.irq_pending, 0);
  571. }
  572. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  573. static int qeth_check_idx_response(struct qeth_card *card,
  574. unsigned char *buffer)
  575. {
  576. if (!buffer)
  577. return 0;
  578. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  579. if ((buffer[2] & 0xc0) == 0xc0) {
  580. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  581. "with cause code 0x%02x%s\n",
  582. buffer[4],
  583. ((buffer[4] == 0x22) ?
  584. " -- try another portname" : ""));
  585. QETH_CARD_TEXT(card, 2, "ckidxres");
  586. QETH_CARD_TEXT(card, 2, " idxterm");
  587. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  588. if (buffer[4] == 0xf6) {
  589. dev_err(&card->gdev->dev,
  590. "The qeth device is not configured "
  591. "for the OSI layer required by z/VM\n");
  592. return -EPERM;
  593. }
  594. return -EIO;
  595. }
  596. return 0;
  597. }
  598. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  599. __u32 len)
  600. {
  601. struct qeth_card *card;
  602. card = CARD_FROM_CDEV(channel->ccwdev);
  603. QETH_CARD_TEXT(card, 4, "setupccw");
  604. if (channel == &card->read)
  605. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  606. else
  607. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  608. channel->ccw.count = len;
  609. channel->ccw.cda = (__u32) __pa(iob);
  610. }
  611. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  612. {
  613. __u8 index;
  614. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "getbuff");
  615. index = channel->io_buf_no;
  616. do {
  617. if (channel->iob[index].state == BUF_STATE_FREE) {
  618. channel->iob[index].state = BUF_STATE_LOCKED;
  619. channel->io_buf_no = (channel->io_buf_no + 1) %
  620. QETH_CMD_BUFFER_NO;
  621. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  622. return channel->iob + index;
  623. }
  624. index = (index + 1) % QETH_CMD_BUFFER_NO;
  625. } while (index != channel->io_buf_no);
  626. return NULL;
  627. }
  628. void qeth_release_buffer(struct qeth_channel *channel,
  629. struct qeth_cmd_buffer *iob)
  630. {
  631. unsigned long flags;
  632. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "relbuff");
  633. spin_lock_irqsave(&channel->iob_lock, flags);
  634. memset(iob->data, 0, QETH_BUFSIZE);
  635. iob->state = BUF_STATE_FREE;
  636. iob->callback = qeth_send_control_data_cb;
  637. iob->rc = 0;
  638. spin_unlock_irqrestore(&channel->iob_lock, flags);
  639. wake_up(&channel->wait_q);
  640. }
  641. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  642. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  643. {
  644. struct qeth_cmd_buffer *buffer = NULL;
  645. unsigned long flags;
  646. spin_lock_irqsave(&channel->iob_lock, flags);
  647. buffer = __qeth_get_buffer(channel);
  648. spin_unlock_irqrestore(&channel->iob_lock, flags);
  649. return buffer;
  650. }
  651. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  652. {
  653. struct qeth_cmd_buffer *buffer;
  654. wait_event(channel->wait_q,
  655. ((buffer = qeth_get_buffer(channel)) != NULL));
  656. return buffer;
  657. }
  658. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  659. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  660. {
  661. int cnt;
  662. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  663. qeth_release_buffer(channel, &channel->iob[cnt]);
  664. channel->buf_no = 0;
  665. channel->io_buf_no = 0;
  666. }
  667. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  668. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  669. struct qeth_cmd_buffer *iob)
  670. {
  671. struct qeth_card *card;
  672. struct qeth_reply *reply, *r;
  673. struct qeth_ipa_cmd *cmd;
  674. unsigned long flags;
  675. int keep_reply;
  676. int rc = 0;
  677. card = CARD_FROM_CDEV(channel->ccwdev);
  678. QETH_CARD_TEXT(card, 4, "sndctlcb");
  679. rc = qeth_check_idx_response(card, iob->data);
  680. switch (rc) {
  681. case 0:
  682. break;
  683. case -EIO:
  684. qeth_clear_ipacmd_list(card);
  685. qeth_schedule_recovery(card);
  686. /* fall through */
  687. default:
  688. goto out;
  689. }
  690. cmd = qeth_check_ipa_data(card, iob);
  691. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  692. goto out;
  693. /*in case of OSN : check if cmd is set */
  694. if (card->info.type == QETH_CARD_TYPE_OSN &&
  695. cmd &&
  696. cmd->hdr.command != IPA_CMD_STARTLAN &&
  697. card->osn_info.assist_cb != NULL) {
  698. card->osn_info.assist_cb(card->dev, cmd);
  699. goto out;
  700. }
  701. spin_lock_irqsave(&card->lock, flags);
  702. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  703. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  704. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  705. qeth_get_reply(reply);
  706. list_del_init(&reply->list);
  707. spin_unlock_irqrestore(&card->lock, flags);
  708. keep_reply = 0;
  709. if (reply->callback != NULL) {
  710. if (cmd) {
  711. reply->offset = (__u16)((char *)cmd -
  712. (char *)iob->data);
  713. keep_reply = reply->callback(card,
  714. reply,
  715. (unsigned long)cmd);
  716. } else
  717. keep_reply = reply->callback(card,
  718. reply,
  719. (unsigned long)iob);
  720. }
  721. if (cmd)
  722. reply->rc = (u16) cmd->hdr.return_code;
  723. else if (iob->rc)
  724. reply->rc = iob->rc;
  725. if (keep_reply) {
  726. spin_lock_irqsave(&card->lock, flags);
  727. list_add_tail(&reply->list,
  728. &card->cmd_waiter_list);
  729. spin_unlock_irqrestore(&card->lock, flags);
  730. } else {
  731. atomic_inc(&reply->received);
  732. wake_up(&reply->wait_q);
  733. }
  734. qeth_put_reply(reply);
  735. goto out;
  736. }
  737. }
  738. spin_unlock_irqrestore(&card->lock, flags);
  739. out:
  740. memcpy(&card->seqno.pdu_hdr_ack,
  741. QETH_PDU_HEADER_SEQ_NO(iob->data),
  742. QETH_SEQ_NO_LENGTH);
  743. qeth_release_buffer(channel, iob);
  744. }
  745. static int qeth_setup_channel(struct qeth_channel *channel)
  746. {
  747. int cnt;
  748. QETH_DBF_TEXT(SETUP, 2, "setupch");
  749. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  750. channel->iob[cnt].data =
  751. kzalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  752. if (channel->iob[cnt].data == NULL)
  753. break;
  754. channel->iob[cnt].state = BUF_STATE_FREE;
  755. channel->iob[cnt].channel = channel;
  756. channel->iob[cnt].callback = qeth_send_control_data_cb;
  757. channel->iob[cnt].rc = 0;
  758. }
  759. if (cnt < QETH_CMD_BUFFER_NO) {
  760. while (cnt-- > 0)
  761. kfree(channel->iob[cnt].data);
  762. return -ENOMEM;
  763. }
  764. channel->buf_no = 0;
  765. channel->io_buf_no = 0;
  766. atomic_set(&channel->irq_pending, 0);
  767. spin_lock_init(&channel->iob_lock);
  768. init_waitqueue_head(&channel->wait_q);
  769. return 0;
  770. }
  771. static int qeth_set_thread_start_bit(struct qeth_card *card,
  772. unsigned long thread)
  773. {
  774. unsigned long flags;
  775. spin_lock_irqsave(&card->thread_mask_lock, flags);
  776. if (!(card->thread_allowed_mask & thread) ||
  777. (card->thread_start_mask & thread)) {
  778. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  779. return -EPERM;
  780. }
  781. card->thread_start_mask |= thread;
  782. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  783. return 0;
  784. }
  785. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  786. {
  787. unsigned long flags;
  788. spin_lock_irqsave(&card->thread_mask_lock, flags);
  789. card->thread_start_mask &= ~thread;
  790. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  791. wake_up(&card->wait_q);
  792. }
  793. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  794. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  795. {
  796. unsigned long flags;
  797. spin_lock_irqsave(&card->thread_mask_lock, flags);
  798. card->thread_running_mask &= ~thread;
  799. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  800. wake_up(&card->wait_q);
  801. }
  802. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  803. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  804. {
  805. unsigned long flags;
  806. int rc = 0;
  807. spin_lock_irqsave(&card->thread_mask_lock, flags);
  808. if (card->thread_start_mask & thread) {
  809. if ((card->thread_allowed_mask & thread) &&
  810. !(card->thread_running_mask & thread)) {
  811. rc = 1;
  812. card->thread_start_mask &= ~thread;
  813. card->thread_running_mask |= thread;
  814. } else
  815. rc = -EPERM;
  816. }
  817. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  818. return rc;
  819. }
  820. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  821. {
  822. int rc = 0;
  823. wait_event(card->wait_q,
  824. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  825. return rc;
  826. }
  827. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  828. void qeth_schedule_recovery(struct qeth_card *card)
  829. {
  830. QETH_CARD_TEXT(card, 2, "startrec");
  831. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  832. schedule_work(&card->kernel_thread_starter);
  833. }
  834. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  835. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  836. {
  837. int dstat, cstat;
  838. char *sense;
  839. struct qeth_card *card;
  840. sense = (char *) irb->ecw;
  841. cstat = irb->scsw.cmd.cstat;
  842. dstat = irb->scsw.cmd.dstat;
  843. card = CARD_FROM_CDEV(cdev);
  844. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  845. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  846. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  847. QETH_CARD_TEXT(card, 2, "CGENCHK");
  848. dev_warn(&cdev->dev, "The qeth device driver "
  849. "failed to recover an error on the device\n");
  850. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x\n",
  851. dev_name(&cdev->dev), dstat, cstat);
  852. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  853. 16, 1, irb, 64, 1);
  854. return 1;
  855. }
  856. if (dstat & DEV_STAT_UNIT_CHECK) {
  857. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  858. SENSE_RESETTING_EVENT_FLAG) {
  859. QETH_CARD_TEXT(card, 2, "REVIND");
  860. return 1;
  861. }
  862. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  863. SENSE_COMMAND_REJECT_FLAG) {
  864. QETH_CARD_TEXT(card, 2, "CMDREJi");
  865. return 1;
  866. }
  867. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  868. QETH_CARD_TEXT(card, 2, "AFFE");
  869. return 1;
  870. }
  871. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  872. QETH_CARD_TEXT(card, 2, "ZEROSEN");
  873. return 0;
  874. }
  875. QETH_CARD_TEXT(card, 2, "DGENCHK");
  876. return 1;
  877. }
  878. return 0;
  879. }
  880. static long __qeth_check_irb_error(struct ccw_device *cdev,
  881. unsigned long intparm, struct irb *irb)
  882. {
  883. struct qeth_card *card;
  884. card = CARD_FROM_CDEV(cdev);
  885. if (!IS_ERR(irb))
  886. return 0;
  887. switch (PTR_ERR(irb)) {
  888. case -EIO:
  889. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  890. dev_name(&cdev->dev));
  891. QETH_CARD_TEXT(card, 2, "ckirberr");
  892. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  893. break;
  894. case -ETIMEDOUT:
  895. dev_warn(&cdev->dev, "A hardware operation timed out"
  896. " on the device\n");
  897. QETH_CARD_TEXT(card, 2, "ckirberr");
  898. QETH_CARD_TEXT_(card, 2, " rc%d", -ETIMEDOUT);
  899. if (intparm == QETH_RCD_PARM) {
  900. if (card && (card->data.ccwdev == cdev)) {
  901. card->data.state = CH_STATE_DOWN;
  902. wake_up(&card->wait_q);
  903. }
  904. }
  905. break;
  906. default:
  907. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  908. dev_name(&cdev->dev), PTR_ERR(irb));
  909. QETH_CARD_TEXT(card, 2, "ckirberr");
  910. QETH_CARD_TEXT(card, 2, " rc???");
  911. }
  912. return PTR_ERR(irb);
  913. }
  914. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  915. struct irb *irb)
  916. {
  917. int rc;
  918. int cstat, dstat;
  919. struct qeth_cmd_buffer *buffer;
  920. struct qeth_channel *channel;
  921. struct qeth_card *card;
  922. struct qeth_cmd_buffer *iob;
  923. __u8 index;
  924. if (__qeth_check_irb_error(cdev, intparm, irb))
  925. return;
  926. cstat = irb->scsw.cmd.cstat;
  927. dstat = irb->scsw.cmd.dstat;
  928. card = CARD_FROM_CDEV(cdev);
  929. if (!card)
  930. return;
  931. QETH_CARD_TEXT(card, 5, "irq");
  932. if (card->read.ccwdev == cdev) {
  933. channel = &card->read;
  934. QETH_CARD_TEXT(card, 5, "read");
  935. } else if (card->write.ccwdev == cdev) {
  936. channel = &card->write;
  937. QETH_CARD_TEXT(card, 5, "write");
  938. } else {
  939. channel = &card->data;
  940. QETH_CARD_TEXT(card, 5, "data");
  941. }
  942. atomic_set(&channel->irq_pending, 0);
  943. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  944. channel->state = CH_STATE_STOPPED;
  945. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  946. channel->state = CH_STATE_HALTED;
  947. /*let's wake up immediately on data channel*/
  948. if ((channel == &card->data) && (intparm != 0) &&
  949. (intparm != QETH_RCD_PARM))
  950. goto out;
  951. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  952. QETH_CARD_TEXT(card, 6, "clrchpar");
  953. /* we don't have to handle this further */
  954. intparm = 0;
  955. }
  956. if (intparm == QETH_HALT_CHANNEL_PARM) {
  957. QETH_CARD_TEXT(card, 6, "hltchpar");
  958. /* we don't have to handle this further */
  959. intparm = 0;
  960. }
  961. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  962. (dstat & DEV_STAT_UNIT_CHECK) ||
  963. (cstat)) {
  964. if (irb->esw.esw0.erw.cons) {
  965. dev_warn(&channel->ccwdev->dev,
  966. "The qeth device driver failed to recover "
  967. "an error on the device\n");
  968. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  969. "0x%X dstat 0x%X\n",
  970. dev_name(&channel->ccwdev->dev), cstat, dstat);
  971. print_hex_dump(KERN_WARNING, "qeth: irb ",
  972. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  973. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  974. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  975. }
  976. if (intparm == QETH_RCD_PARM) {
  977. channel->state = CH_STATE_DOWN;
  978. goto out;
  979. }
  980. rc = qeth_get_problem(cdev, irb);
  981. if (rc) {
  982. qeth_clear_ipacmd_list(card);
  983. qeth_schedule_recovery(card);
  984. goto out;
  985. }
  986. }
  987. if (intparm == QETH_RCD_PARM) {
  988. channel->state = CH_STATE_RCD_DONE;
  989. goto out;
  990. }
  991. if (intparm) {
  992. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  993. buffer->state = BUF_STATE_PROCESSED;
  994. }
  995. if (channel == &card->data)
  996. return;
  997. if (channel == &card->read &&
  998. channel->state == CH_STATE_UP)
  999. qeth_issue_next_read(card);
  1000. iob = channel->iob;
  1001. index = channel->buf_no;
  1002. while (iob[index].state == BUF_STATE_PROCESSED) {
  1003. if (iob[index].callback != NULL)
  1004. iob[index].callback(channel, iob + index);
  1005. index = (index + 1) % QETH_CMD_BUFFER_NO;
  1006. }
  1007. channel->buf_no = index;
  1008. out:
  1009. wake_up(&card->wait_q);
  1010. return;
  1011. }
  1012. static void qeth_notify_skbs(struct qeth_qdio_out_q *q,
  1013. struct qeth_qdio_out_buffer *buf,
  1014. enum iucv_tx_notify notification)
  1015. {
  1016. struct sk_buff *skb;
  1017. if (skb_queue_empty(&buf->skb_list))
  1018. goto out;
  1019. skb = skb_peek(&buf->skb_list);
  1020. while (skb) {
  1021. QETH_CARD_TEXT_(q->card, 5, "skbn%d", notification);
  1022. QETH_CARD_TEXT_(q->card, 5, "%lx", (long) skb);
  1023. if (skb->protocol == ETH_P_AF_IUCV) {
  1024. if (skb->sk) {
  1025. struct iucv_sock *iucv = iucv_sk(skb->sk);
  1026. iucv->sk_txnotify(skb, notification);
  1027. }
  1028. }
  1029. if (skb_queue_is_last(&buf->skb_list, skb))
  1030. skb = NULL;
  1031. else
  1032. skb = skb_queue_next(&buf->skb_list, skb);
  1033. }
  1034. out:
  1035. return;
  1036. }
  1037. static void qeth_release_skbs(struct qeth_qdio_out_buffer *buf)
  1038. {
  1039. struct sk_buff *skb;
  1040. struct iucv_sock *iucv;
  1041. int notify_general_error = 0;
  1042. if (atomic_read(&buf->state) == QETH_QDIO_BUF_PENDING)
  1043. notify_general_error = 1;
  1044. /* release may never happen from within CQ tasklet scope */
  1045. WARN_ON_ONCE(atomic_read(&buf->state) == QETH_QDIO_BUF_IN_CQ);
  1046. skb = skb_dequeue(&buf->skb_list);
  1047. while (skb) {
  1048. QETH_CARD_TEXT(buf->q->card, 5, "skbr");
  1049. QETH_CARD_TEXT_(buf->q->card, 5, "%lx", (long) skb);
  1050. if (notify_general_error && skb->protocol == ETH_P_AF_IUCV) {
  1051. if (skb->sk) {
  1052. iucv = iucv_sk(skb->sk);
  1053. iucv->sk_txnotify(skb, TX_NOTIFY_GENERALERROR);
  1054. }
  1055. }
  1056. atomic_dec(&skb->users);
  1057. dev_kfree_skb_any(skb);
  1058. skb = skb_dequeue(&buf->skb_list);
  1059. }
  1060. }
  1061. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  1062. struct qeth_qdio_out_buffer *buf,
  1063. enum qeth_qdio_buffer_states newbufstate)
  1064. {
  1065. int i;
  1066. /* is PCI flag set on buffer? */
  1067. if (buf->buffer->element[0].sflags & SBAL_SFLAGS0_PCI_REQ)
  1068. atomic_dec(&queue->set_pci_flags_count);
  1069. if (newbufstate == QETH_QDIO_BUF_EMPTY) {
  1070. qeth_release_skbs(buf);
  1071. }
  1072. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  1073. if (buf->buffer->element[i].addr && buf->is_header[i])
  1074. kmem_cache_free(qeth_core_header_cache,
  1075. buf->buffer->element[i].addr);
  1076. buf->is_header[i] = 0;
  1077. buf->buffer->element[i].length = 0;
  1078. buf->buffer->element[i].addr = NULL;
  1079. buf->buffer->element[i].eflags = 0;
  1080. buf->buffer->element[i].sflags = 0;
  1081. }
  1082. buf->buffer->element[15].eflags = 0;
  1083. buf->buffer->element[15].sflags = 0;
  1084. buf->next_element_to_fill = 0;
  1085. atomic_set(&buf->state, newbufstate);
  1086. }
  1087. static void qeth_clear_outq_buffers(struct qeth_qdio_out_q *q, int free)
  1088. {
  1089. int j;
  1090. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1091. if (!q->bufs[j])
  1092. continue;
  1093. qeth_cleanup_handled_pending(q, j, 1);
  1094. qeth_clear_output_buffer(q, q->bufs[j], QETH_QDIO_BUF_EMPTY);
  1095. if (free) {
  1096. kmem_cache_free(qeth_qdio_outbuf_cache, q->bufs[j]);
  1097. q->bufs[j] = NULL;
  1098. }
  1099. }
  1100. }
  1101. void qeth_clear_qdio_buffers(struct qeth_card *card)
  1102. {
  1103. int i;
  1104. QETH_CARD_TEXT(card, 2, "clearqdbf");
  1105. /* clear outbound buffers to free skbs */
  1106. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1107. if (card->qdio.out_qs[i]) {
  1108. qeth_clear_outq_buffers(card->qdio.out_qs[i], 0);
  1109. }
  1110. }
  1111. }
  1112. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  1113. static void qeth_free_buffer_pool(struct qeth_card *card)
  1114. {
  1115. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  1116. int i = 0;
  1117. list_for_each_entry_safe(pool_entry, tmp,
  1118. &card->qdio.init_pool.entry_list, init_list){
  1119. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  1120. free_page((unsigned long)pool_entry->elements[i]);
  1121. list_del(&pool_entry->init_list);
  1122. kfree(pool_entry);
  1123. }
  1124. }
  1125. static void qeth_free_qdio_buffers(struct qeth_card *card)
  1126. {
  1127. int i, j;
  1128. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  1129. QETH_QDIO_UNINITIALIZED)
  1130. return;
  1131. qeth_free_cq(card);
  1132. cancel_delayed_work_sync(&card->buffer_reclaim_work);
  1133. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  1134. dev_kfree_skb_any(card->qdio.in_q->bufs[j].rx_skb);
  1135. kfree(card->qdio.in_q);
  1136. card->qdio.in_q = NULL;
  1137. /* inbound buffer pool */
  1138. qeth_free_buffer_pool(card);
  1139. /* free outbound qdio_qs */
  1140. if (card->qdio.out_qs) {
  1141. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1142. qeth_clear_outq_buffers(card->qdio.out_qs[i], 1);
  1143. kfree(card->qdio.out_qs[i]);
  1144. }
  1145. kfree(card->qdio.out_qs);
  1146. card->qdio.out_qs = NULL;
  1147. }
  1148. }
  1149. static void qeth_clean_channel(struct qeth_channel *channel)
  1150. {
  1151. int cnt;
  1152. QETH_DBF_TEXT(SETUP, 2, "freech");
  1153. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  1154. kfree(channel->iob[cnt].data);
  1155. }
  1156. static void qeth_set_single_write_queues(struct qeth_card *card)
  1157. {
  1158. if ((atomic_read(&card->qdio.state) != QETH_QDIO_UNINITIALIZED) &&
  1159. (card->qdio.no_out_queues == 4))
  1160. qeth_free_qdio_buffers(card);
  1161. card->qdio.no_out_queues = 1;
  1162. if (card->qdio.default_out_queue != 0)
  1163. dev_info(&card->gdev->dev, "Priority Queueing not supported\n");
  1164. card->qdio.default_out_queue = 0;
  1165. }
  1166. static void qeth_set_multiple_write_queues(struct qeth_card *card)
  1167. {
  1168. if ((atomic_read(&card->qdio.state) != QETH_QDIO_UNINITIALIZED) &&
  1169. (card->qdio.no_out_queues == 1)) {
  1170. qeth_free_qdio_buffers(card);
  1171. card->qdio.default_out_queue = 2;
  1172. }
  1173. card->qdio.no_out_queues = 4;
  1174. }
  1175. static void qeth_update_from_chp_desc(struct qeth_card *card)
  1176. {
  1177. struct ccw_device *ccwdev;
  1178. struct channelPath_dsc {
  1179. u8 flags;
  1180. u8 lsn;
  1181. u8 desc;
  1182. u8 chpid;
  1183. u8 swla;
  1184. u8 zeroes;
  1185. u8 chla;
  1186. u8 chpp;
  1187. } *chp_dsc;
  1188. QETH_DBF_TEXT(SETUP, 2, "chp_desc");
  1189. ccwdev = card->data.ccwdev;
  1190. chp_dsc = ccw_device_get_chp_desc(ccwdev, 0);
  1191. if (!chp_dsc)
  1192. goto out;
  1193. card->info.func_level = 0x4100 + chp_dsc->desc;
  1194. if (card->info.type == QETH_CARD_TYPE_IQD)
  1195. goto out;
  1196. /* CHPP field bit 6 == 1 -> single queue */
  1197. if ((chp_dsc->chpp & 0x02) == 0x02)
  1198. qeth_set_single_write_queues(card);
  1199. else
  1200. qeth_set_multiple_write_queues(card);
  1201. out:
  1202. kfree(chp_dsc);
  1203. QETH_DBF_TEXT_(SETUP, 2, "nr:%x", card->qdio.no_out_queues);
  1204. QETH_DBF_TEXT_(SETUP, 2, "lvl:%02x", card->info.func_level);
  1205. }
  1206. static void qeth_init_qdio_info(struct qeth_card *card)
  1207. {
  1208. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  1209. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1210. /* inbound */
  1211. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1212. if (card->info.type == QETH_CARD_TYPE_IQD)
  1213. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_HSDEFAULT;
  1214. else
  1215. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  1216. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  1217. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  1218. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  1219. }
  1220. static void qeth_set_intial_options(struct qeth_card *card)
  1221. {
  1222. card->options.route4.type = NO_ROUTER;
  1223. card->options.route6.type = NO_ROUTER;
  1224. card->options.fake_broadcast = 0;
  1225. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  1226. card->options.performance_stats = 0;
  1227. card->options.rx_sg_cb = QETH_RX_SG_CB;
  1228. card->options.isolation = ISOLATION_MODE_NONE;
  1229. card->options.cq = QETH_CQ_DISABLED;
  1230. }
  1231. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  1232. {
  1233. unsigned long flags;
  1234. int rc = 0;
  1235. spin_lock_irqsave(&card->thread_mask_lock, flags);
  1236. QETH_CARD_TEXT_(card, 4, " %02x%02x%02x",
  1237. (u8) card->thread_start_mask,
  1238. (u8) card->thread_allowed_mask,
  1239. (u8) card->thread_running_mask);
  1240. rc = (card->thread_start_mask & thread);
  1241. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  1242. return rc;
  1243. }
  1244. static void qeth_start_kernel_thread(struct work_struct *work)
  1245. {
  1246. struct task_struct *ts;
  1247. struct qeth_card *card = container_of(work, struct qeth_card,
  1248. kernel_thread_starter);
  1249. QETH_CARD_TEXT(card , 2, "strthrd");
  1250. if (card->read.state != CH_STATE_UP &&
  1251. card->write.state != CH_STATE_UP)
  1252. return;
  1253. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD)) {
  1254. ts = kthread_run(card->discipline->recover, (void *)card,
  1255. "qeth_recover");
  1256. if (IS_ERR(ts)) {
  1257. qeth_clear_thread_start_bit(card, QETH_RECOVER_THREAD);
  1258. qeth_clear_thread_running_bit(card,
  1259. QETH_RECOVER_THREAD);
  1260. }
  1261. }
  1262. }
  1263. static int qeth_setup_card(struct qeth_card *card)
  1264. {
  1265. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  1266. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1267. card->read.state = CH_STATE_DOWN;
  1268. card->write.state = CH_STATE_DOWN;
  1269. card->data.state = CH_STATE_DOWN;
  1270. card->state = CARD_STATE_DOWN;
  1271. card->lan_online = 0;
  1272. card->read_or_write_problem = 0;
  1273. card->dev = NULL;
  1274. spin_lock_init(&card->vlanlock);
  1275. spin_lock_init(&card->mclock);
  1276. spin_lock_init(&card->lock);
  1277. spin_lock_init(&card->ip_lock);
  1278. spin_lock_init(&card->thread_mask_lock);
  1279. mutex_init(&card->conf_mutex);
  1280. mutex_init(&card->discipline_mutex);
  1281. card->thread_start_mask = 0;
  1282. card->thread_allowed_mask = 0;
  1283. card->thread_running_mask = 0;
  1284. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1285. INIT_LIST_HEAD(&card->ip_list);
  1286. INIT_LIST_HEAD(card->ip_tbd_list);
  1287. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1288. init_waitqueue_head(&card->wait_q);
  1289. /* initial options */
  1290. qeth_set_intial_options(card);
  1291. /* IP address takeover */
  1292. INIT_LIST_HEAD(&card->ipato.entries);
  1293. card->ipato.enabled = 0;
  1294. card->ipato.invert4 = 0;
  1295. card->ipato.invert6 = 0;
  1296. /* init QDIO stuff */
  1297. qeth_init_qdio_info(card);
  1298. INIT_DELAYED_WORK(&card->buffer_reclaim_work, qeth_buffer_reclaim_work);
  1299. INIT_WORK(&card->close_dev_work, qeth_close_dev_handler);
  1300. return 0;
  1301. }
  1302. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1303. {
  1304. struct qeth_card *card = container_of(slr, struct qeth_card,
  1305. qeth_service_level);
  1306. if (card->info.mcl_level[0])
  1307. seq_printf(m, "qeth: %s firmware level %s\n",
  1308. CARD_BUS_ID(card), card->info.mcl_level);
  1309. }
  1310. static struct qeth_card *qeth_alloc_card(void)
  1311. {
  1312. struct qeth_card *card;
  1313. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1314. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1315. if (!card)
  1316. goto out;
  1317. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1318. card->ip_tbd_list = kzalloc(sizeof(struct list_head), GFP_KERNEL);
  1319. if (!card->ip_tbd_list) {
  1320. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1321. goto out_card;
  1322. }
  1323. if (qeth_setup_channel(&card->read))
  1324. goto out_ip;
  1325. if (qeth_setup_channel(&card->write))
  1326. goto out_channel;
  1327. card->options.layer2 = -1;
  1328. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1329. register_service_level(&card->qeth_service_level);
  1330. return card;
  1331. out_channel:
  1332. qeth_clean_channel(&card->read);
  1333. out_ip:
  1334. kfree(card->ip_tbd_list);
  1335. out_card:
  1336. kfree(card);
  1337. out:
  1338. return NULL;
  1339. }
  1340. static int qeth_determine_card_type(struct qeth_card *card)
  1341. {
  1342. int i = 0;
  1343. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1344. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1345. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1346. while (known_devices[i][QETH_DEV_MODEL_IND]) {
  1347. if ((CARD_RDEV(card)->id.dev_type ==
  1348. known_devices[i][QETH_DEV_TYPE_IND]) &&
  1349. (CARD_RDEV(card)->id.dev_model ==
  1350. known_devices[i][QETH_DEV_MODEL_IND])) {
  1351. card->info.type = known_devices[i][QETH_DEV_MODEL_IND];
  1352. card->qdio.no_out_queues =
  1353. known_devices[i][QETH_QUEUE_NO_IND];
  1354. card->qdio.no_in_queues = 1;
  1355. card->info.is_multicast_different =
  1356. known_devices[i][QETH_MULTICAST_IND];
  1357. qeth_update_from_chp_desc(card);
  1358. return 0;
  1359. }
  1360. i++;
  1361. }
  1362. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1363. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1364. "unknown type\n");
  1365. return -ENOENT;
  1366. }
  1367. static int qeth_clear_channel(struct qeth_channel *channel)
  1368. {
  1369. unsigned long flags;
  1370. struct qeth_card *card;
  1371. int rc;
  1372. card = CARD_FROM_CDEV(channel->ccwdev);
  1373. QETH_CARD_TEXT(card, 3, "clearch");
  1374. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1375. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1376. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1377. if (rc)
  1378. return rc;
  1379. rc = wait_event_interruptible_timeout(card->wait_q,
  1380. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1381. if (rc == -ERESTARTSYS)
  1382. return rc;
  1383. if (channel->state != CH_STATE_STOPPED)
  1384. return -ETIME;
  1385. channel->state = CH_STATE_DOWN;
  1386. return 0;
  1387. }
  1388. static int qeth_halt_channel(struct qeth_channel *channel)
  1389. {
  1390. unsigned long flags;
  1391. struct qeth_card *card;
  1392. int rc;
  1393. card = CARD_FROM_CDEV(channel->ccwdev);
  1394. QETH_CARD_TEXT(card, 3, "haltch");
  1395. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1396. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1397. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1398. if (rc)
  1399. return rc;
  1400. rc = wait_event_interruptible_timeout(card->wait_q,
  1401. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1402. if (rc == -ERESTARTSYS)
  1403. return rc;
  1404. if (channel->state != CH_STATE_HALTED)
  1405. return -ETIME;
  1406. return 0;
  1407. }
  1408. static int qeth_halt_channels(struct qeth_card *card)
  1409. {
  1410. int rc1 = 0, rc2 = 0, rc3 = 0;
  1411. QETH_CARD_TEXT(card, 3, "haltchs");
  1412. rc1 = qeth_halt_channel(&card->read);
  1413. rc2 = qeth_halt_channel(&card->write);
  1414. rc3 = qeth_halt_channel(&card->data);
  1415. if (rc1)
  1416. return rc1;
  1417. if (rc2)
  1418. return rc2;
  1419. return rc3;
  1420. }
  1421. static int qeth_clear_channels(struct qeth_card *card)
  1422. {
  1423. int rc1 = 0, rc2 = 0, rc3 = 0;
  1424. QETH_CARD_TEXT(card, 3, "clearchs");
  1425. rc1 = qeth_clear_channel(&card->read);
  1426. rc2 = qeth_clear_channel(&card->write);
  1427. rc3 = qeth_clear_channel(&card->data);
  1428. if (rc1)
  1429. return rc1;
  1430. if (rc2)
  1431. return rc2;
  1432. return rc3;
  1433. }
  1434. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1435. {
  1436. int rc = 0;
  1437. QETH_CARD_TEXT(card, 3, "clhacrd");
  1438. if (halt)
  1439. rc = qeth_halt_channels(card);
  1440. if (rc)
  1441. return rc;
  1442. return qeth_clear_channels(card);
  1443. }
  1444. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1445. {
  1446. int rc = 0;
  1447. QETH_CARD_TEXT(card, 3, "qdioclr");
  1448. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1449. QETH_QDIO_CLEANING)) {
  1450. case QETH_QDIO_ESTABLISHED:
  1451. if (card->info.type == QETH_CARD_TYPE_IQD)
  1452. rc = qdio_shutdown(CARD_DDEV(card),
  1453. QDIO_FLAG_CLEANUP_USING_HALT);
  1454. else
  1455. rc = qdio_shutdown(CARD_DDEV(card),
  1456. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1457. if (rc)
  1458. QETH_CARD_TEXT_(card, 3, "1err%d", rc);
  1459. qdio_free(CARD_DDEV(card));
  1460. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1461. break;
  1462. case QETH_QDIO_CLEANING:
  1463. return rc;
  1464. default:
  1465. break;
  1466. }
  1467. rc = qeth_clear_halt_card(card, use_halt);
  1468. if (rc)
  1469. QETH_CARD_TEXT_(card, 3, "2err%d", rc);
  1470. card->state = CARD_STATE_DOWN;
  1471. return rc;
  1472. }
  1473. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1474. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1475. int *length)
  1476. {
  1477. struct ciw *ciw;
  1478. char *rcd_buf;
  1479. int ret;
  1480. struct qeth_channel *channel = &card->data;
  1481. unsigned long flags;
  1482. /*
  1483. * scan for RCD command in extended SenseID data
  1484. */
  1485. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1486. if (!ciw || ciw->cmd == 0)
  1487. return -EOPNOTSUPP;
  1488. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1489. if (!rcd_buf)
  1490. return -ENOMEM;
  1491. channel->ccw.cmd_code = ciw->cmd;
  1492. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1493. channel->ccw.count = ciw->count;
  1494. channel->ccw.flags = CCW_FLAG_SLI;
  1495. channel->state = CH_STATE_RCD;
  1496. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1497. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1498. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1499. QETH_RCD_TIMEOUT);
  1500. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1501. if (!ret)
  1502. wait_event(card->wait_q,
  1503. (channel->state == CH_STATE_RCD_DONE ||
  1504. channel->state == CH_STATE_DOWN));
  1505. if (channel->state == CH_STATE_DOWN)
  1506. ret = -EIO;
  1507. else
  1508. channel->state = CH_STATE_DOWN;
  1509. if (ret) {
  1510. kfree(rcd_buf);
  1511. *buffer = NULL;
  1512. *length = 0;
  1513. } else {
  1514. *length = ciw->count;
  1515. *buffer = rcd_buf;
  1516. }
  1517. return ret;
  1518. }
  1519. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1520. {
  1521. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1522. card->info.chpid = prcd[30];
  1523. card->info.unit_addr2 = prcd[31];
  1524. card->info.cula = prcd[63];
  1525. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1526. (prcd[0x11] == _ascebc['M']));
  1527. }
  1528. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1529. {
  1530. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1531. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 &&
  1532. (prcd[76] == 0xF5 || prcd[76] == 0xF6)) {
  1533. card->info.blkt.time_total = 250;
  1534. card->info.blkt.inter_packet = 5;
  1535. card->info.blkt.inter_packet_jumbo = 15;
  1536. } else {
  1537. card->info.blkt.time_total = 0;
  1538. card->info.blkt.inter_packet = 0;
  1539. card->info.blkt.inter_packet_jumbo = 0;
  1540. }
  1541. }
  1542. static void qeth_init_tokens(struct qeth_card *card)
  1543. {
  1544. card->token.issuer_rm_w = 0x00010103UL;
  1545. card->token.cm_filter_w = 0x00010108UL;
  1546. card->token.cm_connection_w = 0x0001010aUL;
  1547. card->token.ulp_filter_w = 0x0001010bUL;
  1548. card->token.ulp_connection_w = 0x0001010dUL;
  1549. }
  1550. static void qeth_init_func_level(struct qeth_card *card)
  1551. {
  1552. switch (card->info.type) {
  1553. case QETH_CARD_TYPE_IQD:
  1554. card->info.func_level = QETH_IDX_FUNC_LEVEL_IQD;
  1555. break;
  1556. case QETH_CARD_TYPE_OSD:
  1557. case QETH_CARD_TYPE_OSN:
  1558. card->info.func_level = QETH_IDX_FUNC_LEVEL_OSD;
  1559. break;
  1560. default:
  1561. break;
  1562. }
  1563. }
  1564. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1565. void (*idx_reply_cb)(struct qeth_channel *,
  1566. struct qeth_cmd_buffer *))
  1567. {
  1568. struct qeth_cmd_buffer *iob;
  1569. unsigned long flags;
  1570. int rc;
  1571. struct qeth_card *card;
  1572. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1573. card = CARD_FROM_CDEV(channel->ccwdev);
  1574. iob = qeth_get_buffer(channel);
  1575. iob->callback = idx_reply_cb;
  1576. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1577. channel->ccw.count = QETH_BUFSIZE;
  1578. channel->ccw.cda = (__u32) __pa(iob->data);
  1579. wait_event(card->wait_q,
  1580. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1581. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1582. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1583. rc = ccw_device_start(channel->ccwdev,
  1584. &channel->ccw, (addr_t) iob, 0, 0);
  1585. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1586. if (rc) {
  1587. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1588. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1589. atomic_set(&channel->irq_pending, 0);
  1590. wake_up(&card->wait_q);
  1591. return rc;
  1592. }
  1593. rc = wait_event_interruptible_timeout(card->wait_q,
  1594. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1595. if (rc == -ERESTARTSYS)
  1596. return rc;
  1597. if (channel->state != CH_STATE_UP) {
  1598. rc = -ETIME;
  1599. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1600. qeth_clear_cmd_buffers(channel);
  1601. } else
  1602. rc = 0;
  1603. return rc;
  1604. }
  1605. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1606. void (*idx_reply_cb)(struct qeth_channel *,
  1607. struct qeth_cmd_buffer *))
  1608. {
  1609. struct qeth_card *card;
  1610. struct qeth_cmd_buffer *iob;
  1611. unsigned long flags;
  1612. __u16 temp;
  1613. __u8 tmp;
  1614. int rc;
  1615. struct ccw_dev_id temp_devid;
  1616. card = CARD_FROM_CDEV(channel->ccwdev);
  1617. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1618. iob = qeth_get_buffer(channel);
  1619. iob->callback = idx_reply_cb;
  1620. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1621. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1622. channel->ccw.cda = (__u32) __pa(iob->data);
  1623. if (channel == &card->write) {
  1624. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1625. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1626. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1627. card->seqno.trans_hdr++;
  1628. } else {
  1629. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1630. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1631. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1632. }
  1633. tmp = ((__u8)card->info.portno) | 0x80;
  1634. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1635. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1636. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1637. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1638. &card->info.func_level, sizeof(__u16));
  1639. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1640. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1641. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1642. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1643. wait_event(card->wait_q,
  1644. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1645. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1646. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1647. rc = ccw_device_start(channel->ccwdev,
  1648. &channel->ccw, (addr_t) iob, 0, 0);
  1649. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1650. if (rc) {
  1651. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1652. rc);
  1653. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1654. atomic_set(&channel->irq_pending, 0);
  1655. wake_up(&card->wait_q);
  1656. return rc;
  1657. }
  1658. rc = wait_event_interruptible_timeout(card->wait_q,
  1659. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1660. if (rc == -ERESTARTSYS)
  1661. return rc;
  1662. if (channel->state != CH_STATE_ACTIVATING) {
  1663. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1664. " failed to recover an error on the device\n");
  1665. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1666. dev_name(&channel->ccwdev->dev));
  1667. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1668. qeth_clear_cmd_buffers(channel);
  1669. return -ETIME;
  1670. }
  1671. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1672. }
  1673. static int qeth_peer_func_level(int level)
  1674. {
  1675. if ((level & 0xff) == 8)
  1676. return (level & 0xff) + 0x400;
  1677. if (((level >> 8) & 3) == 1)
  1678. return (level & 0xff) + 0x200;
  1679. return level;
  1680. }
  1681. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1682. struct qeth_cmd_buffer *iob)
  1683. {
  1684. struct qeth_card *card;
  1685. __u16 temp;
  1686. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1687. if (channel->state == CH_STATE_DOWN) {
  1688. channel->state = CH_STATE_ACTIVATING;
  1689. goto out;
  1690. }
  1691. card = CARD_FROM_CDEV(channel->ccwdev);
  1692. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1693. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == QETH_IDX_ACT_ERR_EXCL)
  1694. dev_err(&card->write.ccwdev->dev,
  1695. "The adapter is used exclusively by another "
  1696. "host\n");
  1697. else
  1698. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1699. " negative reply\n",
  1700. dev_name(&card->write.ccwdev->dev));
  1701. goto out;
  1702. }
  1703. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1704. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1705. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1706. "function level mismatch (sent: 0x%x, received: "
  1707. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1708. card->info.func_level, temp);
  1709. goto out;
  1710. }
  1711. channel->state = CH_STATE_UP;
  1712. out:
  1713. qeth_release_buffer(channel, iob);
  1714. }
  1715. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1716. struct qeth_cmd_buffer *iob)
  1717. {
  1718. struct qeth_card *card;
  1719. __u16 temp;
  1720. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1721. if (channel->state == CH_STATE_DOWN) {
  1722. channel->state = CH_STATE_ACTIVATING;
  1723. goto out;
  1724. }
  1725. card = CARD_FROM_CDEV(channel->ccwdev);
  1726. if (qeth_check_idx_response(card, iob->data))
  1727. goto out;
  1728. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1729. switch (QETH_IDX_ACT_CAUSE_CODE(iob->data)) {
  1730. case QETH_IDX_ACT_ERR_EXCL:
  1731. dev_err(&card->write.ccwdev->dev,
  1732. "The adapter is used exclusively by another "
  1733. "host\n");
  1734. break;
  1735. case QETH_IDX_ACT_ERR_AUTH:
  1736. case QETH_IDX_ACT_ERR_AUTH_USER:
  1737. dev_err(&card->read.ccwdev->dev,
  1738. "Setting the device online failed because of "
  1739. "insufficient authorization\n");
  1740. break;
  1741. default:
  1742. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1743. " negative reply\n",
  1744. dev_name(&card->read.ccwdev->dev));
  1745. }
  1746. QETH_CARD_TEXT_(card, 2, "idxread%c",
  1747. QETH_IDX_ACT_CAUSE_CODE(iob->data));
  1748. goto out;
  1749. }
  1750. /**
  1751. * * temporary fix for microcode bug
  1752. * * to revert it,replace OR by AND
  1753. * */
  1754. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1755. (card->info.type == QETH_CARD_TYPE_OSD))
  1756. card->info.portname_required = 1;
  1757. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1758. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1759. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1760. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1761. dev_name(&card->read.ccwdev->dev),
  1762. card->info.func_level, temp);
  1763. goto out;
  1764. }
  1765. memcpy(&card->token.issuer_rm_r,
  1766. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1767. QETH_MPC_TOKEN_LENGTH);
  1768. memcpy(&card->info.mcl_level[0],
  1769. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1770. channel->state = CH_STATE_UP;
  1771. out:
  1772. qeth_release_buffer(channel, iob);
  1773. }
  1774. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1775. struct qeth_cmd_buffer *iob)
  1776. {
  1777. qeth_setup_ccw(&card->write, iob->data, len);
  1778. iob->callback = qeth_release_buffer;
  1779. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1780. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1781. card->seqno.trans_hdr++;
  1782. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1783. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1784. card->seqno.pdu_hdr++;
  1785. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1786. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1787. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1788. }
  1789. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1790. int qeth_send_control_data(struct qeth_card *card, int len,
  1791. struct qeth_cmd_buffer *iob,
  1792. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1793. unsigned long),
  1794. void *reply_param)
  1795. {
  1796. int rc;
  1797. unsigned long flags;
  1798. struct qeth_reply *reply = NULL;
  1799. unsigned long timeout, event_timeout;
  1800. struct qeth_ipa_cmd *cmd;
  1801. QETH_CARD_TEXT(card, 2, "sendctl");
  1802. if (card->read_or_write_problem) {
  1803. qeth_release_buffer(iob->channel, iob);
  1804. return -EIO;
  1805. }
  1806. reply = qeth_alloc_reply(card);
  1807. if (!reply) {
  1808. return -ENOMEM;
  1809. }
  1810. reply->callback = reply_cb;
  1811. reply->param = reply_param;
  1812. if (card->state == CARD_STATE_DOWN)
  1813. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1814. else
  1815. reply->seqno = card->seqno.ipa++;
  1816. init_waitqueue_head(&reply->wait_q);
  1817. spin_lock_irqsave(&card->lock, flags);
  1818. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1819. spin_unlock_irqrestore(&card->lock, flags);
  1820. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1821. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1822. qeth_prepare_control_data(card, len, iob);
  1823. if (IS_IPA(iob->data))
  1824. event_timeout = QETH_IPA_TIMEOUT;
  1825. else
  1826. event_timeout = QETH_TIMEOUT;
  1827. timeout = jiffies + event_timeout;
  1828. QETH_CARD_TEXT(card, 6, "noirqpnd");
  1829. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1830. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1831. (addr_t) iob, 0, 0);
  1832. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1833. if (rc) {
  1834. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1835. "ccw_device_start rc = %i\n",
  1836. dev_name(&card->write.ccwdev->dev), rc);
  1837. QETH_CARD_TEXT_(card, 2, " err%d", rc);
  1838. spin_lock_irqsave(&card->lock, flags);
  1839. list_del_init(&reply->list);
  1840. qeth_put_reply(reply);
  1841. spin_unlock_irqrestore(&card->lock, flags);
  1842. qeth_release_buffer(iob->channel, iob);
  1843. atomic_set(&card->write.irq_pending, 0);
  1844. wake_up(&card->wait_q);
  1845. return rc;
  1846. }
  1847. /* we have only one long running ipassist, since we can ensure
  1848. process context of this command we can sleep */
  1849. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1850. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1851. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1852. if (!wait_event_timeout(reply->wait_q,
  1853. atomic_read(&reply->received), event_timeout))
  1854. goto time_err;
  1855. } else {
  1856. while (!atomic_read(&reply->received)) {
  1857. if (time_after(jiffies, timeout))
  1858. goto time_err;
  1859. cpu_relax();
  1860. }
  1861. }
  1862. if (reply->rc == -EIO)
  1863. goto error;
  1864. rc = reply->rc;
  1865. qeth_put_reply(reply);
  1866. return rc;
  1867. time_err:
  1868. reply->rc = -ETIME;
  1869. spin_lock_irqsave(&reply->card->lock, flags);
  1870. list_del_init(&reply->list);
  1871. spin_unlock_irqrestore(&reply->card->lock, flags);
  1872. atomic_inc(&reply->received);
  1873. error:
  1874. atomic_set(&card->write.irq_pending, 0);
  1875. qeth_release_buffer(iob->channel, iob);
  1876. card->write.buf_no = (card->write.buf_no + 1) % QETH_CMD_BUFFER_NO;
  1877. rc = reply->rc;
  1878. qeth_put_reply(reply);
  1879. return rc;
  1880. }
  1881. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1882. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1883. unsigned long data)
  1884. {
  1885. struct qeth_cmd_buffer *iob;
  1886. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1887. iob = (struct qeth_cmd_buffer *) data;
  1888. memcpy(&card->token.cm_filter_r,
  1889. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1890. QETH_MPC_TOKEN_LENGTH);
  1891. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1892. return 0;
  1893. }
  1894. static int qeth_cm_enable(struct qeth_card *card)
  1895. {
  1896. int rc;
  1897. struct qeth_cmd_buffer *iob;
  1898. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1899. iob = qeth_wait_for_buffer(&card->write);
  1900. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1901. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1902. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1903. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1904. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1905. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1906. qeth_cm_enable_cb, NULL);
  1907. return rc;
  1908. }
  1909. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1910. unsigned long data)
  1911. {
  1912. struct qeth_cmd_buffer *iob;
  1913. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1914. iob = (struct qeth_cmd_buffer *) data;
  1915. memcpy(&card->token.cm_connection_r,
  1916. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1917. QETH_MPC_TOKEN_LENGTH);
  1918. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1919. return 0;
  1920. }
  1921. static int qeth_cm_setup(struct qeth_card *card)
  1922. {
  1923. int rc;
  1924. struct qeth_cmd_buffer *iob;
  1925. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1926. iob = qeth_wait_for_buffer(&card->write);
  1927. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1928. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1929. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1930. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1931. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1932. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1933. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1934. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1935. qeth_cm_setup_cb, NULL);
  1936. return rc;
  1937. }
  1938. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1939. {
  1940. switch (card->info.type) {
  1941. case QETH_CARD_TYPE_UNKNOWN:
  1942. return 1500;
  1943. case QETH_CARD_TYPE_IQD:
  1944. return card->info.max_mtu;
  1945. case QETH_CARD_TYPE_OSD:
  1946. switch (card->info.link_type) {
  1947. case QETH_LINK_TYPE_HSTR:
  1948. case QETH_LINK_TYPE_LANE_TR:
  1949. return 2000;
  1950. default:
  1951. return 1492;
  1952. }
  1953. case QETH_CARD_TYPE_OSM:
  1954. case QETH_CARD_TYPE_OSX:
  1955. return 1492;
  1956. default:
  1957. return 1500;
  1958. }
  1959. }
  1960. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1961. {
  1962. switch (framesize) {
  1963. case 0x4000:
  1964. return 8192;
  1965. case 0x6000:
  1966. return 16384;
  1967. case 0xa000:
  1968. return 32768;
  1969. case 0xffff:
  1970. return 57344;
  1971. default:
  1972. return 0;
  1973. }
  1974. }
  1975. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1976. {
  1977. switch (card->info.type) {
  1978. case QETH_CARD_TYPE_OSD:
  1979. case QETH_CARD_TYPE_OSM:
  1980. case QETH_CARD_TYPE_OSX:
  1981. case QETH_CARD_TYPE_IQD:
  1982. return ((mtu >= 576) &&
  1983. (mtu <= card->info.max_mtu));
  1984. case QETH_CARD_TYPE_OSN:
  1985. case QETH_CARD_TYPE_UNKNOWN:
  1986. default:
  1987. return 1;
  1988. }
  1989. }
  1990. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1991. unsigned long data)
  1992. {
  1993. __u16 mtu, framesize;
  1994. __u16 len;
  1995. __u8 link_type;
  1996. struct qeth_cmd_buffer *iob;
  1997. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1998. iob = (struct qeth_cmd_buffer *) data;
  1999. memcpy(&card->token.ulp_filter_r,
  2000. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  2001. QETH_MPC_TOKEN_LENGTH);
  2002. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2003. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  2004. mtu = qeth_get_mtu_outof_framesize(framesize);
  2005. if (!mtu) {
  2006. iob->rc = -EINVAL;
  2007. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2008. return 0;
  2009. }
  2010. if (card->info.initial_mtu && (card->info.initial_mtu != mtu)) {
  2011. /* frame size has changed */
  2012. if (card->dev &&
  2013. ((card->dev->mtu == card->info.initial_mtu) ||
  2014. (card->dev->mtu > mtu)))
  2015. card->dev->mtu = mtu;
  2016. qeth_free_qdio_buffers(card);
  2017. }
  2018. card->info.initial_mtu = mtu;
  2019. card->info.max_mtu = mtu;
  2020. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  2021. } else {
  2022. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  2023. card->info.max_mtu = *(__u16 *)QETH_ULP_ENABLE_RESP_MAX_MTU(
  2024. iob->data);
  2025. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  2026. }
  2027. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  2028. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  2029. memcpy(&link_type,
  2030. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  2031. card->info.link_type = link_type;
  2032. } else
  2033. card->info.link_type = 0;
  2034. QETH_DBF_TEXT_(SETUP, 2, "link%d", card->info.link_type);
  2035. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2036. return 0;
  2037. }
  2038. static int qeth_ulp_enable(struct qeth_card *card)
  2039. {
  2040. int rc;
  2041. char prot_type;
  2042. struct qeth_cmd_buffer *iob;
  2043. /*FIXME: trace view callbacks*/
  2044. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  2045. iob = qeth_wait_for_buffer(&card->write);
  2046. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  2047. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  2048. (__u8) card->info.portno;
  2049. if (card->options.layer2)
  2050. if (card->info.type == QETH_CARD_TYPE_OSN)
  2051. prot_type = QETH_PROT_OSN2;
  2052. else
  2053. prot_type = QETH_PROT_LAYER2;
  2054. else
  2055. prot_type = QETH_PROT_TCPIP;
  2056. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  2057. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  2058. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2059. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  2060. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  2061. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  2062. card->info.portname, 9);
  2063. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  2064. qeth_ulp_enable_cb, NULL);
  2065. return rc;
  2066. }
  2067. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  2068. unsigned long data)
  2069. {
  2070. struct qeth_cmd_buffer *iob;
  2071. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  2072. iob = (struct qeth_cmd_buffer *) data;
  2073. memcpy(&card->token.ulp_connection_r,
  2074. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  2075. QETH_MPC_TOKEN_LENGTH);
  2076. if (!strncmp("00S", QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  2077. 3)) {
  2078. QETH_DBF_TEXT(SETUP, 2, "olmlimit");
  2079. dev_err(&card->gdev->dev, "A connection could not be "
  2080. "established because of an OLM limit\n");
  2081. iob->rc = -EMLINK;
  2082. }
  2083. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2084. return 0;
  2085. }
  2086. static int qeth_ulp_setup(struct qeth_card *card)
  2087. {
  2088. int rc;
  2089. __u16 temp;
  2090. struct qeth_cmd_buffer *iob;
  2091. struct ccw_dev_id dev_id;
  2092. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  2093. iob = qeth_wait_for_buffer(&card->write);
  2094. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  2095. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  2096. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2097. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  2098. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  2099. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  2100. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  2101. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  2102. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  2103. temp = (card->info.cula << 8) + card->info.unit_addr2;
  2104. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  2105. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  2106. qeth_ulp_setup_cb, NULL);
  2107. return rc;
  2108. }
  2109. static int qeth_init_qdio_out_buf(struct qeth_qdio_out_q *q, int bidx)
  2110. {
  2111. int rc;
  2112. struct qeth_qdio_out_buffer *newbuf;
  2113. rc = 0;
  2114. newbuf = kmem_cache_zalloc(qeth_qdio_outbuf_cache, GFP_ATOMIC);
  2115. if (!newbuf) {
  2116. rc = -ENOMEM;
  2117. goto out;
  2118. }
  2119. newbuf->buffer = &q->qdio_bufs[bidx];
  2120. skb_queue_head_init(&newbuf->skb_list);
  2121. lockdep_set_class(&newbuf->skb_list.lock, &qdio_out_skb_queue_key);
  2122. newbuf->q = q;
  2123. newbuf->aob = NULL;
  2124. newbuf->next_pending = q->bufs[bidx];
  2125. atomic_set(&newbuf->state, QETH_QDIO_BUF_EMPTY);
  2126. q->bufs[bidx] = newbuf;
  2127. if (q->bufstates) {
  2128. q->bufstates[bidx].user = newbuf;
  2129. QETH_CARD_TEXT_(q->card, 2, "nbs%d", bidx);
  2130. QETH_CARD_TEXT_(q->card, 2, "%lx", (long) newbuf);
  2131. QETH_CARD_TEXT_(q->card, 2, "%lx",
  2132. (long) newbuf->next_pending);
  2133. }
  2134. out:
  2135. return rc;
  2136. }
  2137. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  2138. {
  2139. int i, j;
  2140. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  2141. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  2142. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  2143. return 0;
  2144. card->qdio.in_q = kzalloc(sizeof(struct qeth_qdio_q),
  2145. GFP_KERNEL);
  2146. if (!card->qdio.in_q)
  2147. goto out_nomem;
  2148. QETH_DBF_TEXT(SETUP, 2, "inq");
  2149. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  2150. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  2151. /* give inbound qeth_qdio_buffers their qdio_buffers */
  2152. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  2153. card->qdio.in_q->bufs[i].buffer =
  2154. &card->qdio.in_q->qdio_bufs[i];
  2155. card->qdio.in_q->bufs[i].rx_skb = NULL;
  2156. }
  2157. /* inbound buffer pool */
  2158. if (qeth_alloc_buffer_pool(card))
  2159. goto out_freeinq;
  2160. /* outbound */
  2161. card->qdio.out_qs =
  2162. kzalloc(card->qdio.no_out_queues *
  2163. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  2164. if (!card->qdio.out_qs)
  2165. goto out_freepool;
  2166. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2167. card->qdio.out_qs[i] = kzalloc(sizeof(struct qeth_qdio_out_q),
  2168. GFP_KERNEL);
  2169. if (!card->qdio.out_qs[i])
  2170. goto out_freeoutq;
  2171. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  2172. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  2173. card->qdio.out_qs[i]->queue_no = i;
  2174. /* give outbound qeth_qdio_buffers their qdio_buffers */
  2175. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2176. WARN_ON(card->qdio.out_qs[i]->bufs[j] != NULL);
  2177. if (qeth_init_qdio_out_buf(card->qdio.out_qs[i], j))
  2178. goto out_freeoutqbufs;
  2179. }
  2180. }
  2181. /* completion */
  2182. if (qeth_alloc_cq(card))
  2183. goto out_freeoutq;
  2184. return 0;
  2185. out_freeoutqbufs:
  2186. while (j > 0) {
  2187. --j;
  2188. kmem_cache_free(qeth_qdio_outbuf_cache,
  2189. card->qdio.out_qs[i]->bufs[j]);
  2190. card->qdio.out_qs[i]->bufs[j] = NULL;
  2191. }
  2192. out_freeoutq:
  2193. while (i > 0) {
  2194. kfree(card->qdio.out_qs[--i]);
  2195. qeth_clear_outq_buffers(card->qdio.out_qs[i], 1);
  2196. }
  2197. kfree(card->qdio.out_qs);
  2198. card->qdio.out_qs = NULL;
  2199. out_freepool:
  2200. qeth_free_buffer_pool(card);
  2201. out_freeinq:
  2202. kfree(card->qdio.in_q);
  2203. card->qdio.in_q = NULL;
  2204. out_nomem:
  2205. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  2206. return -ENOMEM;
  2207. }
  2208. static void qeth_create_qib_param_field(struct qeth_card *card,
  2209. char *param_field)
  2210. {
  2211. param_field[0] = _ascebc['P'];
  2212. param_field[1] = _ascebc['C'];
  2213. param_field[2] = _ascebc['I'];
  2214. param_field[3] = _ascebc['T'];
  2215. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  2216. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  2217. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  2218. }
  2219. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  2220. char *param_field)
  2221. {
  2222. param_field[16] = _ascebc['B'];
  2223. param_field[17] = _ascebc['L'];
  2224. param_field[18] = _ascebc['K'];
  2225. param_field[19] = _ascebc['T'];
  2226. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  2227. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  2228. *((unsigned int *) (&param_field[28])) =
  2229. card->info.blkt.inter_packet_jumbo;
  2230. }
  2231. static int qeth_qdio_activate(struct qeth_card *card)
  2232. {
  2233. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  2234. return qdio_activate(CARD_DDEV(card));
  2235. }
  2236. static int qeth_dm_act(struct qeth_card *card)
  2237. {
  2238. int rc;
  2239. struct qeth_cmd_buffer *iob;
  2240. QETH_DBF_TEXT(SETUP, 2, "dmact");
  2241. iob = qeth_wait_for_buffer(&card->write);
  2242. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  2243. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  2244. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2245. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  2246. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2247. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  2248. return rc;
  2249. }
  2250. static int qeth_mpc_initialize(struct qeth_card *card)
  2251. {
  2252. int rc;
  2253. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  2254. rc = qeth_issue_next_read(card);
  2255. if (rc) {
  2256. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2257. return rc;
  2258. }
  2259. rc = qeth_cm_enable(card);
  2260. if (rc) {
  2261. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  2262. goto out_qdio;
  2263. }
  2264. rc = qeth_cm_setup(card);
  2265. if (rc) {
  2266. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  2267. goto out_qdio;
  2268. }
  2269. rc = qeth_ulp_enable(card);
  2270. if (rc) {
  2271. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  2272. goto out_qdio;
  2273. }
  2274. rc = qeth_ulp_setup(card);
  2275. if (rc) {
  2276. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  2277. goto out_qdio;
  2278. }
  2279. rc = qeth_alloc_qdio_buffers(card);
  2280. if (rc) {
  2281. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  2282. goto out_qdio;
  2283. }
  2284. rc = qeth_qdio_establish(card);
  2285. if (rc) {
  2286. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  2287. qeth_free_qdio_buffers(card);
  2288. goto out_qdio;
  2289. }
  2290. rc = qeth_qdio_activate(card);
  2291. if (rc) {
  2292. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  2293. goto out_qdio;
  2294. }
  2295. rc = qeth_dm_act(card);
  2296. if (rc) {
  2297. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  2298. goto out_qdio;
  2299. }
  2300. return 0;
  2301. out_qdio:
  2302. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  2303. return rc;
  2304. }
  2305. static void qeth_print_status_with_portname(struct qeth_card *card)
  2306. {
  2307. char dbf_text[15];
  2308. int i;
  2309. sprintf(dbf_text, "%s", card->info.portname + 1);
  2310. for (i = 0; i < 8; i++)
  2311. dbf_text[i] =
  2312. (char) _ebcasc[(__u8) dbf_text[i]];
  2313. dbf_text[8] = 0;
  2314. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  2315. "with link type %s (portname: %s)\n",
  2316. qeth_get_cardname(card),
  2317. (card->info.mcl_level[0]) ? " (level: " : "",
  2318. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2319. (card->info.mcl_level[0]) ? ")" : "",
  2320. qeth_get_cardname_short(card),
  2321. dbf_text);
  2322. }
  2323. static void qeth_print_status_no_portname(struct qeth_card *card)
  2324. {
  2325. if (card->info.portname[0])
  2326. dev_info(&card->gdev->dev, "Device is a%s "
  2327. "card%s%s%s\nwith link type %s "
  2328. "(no portname needed by interface).\n",
  2329. qeth_get_cardname(card),
  2330. (card->info.mcl_level[0]) ? " (level: " : "",
  2331. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2332. (card->info.mcl_level[0]) ? ")" : "",
  2333. qeth_get_cardname_short(card));
  2334. else
  2335. dev_info(&card->gdev->dev, "Device is a%s "
  2336. "card%s%s%s\nwith link type %s.\n",
  2337. qeth_get_cardname(card),
  2338. (card->info.mcl_level[0]) ? " (level: " : "",
  2339. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2340. (card->info.mcl_level[0]) ? ")" : "",
  2341. qeth_get_cardname_short(card));
  2342. }
  2343. void qeth_print_status_message(struct qeth_card *card)
  2344. {
  2345. switch (card->info.type) {
  2346. case QETH_CARD_TYPE_OSD:
  2347. case QETH_CARD_TYPE_OSM:
  2348. case QETH_CARD_TYPE_OSX:
  2349. /* VM will use a non-zero first character
  2350. * to indicate a HiperSockets like reporting
  2351. * of the level OSA sets the first character to zero
  2352. * */
  2353. if (!card->info.mcl_level[0]) {
  2354. sprintf(card->info.mcl_level, "%02x%02x",
  2355. card->info.mcl_level[2],
  2356. card->info.mcl_level[3]);
  2357. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2358. break;
  2359. }
  2360. /* fallthrough */
  2361. case QETH_CARD_TYPE_IQD:
  2362. if ((card->info.guestlan) ||
  2363. (card->info.mcl_level[0] & 0x80)) {
  2364. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2365. card->info.mcl_level[0]];
  2366. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2367. card->info.mcl_level[1]];
  2368. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2369. card->info.mcl_level[2]];
  2370. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2371. card->info.mcl_level[3]];
  2372. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2373. }
  2374. break;
  2375. default:
  2376. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2377. }
  2378. if (card->info.portname_required)
  2379. qeth_print_status_with_portname(card);
  2380. else
  2381. qeth_print_status_no_portname(card);
  2382. }
  2383. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2384. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2385. {
  2386. struct qeth_buffer_pool_entry *entry;
  2387. QETH_CARD_TEXT(card, 5, "inwrklst");
  2388. list_for_each_entry(entry,
  2389. &card->qdio.init_pool.entry_list, init_list) {
  2390. qeth_put_buffer_pool_entry(card, entry);
  2391. }
  2392. }
  2393. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2394. struct qeth_card *card)
  2395. {
  2396. struct list_head *plh;
  2397. struct qeth_buffer_pool_entry *entry;
  2398. int i, free;
  2399. struct page *page;
  2400. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2401. return NULL;
  2402. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2403. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2404. free = 1;
  2405. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2406. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2407. free = 0;
  2408. break;
  2409. }
  2410. }
  2411. if (free) {
  2412. list_del_init(&entry->list);
  2413. return entry;
  2414. }
  2415. }
  2416. /* no free buffer in pool so take first one and swap pages */
  2417. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2418. struct qeth_buffer_pool_entry, list);
  2419. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2420. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2421. page = alloc_page(GFP_ATOMIC);
  2422. if (!page) {
  2423. return NULL;
  2424. } else {
  2425. free_page((unsigned long)entry->elements[i]);
  2426. entry->elements[i] = page_address(page);
  2427. if (card->options.performance_stats)
  2428. card->perf_stats.sg_alloc_page_rx++;
  2429. }
  2430. }
  2431. }
  2432. list_del_init(&entry->list);
  2433. return entry;
  2434. }
  2435. static int qeth_init_input_buffer(struct qeth_card *card,
  2436. struct qeth_qdio_buffer *buf)
  2437. {
  2438. struct qeth_buffer_pool_entry *pool_entry;
  2439. int i;
  2440. if ((card->options.cq == QETH_CQ_ENABLED) && (!buf->rx_skb)) {
  2441. buf->rx_skb = dev_alloc_skb(QETH_RX_PULL_LEN + ETH_HLEN);
  2442. if (!buf->rx_skb)
  2443. return 1;
  2444. }
  2445. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2446. if (!pool_entry)
  2447. return 1;
  2448. /*
  2449. * since the buffer is accessed only from the input_tasklet
  2450. * there shouldn't be a need to synchronize; also, since we use
  2451. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2452. * buffers
  2453. */
  2454. buf->pool_entry = pool_entry;
  2455. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2456. buf->buffer->element[i].length = PAGE_SIZE;
  2457. buf->buffer->element[i].addr = pool_entry->elements[i];
  2458. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2459. buf->buffer->element[i].eflags = SBAL_EFLAGS_LAST_ENTRY;
  2460. else
  2461. buf->buffer->element[i].eflags = 0;
  2462. buf->buffer->element[i].sflags = 0;
  2463. }
  2464. return 0;
  2465. }
  2466. int qeth_init_qdio_queues(struct qeth_card *card)
  2467. {
  2468. int i, j;
  2469. int rc;
  2470. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2471. /* inbound queue */
  2472. memset(card->qdio.in_q->qdio_bufs, 0,
  2473. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2474. qeth_initialize_working_pool_list(card);
  2475. /*give only as many buffers to hardware as we have buffer pool entries*/
  2476. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2477. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2478. card->qdio.in_q->next_buf_to_init =
  2479. card->qdio.in_buf_pool.buf_count - 1;
  2480. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2481. card->qdio.in_buf_pool.buf_count - 1);
  2482. if (rc) {
  2483. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2484. return rc;
  2485. }
  2486. /* completion */
  2487. rc = qeth_cq_init(card);
  2488. if (rc) {
  2489. return rc;
  2490. }
  2491. /* outbound queue */
  2492. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2493. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2494. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2495. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2496. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2497. card->qdio.out_qs[i]->bufs[j],
  2498. QETH_QDIO_BUF_EMPTY);
  2499. }
  2500. card->qdio.out_qs[i]->card = card;
  2501. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2502. card->qdio.out_qs[i]->do_pack = 0;
  2503. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2504. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2505. atomic_set(&card->qdio.out_qs[i]->state,
  2506. QETH_OUT_Q_UNLOCKED);
  2507. }
  2508. return 0;
  2509. }
  2510. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2511. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2512. {
  2513. switch (link_type) {
  2514. case QETH_LINK_TYPE_HSTR:
  2515. return 2;
  2516. default:
  2517. return 1;
  2518. }
  2519. }
  2520. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2521. struct qeth_ipa_cmd *cmd, __u8 command,
  2522. enum qeth_prot_versions prot)
  2523. {
  2524. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2525. cmd->hdr.command = command;
  2526. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2527. cmd->hdr.seqno = card->seqno.ipa;
  2528. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2529. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2530. if (card->options.layer2)
  2531. cmd->hdr.prim_version_no = 2;
  2532. else
  2533. cmd->hdr.prim_version_no = 1;
  2534. cmd->hdr.param_count = 1;
  2535. cmd->hdr.prot_version = prot;
  2536. cmd->hdr.ipa_supported = 0;
  2537. cmd->hdr.ipa_enabled = 0;
  2538. }
  2539. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2540. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2541. {
  2542. struct qeth_cmd_buffer *iob;
  2543. struct qeth_ipa_cmd *cmd;
  2544. iob = qeth_wait_for_buffer(&card->write);
  2545. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2546. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2547. return iob;
  2548. }
  2549. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2550. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2551. char prot_type)
  2552. {
  2553. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2554. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2555. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2556. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2557. }
  2558. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2559. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2560. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2561. unsigned long),
  2562. void *reply_param)
  2563. {
  2564. int rc;
  2565. char prot_type;
  2566. QETH_CARD_TEXT(card, 4, "sendipa");
  2567. if (card->options.layer2)
  2568. if (card->info.type == QETH_CARD_TYPE_OSN)
  2569. prot_type = QETH_PROT_OSN2;
  2570. else
  2571. prot_type = QETH_PROT_LAYER2;
  2572. else
  2573. prot_type = QETH_PROT_TCPIP;
  2574. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2575. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2576. iob, reply_cb, reply_param);
  2577. if (rc == -ETIME) {
  2578. qeth_clear_ipacmd_list(card);
  2579. qeth_schedule_recovery(card);
  2580. }
  2581. return rc;
  2582. }
  2583. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2584. int qeth_send_startlan(struct qeth_card *card)
  2585. {
  2586. int rc;
  2587. struct qeth_cmd_buffer *iob;
  2588. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2589. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_STARTLAN, 0);
  2590. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2591. return rc;
  2592. }
  2593. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2594. static int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2595. struct qeth_reply *reply, unsigned long data)
  2596. {
  2597. struct qeth_ipa_cmd *cmd;
  2598. QETH_CARD_TEXT(card, 4, "defadpcb");
  2599. cmd = (struct qeth_ipa_cmd *) data;
  2600. if (cmd->hdr.return_code == 0)
  2601. cmd->hdr.return_code =
  2602. cmd->data.setadapterparms.hdr.return_code;
  2603. return 0;
  2604. }
  2605. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2606. struct qeth_reply *reply, unsigned long data)
  2607. {
  2608. struct qeth_ipa_cmd *cmd;
  2609. QETH_CARD_TEXT(card, 3, "quyadpcb");
  2610. cmd = (struct qeth_ipa_cmd *) data;
  2611. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
  2612. card->info.link_type =
  2613. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2614. QETH_DBF_TEXT_(SETUP, 2, "lnk %d", card->info.link_type);
  2615. }
  2616. card->options.adp.supported_funcs =
  2617. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2618. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2619. }
  2620. static struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2621. __u32 command, __u32 cmdlen)
  2622. {
  2623. struct qeth_cmd_buffer *iob;
  2624. struct qeth_ipa_cmd *cmd;
  2625. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2626. QETH_PROT_IPV4);
  2627. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2628. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2629. cmd->data.setadapterparms.hdr.command_code = command;
  2630. cmd->data.setadapterparms.hdr.used_total = 1;
  2631. cmd->data.setadapterparms.hdr.seq_no = 1;
  2632. return iob;
  2633. }
  2634. int qeth_query_setadapterparms(struct qeth_card *card)
  2635. {
  2636. int rc;
  2637. struct qeth_cmd_buffer *iob;
  2638. QETH_CARD_TEXT(card, 3, "queryadp");
  2639. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2640. sizeof(struct qeth_ipacmd_setadpparms));
  2641. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2642. return rc;
  2643. }
  2644. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2645. static int qeth_query_ipassists_cb(struct qeth_card *card,
  2646. struct qeth_reply *reply, unsigned long data)
  2647. {
  2648. struct qeth_ipa_cmd *cmd;
  2649. QETH_DBF_TEXT(SETUP, 2, "qipasscb");
  2650. cmd = (struct qeth_ipa_cmd *) data;
  2651. switch (cmd->hdr.return_code) {
  2652. case IPA_RC_NOTSUPP:
  2653. case IPA_RC_L2_UNSUPPORTED_CMD:
  2654. QETH_DBF_TEXT(SETUP, 2, "ipaunsup");
  2655. card->options.ipa4.supported_funcs |= IPA_SETADAPTERPARMS;
  2656. card->options.ipa6.supported_funcs |= IPA_SETADAPTERPARMS;
  2657. return -0;
  2658. default:
  2659. if (cmd->hdr.return_code) {
  2660. QETH_DBF_MESSAGE(1, "%s IPA_CMD_QIPASSIST: Unhandled "
  2661. "rc=%d\n",
  2662. dev_name(&card->gdev->dev),
  2663. cmd->hdr.return_code);
  2664. return 0;
  2665. }
  2666. }
  2667. if (cmd->hdr.prot_version == QETH_PROT_IPV4) {
  2668. card->options.ipa4.supported_funcs = cmd->hdr.ipa_supported;
  2669. card->options.ipa4.enabled_funcs = cmd->hdr.ipa_enabled;
  2670. } else if (cmd->hdr.prot_version == QETH_PROT_IPV6) {
  2671. card->options.ipa6.supported_funcs = cmd->hdr.ipa_supported;
  2672. card->options.ipa6.enabled_funcs = cmd->hdr.ipa_enabled;
  2673. } else
  2674. QETH_DBF_MESSAGE(1, "%s IPA_CMD_QIPASSIST: Flawed LIC detected"
  2675. "\n", dev_name(&card->gdev->dev));
  2676. return 0;
  2677. }
  2678. int qeth_query_ipassists(struct qeth_card *card, enum qeth_prot_versions prot)
  2679. {
  2680. int rc;
  2681. struct qeth_cmd_buffer *iob;
  2682. QETH_DBF_TEXT_(SETUP, 2, "qipassi%i", prot);
  2683. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_QIPASSIST, prot);
  2684. rc = qeth_send_ipa_cmd(card, iob, qeth_query_ipassists_cb, NULL);
  2685. return rc;
  2686. }
  2687. EXPORT_SYMBOL_GPL(qeth_query_ipassists);
  2688. static int qeth_query_setdiagass_cb(struct qeth_card *card,
  2689. struct qeth_reply *reply, unsigned long data)
  2690. {
  2691. struct qeth_ipa_cmd *cmd;
  2692. __u16 rc;
  2693. cmd = (struct qeth_ipa_cmd *)data;
  2694. rc = cmd->hdr.return_code;
  2695. if (rc)
  2696. QETH_CARD_TEXT_(card, 2, "diagq:%x", rc);
  2697. else
  2698. card->info.diagass_support = cmd->data.diagass.ext;
  2699. return 0;
  2700. }
  2701. static int qeth_query_setdiagass(struct qeth_card *card)
  2702. {
  2703. struct qeth_cmd_buffer *iob;
  2704. struct qeth_ipa_cmd *cmd;
  2705. QETH_DBF_TEXT(SETUP, 2, "qdiagass");
  2706. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2707. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2708. cmd->data.diagass.subcmd_len = 16;
  2709. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_QUERY;
  2710. return qeth_send_ipa_cmd(card, iob, qeth_query_setdiagass_cb, NULL);
  2711. }
  2712. static void qeth_get_trap_id(struct qeth_card *card, struct qeth_trap_id *tid)
  2713. {
  2714. unsigned long info = get_zeroed_page(GFP_KERNEL);
  2715. struct sysinfo_2_2_2 *info222 = (struct sysinfo_2_2_2 *)info;
  2716. struct sysinfo_3_2_2 *info322 = (struct sysinfo_3_2_2 *)info;
  2717. struct ccw_dev_id ccwid;
  2718. int level;
  2719. tid->chpid = card->info.chpid;
  2720. ccw_device_get_id(CARD_RDEV(card), &ccwid);
  2721. tid->ssid = ccwid.ssid;
  2722. tid->devno = ccwid.devno;
  2723. if (!info)
  2724. return;
  2725. level = stsi(NULL, 0, 0, 0);
  2726. if ((level >= 2) && (stsi(info222, 2, 2, 2) == 0))
  2727. tid->lparnr = info222->lpar_number;
  2728. if ((level >= 3) && (stsi(info322, 3, 2, 2) == 0)) {
  2729. EBCASC(info322->vm[0].name, sizeof(info322->vm[0].name));
  2730. memcpy(tid->vmname, info322->vm[0].name, sizeof(tid->vmname));
  2731. }
  2732. free_page(info);
  2733. return;
  2734. }
  2735. static int qeth_hw_trap_cb(struct qeth_card *card,
  2736. struct qeth_reply *reply, unsigned long data)
  2737. {
  2738. struct qeth_ipa_cmd *cmd;
  2739. __u16 rc;
  2740. cmd = (struct qeth_ipa_cmd *)data;
  2741. rc = cmd->hdr.return_code;
  2742. if (rc)
  2743. QETH_CARD_TEXT_(card, 2, "trapc:%x", rc);
  2744. return 0;
  2745. }
  2746. int qeth_hw_trap(struct qeth_card *card, enum qeth_diags_trap_action action)
  2747. {
  2748. struct qeth_cmd_buffer *iob;
  2749. struct qeth_ipa_cmd *cmd;
  2750. QETH_DBF_TEXT(SETUP, 2, "diagtrap");
  2751. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2752. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2753. cmd->data.diagass.subcmd_len = 80;
  2754. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_TRAP;
  2755. cmd->data.diagass.type = 1;
  2756. cmd->data.diagass.action = action;
  2757. switch (action) {
  2758. case QETH_DIAGS_TRAP_ARM:
  2759. cmd->data.diagass.options = 0x0003;
  2760. cmd->data.diagass.ext = 0x00010000 +
  2761. sizeof(struct qeth_trap_id);
  2762. qeth_get_trap_id(card,
  2763. (struct qeth_trap_id *)cmd->data.diagass.cdata);
  2764. break;
  2765. case QETH_DIAGS_TRAP_DISARM:
  2766. cmd->data.diagass.options = 0x0001;
  2767. break;
  2768. case QETH_DIAGS_TRAP_CAPTURE:
  2769. break;
  2770. }
  2771. return qeth_send_ipa_cmd(card, iob, qeth_hw_trap_cb, NULL);
  2772. }
  2773. EXPORT_SYMBOL_GPL(qeth_hw_trap);
  2774. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2775. unsigned int qdio_error, const char *dbftext)
  2776. {
  2777. if (qdio_error) {
  2778. QETH_CARD_TEXT(card, 2, dbftext);
  2779. QETH_CARD_TEXT_(card, 2, " F15=%02X",
  2780. buf->element[15].sflags);
  2781. QETH_CARD_TEXT_(card, 2, " F14=%02X",
  2782. buf->element[14].sflags);
  2783. QETH_CARD_TEXT_(card, 2, " qerr=%X", qdio_error);
  2784. if ((buf->element[15].sflags) == 0x12) {
  2785. card->stats.rx_dropped++;
  2786. return 0;
  2787. } else
  2788. return 1;
  2789. }
  2790. return 0;
  2791. }
  2792. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2793. void qeth_buffer_reclaim_work(struct work_struct *work)
  2794. {
  2795. struct qeth_card *card = container_of(work, struct qeth_card,
  2796. buffer_reclaim_work.work);
  2797. QETH_CARD_TEXT_(card, 2, "brw:%x", card->reclaim_index);
  2798. qeth_queue_input_buffer(card, card->reclaim_index);
  2799. }
  2800. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2801. {
  2802. struct qeth_qdio_q *queue = card->qdio.in_q;
  2803. struct list_head *lh;
  2804. int count;
  2805. int i;
  2806. int rc;
  2807. int newcount = 0;
  2808. count = (index < queue->next_buf_to_init)?
  2809. card->qdio.in_buf_pool.buf_count -
  2810. (queue->next_buf_to_init - index) :
  2811. card->qdio.in_buf_pool.buf_count -
  2812. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2813. /* only requeue at a certain threshold to avoid SIGAs */
  2814. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2815. for (i = queue->next_buf_to_init;
  2816. i < queue->next_buf_to_init + count; ++i) {
  2817. if (qeth_init_input_buffer(card,
  2818. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2819. break;
  2820. } else {
  2821. newcount++;
  2822. }
  2823. }
  2824. if (newcount < count) {
  2825. /* we are in memory shortage so we switch back to
  2826. traditional skb allocation and drop packages */
  2827. atomic_set(&card->force_alloc_skb, 3);
  2828. count = newcount;
  2829. } else {
  2830. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2831. }
  2832. if (!count) {
  2833. i = 0;
  2834. list_for_each(lh, &card->qdio.in_buf_pool.entry_list)
  2835. i++;
  2836. if (i == card->qdio.in_buf_pool.buf_count) {
  2837. QETH_CARD_TEXT(card, 2, "qsarbw");
  2838. card->reclaim_index = index;
  2839. schedule_delayed_work(
  2840. &card->buffer_reclaim_work,
  2841. QETH_RECLAIM_WORK_TIME);
  2842. }
  2843. return;
  2844. }
  2845. /*
  2846. * according to old code it should be avoided to requeue all
  2847. * 128 buffers in order to benefit from PCI avoidance.
  2848. * this function keeps at least one buffer (the buffer at
  2849. * 'index') un-requeued -> this buffer is the first buffer that
  2850. * will be requeued the next time
  2851. */
  2852. if (card->options.performance_stats) {
  2853. card->perf_stats.inbound_do_qdio_cnt++;
  2854. card->perf_stats.inbound_do_qdio_start_time =
  2855. qeth_get_micros();
  2856. }
  2857. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2858. queue->next_buf_to_init, count);
  2859. if (card->options.performance_stats)
  2860. card->perf_stats.inbound_do_qdio_time +=
  2861. qeth_get_micros() -
  2862. card->perf_stats.inbound_do_qdio_start_time;
  2863. if (rc) {
  2864. QETH_CARD_TEXT(card, 2, "qinberr");
  2865. }
  2866. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2867. QDIO_MAX_BUFFERS_PER_Q;
  2868. }
  2869. }
  2870. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2871. static int qeth_handle_send_error(struct qeth_card *card,
  2872. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2873. {
  2874. int sbalf15 = buffer->buffer->element[15].sflags;
  2875. QETH_CARD_TEXT(card, 6, "hdsnderr");
  2876. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2877. if (sbalf15 == 0) {
  2878. qdio_err = 0;
  2879. } else {
  2880. qdio_err = 1;
  2881. }
  2882. }
  2883. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2884. if (!qdio_err)
  2885. return QETH_SEND_ERROR_NONE;
  2886. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2887. return QETH_SEND_ERROR_RETRY;
  2888. QETH_CARD_TEXT(card, 1, "lnkfail");
  2889. QETH_CARD_TEXT_(card, 1, "%04x %02x",
  2890. (u16)qdio_err, (u8)sbalf15);
  2891. return QETH_SEND_ERROR_LINK_FAILURE;
  2892. }
  2893. /*
  2894. * Switched to packing state if the number of used buffers on a queue
  2895. * reaches a certain limit.
  2896. */
  2897. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2898. {
  2899. if (!queue->do_pack) {
  2900. if (atomic_read(&queue->used_buffers)
  2901. >= QETH_HIGH_WATERMARK_PACK){
  2902. /* switch non-PACKING -> PACKING */
  2903. QETH_CARD_TEXT(queue->card, 6, "np->pack");
  2904. if (queue->card->options.performance_stats)
  2905. queue->card->perf_stats.sc_dp_p++;
  2906. queue->do_pack = 1;
  2907. }
  2908. }
  2909. }
  2910. /*
  2911. * Switches from packing to non-packing mode. If there is a packing
  2912. * buffer on the queue this buffer will be prepared to be flushed.
  2913. * In that case 1 is returned to inform the caller. If no buffer
  2914. * has to be flushed, zero is returned.
  2915. */
  2916. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2917. {
  2918. struct qeth_qdio_out_buffer *buffer;
  2919. int flush_count = 0;
  2920. if (queue->do_pack) {
  2921. if (atomic_read(&queue->used_buffers)
  2922. <= QETH_LOW_WATERMARK_PACK) {
  2923. /* switch PACKING -> non-PACKING */
  2924. QETH_CARD_TEXT(queue->card, 6, "pack->np");
  2925. if (queue->card->options.performance_stats)
  2926. queue->card->perf_stats.sc_p_dp++;
  2927. queue->do_pack = 0;
  2928. /* flush packing buffers */
  2929. buffer = queue->bufs[queue->next_buf_to_fill];
  2930. if ((atomic_read(&buffer->state) ==
  2931. QETH_QDIO_BUF_EMPTY) &&
  2932. (buffer->next_element_to_fill > 0)) {
  2933. atomic_set(&buffer->state,
  2934. QETH_QDIO_BUF_PRIMED);
  2935. flush_count++;
  2936. queue->next_buf_to_fill =
  2937. (queue->next_buf_to_fill + 1) %
  2938. QDIO_MAX_BUFFERS_PER_Q;
  2939. }
  2940. }
  2941. }
  2942. return flush_count;
  2943. }
  2944. /*
  2945. * Called to flush a packing buffer if no more pci flags are on the queue.
  2946. * Checks if there is a packing buffer and prepares it to be flushed.
  2947. * In that case returns 1, otherwise zero.
  2948. */
  2949. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2950. {
  2951. struct qeth_qdio_out_buffer *buffer;
  2952. buffer = queue->bufs[queue->next_buf_to_fill];
  2953. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2954. (buffer->next_element_to_fill > 0)) {
  2955. /* it's a packing buffer */
  2956. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2957. queue->next_buf_to_fill =
  2958. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2959. return 1;
  2960. }
  2961. return 0;
  2962. }
  2963. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2964. int count)
  2965. {
  2966. struct qeth_qdio_out_buffer *buf;
  2967. int rc;
  2968. int i;
  2969. unsigned int qdio_flags;
  2970. for (i = index; i < index + count; ++i) {
  2971. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  2972. buf = queue->bufs[bidx];
  2973. buf->buffer->element[buf->next_element_to_fill - 1].eflags |=
  2974. SBAL_EFLAGS_LAST_ENTRY;
  2975. if (queue->bufstates)
  2976. queue->bufstates[bidx].user = buf;
  2977. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2978. continue;
  2979. if (!queue->do_pack) {
  2980. if ((atomic_read(&queue->used_buffers) >=
  2981. (QETH_HIGH_WATERMARK_PACK -
  2982. QETH_WATERMARK_PACK_FUZZ)) &&
  2983. !atomic_read(&queue->set_pci_flags_count)) {
  2984. /* it's likely that we'll go to packing
  2985. * mode soon */
  2986. atomic_inc(&queue->set_pci_flags_count);
  2987. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  2988. }
  2989. } else {
  2990. if (!atomic_read(&queue->set_pci_flags_count)) {
  2991. /*
  2992. * there's no outstanding PCI any more, so we
  2993. * have to request a PCI to be sure the the PCI
  2994. * will wake at some time in the future then we
  2995. * can flush packed buffers that might still be
  2996. * hanging around, which can happen if no
  2997. * further send was requested by the stack
  2998. */
  2999. atomic_inc(&queue->set_pci_flags_count);
  3000. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  3001. }
  3002. }
  3003. }
  3004. queue->card->dev->trans_start = jiffies;
  3005. if (queue->card->options.performance_stats) {
  3006. queue->card->perf_stats.outbound_do_qdio_cnt++;
  3007. queue->card->perf_stats.outbound_do_qdio_start_time =
  3008. qeth_get_micros();
  3009. }
  3010. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  3011. if (atomic_read(&queue->set_pci_flags_count))
  3012. qdio_flags |= QDIO_FLAG_PCI_OUT;
  3013. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  3014. queue->queue_no, index, count);
  3015. if (queue->card->options.performance_stats)
  3016. queue->card->perf_stats.outbound_do_qdio_time +=
  3017. qeth_get_micros() -
  3018. queue->card->perf_stats.outbound_do_qdio_start_time;
  3019. atomic_add(count, &queue->used_buffers);
  3020. if (rc) {
  3021. queue->card->stats.tx_errors += count;
  3022. /* ignore temporary SIGA errors without busy condition */
  3023. if (rc == -ENOBUFS)
  3024. return;
  3025. QETH_CARD_TEXT(queue->card, 2, "flushbuf");
  3026. QETH_CARD_TEXT_(queue->card, 2, " q%d", queue->queue_no);
  3027. QETH_CARD_TEXT_(queue->card, 2, " idx%d", index);
  3028. QETH_CARD_TEXT_(queue->card, 2, " c%d", count);
  3029. QETH_CARD_TEXT_(queue->card, 2, " err%d", rc);
  3030. /* this must not happen under normal circumstances. if it
  3031. * happens something is really wrong -> recover */
  3032. qeth_schedule_recovery(queue->card);
  3033. return;
  3034. }
  3035. if (queue->card->options.performance_stats)
  3036. queue->card->perf_stats.bufs_sent += count;
  3037. }
  3038. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  3039. {
  3040. int index;
  3041. int flush_cnt = 0;
  3042. int q_was_packing = 0;
  3043. /*
  3044. * check if weed have to switch to non-packing mode or if
  3045. * we have to get a pci flag out on the queue
  3046. */
  3047. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  3048. !atomic_read(&queue->set_pci_flags_count)) {
  3049. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  3050. QETH_OUT_Q_UNLOCKED) {
  3051. /*
  3052. * If we get in here, there was no action in
  3053. * do_send_packet. So, we check if there is a
  3054. * packing buffer to be flushed here.
  3055. */
  3056. netif_stop_queue(queue->card->dev);
  3057. index = queue->next_buf_to_fill;
  3058. q_was_packing = queue->do_pack;
  3059. /* queue->do_pack may change */
  3060. barrier();
  3061. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  3062. if (!flush_cnt &&
  3063. !atomic_read(&queue->set_pci_flags_count))
  3064. flush_cnt +=
  3065. qeth_flush_buffers_on_no_pci(queue);
  3066. if (queue->card->options.performance_stats &&
  3067. q_was_packing)
  3068. queue->card->perf_stats.bufs_sent_pack +=
  3069. flush_cnt;
  3070. if (flush_cnt)
  3071. qeth_flush_buffers(queue, index, flush_cnt);
  3072. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3073. }
  3074. }
  3075. }
  3076. void qeth_qdio_start_poll(struct ccw_device *ccwdev, int queue,
  3077. unsigned long card_ptr)
  3078. {
  3079. struct qeth_card *card = (struct qeth_card *)card_ptr;
  3080. if (card->dev && (card->dev->flags & IFF_UP))
  3081. napi_schedule(&card->napi);
  3082. }
  3083. EXPORT_SYMBOL_GPL(qeth_qdio_start_poll);
  3084. int qeth_configure_cq(struct qeth_card *card, enum qeth_cq cq)
  3085. {
  3086. int rc;
  3087. if (card->options.cq == QETH_CQ_NOTAVAILABLE) {
  3088. rc = -1;
  3089. goto out;
  3090. } else {
  3091. if (card->options.cq == cq) {
  3092. rc = 0;
  3093. goto out;
  3094. }
  3095. if (card->state != CARD_STATE_DOWN &&
  3096. card->state != CARD_STATE_RECOVER) {
  3097. rc = -1;
  3098. goto out;
  3099. }
  3100. qeth_free_qdio_buffers(card);
  3101. card->options.cq = cq;
  3102. rc = 0;
  3103. }
  3104. out:
  3105. return rc;
  3106. }
  3107. EXPORT_SYMBOL_GPL(qeth_configure_cq);
  3108. static void qeth_qdio_cq_handler(struct qeth_card *card,
  3109. unsigned int qdio_err,
  3110. unsigned int queue, int first_element, int count) {
  3111. struct qeth_qdio_q *cq = card->qdio.c_q;
  3112. int i;
  3113. int rc;
  3114. if (!qeth_is_cq(card, queue))
  3115. goto out;
  3116. QETH_CARD_TEXT_(card, 5, "qcqhe%d", first_element);
  3117. QETH_CARD_TEXT_(card, 5, "qcqhc%d", count);
  3118. QETH_CARD_TEXT_(card, 5, "qcqherr%d", qdio_err);
  3119. if (qdio_err) {
  3120. netif_stop_queue(card->dev);
  3121. qeth_schedule_recovery(card);
  3122. goto out;
  3123. }
  3124. if (card->options.performance_stats) {
  3125. card->perf_stats.cq_cnt++;
  3126. card->perf_stats.cq_start_time = qeth_get_micros();
  3127. }
  3128. for (i = first_element; i < first_element + count; ++i) {
  3129. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3130. struct qdio_buffer *buffer = &cq->qdio_bufs[bidx];
  3131. int e;
  3132. e = 0;
  3133. while (buffer->element[e].addr) {
  3134. unsigned long phys_aob_addr;
  3135. phys_aob_addr = (unsigned long) buffer->element[e].addr;
  3136. qeth_qdio_handle_aob(card, phys_aob_addr);
  3137. buffer->element[e].addr = NULL;
  3138. buffer->element[e].eflags = 0;
  3139. buffer->element[e].sflags = 0;
  3140. buffer->element[e].length = 0;
  3141. ++e;
  3142. }
  3143. buffer->element[15].eflags = 0;
  3144. buffer->element[15].sflags = 0;
  3145. }
  3146. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, queue,
  3147. card->qdio.c_q->next_buf_to_init,
  3148. count);
  3149. if (rc) {
  3150. dev_warn(&card->gdev->dev,
  3151. "QDIO reported an error, rc=%i\n", rc);
  3152. QETH_CARD_TEXT(card, 2, "qcqherr");
  3153. }
  3154. card->qdio.c_q->next_buf_to_init = (card->qdio.c_q->next_buf_to_init
  3155. + count) % QDIO_MAX_BUFFERS_PER_Q;
  3156. netif_wake_queue(card->dev);
  3157. if (card->options.performance_stats) {
  3158. int delta_t = qeth_get_micros();
  3159. delta_t -= card->perf_stats.cq_start_time;
  3160. card->perf_stats.cq_time += delta_t;
  3161. }
  3162. out:
  3163. return;
  3164. }
  3165. void qeth_qdio_input_handler(struct ccw_device *ccwdev, unsigned int qdio_err,
  3166. unsigned int queue, int first_elem, int count,
  3167. unsigned long card_ptr)
  3168. {
  3169. struct qeth_card *card = (struct qeth_card *)card_ptr;
  3170. QETH_CARD_TEXT_(card, 2, "qihq%d", queue);
  3171. QETH_CARD_TEXT_(card, 2, "qiec%d", qdio_err);
  3172. if (qeth_is_cq(card, queue))
  3173. qeth_qdio_cq_handler(card, qdio_err, queue, first_elem, count);
  3174. else if (qdio_err)
  3175. qeth_schedule_recovery(card);
  3176. }
  3177. EXPORT_SYMBOL_GPL(qeth_qdio_input_handler);
  3178. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  3179. unsigned int qdio_error, int __queue, int first_element,
  3180. int count, unsigned long card_ptr)
  3181. {
  3182. struct qeth_card *card = (struct qeth_card *) card_ptr;
  3183. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  3184. struct qeth_qdio_out_buffer *buffer;
  3185. int i;
  3186. QETH_CARD_TEXT(card, 6, "qdouhdl");
  3187. if (qdio_error & QDIO_ERROR_FATAL) {
  3188. QETH_CARD_TEXT(card, 2, "achkcond");
  3189. netif_stop_queue(card->dev);
  3190. qeth_schedule_recovery(card);
  3191. return;
  3192. }
  3193. if (card->options.performance_stats) {
  3194. card->perf_stats.outbound_handler_cnt++;
  3195. card->perf_stats.outbound_handler_start_time =
  3196. qeth_get_micros();
  3197. }
  3198. for (i = first_element; i < (first_element + count); ++i) {
  3199. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3200. buffer = queue->bufs[bidx];
  3201. qeth_handle_send_error(card, buffer, qdio_error);
  3202. if (queue->bufstates &&
  3203. (queue->bufstates[bidx].flags &
  3204. QDIO_OUTBUF_STATE_FLAG_PENDING) != 0) {
  3205. WARN_ON_ONCE(card->options.cq != QETH_CQ_ENABLED);
  3206. if (atomic_cmpxchg(&buffer->state,
  3207. QETH_QDIO_BUF_PRIMED,
  3208. QETH_QDIO_BUF_PENDING) ==
  3209. QETH_QDIO_BUF_PRIMED) {
  3210. qeth_notify_skbs(queue, buffer,
  3211. TX_NOTIFY_PENDING);
  3212. }
  3213. buffer->aob = queue->bufstates[bidx].aob;
  3214. QETH_CARD_TEXT_(queue->card, 5, "pel%d", bidx);
  3215. QETH_CARD_TEXT(queue->card, 5, "aob");
  3216. QETH_CARD_TEXT_(queue->card, 5, "%lx",
  3217. virt_to_phys(buffer->aob));
  3218. if (qeth_init_qdio_out_buf(queue, bidx)) {
  3219. QETH_CARD_TEXT(card, 2, "outofbuf");
  3220. qeth_schedule_recovery(card);
  3221. }
  3222. } else {
  3223. if (card->options.cq == QETH_CQ_ENABLED) {
  3224. enum iucv_tx_notify n;
  3225. n = qeth_compute_cq_notification(
  3226. buffer->buffer->element[15].sflags, 0);
  3227. qeth_notify_skbs(queue, buffer, n);
  3228. }
  3229. qeth_clear_output_buffer(queue, buffer,
  3230. QETH_QDIO_BUF_EMPTY);
  3231. }
  3232. qeth_cleanup_handled_pending(queue, bidx, 0);
  3233. }
  3234. atomic_sub(count, &queue->used_buffers);
  3235. /* check if we need to do something on this outbound queue */
  3236. if (card->info.type != QETH_CARD_TYPE_IQD)
  3237. qeth_check_outbound_queue(queue);
  3238. netif_wake_queue(queue->card->dev);
  3239. if (card->options.performance_stats)
  3240. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  3241. card->perf_stats.outbound_handler_start_time;
  3242. }
  3243. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  3244. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  3245. int ipv, int cast_type)
  3246. {
  3247. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSD ||
  3248. card->info.type == QETH_CARD_TYPE_OSX))
  3249. return card->qdio.default_out_queue;
  3250. switch (card->qdio.no_out_queues) {
  3251. case 4:
  3252. if (cast_type && card->info.is_multicast_different)
  3253. return card->info.is_multicast_different &
  3254. (card->qdio.no_out_queues - 1);
  3255. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  3256. const u8 tos = ip_hdr(skb)->tos;
  3257. if (card->qdio.do_prio_queueing ==
  3258. QETH_PRIO_Q_ING_TOS) {
  3259. if (tos & IP_TOS_NOTIMPORTANT)
  3260. return 3;
  3261. if (tos & IP_TOS_HIGHRELIABILITY)
  3262. return 2;
  3263. if (tos & IP_TOS_HIGHTHROUGHPUT)
  3264. return 1;
  3265. if (tos & IP_TOS_LOWDELAY)
  3266. return 0;
  3267. }
  3268. if (card->qdio.do_prio_queueing ==
  3269. QETH_PRIO_Q_ING_PREC)
  3270. return 3 - (tos >> 6);
  3271. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  3272. /* TODO: IPv6!!! */
  3273. }
  3274. return card->qdio.default_out_queue;
  3275. case 1: /* fallthrough for single-out-queue 1920-device */
  3276. default:
  3277. return card->qdio.default_out_queue;
  3278. }
  3279. }
  3280. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  3281. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  3282. struct sk_buff *skb, int elems)
  3283. {
  3284. int dlen = skb->len - skb->data_len;
  3285. int elements_needed = PFN_UP((unsigned long)skb->data + dlen - 1) -
  3286. PFN_DOWN((unsigned long)skb->data);
  3287. elements_needed += skb_shinfo(skb)->nr_frags;
  3288. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  3289. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  3290. "(Number=%d / Length=%d). Discarded.\n",
  3291. (elements_needed+elems), skb->len);
  3292. return 0;
  3293. }
  3294. return elements_needed;
  3295. }
  3296. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  3297. int qeth_hdr_chk_and_bounce(struct sk_buff *skb, int len)
  3298. {
  3299. int hroom, inpage, rest;
  3300. if (((unsigned long)skb->data & PAGE_MASK) !=
  3301. (((unsigned long)skb->data + len - 1) & PAGE_MASK)) {
  3302. hroom = skb_headroom(skb);
  3303. inpage = PAGE_SIZE - ((unsigned long) skb->data % PAGE_SIZE);
  3304. rest = len - inpage;
  3305. if (rest > hroom)
  3306. return 1;
  3307. memmove(skb->data - rest, skb->data, skb->len - skb->data_len);
  3308. skb->data -= rest;
  3309. QETH_DBF_MESSAGE(2, "skb bounce len: %d rest: %d\n", len, rest);
  3310. }
  3311. return 0;
  3312. }
  3313. EXPORT_SYMBOL_GPL(qeth_hdr_chk_and_bounce);
  3314. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  3315. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  3316. int offset)
  3317. {
  3318. int length = skb->len - skb->data_len;
  3319. int length_here;
  3320. int element;
  3321. char *data;
  3322. int first_lap, cnt;
  3323. struct skb_frag_struct *frag;
  3324. element = *next_element_to_fill;
  3325. data = skb->data;
  3326. first_lap = (is_tso == 0 ? 1 : 0);
  3327. if (offset >= 0) {
  3328. data = skb->data + offset;
  3329. length -= offset;
  3330. first_lap = 0;
  3331. }
  3332. while (length > 0) {
  3333. /* length_here is the remaining amount of data in this page */
  3334. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  3335. if (length < length_here)
  3336. length_here = length;
  3337. buffer->element[element].addr = data;
  3338. buffer->element[element].length = length_here;
  3339. length -= length_here;
  3340. if (!length) {
  3341. if (first_lap)
  3342. if (skb_shinfo(skb)->nr_frags)
  3343. buffer->element[element].eflags =
  3344. SBAL_EFLAGS_FIRST_FRAG;
  3345. else
  3346. buffer->element[element].eflags = 0;
  3347. else
  3348. buffer->element[element].eflags =
  3349. SBAL_EFLAGS_MIDDLE_FRAG;
  3350. } else {
  3351. if (first_lap)
  3352. buffer->element[element].eflags =
  3353. SBAL_EFLAGS_FIRST_FRAG;
  3354. else
  3355. buffer->element[element].eflags =
  3356. SBAL_EFLAGS_MIDDLE_FRAG;
  3357. }
  3358. data += length_here;
  3359. element++;
  3360. first_lap = 0;
  3361. }
  3362. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  3363. frag = &skb_shinfo(skb)->frags[cnt];
  3364. buffer->element[element].addr = (char *)
  3365. page_to_phys(skb_frag_page(frag))
  3366. + frag->page_offset;
  3367. buffer->element[element].length = frag->size;
  3368. buffer->element[element].eflags = SBAL_EFLAGS_MIDDLE_FRAG;
  3369. element++;
  3370. }
  3371. if (buffer->element[element - 1].eflags)
  3372. buffer->element[element - 1].eflags = SBAL_EFLAGS_LAST_FRAG;
  3373. *next_element_to_fill = element;
  3374. }
  3375. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  3376. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  3377. struct qeth_hdr *hdr, int offset, int hd_len)
  3378. {
  3379. struct qdio_buffer *buffer;
  3380. int flush_cnt = 0, hdr_len, large_send = 0;
  3381. buffer = buf->buffer;
  3382. atomic_inc(&skb->users);
  3383. skb_queue_tail(&buf->skb_list, skb);
  3384. /*check first on TSO ....*/
  3385. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  3386. int element = buf->next_element_to_fill;
  3387. hdr_len = sizeof(struct qeth_hdr_tso) +
  3388. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  3389. /*fill first buffer entry only with header information */
  3390. buffer->element[element].addr = skb->data;
  3391. buffer->element[element].length = hdr_len;
  3392. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  3393. buf->next_element_to_fill++;
  3394. skb->data += hdr_len;
  3395. skb->len -= hdr_len;
  3396. large_send = 1;
  3397. }
  3398. if (offset >= 0) {
  3399. int element = buf->next_element_to_fill;
  3400. buffer->element[element].addr = hdr;
  3401. buffer->element[element].length = sizeof(struct qeth_hdr) +
  3402. hd_len;
  3403. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  3404. buf->is_header[element] = 1;
  3405. buf->next_element_to_fill++;
  3406. }
  3407. __qeth_fill_buffer(skb, buffer, large_send,
  3408. (int *)&buf->next_element_to_fill, offset);
  3409. if (!queue->do_pack) {
  3410. QETH_CARD_TEXT(queue->card, 6, "fillbfnp");
  3411. /* set state to PRIMED -> will be flushed */
  3412. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  3413. flush_cnt = 1;
  3414. } else {
  3415. QETH_CARD_TEXT(queue->card, 6, "fillbfpa");
  3416. if (queue->card->options.performance_stats)
  3417. queue->card->perf_stats.skbs_sent_pack++;
  3418. if (buf->next_element_to_fill >=
  3419. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  3420. /*
  3421. * packed buffer if full -> set state PRIMED
  3422. * -> will be flushed
  3423. */
  3424. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  3425. flush_cnt = 1;
  3426. }
  3427. }
  3428. return flush_cnt;
  3429. }
  3430. int qeth_do_send_packet_fast(struct qeth_card *card,
  3431. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  3432. struct qeth_hdr *hdr, int elements_needed,
  3433. int offset, int hd_len)
  3434. {
  3435. struct qeth_qdio_out_buffer *buffer;
  3436. int index;
  3437. /* spin until we get the queue ... */
  3438. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  3439. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  3440. /* ... now we've got the queue */
  3441. index = queue->next_buf_to_fill;
  3442. buffer = queue->bufs[queue->next_buf_to_fill];
  3443. /*
  3444. * check if buffer is empty to make sure that we do not 'overtake'
  3445. * ourselves and try to fill a buffer that is already primed
  3446. */
  3447. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  3448. goto out;
  3449. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  3450. QDIO_MAX_BUFFERS_PER_Q;
  3451. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3452. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  3453. qeth_flush_buffers(queue, index, 1);
  3454. return 0;
  3455. out:
  3456. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3457. return -EBUSY;
  3458. }
  3459. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  3460. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  3461. struct sk_buff *skb, struct qeth_hdr *hdr,
  3462. int elements_needed)
  3463. {
  3464. struct qeth_qdio_out_buffer *buffer;
  3465. int start_index;
  3466. int flush_count = 0;
  3467. int do_pack = 0;
  3468. int tmp;
  3469. int rc = 0;
  3470. /* spin until we get the queue ... */
  3471. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  3472. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  3473. start_index = queue->next_buf_to_fill;
  3474. buffer = queue->bufs[queue->next_buf_to_fill];
  3475. /*
  3476. * check if buffer is empty to make sure that we do not 'overtake'
  3477. * ourselves and try to fill a buffer that is already primed
  3478. */
  3479. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  3480. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3481. return -EBUSY;
  3482. }
  3483. /* check if we need to switch packing state of this queue */
  3484. qeth_switch_to_packing_if_needed(queue);
  3485. if (queue->do_pack) {
  3486. do_pack = 1;
  3487. /* does packet fit in current buffer? */
  3488. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  3489. buffer->next_element_to_fill) < elements_needed) {
  3490. /* ... no -> set state PRIMED */
  3491. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  3492. flush_count++;
  3493. queue->next_buf_to_fill =
  3494. (queue->next_buf_to_fill + 1) %
  3495. QDIO_MAX_BUFFERS_PER_Q;
  3496. buffer = queue->bufs[queue->next_buf_to_fill];
  3497. /* we did a step forward, so check buffer state
  3498. * again */
  3499. if (atomic_read(&buffer->state) !=
  3500. QETH_QDIO_BUF_EMPTY) {
  3501. qeth_flush_buffers(queue, start_index,
  3502. flush_count);
  3503. atomic_set(&queue->state,
  3504. QETH_OUT_Q_UNLOCKED);
  3505. return -EBUSY;
  3506. }
  3507. }
  3508. }
  3509. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  3510. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  3511. QDIO_MAX_BUFFERS_PER_Q;
  3512. flush_count += tmp;
  3513. if (flush_count)
  3514. qeth_flush_buffers(queue, start_index, flush_count);
  3515. else if (!atomic_read(&queue->set_pci_flags_count))
  3516. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  3517. /*
  3518. * queue->state will go from LOCKED -> UNLOCKED or from
  3519. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  3520. * (switch packing state or flush buffer to get another pci flag out).
  3521. * In that case we will enter this loop
  3522. */
  3523. while (atomic_dec_return(&queue->state)) {
  3524. flush_count = 0;
  3525. start_index = queue->next_buf_to_fill;
  3526. /* check if we can go back to non-packing state */
  3527. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  3528. /*
  3529. * check if we need to flush a packing buffer to get a pci
  3530. * flag out on the queue
  3531. */
  3532. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  3533. flush_count += qeth_flush_buffers_on_no_pci(queue);
  3534. if (flush_count)
  3535. qeth_flush_buffers(queue, start_index, flush_count);
  3536. }
  3537. /* at this point the queue is UNLOCKED again */
  3538. if (queue->card->options.performance_stats && do_pack)
  3539. queue->card->perf_stats.bufs_sent_pack += flush_count;
  3540. return rc;
  3541. }
  3542. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  3543. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  3544. struct qeth_reply *reply, unsigned long data)
  3545. {
  3546. struct qeth_ipa_cmd *cmd;
  3547. struct qeth_ipacmd_setadpparms *setparms;
  3548. QETH_CARD_TEXT(card, 4, "prmadpcb");
  3549. cmd = (struct qeth_ipa_cmd *) data;
  3550. setparms = &(cmd->data.setadapterparms);
  3551. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  3552. if (cmd->hdr.return_code) {
  3553. QETH_CARD_TEXT_(card, 4, "prmrc%2.2x", cmd->hdr.return_code);
  3554. setparms->data.mode = SET_PROMISC_MODE_OFF;
  3555. }
  3556. card->info.promisc_mode = setparms->data.mode;
  3557. return 0;
  3558. }
  3559. void qeth_setadp_promisc_mode(struct qeth_card *card)
  3560. {
  3561. enum qeth_ipa_promisc_modes mode;
  3562. struct net_device *dev = card->dev;
  3563. struct qeth_cmd_buffer *iob;
  3564. struct qeth_ipa_cmd *cmd;
  3565. QETH_CARD_TEXT(card, 4, "setprom");
  3566. if (((dev->flags & IFF_PROMISC) &&
  3567. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3568. (!(dev->flags & IFF_PROMISC) &&
  3569. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3570. return;
  3571. mode = SET_PROMISC_MODE_OFF;
  3572. if (dev->flags & IFF_PROMISC)
  3573. mode = SET_PROMISC_MODE_ON;
  3574. QETH_CARD_TEXT_(card, 4, "mode:%x", mode);
  3575. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3576. sizeof(struct qeth_ipacmd_setadpparms));
  3577. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3578. cmd->data.setadapterparms.data.mode = mode;
  3579. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3580. }
  3581. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3582. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3583. {
  3584. struct qeth_card *card;
  3585. char dbf_text[15];
  3586. card = dev->ml_priv;
  3587. QETH_CARD_TEXT(card, 4, "chgmtu");
  3588. sprintf(dbf_text, "%8x", new_mtu);
  3589. QETH_CARD_TEXT(card, 4, dbf_text);
  3590. if (new_mtu < 64)
  3591. return -EINVAL;
  3592. if (new_mtu > 65535)
  3593. return -EINVAL;
  3594. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3595. (!qeth_mtu_is_valid(card, new_mtu)))
  3596. return -EINVAL;
  3597. dev->mtu = new_mtu;
  3598. return 0;
  3599. }
  3600. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3601. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3602. {
  3603. struct qeth_card *card;
  3604. card = dev->ml_priv;
  3605. QETH_CARD_TEXT(card, 5, "getstat");
  3606. return &card->stats;
  3607. }
  3608. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3609. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3610. struct qeth_reply *reply, unsigned long data)
  3611. {
  3612. struct qeth_ipa_cmd *cmd;
  3613. QETH_CARD_TEXT(card, 4, "chgmaccb");
  3614. cmd = (struct qeth_ipa_cmd *) data;
  3615. if (!card->options.layer2 ||
  3616. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3617. memcpy(card->dev->dev_addr,
  3618. &cmd->data.setadapterparms.data.change_addr.addr,
  3619. OSA_ADDR_LEN);
  3620. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3621. }
  3622. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3623. return 0;
  3624. }
  3625. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3626. {
  3627. int rc;
  3628. struct qeth_cmd_buffer *iob;
  3629. struct qeth_ipa_cmd *cmd;
  3630. QETH_CARD_TEXT(card, 4, "chgmac");
  3631. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3632. sizeof(struct qeth_ipacmd_setadpparms));
  3633. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3634. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3635. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3636. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3637. card->dev->dev_addr, OSA_ADDR_LEN);
  3638. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3639. NULL);
  3640. return rc;
  3641. }
  3642. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3643. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3644. struct qeth_reply *reply, unsigned long data)
  3645. {
  3646. struct qeth_ipa_cmd *cmd;
  3647. struct qeth_set_access_ctrl *access_ctrl_req;
  3648. int fallback = *(int *)reply->param;
  3649. QETH_CARD_TEXT(card, 4, "setaccb");
  3650. cmd = (struct qeth_ipa_cmd *) data;
  3651. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3652. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3653. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3654. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3655. cmd->data.setadapterparms.hdr.return_code);
  3656. if (cmd->data.setadapterparms.hdr.return_code !=
  3657. SET_ACCESS_CTRL_RC_SUCCESS)
  3658. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3659. card->gdev->dev.kobj.name,
  3660. access_ctrl_req->subcmd_code,
  3661. cmd->data.setadapterparms.hdr.return_code);
  3662. switch (cmd->data.setadapterparms.hdr.return_code) {
  3663. case SET_ACCESS_CTRL_RC_SUCCESS:
  3664. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3665. dev_info(&card->gdev->dev,
  3666. "QDIO data connection isolation is deactivated\n");
  3667. } else {
  3668. dev_info(&card->gdev->dev,
  3669. "QDIO data connection isolation is activated\n");
  3670. }
  3671. break;
  3672. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3673. QETH_DBF_MESSAGE(2, "%s QDIO data connection isolation already "
  3674. "deactivated\n", dev_name(&card->gdev->dev));
  3675. if (fallback)
  3676. card->options.isolation = card->options.prev_isolation;
  3677. break;
  3678. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3679. QETH_DBF_MESSAGE(2, "%s QDIO data connection isolation already"
  3680. " activated\n", dev_name(&card->gdev->dev));
  3681. if (fallback)
  3682. card->options.isolation = card->options.prev_isolation;
  3683. break;
  3684. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3685. dev_err(&card->gdev->dev, "Adapter does not "
  3686. "support QDIO data connection isolation\n");
  3687. break;
  3688. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3689. dev_err(&card->gdev->dev,
  3690. "Adapter is dedicated. "
  3691. "QDIO data connection isolation not supported\n");
  3692. if (fallback)
  3693. card->options.isolation = card->options.prev_isolation;
  3694. break;
  3695. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3696. dev_err(&card->gdev->dev,
  3697. "TSO does not permit QDIO data connection isolation\n");
  3698. if (fallback)
  3699. card->options.isolation = card->options.prev_isolation;
  3700. break;
  3701. case SET_ACCESS_CTRL_RC_REFLREL_UNSUPPORTED:
  3702. dev_err(&card->gdev->dev, "The adjacent switch port does not "
  3703. "support reflective relay mode\n");
  3704. if (fallback)
  3705. card->options.isolation = card->options.prev_isolation;
  3706. break;
  3707. case SET_ACCESS_CTRL_RC_REFLREL_FAILED:
  3708. dev_err(&card->gdev->dev, "The reflective relay mode cannot be "
  3709. "enabled at the adjacent switch port");
  3710. if (fallback)
  3711. card->options.isolation = card->options.prev_isolation;
  3712. break;
  3713. case SET_ACCESS_CTRL_RC_REFLREL_DEACT_FAILED:
  3714. dev_warn(&card->gdev->dev, "Turning off reflective relay mode "
  3715. "at the adjacent switch failed\n");
  3716. break;
  3717. default:
  3718. /* this should never happen */
  3719. if (fallback)
  3720. card->options.isolation = card->options.prev_isolation;
  3721. break;
  3722. }
  3723. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3724. return 0;
  3725. }
  3726. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3727. enum qeth_ipa_isolation_modes isolation, int fallback)
  3728. {
  3729. int rc;
  3730. struct qeth_cmd_buffer *iob;
  3731. struct qeth_ipa_cmd *cmd;
  3732. struct qeth_set_access_ctrl *access_ctrl_req;
  3733. QETH_CARD_TEXT(card, 4, "setacctl");
  3734. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3735. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3736. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3737. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3738. sizeof(struct qeth_set_access_ctrl));
  3739. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3740. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3741. access_ctrl_req->subcmd_code = isolation;
  3742. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3743. &fallback);
  3744. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3745. return rc;
  3746. }
  3747. int qeth_set_access_ctrl_online(struct qeth_card *card, int fallback)
  3748. {
  3749. int rc = 0;
  3750. QETH_CARD_TEXT(card, 4, "setactlo");
  3751. if ((card->info.type == QETH_CARD_TYPE_OSD ||
  3752. card->info.type == QETH_CARD_TYPE_OSX) &&
  3753. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3754. rc = qeth_setadpparms_set_access_ctrl(card,
  3755. card->options.isolation, fallback);
  3756. if (rc) {
  3757. QETH_DBF_MESSAGE(3,
  3758. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed\n",
  3759. card->gdev->dev.kobj.name,
  3760. rc);
  3761. rc = -EOPNOTSUPP;
  3762. }
  3763. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3764. card->options.isolation = ISOLATION_MODE_NONE;
  3765. dev_err(&card->gdev->dev, "Adapter does not "
  3766. "support QDIO data connection isolation\n");
  3767. rc = -EOPNOTSUPP;
  3768. }
  3769. return rc;
  3770. }
  3771. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3772. void qeth_tx_timeout(struct net_device *dev)
  3773. {
  3774. struct qeth_card *card;
  3775. card = dev->ml_priv;
  3776. QETH_CARD_TEXT(card, 4, "txtimeo");
  3777. card->stats.tx_errors++;
  3778. qeth_schedule_recovery(card);
  3779. }
  3780. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3781. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3782. {
  3783. struct qeth_card *card = dev->ml_priv;
  3784. int rc = 0;
  3785. switch (regnum) {
  3786. case MII_BMCR: /* Basic mode control register */
  3787. rc = BMCR_FULLDPLX;
  3788. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3789. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3790. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3791. rc |= BMCR_SPEED100;
  3792. break;
  3793. case MII_BMSR: /* Basic mode status register */
  3794. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3795. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3796. BMSR_100BASE4;
  3797. break;
  3798. case MII_PHYSID1: /* PHYS ID 1 */
  3799. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3800. dev->dev_addr[2];
  3801. rc = (rc >> 5) & 0xFFFF;
  3802. break;
  3803. case MII_PHYSID2: /* PHYS ID 2 */
  3804. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3805. break;
  3806. case MII_ADVERTISE: /* Advertisement control reg */
  3807. rc = ADVERTISE_ALL;
  3808. break;
  3809. case MII_LPA: /* Link partner ability reg */
  3810. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3811. LPA_100BASE4 | LPA_LPACK;
  3812. break;
  3813. case MII_EXPANSION: /* Expansion register */
  3814. break;
  3815. case MII_DCOUNTER: /* disconnect counter */
  3816. break;
  3817. case MII_FCSCOUNTER: /* false carrier counter */
  3818. break;
  3819. case MII_NWAYTEST: /* N-way auto-neg test register */
  3820. break;
  3821. case MII_RERRCOUNTER: /* rx error counter */
  3822. rc = card->stats.rx_errors;
  3823. break;
  3824. case MII_SREVISION: /* silicon revision */
  3825. break;
  3826. case MII_RESV1: /* reserved 1 */
  3827. break;
  3828. case MII_LBRERROR: /* loopback, rx, bypass error */
  3829. break;
  3830. case MII_PHYADDR: /* physical address */
  3831. break;
  3832. case MII_RESV2: /* reserved 2 */
  3833. break;
  3834. case MII_TPISTATUS: /* TPI status for 10mbps */
  3835. break;
  3836. case MII_NCONFIG: /* network interface config */
  3837. break;
  3838. default:
  3839. break;
  3840. }
  3841. return rc;
  3842. }
  3843. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3844. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3845. struct qeth_cmd_buffer *iob, int len,
  3846. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3847. unsigned long),
  3848. void *reply_param)
  3849. {
  3850. u16 s1, s2;
  3851. QETH_CARD_TEXT(card, 4, "sendsnmp");
  3852. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3853. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3854. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3855. /* adjust PDU length fields in IPA_PDU_HEADER */
  3856. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3857. s2 = (u32) len;
  3858. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3859. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3860. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3861. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3862. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3863. reply_cb, reply_param);
  3864. }
  3865. static int qeth_snmp_command_cb(struct qeth_card *card,
  3866. struct qeth_reply *reply, unsigned long sdata)
  3867. {
  3868. struct qeth_ipa_cmd *cmd;
  3869. struct qeth_arp_query_info *qinfo;
  3870. struct qeth_snmp_cmd *snmp;
  3871. unsigned char *data;
  3872. __u16 data_len;
  3873. QETH_CARD_TEXT(card, 3, "snpcmdcb");
  3874. cmd = (struct qeth_ipa_cmd *) sdata;
  3875. data = (unsigned char *)((char *)cmd - reply->offset);
  3876. qinfo = (struct qeth_arp_query_info *) reply->param;
  3877. snmp = &cmd->data.setadapterparms.data.snmp;
  3878. if (cmd->hdr.return_code) {
  3879. QETH_CARD_TEXT_(card, 4, "scer1%i", cmd->hdr.return_code);
  3880. return 0;
  3881. }
  3882. if (cmd->data.setadapterparms.hdr.return_code) {
  3883. cmd->hdr.return_code =
  3884. cmd->data.setadapterparms.hdr.return_code;
  3885. QETH_CARD_TEXT_(card, 4, "scer2%i", cmd->hdr.return_code);
  3886. return 0;
  3887. }
  3888. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3889. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3890. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3891. else
  3892. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3893. /* check if there is enough room in userspace */
  3894. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3895. QETH_CARD_TEXT_(card, 4, "scer3%i", -ENOMEM);
  3896. cmd->hdr.return_code = IPA_RC_ENOMEM;
  3897. return 0;
  3898. }
  3899. QETH_CARD_TEXT_(card, 4, "snore%i",
  3900. cmd->data.setadapterparms.hdr.used_total);
  3901. QETH_CARD_TEXT_(card, 4, "sseqn%i",
  3902. cmd->data.setadapterparms.hdr.seq_no);
  3903. /*copy entries to user buffer*/
  3904. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3905. memcpy(qinfo->udata + qinfo->udata_offset,
  3906. (char *)snmp,
  3907. data_len + offsetof(struct qeth_snmp_cmd, data));
  3908. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3909. } else {
  3910. memcpy(qinfo->udata + qinfo->udata_offset,
  3911. (char *)&snmp->request, data_len);
  3912. }
  3913. qinfo->udata_offset += data_len;
  3914. /* check if all replies received ... */
  3915. QETH_CARD_TEXT_(card, 4, "srtot%i",
  3916. cmd->data.setadapterparms.hdr.used_total);
  3917. QETH_CARD_TEXT_(card, 4, "srseq%i",
  3918. cmd->data.setadapterparms.hdr.seq_no);
  3919. if (cmd->data.setadapterparms.hdr.seq_no <
  3920. cmd->data.setadapterparms.hdr.used_total)
  3921. return 1;
  3922. return 0;
  3923. }
  3924. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3925. {
  3926. struct qeth_cmd_buffer *iob;
  3927. struct qeth_ipa_cmd *cmd;
  3928. struct qeth_snmp_ureq *ureq;
  3929. int req_len;
  3930. struct qeth_arp_query_info qinfo = {0, };
  3931. int rc = 0;
  3932. QETH_CARD_TEXT(card, 3, "snmpcmd");
  3933. if (card->info.guestlan)
  3934. return -EOPNOTSUPP;
  3935. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3936. (!card->options.layer2)) {
  3937. return -EOPNOTSUPP;
  3938. }
  3939. /* skip 4 bytes (data_len struct member) to get req_len */
  3940. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3941. return -EFAULT;
  3942. ureq = memdup_user(udata, req_len + sizeof(struct qeth_snmp_ureq_hdr));
  3943. if (IS_ERR(ureq)) {
  3944. QETH_CARD_TEXT(card, 2, "snmpnome");
  3945. return PTR_ERR(ureq);
  3946. }
  3947. qinfo.udata_len = ureq->hdr.data_len;
  3948. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3949. if (!qinfo.udata) {
  3950. kfree(ureq);
  3951. return -ENOMEM;
  3952. }
  3953. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3954. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3955. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3956. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3957. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3958. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3959. qeth_snmp_command_cb, (void *)&qinfo);
  3960. if (rc)
  3961. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3962. QETH_CARD_IFNAME(card), rc);
  3963. else {
  3964. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3965. rc = -EFAULT;
  3966. }
  3967. kfree(ureq);
  3968. kfree(qinfo.udata);
  3969. return rc;
  3970. }
  3971. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3972. static int qeth_setadpparms_query_oat_cb(struct qeth_card *card,
  3973. struct qeth_reply *reply, unsigned long data)
  3974. {
  3975. struct qeth_ipa_cmd *cmd;
  3976. struct qeth_qoat_priv *priv;
  3977. char *resdata;
  3978. int resdatalen;
  3979. QETH_CARD_TEXT(card, 3, "qoatcb");
  3980. cmd = (struct qeth_ipa_cmd *)data;
  3981. priv = (struct qeth_qoat_priv *)reply->param;
  3982. resdatalen = cmd->data.setadapterparms.hdr.cmdlength;
  3983. resdata = (char *)data + 28;
  3984. if (resdatalen > (priv->buffer_len - priv->response_len)) {
  3985. cmd->hdr.return_code = IPA_RC_FFFF;
  3986. return 0;
  3987. }
  3988. memcpy((priv->buffer + priv->response_len), resdata,
  3989. resdatalen);
  3990. priv->response_len += resdatalen;
  3991. if (cmd->data.setadapterparms.hdr.seq_no <
  3992. cmd->data.setadapterparms.hdr.used_total)
  3993. return 1;
  3994. return 0;
  3995. }
  3996. int qeth_query_oat_command(struct qeth_card *card, char __user *udata)
  3997. {
  3998. int rc = 0;
  3999. struct qeth_cmd_buffer *iob;
  4000. struct qeth_ipa_cmd *cmd;
  4001. struct qeth_query_oat *oat_req;
  4002. struct qeth_query_oat_data oat_data;
  4003. struct qeth_qoat_priv priv;
  4004. void __user *tmp;
  4005. QETH_CARD_TEXT(card, 3, "qoatcmd");
  4006. if (!qeth_adp_supported(card, IPA_SETADP_QUERY_OAT)) {
  4007. rc = -EOPNOTSUPP;
  4008. goto out;
  4009. }
  4010. if (copy_from_user(&oat_data, udata,
  4011. sizeof(struct qeth_query_oat_data))) {
  4012. rc = -EFAULT;
  4013. goto out;
  4014. }
  4015. priv.buffer_len = oat_data.buffer_len;
  4016. priv.response_len = 0;
  4017. priv.buffer = kzalloc(oat_data.buffer_len, GFP_KERNEL);
  4018. if (!priv.buffer) {
  4019. rc = -ENOMEM;
  4020. goto out;
  4021. }
  4022. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_OAT,
  4023. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  4024. sizeof(struct qeth_query_oat));
  4025. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  4026. oat_req = &cmd->data.setadapterparms.data.query_oat;
  4027. oat_req->subcmd_code = oat_data.command;
  4028. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_query_oat_cb,
  4029. &priv);
  4030. if (!rc) {
  4031. if (is_compat_task())
  4032. tmp = compat_ptr(oat_data.ptr);
  4033. else
  4034. tmp = (void __user *)(unsigned long)oat_data.ptr;
  4035. if (copy_to_user(tmp, priv.buffer,
  4036. priv.response_len)) {
  4037. rc = -EFAULT;
  4038. goto out_free;
  4039. }
  4040. oat_data.response_len = priv.response_len;
  4041. if (copy_to_user(udata, &oat_data,
  4042. sizeof(struct qeth_query_oat_data)))
  4043. rc = -EFAULT;
  4044. } else
  4045. if (rc == IPA_RC_FFFF)
  4046. rc = -EFAULT;
  4047. out_free:
  4048. kfree(priv.buffer);
  4049. out:
  4050. return rc;
  4051. }
  4052. EXPORT_SYMBOL_GPL(qeth_query_oat_command);
  4053. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  4054. {
  4055. switch (card->info.type) {
  4056. case QETH_CARD_TYPE_IQD:
  4057. return 2;
  4058. default:
  4059. return 0;
  4060. }
  4061. }
  4062. static void qeth_determine_capabilities(struct qeth_card *card)
  4063. {
  4064. int rc;
  4065. int length;
  4066. char *prcd;
  4067. struct ccw_device *ddev;
  4068. int ddev_offline = 0;
  4069. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  4070. ddev = CARD_DDEV(card);
  4071. if (!ddev->online) {
  4072. ddev_offline = 1;
  4073. rc = ccw_device_set_online(ddev);
  4074. if (rc) {
  4075. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4076. goto out;
  4077. }
  4078. }
  4079. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  4080. if (rc) {
  4081. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  4082. dev_name(&card->gdev->dev), rc);
  4083. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  4084. goto out_offline;
  4085. }
  4086. qeth_configure_unitaddr(card, prcd);
  4087. if (ddev_offline)
  4088. qeth_configure_blkt_default(card, prcd);
  4089. kfree(prcd);
  4090. rc = qdio_get_ssqd_desc(ddev, &card->ssqd);
  4091. if (rc)
  4092. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  4093. QETH_DBF_TEXT_(SETUP, 2, "qfmt%d", card->ssqd.qfmt);
  4094. QETH_DBF_TEXT_(SETUP, 2, "%d", card->ssqd.qdioac1);
  4095. QETH_DBF_TEXT_(SETUP, 2, "%d", card->ssqd.qdioac3);
  4096. QETH_DBF_TEXT_(SETUP, 2, "icnt%d", card->ssqd.icnt);
  4097. if (!((card->ssqd.qfmt != QDIO_IQDIO_QFMT) ||
  4098. ((card->ssqd.qdioac1 & CHSC_AC1_INITIATE_INPUTQ) == 0) ||
  4099. ((card->ssqd.qdioac3 & CHSC_AC3_FORMAT2_CQ_AVAILABLE) == 0))) {
  4100. dev_info(&card->gdev->dev,
  4101. "Completion Queueing supported\n");
  4102. } else {
  4103. card->options.cq = QETH_CQ_NOTAVAILABLE;
  4104. }
  4105. out_offline:
  4106. if (ddev_offline == 1)
  4107. ccw_device_set_offline(ddev);
  4108. out:
  4109. return;
  4110. }
  4111. static inline void qeth_qdio_establish_cq(struct qeth_card *card,
  4112. struct qdio_buffer **in_sbal_ptrs,
  4113. void (**queue_start_poll) (struct ccw_device *, int, unsigned long)) {
  4114. int i;
  4115. if (card->options.cq == QETH_CQ_ENABLED) {
  4116. int offset = QDIO_MAX_BUFFERS_PER_Q *
  4117. (card->qdio.no_in_queues - 1);
  4118. i = QDIO_MAX_BUFFERS_PER_Q * (card->qdio.no_in_queues - 1);
  4119. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  4120. in_sbal_ptrs[offset + i] = (struct qdio_buffer *)
  4121. virt_to_phys(card->qdio.c_q->bufs[i].buffer);
  4122. }
  4123. queue_start_poll[card->qdio.no_in_queues - 1] = NULL;
  4124. }
  4125. }
  4126. static int qeth_qdio_establish(struct qeth_card *card)
  4127. {
  4128. struct qdio_initialize init_data;
  4129. char *qib_param_field;
  4130. struct qdio_buffer **in_sbal_ptrs;
  4131. void (**queue_start_poll) (struct ccw_device *, int, unsigned long);
  4132. struct qdio_buffer **out_sbal_ptrs;
  4133. int i, j, k;
  4134. int rc = 0;
  4135. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  4136. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  4137. GFP_KERNEL);
  4138. if (!qib_param_field) {
  4139. rc = -ENOMEM;
  4140. goto out_free_nothing;
  4141. }
  4142. qeth_create_qib_param_field(card, qib_param_field);
  4143. qeth_create_qib_param_field_blkt(card, qib_param_field);
  4144. in_sbal_ptrs = kzalloc(card->qdio.no_in_queues *
  4145. QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  4146. GFP_KERNEL);
  4147. if (!in_sbal_ptrs) {
  4148. rc = -ENOMEM;
  4149. goto out_free_qib_param;
  4150. }
  4151. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  4152. in_sbal_ptrs[i] = (struct qdio_buffer *)
  4153. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  4154. }
  4155. queue_start_poll = kzalloc(sizeof(void *) * card->qdio.no_in_queues,
  4156. GFP_KERNEL);
  4157. if (!queue_start_poll) {
  4158. rc = -ENOMEM;
  4159. goto out_free_in_sbals;
  4160. }
  4161. for (i = 0; i < card->qdio.no_in_queues; ++i)
  4162. queue_start_poll[i] = card->discipline->start_poll;
  4163. qeth_qdio_establish_cq(card, in_sbal_ptrs, queue_start_poll);
  4164. out_sbal_ptrs =
  4165. kzalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  4166. sizeof(void *), GFP_KERNEL);
  4167. if (!out_sbal_ptrs) {
  4168. rc = -ENOMEM;
  4169. goto out_free_queue_start_poll;
  4170. }
  4171. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  4172. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  4173. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  4174. card->qdio.out_qs[i]->bufs[j]->buffer);
  4175. }
  4176. memset(&init_data, 0, sizeof(struct qdio_initialize));
  4177. init_data.cdev = CARD_DDEV(card);
  4178. init_data.q_format = qeth_get_qdio_q_format(card);
  4179. init_data.qib_param_field_format = 0;
  4180. init_data.qib_param_field = qib_param_field;
  4181. init_data.no_input_qs = card->qdio.no_in_queues;
  4182. init_data.no_output_qs = card->qdio.no_out_queues;
  4183. init_data.input_handler = card->discipline->input_handler;
  4184. init_data.output_handler = card->discipline->output_handler;
  4185. init_data.queue_start_poll_array = queue_start_poll;
  4186. init_data.int_parm = (unsigned long) card;
  4187. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  4188. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  4189. init_data.output_sbal_state_array = card->qdio.out_bufstates;
  4190. init_data.scan_threshold =
  4191. (card->info.type == QETH_CARD_TYPE_IQD) ? 1 : 32;
  4192. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  4193. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  4194. rc = qdio_allocate(&init_data);
  4195. if (rc) {
  4196. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  4197. goto out;
  4198. }
  4199. rc = qdio_establish(&init_data);
  4200. if (rc) {
  4201. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  4202. qdio_free(CARD_DDEV(card));
  4203. }
  4204. }
  4205. switch (card->options.cq) {
  4206. case QETH_CQ_ENABLED:
  4207. dev_info(&card->gdev->dev, "Completion Queue support enabled");
  4208. break;
  4209. case QETH_CQ_DISABLED:
  4210. dev_info(&card->gdev->dev, "Completion Queue support disabled");
  4211. break;
  4212. default:
  4213. break;
  4214. }
  4215. out:
  4216. kfree(out_sbal_ptrs);
  4217. out_free_queue_start_poll:
  4218. kfree(queue_start_poll);
  4219. out_free_in_sbals:
  4220. kfree(in_sbal_ptrs);
  4221. out_free_qib_param:
  4222. kfree(qib_param_field);
  4223. out_free_nothing:
  4224. return rc;
  4225. }
  4226. static void qeth_core_free_card(struct qeth_card *card)
  4227. {
  4228. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  4229. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  4230. qeth_clean_channel(&card->read);
  4231. qeth_clean_channel(&card->write);
  4232. if (card->dev)
  4233. free_netdev(card->dev);
  4234. kfree(card->ip_tbd_list);
  4235. qeth_free_qdio_buffers(card);
  4236. unregister_service_level(&card->qeth_service_level);
  4237. kfree(card);
  4238. }
  4239. void qeth_trace_features(struct qeth_card *card)
  4240. {
  4241. QETH_CARD_TEXT(card, 2, "features");
  4242. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa4.supported_funcs);
  4243. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa4.enabled_funcs);
  4244. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa6.supported_funcs);
  4245. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa6.enabled_funcs);
  4246. QETH_CARD_TEXT_(card, 2, "%x", card->options.adp.supported_funcs);
  4247. QETH_CARD_TEXT_(card, 2, "%x", card->options.adp.enabled_funcs);
  4248. QETH_CARD_TEXT_(card, 2, "%x", card->info.diagass_support);
  4249. }
  4250. EXPORT_SYMBOL_GPL(qeth_trace_features);
  4251. static struct ccw_device_id qeth_ids[] = {
  4252. {CCW_DEVICE_DEVTYPE(0x1731, 0x01, 0x1732, 0x01),
  4253. .driver_info = QETH_CARD_TYPE_OSD},
  4254. {CCW_DEVICE_DEVTYPE(0x1731, 0x05, 0x1732, 0x05),
  4255. .driver_info = QETH_CARD_TYPE_IQD},
  4256. {CCW_DEVICE_DEVTYPE(0x1731, 0x06, 0x1732, 0x06),
  4257. .driver_info = QETH_CARD_TYPE_OSN},
  4258. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x03),
  4259. .driver_info = QETH_CARD_TYPE_OSM},
  4260. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x02),
  4261. .driver_info = QETH_CARD_TYPE_OSX},
  4262. {},
  4263. };
  4264. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  4265. static struct ccw_driver qeth_ccw_driver = {
  4266. .driver = {
  4267. .owner = THIS_MODULE,
  4268. .name = "qeth",
  4269. },
  4270. .ids = qeth_ids,
  4271. .probe = ccwgroup_probe_ccwdev,
  4272. .remove = ccwgroup_remove_ccwdev,
  4273. };
  4274. int qeth_core_hardsetup_card(struct qeth_card *card)
  4275. {
  4276. int retries = 3;
  4277. int rc;
  4278. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  4279. atomic_set(&card->force_alloc_skb, 0);
  4280. qeth_update_from_chp_desc(card);
  4281. retry:
  4282. if (retries < 3)
  4283. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  4284. dev_name(&card->gdev->dev));
  4285. ccw_device_set_offline(CARD_DDEV(card));
  4286. ccw_device_set_offline(CARD_WDEV(card));
  4287. ccw_device_set_offline(CARD_RDEV(card));
  4288. rc = ccw_device_set_online(CARD_RDEV(card));
  4289. if (rc)
  4290. goto retriable;
  4291. rc = ccw_device_set_online(CARD_WDEV(card));
  4292. if (rc)
  4293. goto retriable;
  4294. rc = ccw_device_set_online(CARD_DDEV(card));
  4295. if (rc)
  4296. goto retriable;
  4297. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  4298. retriable:
  4299. if (rc == -ERESTARTSYS) {
  4300. QETH_DBF_TEXT(SETUP, 2, "break1");
  4301. return rc;
  4302. } else if (rc) {
  4303. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  4304. if (--retries < 0)
  4305. goto out;
  4306. else
  4307. goto retry;
  4308. }
  4309. qeth_determine_capabilities(card);
  4310. qeth_init_tokens(card);
  4311. qeth_init_func_level(card);
  4312. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  4313. if (rc == -ERESTARTSYS) {
  4314. QETH_DBF_TEXT(SETUP, 2, "break2");
  4315. return rc;
  4316. } else if (rc) {
  4317. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4318. if (--retries < 0)
  4319. goto out;
  4320. else
  4321. goto retry;
  4322. }
  4323. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  4324. if (rc == -ERESTARTSYS) {
  4325. QETH_DBF_TEXT(SETUP, 2, "break3");
  4326. return rc;
  4327. } else if (rc) {
  4328. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  4329. if (--retries < 0)
  4330. goto out;
  4331. else
  4332. goto retry;
  4333. }
  4334. card->read_or_write_problem = 0;
  4335. rc = qeth_mpc_initialize(card);
  4336. if (rc) {
  4337. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  4338. goto out;
  4339. }
  4340. card->options.ipa4.supported_funcs = 0;
  4341. card->options.adp.supported_funcs = 0;
  4342. card->info.diagass_support = 0;
  4343. qeth_query_ipassists(card, QETH_PROT_IPV4);
  4344. if (qeth_is_supported(card, IPA_SETADAPTERPARMS))
  4345. qeth_query_setadapterparms(card);
  4346. if (qeth_adp_supported(card, IPA_SETADP_SET_DIAG_ASSIST))
  4347. qeth_query_setdiagass(card);
  4348. return 0;
  4349. out:
  4350. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  4351. "an error on the device\n");
  4352. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  4353. dev_name(&card->gdev->dev), rc);
  4354. return rc;
  4355. }
  4356. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  4357. static inline int qeth_create_skb_frag(struct qeth_qdio_buffer *qethbuffer,
  4358. struct qdio_buffer_element *element,
  4359. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  4360. {
  4361. struct page *page = virt_to_page(element->addr);
  4362. if (*pskb == NULL) {
  4363. if (qethbuffer->rx_skb) {
  4364. /* only if qeth_card.options.cq == QETH_CQ_ENABLED */
  4365. *pskb = qethbuffer->rx_skb;
  4366. qethbuffer->rx_skb = NULL;
  4367. } else {
  4368. *pskb = dev_alloc_skb(QETH_RX_PULL_LEN + ETH_HLEN);
  4369. if (!(*pskb))
  4370. return -ENOMEM;
  4371. }
  4372. skb_reserve(*pskb, ETH_HLEN);
  4373. if (data_len <= QETH_RX_PULL_LEN) {
  4374. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  4375. data_len);
  4376. } else {
  4377. get_page(page);
  4378. memcpy(skb_put(*pskb, QETH_RX_PULL_LEN),
  4379. element->addr + offset, QETH_RX_PULL_LEN);
  4380. skb_fill_page_desc(*pskb, *pfrag, page,
  4381. offset + QETH_RX_PULL_LEN,
  4382. data_len - QETH_RX_PULL_LEN);
  4383. (*pskb)->data_len += data_len - QETH_RX_PULL_LEN;
  4384. (*pskb)->len += data_len - QETH_RX_PULL_LEN;
  4385. (*pskb)->truesize += data_len - QETH_RX_PULL_LEN;
  4386. (*pfrag)++;
  4387. }
  4388. } else {
  4389. get_page(page);
  4390. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  4391. (*pskb)->data_len += data_len;
  4392. (*pskb)->len += data_len;
  4393. (*pskb)->truesize += data_len;
  4394. (*pfrag)++;
  4395. }
  4396. return 0;
  4397. }
  4398. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  4399. struct qeth_qdio_buffer *qethbuffer,
  4400. struct qdio_buffer_element **__element, int *__offset,
  4401. struct qeth_hdr **hdr)
  4402. {
  4403. struct qdio_buffer_element *element = *__element;
  4404. struct qdio_buffer *buffer = qethbuffer->buffer;
  4405. int offset = *__offset;
  4406. struct sk_buff *skb = NULL;
  4407. int skb_len = 0;
  4408. void *data_ptr;
  4409. int data_len;
  4410. int headroom = 0;
  4411. int use_rx_sg = 0;
  4412. int frag = 0;
  4413. /* qeth_hdr must not cross element boundaries */
  4414. if (element->length < offset + sizeof(struct qeth_hdr)) {
  4415. if (qeth_is_last_sbale(element))
  4416. return NULL;
  4417. element++;
  4418. offset = 0;
  4419. if (element->length < sizeof(struct qeth_hdr))
  4420. return NULL;
  4421. }
  4422. *hdr = element->addr + offset;
  4423. offset += sizeof(struct qeth_hdr);
  4424. switch ((*hdr)->hdr.l2.id) {
  4425. case QETH_HEADER_TYPE_LAYER2:
  4426. skb_len = (*hdr)->hdr.l2.pkt_length;
  4427. break;
  4428. case QETH_HEADER_TYPE_LAYER3:
  4429. skb_len = (*hdr)->hdr.l3.length;
  4430. headroom = ETH_HLEN;
  4431. break;
  4432. case QETH_HEADER_TYPE_OSN:
  4433. skb_len = (*hdr)->hdr.osn.pdu_length;
  4434. headroom = sizeof(struct qeth_hdr);
  4435. break;
  4436. default:
  4437. break;
  4438. }
  4439. if (!skb_len)
  4440. return NULL;
  4441. if (((skb_len >= card->options.rx_sg_cb) &&
  4442. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  4443. (!atomic_read(&card->force_alloc_skb))) ||
  4444. (card->options.cq == QETH_CQ_ENABLED)) {
  4445. use_rx_sg = 1;
  4446. } else {
  4447. skb = dev_alloc_skb(skb_len + headroom);
  4448. if (!skb)
  4449. goto no_mem;
  4450. if (headroom)
  4451. skb_reserve(skb, headroom);
  4452. }
  4453. data_ptr = element->addr + offset;
  4454. while (skb_len) {
  4455. data_len = min(skb_len, (int)(element->length - offset));
  4456. if (data_len) {
  4457. if (use_rx_sg) {
  4458. if (qeth_create_skb_frag(qethbuffer, element,
  4459. &skb, offset, &frag, data_len))
  4460. goto no_mem;
  4461. } else {
  4462. memcpy(skb_put(skb, data_len), data_ptr,
  4463. data_len);
  4464. }
  4465. }
  4466. skb_len -= data_len;
  4467. if (skb_len) {
  4468. if (qeth_is_last_sbale(element)) {
  4469. QETH_CARD_TEXT(card, 4, "unexeob");
  4470. QETH_CARD_HEX(card, 2, buffer, sizeof(void *));
  4471. dev_kfree_skb_any(skb);
  4472. card->stats.rx_errors++;
  4473. return NULL;
  4474. }
  4475. element++;
  4476. offset = 0;
  4477. data_ptr = element->addr;
  4478. } else {
  4479. offset += data_len;
  4480. }
  4481. }
  4482. *__element = element;
  4483. *__offset = offset;
  4484. if (use_rx_sg && card->options.performance_stats) {
  4485. card->perf_stats.sg_skbs_rx++;
  4486. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  4487. }
  4488. return skb;
  4489. no_mem:
  4490. if (net_ratelimit()) {
  4491. QETH_CARD_TEXT(card, 2, "noskbmem");
  4492. }
  4493. card->stats.rx_dropped++;
  4494. return NULL;
  4495. }
  4496. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  4497. static void qeth_unregister_dbf_views(void)
  4498. {
  4499. int x;
  4500. for (x = 0; x < QETH_DBF_INFOS; x++) {
  4501. debug_unregister(qeth_dbf[x].id);
  4502. qeth_dbf[x].id = NULL;
  4503. }
  4504. }
  4505. void qeth_dbf_longtext(debug_info_t *id, int level, char *fmt, ...)
  4506. {
  4507. char dbf_txt_buf[32];
  4508. va_list args;
  4509. if (level > id->level)
  4510. return;
  4511. va_start(args, fmt);
  4512. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  4513. va_end(args);
  4514. debug_text_event(id, level, dbf_txt_buf);
  4515. }
  4516. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  4517. static int qeth_register_dbf_views(void)
  4518. {
  4519. int ret;
  4520. int x;
  4521. for (x = 0; x < QETH_DBF_INFOS; x++) {
  4522. /* register the areas */
  4523. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  4524. qeth_dbf[x].pages,
  4525. qeth_dbf[x].areas,
  4526. qeth_dbf[x].len);
  4527. if (qeth_dbf[x].id == NULL) {
  4528. qeth_unregister_dbf_views();
  4529. return -ENOMEM;
  4530. }
  4531. /* register a view */
  4532. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  4533. if (ret) {
  4534. qeth_unregister_dbf_views();
  4535. return ret;
  4536. }
  4537. /* set a passing level */
  4538. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  4539. }
  4540. return 0;
  4541. }
  4542. int qeth_core_load_discipline(struct qeth_card *card,
  4543. enum qeth_discipline_id discipline)
  4544. {
  4545. int rc = 0;
  4546. mutex_lock(&qeth_mod_mutex);
  4547. switch (discipline) {
  4548. case QETH_DISCIPLINE_LAYER3:
  4549. card->discipline = try_then_request_module(
  4550. symbol_get(qeth_l3_discipline), "qeth_l3");
  4551. break;
  4552. case QETH_DISCIPLINE_LAYER2:
  4553. card->discipline = try_then_request_module(
  4554. symbol_get(qeth_l2_discipline), "qeth_l2");
  4555. break;
  4556. }
  4557. if (!card->discipline) {
  4558. dev_err(&card->gdev->dev, "There is no kernel module to "
  4559. "support discipline %d\n", discipline);
  4560. rc = -EINVAL;
  4561. }
  4562. mutex_unlock(&qeth_mod_mutex);
  4563. return rc;
  4564. }
  4565. void qeth_core_free_discipline(struct qeth_card *card)
  4566. {
  4567. if (card->options.layer2)
  4568. symbol_put(qeth_l2_discipline);
  4569. else
  4570. symbol_put(qeth_l3_discipline);
  4571. card->discipline = NULL;
  4572. }
  4573. static const struct device_type qeth_generic_devtype = {
  4574. .name = "qeth_generic",
  4575. .groups = qeth_generic_attr_groups,
  4576. };
  4577. static const struct device_type qeth_osn_devtype = {
  4578. .name = "qeth_osn",
  4579. .groups = qeth_osn_attr_groups,
  4580. };
  4581. #define DBF_NAME_LEN 20
  4582. struct qeth_dbf_entry {
  4583. char dbf_name[DBF_NAME_LEN];
  4584. debug_info_t *dbf_info;
  4585. struct list_head dbf_list;
  4586. };
  4587. static LIST_HEAD(qeth_dbf_list);
  4588. static DEFINE_MUTEX(qeth_dbf_list_mutex);
  4589. static debug_info_t *qeth_get_dbf_entry(char *name)
  4590. {
  4591. struct qeth_dbf_entry *entry;
  4592. debug_info_t *rc = NULL;
  4593. mutex_lock(&qeth_dbf_list_mutex);
  4594. list_for_each_entry(entry, &qeth_dbf_list, dbf_list) {
  4595. if (strcmp(entry->dbf_name, name) == 0) {
  4596. rc = entry->dbf_info;
  4597. break;
  4598. }
  4599. }
  4600. mutex_unlock(&qeth_dbf_list_mutex);
  4601. return rc;
  4602. }
  4603. static int qeth_add_dbf_entry(struct qeth_card *card, char *name)
  4604. {
  4605. struct qeth_dbf_entry *new_entry;
  4606. card->debug = debug_register(name, 2, 1, 8);
  4607. if (!card->debug) {
  4608. QETH_DBF_TEXT_(SETUP, 2, "%s", "qcdbf");
  4609. goto err;
  4610. }
  4611. if (debug_register_view(card->debug, &debug_hex_ascii_view))
  4612. goto err_dbg;
  4613. new_entry = kzalloc(sizeof(struct qeth_dbf_entry), GFP_KERNEL);
  4614. if (!new_entry)
  4615. goto err_dbg;
  4616. strncpy(new_entry->dbf_name, name, DBF_NAME_LEN);
  4617. new_entry->dbf_info = card->debug;
  4618. mutex_lock(&qeth_dbf_list_mutex);
  4619. list_add(&new_entry->dbf_list, &qeth_dbf_list);
  4620. mutex_unlock(&qeth_dbf_list_mutex);
  4621. return 0;
  4622. err_dbg:
  4623. debug_unregister(card->debug);
  4624. err:
  4625. return -ENOMEM;
  4626. }
  4627. static void qeth_clear_dbf_list(void)
  4628. {
  4629. struct qeth_dbf_entry *entry, *tmp;
  4630. mutex_lock(&qeth_dbf_list_mutex);
  4631. list_for_each_entry_safe(entry, tmp, &qeth_dbf_list, dbf_list) {
  4632. list_del(&entry->dbf_list);
  4633. debug_unregister(entry->dbf_info);
  4634. kfree(entry);
  4635. }
  4636. mutex_unlock(&qeth_dbf_list_mutex);
  4637. }
  4638. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  4639. {
  4640. struct qeth_card *card;
  4641. struct device *dev;
  4642. int rc;
  4643. unsigned long flags;
  4644. char dbf_name[DBF_NAME_LEN];
  4645. QETH_DBF_TEXT(SETUP, 2, "probedev");
  4646. dev = &gdev->dev;
  4647. if (!get_device(dev))
  4648. return -ENODEV;
  4649. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  4650. card = qeth_alloc_card();
  4651. if (!card) {
  4652. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  4653. rc = -ENOMEM;
  4654. goto err_dev;
  4655. }
  4656. snprintf(dbf_name, sizeof(dbf_name), "qeth_card_%s",
  4657. dev_name(&gdev->dev));
  4658. card->debug = qeth_get_dbf_entry(dbf_name);
  4659. if (!card->debug) {
  4660. rc = qeth_add_dbf_entry(card, dbf_name);
  4661. if (rc)
  4662. goto err_card;
  4663. }
  4664. card->read.ccwdev = gdev->cdev[0];
  4665. card->write.ccwdev = gdev->cdev[1];
  4666. card->data.ccwdev = gdev->cdev[2];
  4667. dev_set_drvdata(&gdev->dev, card);
  4668. card->gdev = gdev;
  4669. gdev->cdev[0]->handler = qeth_irq;
  4670. gdev->cdev[1]->handler = qeth_irq;
  4671. gdev->cdev[2]->handler = qeth_irq;
  4672. rc = qeth_determine_card_type(card);
  4673. if (rc) {
  4674. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4675. goto err_card;
  4676. }
  4677. rc = qeth_setup_card(card);
  4678. if (rc) {
  4679. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  4680. goto err_card;
  4681. }
  4682. if (card->info.type == QETH_CARD_TYPE_OSN)
  4683. gdev->dev.type = &qeth_osn_devtype;
  4684. else
  4685. gdev->dev.type = &qeth_generic_devtype;
  4686. switch (card->info.type) {
  4687. case QETH_CARD_TYPE_OSN:
  4688. case QETH_CARD_TYPE_OSM:
  4689. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  4690. if (rc)
  4691. goto err_card;
  4692. rc = card->discipline->setup(card->gdev);
  4693. if (rc)
  4694. goto err_disc;
  4695. case QETH_CARD_TYPE_OSD:
  4696. case QETH_CARD_TYPE_OSX:
  4697. default:
  4698. break;
  4699. }
  4700. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4701. list_add_tail(&card->list, &qeth_core_card_list.list);
  4702. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4703. qeth_determine_capabilities(card);
  4704. return 0;
  4705. err_disc:
  4706. qeth_core_free_discipline(card);
  4707. err_card:
  4708. qeth_core_free_card(card);
  4709. err_dev:
  4710. put_device(dev);
  4711. return rc;
  4712. }
  4713. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  4714. {
  4715. unsigned long flags;
  4716. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4717. QETH_DBF_TEXT(SETUP, 2, "removedv");
  4718. if (card->discipline) {
  4719. card->discipline->remove(gdev);
  4720. qeth_core_free_discipline(card);
  4721. }
  4722. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4723. list_del(&card->list);
  4724. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4725. qeth_core_free_card(card);
  4726. dev_set_drvdata(&gdev->dev, NULL);
  4727. put_device(&gdev->dev);
  4728. return;
  4729. }
  4730. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  4731. {
  4732. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4733. int rc = 0;
  4734. int def_discipline;
  4735. if (!card->discipline) {
  4736. if (card->info.type == QETH_CARD_TYPE_IQD)
  4737. def_discipline = QETH_DISCIPLINE_LAYER3;
  4738. else
  4739. def_discipline = QETH_DISCIPLINE_LAYER2;
  4740. rc = qeth_core_load_discipline(card, def_discipline);
  4741. if (rc)
  4742. goto err;
  4743. rc = card->discipline->setup(card->gdev);
  4744. if (rc)
  4745. goto err;
  4746. }
  4747. rc = card->discipline->set_online(gdev);
  4748. err:
  4749. return rc;
  4750. }
  4751. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  4752. {
  4753. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4754. return card->discipline->set_offline(gdev);
  4755. }
  4756. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  4757. {
  4758. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4759. if (card->discipline && card->discipline->shutdown)
  4760. card->discipline->shutdown(gdev);
  4761. }
  4762. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  4763. {
  4764. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4765. if (card->discipline && card->discipline->prepare)
  4766. return card->discipline->prepare(gdev);
  4767. return 0;
  4768. }
  4769. static void qeth_core_complete(struct ccwgroup_device *gdev)
  4770. {
  4771. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4772. if (card->discipline && card->discipline->complete)
  4773. card->discipline->complete(gdev);
  4774. }
  4775. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  4776. {
  4777. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4778. if (card->discipline && card->discipline->freeze)
  4779. return card->discipline->freeze(gdev);
  4780. return 0;
  4781. }
  4782. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  4783. {
  4784. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4785. if (card->discipline && card->discipline->thaw)
  4786. return card->discipline->thaw(gdev);
  4787. return 0;
  4788. }
  4789. static int qeth_core_restore(struct ccwgroup_device *gdev)
  4790. {
  4791. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4792. if (card->discipline && card->discipline->restore)
  4793. return card->discipline->restore(gdev);
  4794. return 0;
  4795. }
  4796. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  4797. .driver = {
  4798. .owner = THIS_MODULE,
  4799. .name = "qeth",
  4800. },
  4801. .setup = qeth_core_probe_device,
  4802. .remove = qeth_core_remove_device,
  4803. .set_online = qeth_core_set_online,
  4804. .set_offline = qeth_core_set_offline,
  4805. .shutdown = qeth_core_shutdown,
  4806. .prepare = qeth_core_prepare,
  4807. .complete = qeth_core_complete,
  4808. .freeze = qeth_core_freeze,
  4809. .thaw = qeth_core_thaw,
  4810. .restore = qeth_core_restore,
  4811. };
  4812. static ssize_t qeth_core_driver_group_store(struct device_driver *ddrv,
  4813. const char *buf, size_t count)
  4814. {
  4815. int err;
  4816. err = ccwgroup_create_dev(qeth_core_root_dev,
  4817. &qeth_core_ccwgroup_driver, 3, buf);
  4818. return err ? err : count;
  4819. }
  4820. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  4821. static struct attribute *qeth_drv_attrs[] = {
  4822. &driver_attr_group.attr,
  4823. NULL,
  4824. };
  4825. static struct attribute_group qeth_drv_attr_group = {
  4826. .attrs = qeth_drv_attrs,
  4827. };
  4828. static const struct attribute_group *qeth_drv_attr_groups[] = {
  4829. &qeth_drv_attr_group,
  4830. NULL,
  4831. };
  4832. static struct {
  4833. const char str[ETH_GSTRING_LEN];
  4834. } qeth_ethtool_stats_keys[] = {
  4835. /* 0 */{"rx skbs"},
  4836. {"rx buffers"},
  4837. {"tx skbs"},
  4838. {"tx buffers"},
  4839. {"tx skbs no packing"},
  4840. {"tx buffers no packing"},
  4841. {"tx skbs packing"},
  4842. {"tx buffers packing"},
  4843. {"tx sg skbs"},
  4844. {"tx sg frags"},
  4845. /* 10 */{"rx sg skbs"},
  4846. {"rx sg frags"},
  4847. {"rx sg page allocs"},
  4848. {"tx large kbytes"},
  4849. {"tx large count"},
  4850. {"tx pk state ch n->p"},
  4851. {"tx pk state ch p->n"},
  4852. {"tx pk watermark low"},
  4853. {"tx pk watermark high"},
  4854. {"queue 0 buffer usage"},
  4855. /* 20 */{"queue 1 buffer usage"},
  4856. {"queue 2 buffer usage"},
  4857. {"queue 3 buffer usage"},
  4858. {"rx poll time"},
  4859. {"rx poll count"},
  4860. {"rx do_QDIO time"},
  4861. {"rx do_QDIO count"},
  4862. {"tx handler time"},
  4863. {"tx handler count"},
  4864. {"tx time"},
  4865. /* 30 */{"tx count"},
  4866. {"tx do_QDIO time"},
  4867. {"tx do_QDIO count"},
  4868. {"tx csum"},
  4869. {"tx lin"},
  4870. {"cq handler count"},
  4871. {"cq handler time"}
  4872. };
  4873. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4874. {
  4875. switch (stringset) {
  4876. case ETH_SS_STATS:
  4877. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4878. default:
  4879. return -EINVAL;
  4880. }
  4881. }
  4882. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4883. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4884. struct ethtool_stats *stats, u64 *data)
  4885. {
  4886. struct qeth_card *card = dev->ml_priv;
  4887. data[0] = card->stats.rx_packets -
  4888. card->perf_stats.initial_rx_packets;
  4889. data[1] = card->perf_stats.bufs_rec;
  4890. data[2] = card->stats.tx_packets -
  4891. card->perf_stats.initial_tx_packets;
  4892. data[3] = card->perf_stats.bufs_sent;
  4893. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4894. - card->perf_stats.skbs_sent_pack;
  4895. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4896. data[6] = card->perf_stats.skbs_sent_pack;
  4897. data[7] = card->perf_stats.bufs_sent_pack;
  4898. data[8] = card->perf_stats.sg_skbs_sent;
  4899. data[9] = card->perf_stats.sg_frags_sent;
  4900. data[10] = card->perf_stats.sg_skbs_rx;
  4901. data[11] = card->perf_stats.sg_frags_rx;
  4902. data[12] = card->perf_stats.sg_alloc_page_rx;
  4903. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4904. data[14] = card->perf_stats.large_send_cnt;
  4905. data[15] = card->perf_stats.sc_dp_p;
  4906. data[16] = card->perf_stats.sc_p_dp;
  4907. data[17] = QETH_LOW_WATERMARK_PACK;
  4908. data[18] = QETH_HIGH_WATERMARK_PACK;
  4909. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4910. data[20] = (card->qdio.no_out_queues > 1) ?
  4911. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4912. data[21] = (card->qdio.no_out_queues > 2) ?
  4913. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4914. data[22] = (card->qdio.no_out_queues > 3) ?
  4915. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4916. data[23] = card->perf_stats.inbound_time;
  4917. data[24] = card->perf_stats.inbound_cnt;
  4918. data[25] = card->perf_stats.inbound_do_qdio_time;
  4919. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4920. data[27] = card->perf_stats.outbound_handler_time;
  4921. data[28] = card->perf_stats.outbound_handler_cnt;
  4922. data[29] = card->perf_stats.outbound_time;
  4923. data[30] = card->perf_stats.outbound_cnt;
  4924. data[31] = card->perf_stats.outbound_do_qdio_time;
  4925. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4926. data[33] = card->perf_stats.tx_csum;
  4927. data[34] = card->perf_stats.tx_lin;
  4928. data[35] = card->perf_stats.cq_cnt;
  4929. data[36] = card->perf_stats.cq_time;
  4930. }
  4931. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4932. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4933. {
  4934. switch (stringset) {
  4935. case ETH_SS_STATS:
  4936. memcpy(data, &qeth_ethtool_stats_keys,
  4937. sizeof(qeth_ethtool_stats_keys));
  4938. break;
  4939. default:
  4940. WARN_ON(1);
  4941. break;
  4942. }
  4943. }
  4944. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4945. void qeth_core_get_drvinfo(struct net_device *dev,
  4946. struct ethtool_drvinfo *info)
  4947. {
  4948. struct qeth_card *card = dev->ml_priv;
  4949. strlcpy(info->driver, card->options.layer2 ? "qeth_l2" : "qeth_l3",
  4950. sizeof(info->driver));
  4951. strlcpy(info->version, "1.0", sizeof(info->version));
  4952. strlcpy(info->fw_version, card->info.mcl_level,
  4953. sizeof(info->fw_version));
  4954. snprintf(info->bus_info, sizeof(info->bus_info), "%s/%s/%s",
  4955. CARD_RDEV_ID(card), CARD_WDEV_ID(card), CARD_DDEV_ID(card));
  4956. }
  4957. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4958. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4959. struct ethtool_cmd *ecmd)
  4960. {
  4961. struct qeth_card *card = netdev->ml_priv;
  4962. enum qeth_link_types link_type;
  4963. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4964. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4965. else
  4966. link_type = card->info.link_type;
  4967. ecmd->transceiver = XCVR_INTERNAL;
  4968. ecmd->supported = SUPPORTED_Autoneg;
  4969. ecmd->advertising = ADVERTISED_Autoneg;
  4970. ecmd->duplex = DUPLEX_FULL;
  4971. ecmd->autoneg = AUTONEG_ENABLE;
  4972. switch (link_type) {
  4973. case QETH_LINK_TYPE_FAST_ETH:
  4974. case QETH_LINK_TYPE_LANE_ETH100:
  4975. ecmd->supported |= SUPPORTED_10baseT_Half |
  4976. SUPPORTED_10baseT_Full |
  4977. SUPPORTED_100baseT_Half |
  4978. SUPPORTED_100baseT_Full |
  4979. SUPPORTED_TP;
  4980. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4981. ADVERTISED_10baseT_Full |
  4982. ADVERTISED_100baseT_Half |
  4983. ADVERTISED_100baseT_Full |
  4984. ADVERTISED_TP;
  4985. ecmd->speed = SPEED_100;
  4986. ecmd->port = PORT_TP;
  4987. break;
  4988. case QETH_LINK_TYPE_GBIT_ETH:
  4989. case QETH_LINK_TYPE_LANE_ETH1000:
  4990. ecmd->supported |= SUPPORTED_10baseT_Half |
  4991. SUPPORTED_10baseT_Full |
  4992. SUPPORTED_100baseT_Half |
  4993. SUPPORTED_100baseT_Full |
  4994. SUPPORTED_1000baseT_Half |
  4995. SUPPORTED_1000baseT_Full |
  4996. SUPPORTED_FIBRE;
  4997. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4998. ADVERTISED_10baseT_Full |
  4999. ADVERTISED_100baseT_Half |
  5000. ADVERTISED_100baseT_Full |
  5001. ADVERTISED_1000baseT_Half |
  5002. ADVERTISED_1000baseT_Full |
  5003. ADVERTISED_FIBRE;
  5004. ecmd->speed = SPEED_1000;
  5005. ecmd->port = PORT_FIBRE;
  5006. break;
  5007. case QETH_LINK_TYPE_10GBIT_ETH:
  5008. ecmd->supported |= SUPPORTED_10baseT_Half |
  5009. SUPPORTED_10baseT_Full |
  5010. SUPPORTED_100baseT_Half |
  5011. SUPPORTED_100baseT_Full |
  5012. SUPPORTED_1000baseT_Half |
  5013. SUPPORTED_1000baseT_Full |
  5014. SUPPORTED_10000baseT_Full |
  5015. SUPPORTED_FIBRE;
  5016. ecmd->advertising |= ADVERTISED_10baseT_Half |
  5017. ADVERTISED_10baseT_Full |
  5018. ADVERTISED_100baseT_Half |
  5019. ADVERTISED_100baseT_Full |
  5020. ADVERTISED_1000baseT_Half |
  5021. ADVERTISED_1000baseT_Full |
  5022. ADVERTISED_10000baseT_Full |
  5023. ADVERTISED_FIBRE;
  5024. ecmd->speed = SPEED_10000;
  5025. ecmd->port = PORT_FIBRE;
  5026. break;
  5027. default:
  5028. ecmd->supported |= SUPPORTED_10baseT_Half |
  5029. SUPPORTED_10baseT_Full |
  5030. SUPPORTED_TP;
  5031. ecmd->advertising |= ADVERTISED_10baseT_Half |
  5032. ADVERTISED_10baseT_Full |
  5033. ADVERTISED_TP;
  5034. ecmd->speed = SPEED_10;
  5035. ecmd->port = PORT_TP;
  5036. }
  5037. return 0;
  5038. }
  5039. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  5040. static int __init qeth_core_init(void)
  5041. {
  5042. int rc;
  5043. pr_info("loading core functions\n");
  5044. INIT_LIST_HEAD(&qeth_core_card_list.list);
  5045. INIT_LIST_HEAD(&qeth_dbf_list);
  5046. rwlock_init(&qeth_core_card_list.rwlock);
  5047. mutex_init(&qeth_mod_mutex);
  5048. qeth_wq = create_singlethread_workqueue("qeth_wq");
  5049. rc = qeth_register_dbf_views();
  5050. if (rc)
  5051. goto out_err;
  5052. qeth_core_root_dev = root_device_register("qeth");
  5053. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  5054. if (rc)
  5055. goto register_err;
  5056. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  5057. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  5058. if (!qeth_core_header_cache) {
  5059. rc = -ENOMEM;
  5060. goto slab_err;
  5061. }
  5062. qeth_qdio_outbuf_cache = kmem_cache_create("qeth_buf",
  5063. sizeof(struct qeth_qdio_out_buffer), 0, 0, NULL);
  5064. if (!qeth_qdio_outbuf_cache) {
  5065. rc = -ENOMEM;
  5066. goto cqslab_err;
  5067. }
  5068. rc = ccw_driver_register(&qeth_ccw_driver);
  5069. if (rc)
  5070. goto ccw_err;
  5071. qeth_core_ccwgroup_driver.driver.groups = qeth_drv_attr_groups;
  5072. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  5073. if (rc)
  5074. goto ccwgroup_err;
  5075. return 0;
  5076. ccwgroup_err:
  5077. ccw_driver_unregister(&qeth_ccw_driver);
  5078. ccw_err:
  5079. kmem_cache_destroy(qeth_qdio_outbuf_cache);
  5080. cqslab_err:
  5081. kmem_cache_destroy(qeth_core_header_cache);
  5082. slab_err:
  5083. root_device_unregister(qeth_core_root_dev);
  5084. register_err:
  5085. qeth_unregister_dbf_views();
  5086. out_err:
  5087. pr_err("Initializing the qeth device driver failed\n");
  5088. return rc;
  5089. }
  5090. static void __exit qeth_core_exit(void)
  5091. {
  5092. qeth_clear_dbf_list();
  5093. destroy_workqueue(qeth_wq);
  5094. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  5095. ccw_driver_unregister(&qeth_ccw_driver);
  5096. kmem_cache_destroy(qeth_qdio_outbuf_cache);
  5097. kmem_cache_destroy(qeth_core_header_cache);
  5098. root_device_unregister(qeth_core_root_dev);
  5099. qeth_unregister_dbf_views();
  5100. pr_info("core functions removed\n");
  5101. }
  5102. module_init(qeth_core_init);
  5103. module_exit(qeth_core_exit);
  5104. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  5105. MODULE_DESCRIPTION("qeth core functions");
  5106. MODULE_LICENSE("GPL");