fw.c 24 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2013 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include "../wifi.h"
  30. #include "../pci.h"
  31. #include "../base.h"
  32. #include "reg.h"
  33. #include "def.h"
  34. #include "fw.h"
  35. #include <linux/kmemleak.h>
  36. static void _rtl88e_enable_fw_download(struct ieee80211_hw *hw, bool enable)
  37. {
  38. struct rtl_priv *rtlpriv = rtl_priv(hw);
  39. u8 tmp;
  40. if (enable) {
  41. tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  42. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp | 0x04);
  43. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
  44. rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01);
  45. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2);
  46. rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7);
  47. } else {
  48. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
  49. rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe);
  50. rtl_write_byte(rtlpriv, REG_MCUFWDL + 1, 0x00);
  51. }
  52. }
  53. static void _rtl88e_fw_block_write(struct ieee80211_hw *hw,
  54. const u8 *buffer, u32 size)
  55. {
  56. struct rtl_priv *rtlpriv = rtl_priv(hw);
  57. u32 blk_sz = sizeof(u32);
  58. u8 *buf_ptr = (u8 *)buffer;
  59. u32 *pu4BytePtr = (u32 *)buffer;
  60. u32 i, offset, blk_cnt, remain;
  61. blk_cnt = size / blk_sz;
  62. remain = size % blk_sz;
  63. for (i = 0; i < blk_cnt; i++) {
  64. offset = i * blk_sz;
  65. rtl_write_dword(rtlpriv, (FW_8192C_START_ADDRESS + offset),
  66. *(pu4BytePtr + i));
  67. }
  68. if (remain) {
  69. offset = blk_cnt * blk_sz;
  70. buf_ptr += offset;
  71. for (i = 0; i < remain; i++) {
  72. rtl_write_byte(rtlpriv, (FW_8192C_START_ADDRESS +
  73. offset + i), *(buf_ptr + i));
  74. }
  75. }
  76. }
  77. static void _rtl88e_fw_page_write(struct ieee80211_hw *hw,
  78. u32 page, const u8 *buffer, u32 size)
  79. {
  80. struct rtl_priv *rtlpriv = rtl_priv(hw);
  81. u8 value8;
  82. u8 u8page = (u8) (page & 0x07);
  83. value8 = (rtl_read_byte(rtlpriv, REG_MCUFWDL + 2) & 0xF8) | u8page;
  84. rtl_write_byte(rtlpriv, (REG_MCUFWDL + 2), value8);
  85. _rtl88e_fw_block_write(hw, buffer, size);
  86. }
  87. static void _rtl88e_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
  88. {
  89. u32 fwlen = *pfwlen;
  90. u8 remain = (u8) (fwlen % 4);
  91. remain = (remain == 0) ? 0 : (4 - remain);
  92. while (remain > 0) {
  93. pfwbuf[fwlen] = 0;
  94. fwlen++;
  95. remain--;
  96. }
  97. *pfwlen = fwlen;
  98. }
  99. static void _rtl88e_write_fw(struct ieee80211_hw *hw,
  100. enum version_8188e version, u8 *buffer, u32 size)
  101. {
  102. struct rtl_priv *rtlpriv = rtl_priv(hw);
  103. u8 *buf_ptr = (u8 *)buffer;
  104. u32 page_no, remain;
  105. u32 page, offset;
  106. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "FW size is %d bytes,\n", size);
  107. _rtl88e_fill_dummy(buf_ptr, &size);
  108. page_no = size / FW_8192C_PAGE_SIZE;
  109. remain = size % FW_8192C_PAGE_SIZE;
  110. if (page_no > 8) {
  111. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  112. "Page numbers should not greater then 8\n");
  113. }
  114. for (page = 0; page < page_no; page++) {
  115. offset = page * FW_8192C_PAGE_SIZE;
  116. _rtl88e_fw_page_write(hw, page, (buf_ptr + offset),
  117. FW_8192C_PAGE_SIZE);
  118. }
  119. if (remain) {
  120. offset = page_no * FW_8192C_PAGE_SIZE;
  121. page = page_no;
  122. _rtl88e_fw_page_write(hw, page, (buf_ptr + offset), remain);
  123. }
  124. }
  125. static int _rtl88e_fw_free_to_go(struct ieee80211_hw *hw)
  126. {
  127. struct rtl_priv *rtlpriv = rtl_priv(hw);
  128. int err = -EIO;
  129. u32 counter = 0;
  130. u32 value32;
  131. do {
  132. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  133. } while ((counter++ < FW_8192C_POLLING_TIMEOUT_COUNT) &&
  134. (!(value32 & FWDL_CHKSUM_RPT)));
  135. if (counter >= FW_8192C_POLLING_TIMEOUT_COUNT) {
  136. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  137. "chksum report faill ! REG_MCUFWDL:0x%08x .\n",
  138. value32);
  139. goto exit;
  140. }
  141. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  142. "Checksum report OK ! REG_MCUFWDL:0x%08x .\n", value32);
  143. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  144. value32 |= MCUFWDL_RDY;
  145. value32 &= ~WINTINI_RDY;
  146. rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
  147. rtl88e_firmware_selfreset(hw);
  148. counter = 0;
  149. do {
  150. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  151. if (value32 & WINTINI_RDY) {
  152. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  153. "Polling FW ready success!! REG_MCUFWDL:0x%08x.\n",
  154. value32);
  155. err = 0;
  156. goto exit;
  157. }
  158. udelay(FW_8192C_POLLING_DELAY);
  159. } while (counter++ < FW_8192C_POLLING_TIMEOUT_COUNT);
  160. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  161. "Polling FW ready fail!! REG_MCUFWDL:0x%08x .\n", value32);
  162. exit:
  163. return err;
  164. }
  165. int rtl88e_download_fw(struct ieee80211_hw *hw, bool buse_wake_on_wlan_fw)
  166. {
  167. struct rtl_priv *rtlpriv = rtl_priv(hw);
  168. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  169. struct rtl92c_firmware_header *pfwheader;
  170. u8 *pfwdata;
  171. u32 fwsize;
  172. int err;
  173. enum version_8188e version = rtlhal->version;
  174. if (!rtlhal->pfirmware)
  175. return 1;
  176. pfwheader = (struct rtl92c_firmware_header *)rtlhal->pfirmware;
  177. pfwdata = (u8 *)rtlhal->pfirmware;
  178. fwsize = rtlhal->fwsize;
  179. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
  180. "normal Firmware SIZE %d\n", fwsize);
  181. if (IS_FW_HEADER_EXIST(pfwheader)) {
  182. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
  183. "Firmware Version(%d), Signature(%#x), Size(%d)\n",
  184. pfwheader->version, pfwheader->signature,
  185. (int)sizeof(struct rtl92c_firmware_header));
  186. pfwdata = pfwdata + sizeof(struct rtl92c_firmware_header);
  187. fwsize = fwsize - sizeof(struct rtl92c_firmware_header);
  188. }
  189. if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) {
  190. rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
  191. rtl88e_firmware_selfreset(hw);
  192. }
  193. _rtl88e_enable_fw_download(hw, true);
  194. _rtl88e_write_fw(hw, version, pfwdata, fwsize);
  195. _rtl88e_enable_fw_download(hw, false);
  196. err = _rtl88e_fw_free_to_go(hw);
  197. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
  198. "Firmware is%s ready to run!\n", err ? " not" : "");
  199. return 0;
  200. }
  201. static bool _rtl88e_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
  202. {
  203. struct rtl_priv *rtlpriv = rtl_priv(hw);
  204. u8 val_hmetfr;
  205. val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
  206. if (((val_hmetfr >> boxnum) & BIT(0)) == 0)
  207. return true;
  208. return false;
  209. }
  210. static void _rtl88e_fill_h2c_command(struct ieee80211_hw *hw,
  211. u8 element_id, u32 cmd_len,
  212. u8 *cmd_b)
  213. {
  214. struct rtl_priv *rtlpriv = rtl_priv(hw);
  215. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  216. u8 boxnum;
  217. u16 box_reg = 0, box_extreg = 0;
  218. u8 u1b_tmp;
  219. bool isfw_read = false;
  220. u8 buf_index = 0;
  221. bool write_sucess = false;
  222. u8 wait_h2c_limit = 100;
  223. u8 wait_writeh2c_limit = 100;
  224. u8 boxc[4], boxext[2];
  225. u32 h2c_waitcounter = 0;
  226. unsigned long flag;
  227. u8 idx;
  228. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "come in\n");
  229. while (true) {
  230. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  231. if (rtlhal->h2c_setinprogress) {
  232. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  233. "H2C set in progress! Wait to set..element_id(%d).\n",
  234. element_id);
  235. while (rtlhal->h2c_setinprogress) {
  236. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
  237. flag);
  238. h2c_waitcounter++;
  239. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  240. "Wait 100 us (%d times)...\n",
  241. h2c_waitcounter);
  242. udelay(100);
  243. if (h2c_waitcounter > 1000)
  244. return;
  245. spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
  246. flag);
  247. }
  248. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  249. } else {
  250. rtlhal->h2c_setinprogress = true;
  251. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  252. break;
  253. }
  254. }
  255. while (!write_sucess) {
  256. wait_writeh2c_limit--;
  257. if (wait_writeh2c_limit == 0) {
  258. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  259. "Write H2C fail because no trigger for FW INT!\n");
  260. break;
  261. }
  262. boxnum = rtlhal->last_hmeboxnum;
  263. switch (boxnum) {
  264. case 0:
  265. box_reg = REG_HMEBOX_0;
  266. box_extreg = REG_HMEBOX_EXT_0;
  267. break;
  268. case 1:
  269. box_reg = REG_HMEBOX_1;
  270. box_extreg = REG_HMEBOX_EXT_1;
  271. break;
  272. case 2:
  273. box_reg = REG_HMEBOX_2;
  274. box_extreg = REG_HMEBOX_EXT_2;
  275. break;
  276. case 3:
  277. box_reg = REG_HMEBOX_3;
  278. box_extreg = REG_HMEBOX_EXT_3;
  279. break;
  280. default:
  281. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  282. "switch case not processed\n");
  283. break;
  284. }
  285. isfw_read = _rtl88e_check_fw_read_last_h2c(hw, boxnum);
  286. while (!isfw_read) {
  287. wait_h2c_limit--;
  288. if (wait_h2c_limit == 0) {
  289. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  290. "Wating too long for FW read "
  291. "clear HMEBox(%d)!\n", boxnum);
  292. break;
  293. }
  294. udelay(10);
  295. isfw_read = _rtl88e_check_fw_read_last_h2c(hw, boxnum);
  296. u1b_tmp = rtl_read_byte(rtlpriv, 0x130);
  297. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  298. "Wating for FW read clear HMEBox(%d)!!! "
  299. "0x130 = %2x\n", boxnum, u1b_tmp);
  300. }
  301. if (!isfw_read) {
  302. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  303. "Write H2C register BOX[%d] fail!!!!! "
  304. "Fw do not read.\n", boxnum);
  305. break;
  306. }
  307. memset(boxc, 0, sizeof(boxc));
  308. memset(boxext, 0, sizeof(boxext));
  309. boxc[0] = element_id;
  310. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  311. "Write element_id box_reg(%4x) = %2x\n",
  312. box_reg, element_id);
  313. switch (cmd_len) {
  314. case 1:
  315. case 2:
  316. case 3:
  317. /*boxc[0] &= ~(BIT(7));*/
  318. memcpy((u8 *)(boxc) + 1, cmd_b + buf_index, cmd_len);
  319. for (idx = 0; idx < 4; idx++)
  320. rtl_write_byte(rtlpriv, box_reg+idx, boxc[idx]);
  321. break;
  322. case 4:
  323. case 5:
  324. case 6:
  325. case 7:
  326. /*boxc[0] |= (BIT(7));*/
  327. memcpy((u8 *)(boxext), cmd_b + buf_index+3, cmd_len-3);
  328. memcpy((u8 *)(boxc) + 1, cmd_b + buf_index, 3);
  329. for (idx = 0; idx < 2; idx++) {
  330. rtl_write_byte(rtlpriv, box_extreg + idx,
  331. boxext[idx]);
  332. }
  333. for (idx = 0; idx < 4; idx++) {
  334. rtl_write_byte(rtlpriv, box_reg + idx,
  335. boxc[idx]);
  336. }
  337. break;
  338. default:
  339. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  340. "switch case not processed\n");
  341. break;
  342. }
  343. write_sucess = true;
  344. rtlhal->last_hmeboxnum = boxnum + 1;
  345. if (rtlhal->last_hmeboxnum == 4)
  346. rtlhal->last_hmeboxnum = 0;
  347. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  348. "pHalData->last_hmeboxnum = %d\n",
  349. rtlhal->last_hmeboxnum);
  350. }
  351. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  352. rtlhal->h2c_setinprogress = false;
  353. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  354. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n");
  355. }
  356. void rtl88e_fill_h2c_cmd(struct ieee80211_hw *hw,
  357. u8 element_id, u32 cmd_len, u8 *cmd_b)
  358. {
  359. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  360. u32 tmp_cmdbuf[2];
  361. if (rtlhal->fw_ready == false) {
  362. RT_ASSERT(false, "fail H2C cmd - Fw download fail!!!\n");
  363. return;
  364. }
  365. memset(tmp_cmdbuf, 0, 8);
  366. memcpy(tmp_cmdbuf, cmd_b, cmd_len);
  367. _rtl88e_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf);
  368. return;
  369. }
  370. void rtl88e_firmware_selfreset(struct ieee80211_hw *hw)
  371. {
  372. u8 u1b_tmp;
  373. struct rtl_priv *rtlpriv = rtl_priv(hw);
  374. u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
  375. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
  376. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp | BIT(2)));
  377. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
  378. "8051Reset88E(): 8051 reset success.\n");
  379. }
  380. void rtl88e_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
  381. {
  382. struct rtl_priv *rtlpriv = rtl_priv(hw);
  383. u8 u1_h2c_set_pwrmode[H2C_88E_PWEMODE_LENGTH] = { 0 };
  384. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  385. u8 power_state = 0;
  386. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "FW LPS mode = %d\n", mode);
  387. SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, ((mode) ? 1 : 0));
  388. SET_H2CCMD_PWRMODE_PARM_RLBM(u1_h2c_set_pwrmode, 0);
  389. SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode,
  390. (rtlpriv->mac80211.p2p) ?
  391. ppsc->smart_ps : 1);
  392. SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(u1_h2c_set_pwrmode,
  393. ppsc->reg_max_lps_awakeintvl);
  394. SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1_h2c_set_pwrmode, 0);
  395. if (mode == FW_PS_ACTIVE_MODE)
  396. power_state |= FW_PWR_STATE_ACTIVE;
  397. else
  398. power_state |= FW_PWR_STATE_RF_OFF;
  399. SET_H2CCMD_PWRMODE_PARM_PWR_STATE(u1_h2c_set_pwrmode, power_state);
  400. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  401. "rtl92c_set_fw_pwrmode(): u1_h2c_set_pwrmode\n",
  402. u1_h2c_set_pwrmode, H2C_88E_PWEMODE_LENGTH);
  403. rtl88e_fill_h2c_cmd(hw, H2C_88E_SETPWRMODE, H2C_88E_PWEMODE_LENGTH,
  404. u1_h2c_set_pwrmode);
  405. }
  406. void rtl88e_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
  407. {
  408. u8 u1_joinbssrpt_parm[1] = { 0 };
  409. SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus);
  410. rtl88e_fill_h2c_cmd(hw, H2C_88E_JOINBSSRPT, 1, u1_joinbssrpt_parm);
  411. }
  412. void rtl88e_set_fw_ap_off_load_cmd(struct ieee80211_hw *hw,
  413. u8 ap_offload_enable)
  414. {
  415. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  416. u8 u1_apoffload_parm[H2C_88E_AP_OFFLOAD_LENGTH] = { 0 };
  417. SET_H2CCMD_AP_OFFLOAD_ON(u1_apoffload_parm, ap_offload_enable);
  418. SET_H2CCMD_AP_OFFLOAD_HIDDEN(u1_apoffload_parm, mac->hiddenssid);
  419. SET_H2CCMD_AP_OFFLOAD_DENYANY(u1_apoffload_parm, 0);
  420. rtl88e_fill_h2c_cmd(hw, H2C_88E_AP_OFFLOAD, H2C_88E_AP_OFFLOAD_LENGTH,
  421. u1_apoffload_parm);
  422. }
  423. static bool _rtl88e_cmd_send_packet(struct ieee80211_hw *hw,
  424. struct sk_buff *skb)
  425. {
  426. struct rtl_priv *rtlpriv = rtl_priv(hw);
  427. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  428. struct rtl8192_tx_ring *ring;
  429. struct rtl_tx_desc *pdesc;
  430. struct sk_buff *pskb = NULL;
  431. unsigned long flags;
  432. ring = &rtlpci->tx_ring[BEACON_QUEUE];
  433. pskb = __skb_dequeue(&ring->queue);
  434. if (pskb)
  435. kfree_skb(pskb);
  436. spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  437. pdesc = &ring->desc[0];
  438. rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, 1, 1, skb);
  439. __skb_queue_tail(&ring->queue, skb);
  440. spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  441. rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
  442. return true;
  443. }
  444. #define BEACON_PG 0 /* ->1 */
  445. #define PSPOLL_PG 2
  446. #define NULL_PG 3
  447. #define PROBERSP_PG 4 /* ->5 */
  448. #define TOTAL_RESERVED_PKT_LEN 768
  449. static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
  450. /* page 0 beacon */
  451. 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
  452. 0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  453. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x50, 0x08,
  454. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  455. 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
  456. 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
  457. 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
  458. 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
  459. 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
  460. 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
  461. 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  462. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  463. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  464. 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
  465. 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  466. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  467. /* page 1 beacon */
  468. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  469. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  470. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  471. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  472. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  473. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  474. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  475. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  476. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  477. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  478. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  479. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  480. 0x10, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x10, 0x00,
  481. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  482. 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  483. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  484. /* page 2 ps-poll */
  485. 0xA4, 0x10, 0x01, 0xC0, 0x00, 0x40, 0x10, 0x10,
  486. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  487. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  488. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  489. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  490. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  491. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  492. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  493. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  494. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  495. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  496. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  497. 0x18, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
  498. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
  499. 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  500. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  501. /* page 3 null */
  502. 0x48, 0x01, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
  503. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  504. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
  505. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  506. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  507. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  508. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  509. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  510. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  511. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  512. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  513. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  514. 0x72, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
  515. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
  516. 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  517. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  518. /* page 4 probe_resp */
  519. 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
  520. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  521. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
  522. 0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
  523. 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
  524. 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
  525. 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
  526. 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
  527. 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
  528. 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
  529. 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  530. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  531. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  532. 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
  533. 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  534. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  535. /* page 5 probe_resp */
  536. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  537. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  538. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  539. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  540. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  541. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  542. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  543. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  544. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  545. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  546. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  547. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  548. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  549. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  550. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  551. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  552. };
  553. void rtl88e_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
  554. {
  555. struct rtl_priv *rtlpriv = rtl_priv(hw);
  556. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  557. struct sk_buff *skb = NULL;
  558. u32 totalpacketlen;
  559. u8 u1RsvdPageLoc[5] = { 0 };
  560. u8 *beacon;
  561. u8 *pspoll;
  562. u8 *nullfunc;
  563. u8 *probersp;
  564. /*---------------------------------------------------------
  565. * (1) beacon
  566. *---------------------------------------------------------
  567. */
  568. beacon = &reserved_page_packet[BEACON_PG * 128];
  569. SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
  570. SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
  571. /*-------------------------------------------------------
  572. * (2) ps-poll
  573. *--------------------------------------------------------
  574. */
  575. pspoll = &reserved_page_packet[PSPOLL_PG * 128];
  576. SET_80211_PS_POLL_AID(pspoll, (mac->assoc_id | 0xc000));
  577. SET_80211_PS_POLL_BSSID(pspoll, mac->bssid);
  578. SET_80211_PS_POLL_TA(pspoll, mac->mac_addr);
  579. SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1RsvdPageLoc, PSPOLL_PG);
  580. /*--------------------------------------------------------
  581. * (3) null data
  582. *---------------------------------------------------------
  583. */
  584. nullfunc = &reserved_page_packet[NULL_PG * 128];
  585. SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
  586. SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
  587. SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
  588. SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1RsvdPageLoc, NULL_PG);
  589. /*---------------------------------------------------------
  590. * (4) probe response
  591. *----------------------------------------------------------
  592. */
  593. probersp = &reserved_page_packet[PROBERSP_PG * 128];
  594. SET_80211_HDR_ADDRESS1(probersp, mac->bssid);
  595. SET_80211_HDR_ADDRESS2(probersp, mac->mac_addr);
  596. SET_80211_HDR_ADDRESS3(probersp, mac->bssid);
  597. SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1RsvdPageLoc, PROBERSP_PG);
  598. totalpacketlen = TOTAL_RESERVED_PKT_LEN;
  599. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
  600. "rtl88e_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
  601. &reserved_page_packet[0], totalpacketlen);
  602. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  603. "rtl88e_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
  604. u1RsvdPageLoc, 3);
  605. skb = dev_alloc_skb(totalpacketlen);
  606. if (!skb)
  607. return;
  608. kmemleak_not_leak(skb);
  609. memcpy(skb_put(skb, totalpacketlen),
  610. &reserved_page_packet, totalpacketlen);
  611. if (_rtl88e_cmd_send_packet(hw, skb)) {
  612. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  613. "Set RSVD page location to Fw.\n");
  614. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  615. "H2C_RSVDPAGE:\n", u1RsvdPageLoc, 3);
  616. rtl88e_fill_h2c_cmd(hw, H2C_88E_RSVDPAGE,
  617. sizeof(u1RsvdPageLoc), u1RsvdPageLoc);
  618. } else
  619. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  620. "Set RSVD page location to Fw FAIL!!!!!!.\n");
  621. }
  622. /*Shoud check FW support p2p or not.*/
  623. static void rtl88e_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw, u8 ctwindow)
  624. {
  625. u8 u1_ctwindow_period[1] = {ctwindow};
  626. rtl88e_fill_h2c_cmd(hw, H2C_88E_P2P_PS_CTW_CMD, 1, u1_ctwindow_period);
  627. }
  628. void rtl88e_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
  629. {
  630. struct rtl_priv *rtlpriv = rtl_priv(hw);
  631. struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
  632. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  633. struct rtl_p2p_ps_info *p2pinfo = &(rtlps->p2p_ps_info);
  634. struct p2p_ps_offload_t *p2p_ps_offload = &rtlhal->p2p_ps_offload;
  635. u8 i;
  636. u16 ctwindow;
  637. u32 start_time, tsf_low;
  638. switch (p2p_ps_state) {
  639. case P2P_PS_DISABLE:
  640. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_DISABLE\n");
  641. memset(p2p_ps_offload, 0, sizeof(struct p2p_ps_offload_t));
  642. break;
  643. case P2P_PS_ENABLE:
  644. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_ENABLE\n");
  645. /* update CTWindow value. */
  646. if (p2pinfo->ctwindow > 0) {
  647. p2p_ps_offload->ctwindow_en = 1;
  648. ctwindow = p2pinfo->ctwindow;
  649. rtl88e_set_p2p_ctw_period_cmd(hw, ctwindow);
  650. }
  651. /* hw only support 2 set of NoA */
  652. for (i = 0; i < p2pinfo->noa_num; i++) {
  653. /* To control the register setting for which NOA*/
  654. rtl_write_byte(rtlpriv, 0x5cf, (i << 4));
  655. if (i == 0)
  656. p2p_ps_offload->noa0_en = 1;
  657. else
  658. p2p_ps_offload->noa1_en = 1;
  659. /* config P2P NoA Descriptor Register */
  660. rtl_write_dword(rtlpriv, 0x5E0,
  661. p2pinfo->noa_duration[i]);
  662. rtl_write_dword(rtlpriv, 0x5E4,
  663. p2pinfo->noa_interval[i]);
  664. /*Get Current TSF value */
  665. tsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
  666. start_time = p2pinfo->noa_start_time[i];
  667. if (p2pinfo->noa_count_type[i] != 1) {
  668. while (start_time <= (tsf_low + (50 * 1024))) {
  669. start_time += p2pinfo->noa_interval[i];
  670. if (p2pinfo->noa_count_type[i] != 255)
  671. p2pinfo->noa_count_type[i]--;
  672. }
  673. }
  674. rtl_write_dword(rtlpriv, 0x5E8, start_time);
  675. rtl_write_dword(rtlpriv, 0x5EC,
  676. p2pinfo->noa_count_type[i]);
  677. }
  678. if ((p2pinfo->opp_ps == 1) || (p2pinfo->noa_num > 0)) {
  679. /* rst p2p circuit */
  680. rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4));
  681. p2p_ps_offload->offload_en = 1;
  682. if (P2P_ROLE_GO == rtlpriv->mac80211.p2p) {
  683. p2p_ps_offload->role = 1;
  684. p2p_ps_offload->allstasleep = 0;
  685. } else {
  686. p2p_ps_offload->role = 0;
  687. }
  688. p2p_ps_offload->discovery = 0;
  689. }
  690. break;
  691. case P2P_PS_SCAN:
  692. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN\n");
  693. p2p_ps_offload->discovery = 1;
  694. break;
  695. case P2P_PS_SCAN_DONE:
  696. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN_DONE\n");
  697. p2p_ps_offload->discovery = 0;
  698. p2pinfo->p2p_ps_state = P2P_PS_ENABLE;
  699. break;
  700. default:
  701. break;
  702. }
  703. rtl88e_fill_h2c_cmd(hw, H2C_88E_P2P_PS_OFFLOAD, 1,
  704. (u8 *)p2p_ps_offload);
  705. }