fec.c 49 KB

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  1. /*
  2. * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
  3. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
  4. *
  5. * Right now, I am very wasteful with the buffers. I allocate memory
  6. * pages and then divide them into 2K frame buffers. This way I know I
  7. * have buffers large enough to hold one frame within one buffer descriptor.
  8. * Once I get this working, I will use 64 or 128 byte CPM buffers, which
  9. * will be much more memory efficient and will easily handle lots of
  10. * small packets.
  11. *
  12. * Much better multiple PHY support by Magnus Damm.
  13. * Copyright (c) 2000 Ericsson Radio Systems AB.
  14. *
  15. * Support for FEC controller of ColdFire processors.
  16. * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
  17. *
  18. * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
  19. * Copyright (c) 2004-2006 Macq Electronique SA.
  20. *
  21. * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  22. */
  23. #include <linux/module.h>
  24. #include <linux/kernel.h>
  25. #include <linux/string.h>
  26. #include <linux/ptrace.h>
  27. #include <linux/errno.h>
  28. #include <linux/ioport.h>
  29. #include <linux/slab.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/pci.h>
  32. #include <linux/init.h>
  33. #include <linux/delay.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/etherdevice.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/spinlock.h>
  38. #include <linux/workqueue.h>
  39. #include <linux/bitops.h>
  40. #include <linux/io.h>
  41. #include <linux/irq.h>
  42. #include <linux/clk.h>
  43. #include <linux/platform_device.h>
  44. #include <linux/phy.h>
  45. #include <linux/fec.h>
  46. #include <linux/of.h>
  47. #include <linux/of_device.h>
  48. #include <linux/of_gpio.h>
  49. #include <linux/of_net.h>
  50. #include <linux/pinctrl/consumer.h>
  51. #include <linux/regulator/consumer.h>
  52. #include <asm/cacheflush.h>
  53. #ifndef CONFIG_ARM
  54. #include <asm/coldfire.h>
  55. #include <asm/mcfsim.h>
  56. #endif
  57. #include "fec.h"
  58. #if defined(CONFIG_ARM)
  59. #define FEC_ALIGNMENT 0xf
  60. #else
  61. #define FEC_ALIGNMENT 0x3
  62. #endif
  63. #define DRIVER_NAME "fec"
  64. #define FEC_NAPI_WEIGHT 64
  65. /* Pause frame feild and FIFO threshold */
  66. #define FEC_ENET_FCE (1 << 5)
  67. #define FEC_ENET_RSEM_V 0x84
  68. #define FEC_ENET_RSFL_V 16
  69. #define FEC_ENET_RAEM_V 0x8
  70. #define FEC_ENET_RAFL_V 0x8
  71. #define FEC_ENET_OPD_V 0xFFF0
  72. /* Controller is ENET-MAC */
  73. #define FEC_QUIRK_ENET_MAC (1 << 0)
  74. /* Controller needs driver to swap frame */
  75. #define FEC_QUIRK_SWAP_FRAME (1 << 1)
  76. /* Controller uses gasket */
  77. #define FEC_QUIRK_USE_GASKET (1 << 2)
  78. /* Controller has GBIT support */
  79. #define FEC_QUIRK_HAS_GBIT (1 << 3)
  80. /* Controller has extend desc buffer */
  81. #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
  82. static struct platform_device_id fec_devtype[] = {
  83. {
  84. /* keep it for coldfire */
  85. .name = DRIVER_NAME,
  86. .driver_data = 0,
  87. }, {
  88. .name = "imx25-fec",
  89. .driver_data = FEC_QUIRK_USE_GASKET,
  90. }, {
  91. .name = "imx27-fec",
  92. .driver_data = 0,
  93. }, {
  94. .name = "imx28-fec",
  95. .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
  96. }, {
  97. .name = "imx6q-fec",
  98. .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
  99. FEC_QUIRK_HAS_BUFDESC_EX,
  100. }, {
  101. /* sentinel */
  102. }
  103. };
  104. MODULE_DEVICE_TABLE(platform, fec_devtype);
  105. enum imx_fec_type {
  106. IMX25_FEC = 1, /* runs on i.mx25/50/53 */
  107. IMX27_FEC, /* runs on i.mx27/35/51 */
  108. IMX28_FEC,
  109. IMX6Q_FEC,
  110. };
  111. static const struct of_device_id fec_dt_ids[] = {
  112. { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
  113. { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
  114. { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
  115. { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
  116. { /* sentinel */ }
  117. };
  118. MODULE_DEVICE_TABLE(of, fec_dt_ids);
  119. static unsigned char macaddr[ETH_ALEN];
  120. module_param_array(macaddr, byte, NULL, 0);
  121. MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
  122. #if defined(CONFIG_M5272)
  123. /*
  124. * Some hardware gets it MAC address out of local flash memory.
  125. * if this is non-zero then assume it is the address to get MAC from.
  126. */
  127. #if defined(CONFIG_NETtel)
  128. #define FEC_FLASHMAC 0xf0006006
  129. #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
  130. #define FEC_FLASHMAC 0xf0006000
  131. #elif defined(CONFIG_CANCam)
  132. #define FEC_FLASHMAC 0xf0020000
  133. #elif defined (CONFIG_M5272C3)
  134. #define FEC_FLASHMAC (0xffe04000 + 4)
  135. #elif defined(CONFIG_MOD5272)
  136. #define FEC_FLASHMAC 0xffc0406b
  137. #else
  138. #define FEC_FLASHMAC 0
  139. #endif
  140. #endif /* CONFIG_M5272 */
  141. #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
  142. #error "FEC: descriptor ring size constants too large"
  143. #endif
  144. /* Interrupt events/masks. */
  145. #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
  146. #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
  147. #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
  148. #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
  149. #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
  150. #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
  151. #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
  152. #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
  153. #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
  154. #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
  155. #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
  156. #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
  157. /* The FEC stores dest/src/type, data, and checksum for receive packets.
  158. */
  159. #define PKT_MAXBUF_SIZE 1518
  160. #define PKT_MINBUF_SIZE 64
  161. #define PKT_MAXBLR_SIZE 1520
  162. /*
  163. * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
  164. * size bits. Other FEC hardware does not, so we need to take that into
  165. * account when setting it.
  166. */
  167. #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
  168. defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
  169. #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
  170. #else
  171. #define OPT_FRAME_SIZE 0
  172. #endif
  173. /* FEC MII MMFR bits definition */
  174. #define FEC_MMFR_ST (1 << 30)
  175. #define FEC_MMFR_OP_READ (2 << 28)
  176. #define FEC_MMFR_OP_WRITE (1 << 28)
  177. #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
  178. #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
  179. #define FEC_MMFR_TA (2 << 16)
  180. #define FEC_MMFR_DATA(v) (v & 0xffff)
  181. #define FEC_MII_TIMEOUT 30000 /* us */
  182. /* Transmitter timeout */
  183. #define TX_TIMEOUT (2 * HZ)
  184. #define FEC_PAUSE_FLAG_AUTONEG 0x1
  185. #define FEC_PAUSE_FLAG_ENABLE 0x2
  186. static int mii_cnt;
  187. static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
  188. {
  189. struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
  190. if (is_ex)
  191. return (struct bufdesc *)(ex + 1);
  192. else
  193. return bdp + 1;
  194. }
  195. static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex)
  196. {
  197. struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
  198. if (is_ex)
  199. return (struct bufdesc *)(ex - 1);
  200. else
  201. return bdp - 1;
  202. }
  203. static void *swap_buffer(void *bufaddr, int len)
  204. {
  205. int i;
  206. unsigned int *buf = bufaddr;
  207. for (i = 0; i < (len + 3) / 4; i++, buf++)
  208. *buf = cpu_to_be32(*buf);
  209. return bufaddr;
  210. }
  211. static netdev_tx_t
  212. fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
  213. {
  214. struct fec_enet_private *fep = netdev_priv(ndev);
  215. const struct platform_device_id *id_entry =
  216. platform_get_device_id(fep->pdev);
  217. struct bufdesc *bdp;
  218. void *bufaddr;
  219. unsigned short status;
  220. unsigned int index;
  221. if (!fep->link) {
  222. /* Link is down or autonegotiation is in progress. */
  223. return NETDEV_TX_BUSY;
  224. }
  225. /* Fill in a Tx ring entry */
  226. bdp = fep->cur_tx;
  227. status = bdp->cbd_sc;
  228. if (status & BD_ENET_TX_READY) {
  229. /* Ooops. All transmit buffers are full. Bail out.
  230. * This should not happen, since ndev->tbusy should be set.
  231. */
  232. printk("%s: tx queue full!.\n", ndev->name);
  233. return NETDEV_TX_BUSY;
  234. }
  235. /* Clear all of the status flags */
  236. status &= ~BD_ENET_TX_STATS;
  237. /* Set buffer length and buffer pointer */
  238. bufaddr = skb->data;
  239. bdp->cbd_datlen = skb->len;
  240. /*
  241. * On some FEC implementations data must be aligned on
  242. * 4-byte boundaries. Use bounce buffers to copy data
  243. * and get it aligned. Ugh.
  244. */
  245. if (fep->bufdesc_ex)
  246. index = (struct bufdesc_ex *)bdp -
  247. (struct bufdesc_ex *)fep->tx_bd_base;
  248. else
  249. index = bdp - fep->tx_bd_base;
  250. if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
  251. memcpy(fep->tx_bounce[index], skb->data, skb->len);
  252. bufaddr = fep->tx_bounce[index];
  253. }
  254. /*
  255. * Some design made an incorrect assumption on endian mode of
  256. * the system that it's running on. As the result, driver has to
  257. * swap every frame going to and coming from the controller.
  258. */
  259. if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
  260. swap_buffer(bufaddr, skb->len);
  261. /* Save skb pointer */
  262. fep->tx_skbuff[index] = skb;
  263. /* Push the data cache so the CPM does not get stale memory
  264. * data.
  265. */
  266. bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
  267. FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
  268. /* Send it on its way. Tell FEC it's ready, interrupt when done,
  269. * it's the last BD of the frame, and to put the CRC on the end.
  270. */
  271. status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
  272. | BD_ENET_TX_LAST | BD_ENET_TX_TC);
  273. bdp->cbd_sc = status;
  274. if (fep->bufdesc_ex) {
  275. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  276. ebdp->cbd_bdu = 0;
  277. if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
  278. fep->hwts_tx_en)) {
  279. ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
  280. skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
  281. } else {
  282. ebdp->cbd_esc = BD_ENET_TX_INT;
  283. }
  284. }
  285. /* If this was the last BD in the ring, start at the beginning again. */
  286. if (status & BD_ENET_TX_WRAP)
  287. bdp = fep->tx_bd_base;
  288. else
  289. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  290. fep->cur_tx = bdp;
  291. if (fep->cur_tx == fep->dirty_tx)
  292. netif_stop_queue(ndev);
  293. /* Trigger transmission start */
  294. writel(0, fep->hwp + FEC_X_DES_ACTIVE);
  295. skb_tx_timestamp(skb);
  296. return NETDEV_TX_OK;
  297. }
  298. /* This function is called to start or restart the FEC during a link
  299. * change. This only happens when switching between half and full
  300. * duplex.
  301. */
  302. static void
  303. fec_restart(struct net_device *ndev, int duplex)
  304. {
  305. struct fec_enet_private *fep = netdev_priv(ndev);
  306. const struct platform_device_id *id_entry =
  307. platform_get_device_id(fep->pdev);
  308. int i;
  309. u32 temp_mac[2];
  310. u32 rcntl = OPT_FRAME_SIZE | 0x04;
  311. u32 ecntl = 0x2; /* ETHEREN */
  312. /* Whack a reset. We should wait for this. */
  313. writel(1, fep->hwp + FEC_ECNTRL);
  314. udelay(10);
  315. /*
  316. * enet-mac reset will reset mac address registers too,
  317. * so need to reconfigure it.
  318. */
  319. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
  320. memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
  321. writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
  322. writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
  323. }
  324. /* Clear any outstanding interrupt. */
  325. writel(0xffc00000, fep->hwp + FEC_IEVENT);
  326. /* Reset all multicast. */
  327. writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  328. writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  329. #ifndef CONFIG_M5272
  330. writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
  331. writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
  332. #endif
  333. /* Set maximum receive buffer size. */
  334. writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
  335. /* Set receive and transmit descriptor base. */
  336. writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
  337. if (fep->bufdesc_ex)
  338. writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
  339. * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
  340. else
  341. writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
  342. * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
  343. fep->cur_rx = fep->rx_bd_base;
  344. for (i = 0; i <= TX_RING_MOD_MASK; i++) {
  345. if (fep->tx_skbuff[i]) {
  346. dev_kfree_skb_any(fep->tx_skbuff[i]);
  347. fep->tx_skbuff[i] = NULL;
  348. }
  349. }
  350. /* Enable MII mode */
  351. if (duplex) {
  352. /* FD enable */
  353. writel(0x04, fep->hwp + FEC_X_CNTRL);
  354. } else {
  355. /* No Rcv on Xmit */
  356. rcntl |= 0x02;
  357. writel(0x0, fep->hwp + FEC_X_CNTRL);
  358. }
  359. fep->full_duplex = duplex;
  360. /* Set MII speed */
  361. writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
  362. /*
  363. * The phy interface and speed need to get configured
  364. * differently on enet-mac.
  365. */
  366. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
  367. /* Enable flow control and length check */
  368. rcntl |= 0x40000000 | 0x00000020;
  369. /* RGMII, RMII or MII */
  370. if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
  371. rcntl |= (1 << 6);
  372. else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
  373. rcntl |= (1 << 8);
  374. else
  375. rcntl &= ~(1 << 8);
  376. /* 1G, 100M or 10M */
  377. if (fep->phy_dev) {
  378. if (fep->phy_dev->speed == SPEED_1000)
  379. ecntl |= (1 << 5);
  380. else if (fep->phy_dev->speed == SPEED_100)
  381. rcntl &= ~(1 << 9);
  382. else
  383. rcntl |= (1 << 9);
  384. }
  385. } else {
  386. #ifdef FEC_MIIGSK_ENR
  387. if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
  388. u32 cfgr;
  389. /* disable the gasket and wait */
  390. writel(0, fep->hwp + FEC_MIIGSK_ENR);
  391. while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
  392. udelay(1);
  393. /*
  394. * configure the gasket:
  395. * RMII, 50 MHz, no loopback, no echo
  396. * MII, 25 MHz, no loopback, no echo
  397. */
  398. cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
  399. ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
  400. if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
  401. cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
  402. writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
  403. /* re-enable the gasket */
  404. writel(2, fep->hwp + FEC_MIIGSK_ENR);
  405. }
  406. #endif
  407. }
  408. /* enable pause frame*/
  409. if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
  410. ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
  411. fep->phy_dev && fep->phy_dev->pause)) {
  412. rcntl |= FEC_ENET_FCE;
  413. /* set FIFO thresh hold parameter to reduce overrun */
  414. writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
  415. writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
  416. writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
  417. writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
  418. /* OPD */
  419. writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
  420. } else {
  421. rcntl &= ~FEC_ENET_FCE;
  422. }
  423. writel(rcntl, fep->hwp + FEC_R_CNTRL);
  424. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
  425. /* enable ENET endian swap */
  426. ecntl |= (1 << 8);
  427. /* enable ENET store and forward mode */
  428. writel(1 << 8, fep->hwp + FEC_X_WMRK);
  429. }
  430. if (fep->bufdesc_ex)
  431. ecntl |= (1 << 4);
  432. /* And last, enable the transmit and receive processing */
  433. writel(ecntl, fep->hwp + FEC_ECNTRL);
  434. writel(0, fep->hwp + FEC_R_DES_ACTIVE);
  435. if (fep->bufdesc_ex)
  436. fec_ptp_start_cyclecounter(ndev);
  437. /* Enable interrupts we wish to service */
  438. writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
  439. }
  440. static void
  441. fec_stop(struct net_device *ndev)
  442. {
  443. struct fec_enet_private *fep = netdev_priv(ndev);
  444. const struct platform_device_id *id_entry =
  445. platform_get_device_id(fep->pdev);
  446. u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
  447. /* We cannot expect a graceful transmit stop without link !!! */
  448. if (fep->link) {
  449. writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
  450. udelay(10);
  451. if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
  452. printk("fec_stop : Graceful transmit stop did not complete !\n");
  453. }
  454. /* Whack a reset. We should wait for this. */
  455. writel(1, fep->hwp + FEC_ECNTRL);
  456. udelay(10);
  457. writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
  458. writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
  459. /* We have to keep ENET enabled to have MII interrupt stay working */
  460. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
  461. writel(2, fep->hwp + FEC_ECNTRL);
  462. writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
  463. }
  464. }
  465. static void
  466. fec_timeout(struct net_device *ndev)
  467. {
  468. struct fec_enet_private *fep = netdev_priv(ndev);
  469. ndev->stats.tx_errors++;
  470. fec_restart(ndev, fep->full_duplex);
  471. netif_wake_queue(ndev);
  472. }
  473. static void
  474. fec_enet_tx(struct net_device *ndev)
  475. {
  476. struct fec_enet_private *fep;
  477. struct bufdesc *bdp;
  478. unsigned short status;
  479. struct sk_buff *skb;
  480. int index = 0;
  481. fep = netdev_priv(ndev);
  482. bdp = fep->dirty_tx;
  483. /* get next bdp of dirty_tx */
  484. if (bdp->cbd_sc & BD_ENET_TX_WRAP)
  485. bdp = fep->tx_bd_base;
  486. else
  487. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  488. while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
  489. /* current queue is empty */
  490. if (bdp == fep->cur_tx)
  491. break;
  492. if (fep->bufdesc_ex)
  493. index = (struct bufdesc_ex *)bdp -
  494. (struct bufdesc_ex *)fep->tx_bd_base;
  495. else
  496. index = bdp - fep->tx_bd_base;
  497. dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
  498. FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
  499. bdp->cbd_bufaddr = 0;
  500. skb = fep->tx_skbuff[index];
  501. /* Check for errors. */
  502. if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
  503. BD_ENET_TX_RL | BD_ENET_TX_UN |
  504. BD_ENET_TX_CSL)) {
  505. ndev->stats.tx_errors++;
  506. if (status & BD_ENET_TX_HB) /* No heartbeat */
  507. ndev->stats.tx_heartbeat_errors++;
  508. if (status & BD_ENET_TX_LC) /* Late collision */
  509. ndev->stats.tx_window_errors++;
  510. if (status & BD_ENET_TX_RL) /* Retrans limit */
  511. ndev->stats.tx_aborted_errors++;
  512. if (status & BD_ENET_TX_UN) /* Underrun */
  513. ndev->stats.tx_fifo_errors++;
  514. if (status & BD_ENET_TX_CSL) /* Carrier lost */
  515. ndev->stats.tx_carrier_errors++;
  516. } else {
  517. ndev->stats.tx_packets++;
  518. }
  519. if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
  520. fep->bufdesc_ex) {
  521. struct skb_shared_hwtstamps shhwtstamps;
  522. unsigned long flags;
  523. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  524. memset(&shhwtstamps, 0, sizeof(shhwtstamps));
  525. spin_lock_irqsave(&fep->tmreg_lock, flags);
  526. shhwtstamps.hwtstamp = ns_to_ktime(
  527. timecounter_cyc2time(&fep->tc, ebdp->ts));
  528. spin_unlock_irqrestore(&fep->tmreg_lock, flags);
  529. skb_tstamp_tx(skb, &shhwtstamps);
  530. }
  531. if (status & BD_ENET_TX_READY)
  532. printk("HEY! Enet xmit interrupt and TX_READY.\n");
  533. /* Deferred means some collisions occurred during transmit,
  534. * but we eventually sent the packet OK.
  535. */
  536. if (status & BD_ENET_TX_DEF)
  537. ndev->stats.collisions++;
  538. /* Free the sk buffer associated with this last transmit */
  539. dev_kfree_skb_any(skb);
  540. fep->tx_skbuff[index] = NULL;
  541. fep->dirty_tx = bdp;
  542. /* Update pointer to next buffer descriptor to be transmitted */
  543. if (status & BD_ENET_TX_WRAP)
  544. bdp = fep->tx_bd_base;
  545. else
  546. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  547. /* Since we have freed up a buffer, the ring is no longer full
  548. */
  549. if (fep->dirty_tx != fep->cur_tx) {
  550. if (netif_queue_stopped(ndev))
  551. netif_wake_queue(ndev);
  552. }
  553. }
  554. return;
  555. }
  556. /* During a receive, the cur_rx points to the current incoming buffer.
  557. * When we update through the ring, if the next incoming buffer has
  558. * not been given to the system, we just set the empty indicator,
  559. * effectively tossing the packet.
  560. */
  561. static int
  562. fec_enet_rx(struct net_device *ndev, int budget)
  563. {
  564. struct fec_enet_private *fep = netdev_priv(ndev);
  565. const struct platform_device_id *id_entry =
  566. platform_get_device_id(fep->pdev);
  567. struct bufdesc *bdp;
  568. unsigned short status;
  569. struct sk_buff *skb;
  570. ushort pkt_len;
  571. __u8 *data;
  572. int pkt_received = 0;
  573. #ifdef CONFIG_M532x
  574. flush_cache_all();
  575. #endif
  576. /* First, grab all of the stats for the incoming packet.
  577. * These get messed up if we get called due to a busy condition.
  578. */
  579. bdp = fep->cur_rx;
  580. while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
  581. if (pkt_received >= budget)
  582. break;
  583. pkt_received++;
  584. /* Since we have allocated space to hold a complete frame,
  585. * the last indicator should be set.
  586. */
  587. if ((status & BD_ENET_RX_LAST) == 0)
  588. printk("FEC ENET: rcv is not +last\n");
  589. if (!fep->opened)
  590. goto rx_processing_done;
  591. /* Check for errors. */
  592. if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
  593. BD_ENET_RX_CR | BD_ENET_RX_OV)) {
  594. ndev->stats.rx_errors++;
  595. if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
  596. /* Frame too long or too short. */
  597. ndev->stats.rx_length_errors++;
  598. }
  599. if (status & BD_ENET_RX_NO) /* Frame alignment */
  600. ndev->stats.rx_frame_errors++;
  601. if (status & BD_ENET_RX_CR) /* CRC Error */
  602. ndev->stats.rx_crc_errors++;
  603. if (status & BD_ENET_RX_OV) /* FIFO overrun */
  604. ndev->stats.rx_fifo_errors++;
  605. }
  606. /* Report late collisions as a frame error.
  607. * On this error, the BD is closed, but we don't know what we
  608. * have in the buffer. So, just drop this frame on the floor.
  609. */
  610. if (status & BD_ENET_RX_CL) {
  611. ndev->stats.rx_errors++;
  612. ndev->stats.rx_frame_errors++;
  613. goto rx_processing_done;
  614. }
  615. /* Process the incoming frame. */
  616. ndev->stats.rx_packets++;
  617. pkt_len = bdp->cbd_datlen;
  618. ndev->stats.rx_bytes += pkt_len;
  619. data = (__u8*)__va(bdp->cbd_bufaddr);
  620. dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
  621. FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
  622. if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
  623. swap_buffer(data, pkt_len);
  624. /* This does 16 byte alignment, exactly what we need.
  625. * The packet length includes FCS, but we don't want to
  626. * include that when passing upstream as it messes up
  627. * bridging applications.
  628. */
  629. skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
  630. if (unlikely(!skb)) {
  631. printk("%s: Memory squeeze, dropping packet.\n",
  632. ndev->name);
  633. ndev->stats.rx_dropped++;
  634. } else {
  635. skb_reserve(skb, NET_IP_ALIGN);
  636. skb_put(skb, pkt_len - 4); /* Make room */
  637. skb_copy_to_linear_data(skb, data, pkt_len - 4);
  638. skb->protocol = eth_type_trans(skb, ndev);
  639. /* Get receive timestamp from the skb */
  640. if (fep->hwts_rx_en && fep->bufdesc_ex) {
  641. struct skb_shared_hwtstamps *shhwtstamps =
  642. skb_hwtstamps(skb);
  643. unsigned long flags;
  644. struct bufdesc_ex *ebdp =
  645. (struct bufdesc_ex *)bdp;
  646. memset(shhwtstamps, 0, sizeof(*shhwtstamps));
  647. spin_lock_irqsave(&fep->tmreg_lock, flags);
  648. shhwtstamps->hwtstamp = ns_to_ktime(
  649. timecounter_cyc2time(&fep->tc, ebdp->ts));
  650. spin_unlock_irqrestore(&fep->tmreg_lock, flags);
  651. }
  652. if (!skb_defer_rx_timestamp(skb))
  653. napi_gro_receive(&fep->napi, skb);
  654. }
  655. bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
  656. FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
  657. rx_processing_done:
  658. /* Clear the status flags for this buffer */
  659. status &= ~BD_ENET_RX_STATS;
  660. /* Mark the buffer empty */
  661. status |= BD_ENET_RX_EMPTY;
  662. bdp->cbd_sc = status;
  663. if (fep->bufdesc_ex) {
  664. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  665. ebdp->cbd_esc = BD_ENET_RX_INT;
  666. ebdp->cbd_prot = 0;
  667. ebdp->cbd_bdu = 0;
  668. }
  669. /* Update BD pointer to next entry */
  670. if (status & BD_ENET_RX_WRAP)
  671. bdp = fep->rx_bd_base;
  672. else
  673. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  674. /* Doing this here will keep the FEC running while we process
  675. * incoming frames. On a heavily loaded network, we should be
  676. * able to keep up at the expense of system resources.
  677. */
  678. writel(0, fep->hwp + FEC_R_DES_ACTIVE);
  679. }
  680. fep->cur_rx = bdp;
  681. return pkt_received;
  682. }
  683. static irqreturn_t
  684. fec_enet_interrupt(int irq, void *dev_id)
  685. {
  686. struct net_device *ndev = dev_id;
  687. struct fec_enet_private *fep = netdev_priv(ndev);
  688. uint int_events;
  689. irqreturn_t ret = IRQ_NONE;
  690. do {
  691. int_events = readl(fep->hwp + FEC_IEVENT);
  692. writel(int_events, fep->hwp + FEC_IEVENT);
  693. if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
  694. ret = IRQ_HANDLED;
  695. /* Disable the RX interrupt */
  696. if (napi_schedule_prep(&fep->napi)) {
  697. writel(FEC_RX_DISABLED_IMASK,
  698. fep->hwp + FEC_IMASK);
  699. __napi_schedule(&fep->napi);
  700. }
  701. }
  702. if (int_events & FEC_ENET_MII) {
  703. ret = IRQ_HANDLED;
  704. complete(&fep->mdio_done);
  705. }
  706. } while (int_events);
  707. return ret;
  708. }
  709. static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
  710. {
  711. struct net_device *ndev = napi->dev;
  712. int pkts = fec_enet_rx(ndev, budget);
  713. struct fec_enet_private *fep = netdev_priv(ndev);
  714. fec_enet_tx(ndev);
  715. if (pkts < budget) {
  716. napi_complete(napi);
  717. writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
  718. }
  719. return pkts;
  720. }
  721. /* ------------------------------------------------------------------------- */
  722. static void fec_get_mac(struct net_device *ndev)
  723. {
  724. struct fec_enet_private *fep = netdev_priv(ndev);
  725. struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
  726. unsigned char *iap, tmpaddr[ETH_ALEN];
  727. /*
  728. * try to get mac address in following order:
  729. *
  730. * 1) module parameter via kernel command line in form
  731. * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
  732. */
  733. iap = macaddr;
  734. #ifdef CONFIG_OF
  735. /*
  736. * 2) from device tree data
  737. */
  738. if (!is_valid_ether_addr(iap)) {
  739. struct device_node *np = fep->pdev->dev.of_node;
  740. if (np) {
  741. const char *mac = of_get_mac_address(np);
  742. if (mac)
  743. iap = (unsigned char *) mac;
  744. }
  745. }
  746. #endif
  747. /*
  748. * 3) from flash or fuse (via platform data)
  749. */
  750. if (!is_valid_ether_addr(iap)) {
  751. #ifdef CONFIG_M5272
  752. if (FEC_FLASHMAC)
  753. iap = (unsigned char *)FEC_FLASHMAC;
  754. #else
  755. if (pdata)
  756. iap = (unsigned char *)&pdata->mac;
  757. #endif
  758. }
  759. /*
  760. * 4) FEC mac registers set by bootloader
  761. */
  762. if (!is_valid_ether_addr(iap)) {
  763. *((unsigned long *) &tmpaddr[0]) =
  764. be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
  765. *((unsigned short *) &tmpaddr[4]) =
  766. be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
  767. iap = &tmpaddr[0];
  768. }
  769. memcpy(ndev->dev_addr, iap, ETH_ALEN);
  770. /* Adjust MAC if using macaddr */
  771. if (iap == macaddr)
  772. ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
  773. }
  774. /* ------------------------------------------------------------------------- */
  775. /*
  776. * Phy section
  777. */
  778. static void fec_enet_adjust_link(struct net_device *ndev)
  779. {
  780. struct fec_enet_private *fep = netdev_priv(ndev);
  781. struct phy_device *phy_dev = fep->phy_dev;
  782. unsigned long flags;
  783. int status_change = 0;
  784. spin_lock_irqsave(&fep->hw_lock, flags);
  785. /* Prevent a state halted on mii error */
  786. if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
  787. phy_dev->state = PHY_RESUMING;
  788. goto spin_unlock;
  789. }
  790. /* Duplex link change */
  791. if (phy_dev->link) {
  792. if (fep->full_duplex != phy_dev->duplex) {
  793. fec_restart(ndev, phy_dev->duplex);
  794. /* prevent unnecessary second fec_restart() below */
  795. fep->link = phy_dev->link;
  796. status_change = 1;
  797. }
  798. }
  799. /* Link on or off change */
  800. if (phy_dev->link != fep->link) {
  801. fep->link = phy_dev->link;
  802. if (phy_dev->link)
  803. fec_restart(ndev, phy_dev->duplex);
  804. else
  805. fec_stop(ndev);
  806. status_change = 1;
  807. }
  808. spin_unlock:
  809. spin_unlock_irqrestore(&fep->hw_lock, flags);
  810. if (status_change)
  811. phy_print_status(phy_dev);
  812. }
  813. static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
  814. {
  815. struct fec_enet_private *fep = bus->priv;
  816. unsigned long time_left;
  817. fep->mii_timeout = 0;
  818. init_completion(&fep->mdio_done);
  819. /* start a read op */
  820. writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
  821. FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
  822. FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
  823. /* wait for end of transfer */
  824. time_left = wait_for_completion_timeout(&fep->mdio_done,
  825. usecs_to_jiffies(FEC_MII_TIMEOUT));
  826. if (time_left == 0) {
  827. fep->mii_timeout = 1;
  828. printk(KERN_ERR "FEC: MDIO read timeout\n");
  829. return -ETIMEDOUT;
  830. }
  831. /* return value */
  832. return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
  833. }
  834. static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
  835. u16 value)
  836. {
  837. struct fec_enet_private *fep = bus->priv;
  838. unsigned long time_left;
  839. fep->mii_timeout = 0;
  840. init_completion(&fep->mdio_done);
  841. /* start a write op */
  842. writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
  843. FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
  844. FEC_MMFR_TA | FEC_MMFR_DATA(value),
  845. fep->hwp + FEC_MII_DATA);
  846. /* wait for end of transfer */
  847. time_left = wait_for_completion_timeout(&fep->mdio_done,
  848. usecs_to_jiffies(FEC_MII_TIMEOUT));
  849. if (time_left == 0) {
  850. fep->mii_timeout = 1;
  851. printk(KERN_ERR "FEC: MDIO write timeout\n");
  852. return -ETIMEDOUT;
  853. }
  854. return 0;
  855. }
  856. static int fec_enet_mdio_reset(struct mii_bus *bus)
  857. {
  858. return 0;
  859. }
  860. static int fec_enet_mii_probe(struct net_device *ndev)
  861. {
  862. struct fec_enet_private *fep = netdev_priv(ndev);
  863. const struct platform_device_id *id_entry =
  864. platform_get_device_id(fep->pdev);
  865. struct phy_device *phy_dev = NULL;
  866. char mdio_bus_id[MII_BUS_ID_SIZE];
  867. char phy_name[MII_BUS_ID_SIZE + 3];
  868. int phy_id;
  869. int dev_id = fep->dev_id;
  870. fep->phy_dev = NULL;
  871. /* check for attached phy */
  872. for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
  873. if ((fep->mii_bus->phy_mask & (1 << phy_id)))
  874. continue;
  875. if (fep->mii_bus->phy_map[phy_id] == NULL)
  876. continue;
  877. if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
  878. continue;
  879. if (dev_id--)
  880. continue;
  881. strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
  882. break;
  883. }
  884. if (phy_id >= PHY_MAX_ADDR) {
  885. printk(KERN_INFO
  886. "%s: no PHY, assuming direct connection to switch\n",
  887. ndev->name);
  888. strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
  889. phy_id = 0;
  890. }
  891. snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
  892. phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
  893. fep->phy_interface);
  894. if (IS_ERR(phy_dev)) {
  895. printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
  896. return PTR_ERR(phy_dev);
  897. }
  898. /* mask with MAC supported features */
  899. if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
  900. phy_dev->supported &= PHY_GBIT_FEATURES;
  901. phy_dev->supported |= SUPPORTED_Pause;
  902. }
  903. else
  904. phy_dev->supported &= PHY_BASIC_FEATURES;
  905. phy_dev->advertising = phy_dev->supported;
  906. fep->phy_dev = phy_dev;
  907. fep->link = 0;
  908. fep->full_duplex = 0;
  909. printk(KERN_INFO
  910. "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
  911. ndev->name,
  912. fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
  913. fep->phy_dev->irq);
  914. return 0;
  915. }
  916. static int fec_enet_mii_init(struct platform_device *pdev)
  917. {
  918. static struct mii_bus *fec0_mii_bus;
  919. struct net_device *ndev = platform_get_drvdata(pdev);
  920. struct fec_enet_private *fep = netdev_priv(ndev);
  921. const struct platform_device_id *id_entry =
  922. platform_get_device_id(fep->pdev);
  923. int err = -ENXIO, i;
  924. /*
  925. * The dual fec interfaces are not equivalent with enet-mac.
  926. * Here are the differences:
  927. *
  928. * - fec0 supports MII & RMII modes while fec1 only supports RMII
  929. * - fec0 acts as the 1588 time master while fec1 is slave
  930. * - external phys can only be configured by fec0
  931. *
  932. * That is to say fec1 can not work independently. It only works
  933. * when fec0 is working. The reason behind this design is that the
  934. * second interface is added primarily for Switch mode.
  935. *
  936. * Because of the last point above, both phys are attached on fec0
  937. * mdio interface in board design, and need to be configured by
  938. * fec0 mii_bus.
  939. */
  940. if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
  941. /* fec1 uses fec0 mii_bus */
  942. if (mii_cnt && fec0_mii_bus) {
  943. fep->mii_bus = fec0_mii_bus;
  944. mii_cnt++;
  945. return 0;
  946. }
  947. return -ENOENT;
  948. }
  949. fep->mii_timeout = 0;
  950. /*
  951. * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
  952. *
  953. * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
  954. * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
  955. * Reference Manual has an error on this, and gets fixed on i.MX6Q
  956. * document.
  957. */
  958. fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
  959. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
  960. fep->phy_speed--;
  961. fep->phy_speed <<= 1;
  962. writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
  963. fep->mii_bus = mdiobus_alloc();
  964. if (fep->mii_bus == NULL) {
  965. err = -ENOMEM;
  966. goto err_out;
  967. }
  968. fep->mii_bus->name = "fec_enet_mii_bus";
  969. fep->mii_bus->read = fec_enet_mdio_read;
  970. fep->mii_bus->write = fec_enet_mdio_write;
  971. fep->mii_bus->reset = fec_enet_mdio_reset;
  972. snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
  973. pdev->name, fep->dev_id + 1);
  974. fep->mii_bus->priv = fep;
  975. fep->mii_bus->parent = &pdev->dev;
  976. fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
  977. if (!fep->mii_bus->irq) {
  978. err = -ENOMEM;
  979. goto err_out_free_mdiobus;
  980. }
  981. for (i = 0; i < PHY_MAX_ADDR; i++)
  982. fep->mii_bus->irq[i] = PHY_POLL;
  983. if (mdiobus_register(fep->mii_bus))
  984. goto err_out_free_mdio_irq;
  985. mii_cnt++;
  986. /* save fec0 mii_bus */
  987. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
  988. fec0_mii_bus = fep->mii_bus;
  989. return 0;
  990. err_out_free_mdio_irq:
  991. kfree(fep->mii_bus->irq);
  992. err_out_free_mdiobus:
  993. mdiobus_free(fep->mii_bus);
  994. err_out:
  995. return err;
  996. }
  997. static void fec_enet_mii_remove(struct fec_enet_private *fep)
  998. {
  999. if (--mii_cnt == 0) {
  1000. mdiobus_unregister(fep->mii_bus);
  1001. kfree(fep->mii_bus->irq);
  1002. mdiobus_free(fep->mii_bus);
  1003. }
  1004. }
  1005. static int fec_enet_get_settings(struct net_device *ndev,
  1006. struct ethtool_cmd *cmd)
  1007. {
  1008. struct fec_enet_private *fep = netdev_priv(ndev);
  1009. struct phy_device *phydev = fep->phy_dev;
  1010. if (!phydev)
  1011. return -ENODEV;
  1012. return phy_ethtool_gset(phydev, cmd);
  1013. }
  1014. static int fec_enet_set_settings(struct net_device *ndev,
  1015. struct ethtool_cmd *cmd)
  1016. {
  1017. struct fec_enet_private *fep = netdev_priv(ndev);
  1018. struct phy_device *phydev = fep->phy_dev;
  1019. if (!phydev)
  1020. return -ENODEV;
  1021. return phy_ethtool_sset(phydev, cmd);
  1022. }
  1023. static void fec_enet_get_drvinfo(struct net_device *ndev,
  1024. struct ethtool_drvinfo *info)
  1025. {
  1026. struct fec_enet_private *fep = netdev_priv(ndev);
  1027. strlcpy(info->driver, fep->pdev->dev.driver->name,
  1028. sizeof(info->driver));
  1029. strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
  1030. strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
  1031. }
  1032. static int fec_enet_get_ts_info(struct net_device *ndev,
  1033. struct ethtool_ts_info *info)
  1034. {
  1035. struct fec_enet_private *fep = netdev_priv(ndev);
  1036. if (fep->bufdesc_ex) {
  1037. info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
  1038. SOF_TIMESTAMPING_RX_SOFTWARE |
  1039. SOF_TIMESTAMPING_SOFTWARE |
  1040. SOF_TIMESTAMPING_TX_HARDWARE |
  1041. SOF_TIMESTAMPING_RX_HARDWARE |
  1042. SOF_TIMESTAMPING_RAW_HARDWARE;
  1043. if (fep->ptp_clock)
  1044. info->phc_index = ptp_clock_index(fep->ptp_clock);
  1045. else
  1046. info->phc_index = -1;
  1047. info->tx_types = (1 << HWTSTAMP_TX_OFF) |
  1048. (1 << HWTSTAMP_TX_ON);
  1049. info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
  1050. (1 << HWTSTAMP_FILTER_ALL);
  1051. return 0;
  1052. } else {
  1053. return ethtool_op_get_ts_info(ndev, info);
  1054. }
  1055. }
  1056. static void fec_enet_get_pauseparam(struct net_device *ndev,
  1057. struct ethtool_pauseparam *pause)
  1058. {
  1059. struct fec_enet_private *fep = netdev_priv(ndev);
  1060. pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
  1061. pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
  1062. pause->rx_pause = pause->tx_pause;
  1063. }
  1064. static int fec_enet_set_pauseparam(struct net_device *ndev,
  1065. struct ethtool_pauseparam *pause)
  1066. {
  1067. struct fec_enet_private *fep = netdev_priv(ndev);
  1068. if (pause->tx_pause != pause->rx_pause) {
  1069. netdev_info(ndev,
  1070. "hardware only support enable/disable both tx and rx");
  1071. return -EINVAL;
  1072. }
  1073. fep->pause_flag = 0;
  1074. /* tx pause must be same as rx pause */
  1075. fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
  1076. fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
  1077. if (pause->rx_pause || pause->autoneg) {
  1078. fep->phy_dev->supported |= ADVERTISED_Pause;
  1079. fep->phy_dev->advertising |= ADVERTISED_Pause;
  1080. } else {
  1081. fep->phy_dev->supported &= ~ADVERTISED_Pause;
  1082. fep->phy_dev->advertising &= ~ADVERTISED_Pause;
  1083. }
  1084. if (pause->autoneg) {
  1085. if (netif_running(ndev))
  1086. fec_stop(ndev);
  1087. phy_start_aneg(fep->phy_dev);
  1088. }
  1089. if (netif_running(ndev))
  1090. fec_restart(ndev, 0);
  1091. return 0;
  1092. }
  1093. static const struct ethtool_ops fec_enet_ethtool_ops = {
  1094. .get_pauseparam = fec_enet_get_pauseparam,
  1095. .set_pauseparam = fec_enet_set_pauseparam,
  1096. .get_settings = fec_enet_get_settings,
  1097. .set_settings = fec_enet_set_settings,
  1098. .get_drvinfo = fec_enet_get_drvinfo,
  1099. .get_link = ethtool_op_get_link,
  1100. .get_ts_info = fec_enet_get_ts_info,
  1101. };
  1102. static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
  1103. {
  1104. struct fec_enet_private *fep = netdev_priv(ndev);
  1105. struct phy_device *phydev = fep->phy_dev;
  1106. if (!netif_running(ndev))
  1107. return -EINVAL;
  1108. if (!phydev)
  1109. return -ENODEV;
  1110. if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
  1111. return fec_ptp_ioctl(ndev, rq, cmd);
  1112. return phy_mii_ioctl(phydev, rq, cmd);
  1113. }
  1114. static void fec_enet_free_buffers(struct net_device *ndev)
  1115. {
  1116. struct fec_enet_private *fep = netdev_priv(ndev);
  1117. int i;
  1118. struct sk_buff *skb;
  1119. struct bufdesc *bdp;
  1120. bdp = fep->rx_bd_base;
  1121. for (i = 0; i < RX_RING_SIZE; i++) {
  1122. skb = fep->rx_skbuff[i];
  1123. if (bdp->cbd_bufaddr)
  1124. dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
  1125. FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
  1126. if (skb)
  1127. dev_kfree_skb(skb);
  1128. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  1129. }
  1130. bdp = fep->tx_bd_base;
  1131. for (i = 0; i < TX_RING_SIZE; i++)
  1132. kfree(fep->tx_bounce[i]);
  1133. }
  1134. static int fec_enet_alloc_buffers(struct net_device *ndev)
  1135. {
  1136. struct fec_enet_private *fep = netdev_priv(ndev);
  1137. int i;
  1138. struct sk_buff *skb;
  1139. struct bufdesc *bdp;
  1140. bdp = fep->rx_bd_base;
  1141. for (i = 0; i < RX_RING_SIZE; i++) {
  1142. skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
  1143. if (!skb) {
  1144. fec_enet_free_buffers(ndev);
  1145. return -ENOMEM;
  1146. }
  1147. fep->rx_skbuff[i] = skb;
  1148. bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
  1149. FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
  1150. bdp->cbd_sc = BD_ENET_RX_EMPTY;
  1151. if (fep->bufdesc_ex) {
  1152. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  1153. ebdp->cbd_esc = BD_ENET_RX_INT;
  1154. }
  1155. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  1156. }
  1157. /* Set the last buffer to wrap. */
  1158. bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
  1159. bdp->cbd_sc |= BD_SC_WRAP;
  1160. bdp = fep->tx_bd_base;
  1161. for (i = 0; i < TX_RING_SIZE; i++) {
  1162. fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
  1163. bdp->cbd_sc = 0;
  1164. bdp->cbd_bufaddr = 0;
  1165. if (fep->bufdesc_ex) {
  1166. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  1167. ebdp->cbd_esc = BD_ENET_RX_INT;
  1168. }
  1169. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  1170. }
  1171. /* Set the last buffer to wrap. */
  1172. bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
  1173. bdp->cbd_sc |= BD_SC_WRAP;
  1174. return 0;
  1175. }
  1176. static int
  1177. fec_enet_open(struct net_device *ndev)
  1178. {
  1179. struct fec_enet_private *fep = netdev_priv(ndev);
  1180. int ret;
  1181. napi_enable(&fep->napi);
  1182. /* I should reset the ring buffers here, but I don't yet know
  1183. * a simple way to do that.
  1184. */
  1185. ret = fec_enet_alloc_buffers(ndev);
  1186. if (ret)
  1187. return ret;
  1188. /* Probe and connect to PHY when open the interface */
  1189. ret = fec_enet_mii_probe(ndev);
  1190. if (ret) {
  1191. fec_enet_free_buffers(ndev);
  1192. return ret;
  1193. }
  1194. phy_start(fep->phy_dev);
  1195. netif_start_queue(ndev);
  1196. fep->opened = 1;
  1197. return 0;
  1198. }
  1199. static int
  1200. fec_enet_close(struct net_device *ndev)
  1201. {
  1202. struct fec_enet_private *fep = netdev_priv(ndev);
  1203. /* Don't know what to do yet. */
  1204. fep->opened = 0;
  1205. netif_stop_queue(ndev);
  1206. fec_stop(ndev);
  1207. if (fep->phy_dev) {
  1208. phy_stop(fep->phy_dev);
  1209. phy_disconnect(fep->phy_dev);
  1210. }
  1211. fec_enet_free_buffers(ndev);
  1212. return 0;
  1213. }
  1214. /* Set or clear the multicast filter for this adaptor.
  1215. * Skeleton taken from sunlance driver.
  1216. * The CPM Ethernet implementation allows Multicast as well as individual
  1217. * MAC address filtering. Some of the drivers check to make sure it is
  1218. * a group multicast address, and discard those that are not. I guess I
  1219. * will do the same for now, but just remove the test if you want
  1220. * individual filtering as well (do the upper net layers want or support
  1221. * this kind of feature?).
  1222. */
  1223. #define HASH_BITS 6 /* #bits in hash */
  1224. #define CRC32_POLY 0xEDB88320
  1225. static void set_multicast_list(struct net_device *ndev)
  1226. {
  1227. struct fec_enet_private *fep = netdev_priv(ndev);
  1228. struct netdev_hw_addr *ha;
  1229. unsigned int i, bit, data, crc, tmp;
  1230. unsigned char hash;
  1231. if (ndev->flags & IFF_PROMISC) {
  1232. tmp = readl(fep->hwp + FEC_R_CNTRL);
  1233. tmp |= 0x8;
  1234. writel(tmp, fep->hwp + FEC_R_CNTRL);
  1235. return;
  1236. }
  1237. tmp = readl(fep->hwp + FEC_R_CNTRL);
  1238. tmp &= ~0x8;
  1239. writel(tmp, fep->hwp + FEC_R_CNTRL);
  1240. if (ndev->flags & IFF_ALLMULTI) {
  1241. /* Catch all multicast addresses, so set the
  1242. * filter to all 1's
  1243. */
  1244. writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  1245. writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  1246. return;
  1247. }
  1248. /* Clear filter and add the addresses in hash register
  1249. */
  1250. writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  1251. writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  1252. netdev_for_each_mc_addr(ha, ndev) {
  1253. /* calculate crc32 value of mac address */
  1254. crc = 0xffffffff;
  1255. for (i = 0; i < ndev->addr_len; i++) {
  1256. data = ha->addr[i];
  1257. for (bit = 0; bit < 8; bit++, data >>= 1) {
  1258. crc = (crc >> 1) ^
  1259. (((crc ^ data) & 1) ? CRC32_POLY : 0);
  1260. }
  1261. }
  1262. /* only upper 6 bits (HASH_BITS) are used
  1263. * which point to specific bit in he hash registers
  1264. */
  1265. hash = (crc >> (32 - HASH_BITS)) & 0x3f;
  1266. if (hash > 31) {
  1267. tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  1268. tmp |= 1 << (hash - 32);
  1269. writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  1270. } else {
  1271. tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  1272. tmp |= 1 << hash;
  1273. writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  1274. }
  1275. }
  1276. }
  1277. /* Set a MAC change in hardware. */
  1278. static int
  1279. fec_set_mac_address(struct net_device *ndev, void *p)
  1280. {
  1281. struct fec_enet_private *fep = netdev_priv(ndev);
  1282. struct sockaddr *addr = p;
  1283. if (!is_valid_ether_addr(addr->sa_data))
  1284. return -EADDRNOTAVAIL;
  1285. memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
  1286. writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
  1287. (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
  1288. fep->hwp + FEC_ADDR_LOW);
  1289. writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
  1290. fep->hwp + FEC_ADDR_HIGH);
  1291. return 0;
  1292. }
  1293. #ifdef CONFIG_NET_POLL_CONTROLLER
  1294. /**
  1295. * fec_poll_controller - FEC Poll controller function
  1296. * @dev: The FEC network adapter
  1297. *
  1298. * Polled functionality used by netconsole and others in non interrupt mode
  1299. *
  1300. */
  1301. void fec_poll_controller(struct net_device *dev)
  1302. {
  1303. int i;
  1304. struct fec_enet_private *fep = netdev_priv(dev);
  1305. for (i = 0; i < FEC_IRQ_NUM; i++) {
  1306. if (fep->irq[i] > 0) {
  1307. disable_irq(fep->irq[i]);
  1308. fec_enet_interrupt(fep->irq[i], dev);
  1309. enable_irq(fep->irq[i]);
  1310. }
  1311. }
  1312. }
  1313. #endif
  1314. static const struct net_device_ops fec_netdev_ops = {
  1315. .ndo_open = fec_enet_open,
  1316. .ndo_stop = fec_enet_close,
  1317. .ndo_start_xmit = fec_enet_start_xmit,
  1318. .ndo_set_rx_mode = set_multicast_list,
  1319. .ndo_change_mtu = eth_change_mtu,
  1320. .ndo_validate_addr = eth_validate_addr,
  1321. .ndo_tx_timeout = fec_timeout,
  1322. .ndo_set_mac_address = fec_set_mac_address,
  1323. .ndo_do_ioctl = fec_enet_ioctl,
  1324. #ifdef CONFIG_NET_POLL_CONTROLLER
  1325. .ndo_poll_controller = fec_poll_controller,
  1326. #endif
  1327. };
  1328. /*
  1329. * XXX: We need to clean up on failure exits here.
  1330. *
  1331. */
  1332. static int fec_enet_init(struct net_device *ndev)
  1333. {
  1334. struct fec_enet_private *fep = netdev_priv(ndev);
  1335. struct bufdesc *cbd_base;
  1336. struct bufdesc *bdp;
  1337. int i;
  1338. /* Allocate memory for buffer descriptors. */
  1339. cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
  1340. GFP_KERNEL);
  1341. if (!cbd_base) {
  1342. printk("FEC: allocate descriptor memory failed?\n");
  1343. return -ENOMEM;
  1344. }
  1345. spin_lock_init(&fep->hw_lock);
  1346. fep->netdev = ndev;
  1347. /* Get the Ethernet address */
  1348. fec_get_mac(ndev);
  1349. /* Set receive and transmit descriptor base. */
  1350. fep->rx_bd_base = cbd_base;
  1351. if (fep->bufdesc_ex)
  1352. fep->tx_bd_base = (struct bufdesc *)
  1353. (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE);
  1354. else
  1355. fep->tx_bd_base = cbd_base + RX_RING_SIZE;
  1356. /* The FEC Ethernet specific entries in the device structure */
  1357. ndev->watchdog_timeo = TX_TIMEOUT;
  1358. ndev->netdev_ops = &fec_netdev_ops;
  1359. ndev->ethtool_ops = &fec_enet_ethtool_ops;
  1360. writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
  1361. netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
  1362. /* Initialize the receive buffer descriptors. */
  1363. bdp = fep->rx_bd_base;
  1364. for (i = 0; i < RX_RING_SIZE; i++) {
  1365. /* Initialize the BD for every fragment in the page. */
  1366. bdp->cbd_sc = 0;
  1367. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  1368. }
  1369. /* Set the last buffer to wrap */
  1370. bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
  1371. bdp->cbd_sc |= BD_SC_WRAP;
  1372. /* ...and the same for transmit */
  1373. bdp = fep->tx_bd_base;
  1374. fep->cur_tx = bdp;
  1375. for (i = 0; i < TX_RING_SIZE; i++) {
  1376. /* Initialize the BD for every fragment in the page. */
  1377. bdp->cbd_sc = 0;
  1378. bdp->cbd_bufaddr = 0;
  1379. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  1380. }
  1381. /* Set the last buffer to wrap */
  1382. bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
  1383. bdp->cbd_sc |= BD_SC_WRAP;
  1384. fep->dirty_tx = bdp;
  1385. fec_restart(ndev, 0);
  1386. return 0;
  1387. }
  1388. #ifdef CONFIG_OF
  1389. static int fec_get_phy_mode_dt(struct platform_device *pdev)
  1390. {
  1391. struct device_node *np = pdev->dev.of_node;
  1392. if (np)
  1393. return of_get_phy_mode(np);
  1394. return -ENODEV;
  1395. }
  1396. static void fec_reset_phy(struct platform_device *pdev)
  1397. {
  1398. int err, phy_reset;
  1399. int msec = 1;
  1400. struct device_node *np = pdev->dev.of_node;
  1401. if (!np)
  1402. return;
  1403. of_property_read_u32(np, "phy-reset-duration", &msec);
  1404. /* A sane reset duration should not be longer than 1s */
  1405. if (msec > 1000)
  1406. msec = 1;
  1407. phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
  1408. if (!gpio_is_valid(phy_reset))
  1409. return;
  1410. err = devm_gpio_request_one(&pdev->dev, phy_reset,
  1411. GPIOF_OUT_INIT_LOW, "phy-reset");
  1412. if (err) {
  1413. dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
  1414. return;
  1415. }
  1416. msleep(msec);
  1417. gpio_set_value(phy_reset, 1);
  1418. }
  1419. #else /* CONFIG_OF */
  1420. static int fec_get_phy_mode_dt(struct platform_device *pdev)
  1421. {
  1422. return -ENODEV;
  1423. }
  1424. static void fec_reset_phy(struct platform_device *pdev)
  1425. {
  1426. /*
  1427. * In case of platform probe, the reset has been done
  1428. * by machine code.
  1429. */
  1430. }
  1431. #endif /* CONFIG_OF */
  1432. static int
  1433. fec_probe(struct platform_device *pdev)
  1434. {
  1435. struct fec_enet_private *fep;
  1436. struct fec_platform_data *pdata;
  1437. struct net_device *ndev;
  1438. int i, irq, ret = 0;
  1439. struct resource *r;
  1440. const struct of_device_id *of_id;
  1441. static int dev_id;
  1442. struct pinctrl *pinctrl;
  1443. struct regulator *reg_phy;
  1444. of_id = of_match_device(fec_dt_ids, &pdev->dev);
  1445. if (of_id)
  1446. pdev->id_entry = of_id->data;
  1447. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1448. if (!r)
  1449. return -ENXIO;
  1450. r = request_mem_region(r->start, resource_size(r), pdev->name);
  1451. if (!r)
  1452. return -EBUSY;
  1453. /* Init network device */
  1454. ndev = alloc_etherdev(sizeof(struct fec_enet_private));
  1455. if (!ndev) {
  1456. ret = -ENOMEM;
  1457. goto failed_alloc_etherdev;
  1458. }
  1459. SET_NETDEV_DEV(ndev, &pdev->dev);
  1460. /* setup board info structure */
  1461. fep = netdev_priv(ndev);
  1462. /* default enable pause frame auto negotiation */
  1463. if (pdev->id_entry &&
  1464. (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
  1465. fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
  1466. fep->hwp = ioremap(r->start, resource_size(r));
  1467. fep->pdev = pdev;
  1468. fep->dev_id = dev_id++;
  1469. fep->bufdesc_ex = 0;
  1470. if (!fep->hwp) {
  1471. ret = -ENOMEM;
  1472. goto failed_ioremap;
  1473. }
  1474. platform_set_drvdata(pdev, ndev);
  1475. ret = fec_get_phy_mode_dt(pdev);
  1476. if (ret < 0) {
  1477. pdata = pdev->dev.platform_data;
  1478. if (pdata)
  1479. fep->phy_interface = pdata->phy;
  1480. else
  1481. fep->phy_interface = PHY_INTERFACE_MODE_MII;
  1482. } else {
  1483. fep->phy_interface = ret;
  1484. }
  1485. pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
  1486. if (IS_ERR(pinctrl)) {
  1487. ret = PTR_ERR(pinctrl);
  1488. goto failed_pin;
  1489. }
  1490. fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
  1491. if (IS_ERR(fep->clk_ipg)) {
  1492. ret = PTR_ERR(fep->clk_ipg);
  1493. goto failed_clk;
  1494. }
  1495. fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
  1496. if (IS_ERR(fep->clk_ahb)) {
  1497. ret = PTR_ERR(fep->clk_ahb);
  1498. goto failed_clk;
  1499. }
  1500. fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
  1501. fep->bufdesc_ex =
  1502. pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
  1503. if (IS_ERR(fep->clk_ptp)) {
  1504. ret = PTR_ERR(fep->clk_ptp);
  1505. fep->bufdesc_ex = 0;
  1506. }
  1507. clk_prepare_enable(fep->clk_ahb);
  1508. clk_prepare_enable(fep->clk_ipg);
  1509. if (!IS_ERR(fep->clk_ptp))
  1510. clk_prepare_enable(fep->clk_ptp);
  1511. reg_phy = devm_regulator_get(&pdev->dev, "phy");
  1512. if (!IS_ERR(reg_phy)) {
  1513. ret = regulator_enable(reg_phy);
  1514. if (ret) {
  1515. dev_err(&pdev->dev,
  1516. "Failed to enable phy regulator: %d\n", ret);
  1517. goto failed_regulator;
  1518. }
  1519. }
  1520. fec_reset_phy(pdev);
  1521. if (fep->bufdesc_ex)
  1522. fec_ptp_init(ndev, pdev);
  1523. ret = fec_enet_init(ndev);
  1524. if (ret)
  1525. goto failed_init;
  1526. for (i = 0; i < FEC_IRQ_NUM; i++) {
  1527. irq = platform_get_irq(pdev, i);
  1528. if (irq < 0) {
  1529. if (i)
  1530. break;
  1531. ret = irq;
  1532. goto failed_irq;
  1533. }
  1534. ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
  1535. if (ret) {
  1536. while (--i >= 0) {
  1537. irq = platform_get_irq(pdev, i);
  1538. free_irq(irq, ndev);
  1539. }
  1540. goto failed_irq;
  1541. }
  1542. }
  1543. ret = fec_enet_mii_init(pdev);
  1544. if (ret)
  1545. goto failed_mii_init;
  1546. /* Carrier starts down, phylib will bring it up */
  1547. netif_carrier_off(ndev);
  1548. ret = register_netdev(ndev);
  1549. if (ret)
  1550. goto failed_register;
  1551. return 0;
  1552. failed_register:
  1553. fec_enet_mii_remove(fep);
  1554. failed_mii_init:
  1555. failed_init:
  1556. for (i = 0; i < FEC_IRQ_NUM; i++) {
  1557. irq = platform_get_irq(pdev, i);
  1558. if (irq > 0)
  1559. free_irq(irq, ndev);
  1560. }
  1561. failed_irq:
  1562. failed_regulator:
  1563. clk_disable_unprepare(fep->clk_ahb);
  1564. clk_disable_unprepare(fep->clk_ipg);
  1565. if (!IS_ERR(fep->clk_ptp))
  1566. clk_disable_unprepare(fep->clk_ptp);
  1567. failed_pin:
  1568. failed_clk:
  1569. iounmap(fep->hwp);
  1570. failed_ioremap:
  1571. free_netdev(ndev);
  1572. failed_alloc_etherdev:
  1573. release_mem_region(r->start, resource_size(r));
  1574. return ret;
  1575. }
  1576. static int
  1577. fec_drv_remove(struct platform_device *pdev)
  1578. {
  1579. struct net_device *ndev = platform_get_drvdata(pdev);
  1580. struct fec_enet_private *fep = netdev_priv(ndev);
  1581. struct resource *r;
  1582. int i;
  1583. unregister_netdev(ndev);
  1584. fec_enet_mii_remove(fep);
  1585. del_timer_sync(&fep->time_keep);
  1586. clk_disable_unprepare(fep->clk_ptp);
  1587. if (fep->ptp_clock)
  1588. ptp_clock_unregister(fep->ptp_clock);
  1589. clk_disable_unprepare(fep->clk_ahb);
  1590. clk_disable_unprepare(fep->clk_ipg);
  1591. for (i = 0; i < FEC_IRQ_NUM; i++) {
  1592. int irq = platform_get_irq(pdev, i);
  1593. if (irq > 0)
  1594. free_irq(irq, ndev);
  1595. }
  1596. iounmap(fep->hwp);
  1597. free_netdev(ndev);
  1598. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1599. BUG_ON(!r);
  1600. release_mem_region(r->start, resource_size(r));
  1601. platform_set_drvdata(pdev, NULL);
  1602. return 0;
  1603. }
  1604. #ifdef CONFIG_PM
  1605. static int
  1606. fec_suspend(struct device *dev)
  1607. {
  1608. struct net_device *ndev = dev_get_drvdata(dev);
  1609. struct fec_enet_private *fep = netdev_priv(ndev);
  1610. if (netif_running(ndev)) {
  1611. fec_stop(ndev);
  1612. netif_device_detach(ndev);
  1613. }
  1614. clk_disable_unprepare(fep->clk_ahb);
  1615. clk_disable_unprepare(fep->clk_ipg);
  1616. return 0;
  1617. }
  1618. static int
  1619. fec_resume(struct device *dev)
  1620. {
  1621. struct net_device *ndev = dev_get_drvdata(dev);
  1622. struct fec_enet_private *fep = netdev_priv(ndev);
  1623. clk_prepare_enable(fep->clk_ahb);
  1624. clk_prepare_enable(fep->clk_ipg);
  1625. if (netif_running(ndev)) {
  1626. fec_restart(ndev, fep->full_duplex);
  1627. netif_device_attach(ndev);
  1628. }
  1629. return 0;
  1630. }
  1631. static const struct dev_pm_ops fec_pm_ops = {
  1632. .suspend = fec_suspend,
  1633. .resume = fec_resume,
  1634. .freeze = fec_suspend,
  1635. .thaw = fec_resume,
  1636. .poweroff = fec_suspend,
  1637. .restore = fec_resume,
  1638. };
  1639. #endif
  1640. static struct platform_driver fec_driver = {
  1641. .driver = {
  1642. .name = DRIVER_NAME,
  1643. .owner = THIS_MODULE,
  1644. #ifdef CONFIG_PM
  1645. .pm = &fec_pm_ops,
  1646. #endif
  1647. .of_match_table = fec_dt_ids,
  1648. },
  1649. .id_table = fec_devtype,
  1650. .probe = fec_probe,
  1651. .remove = fec_drv_remove,
  1652. };
  1653. module_platform_driver(fec_driver);
  1654. MODULE_LICENSE("GPL");