gpmi-nand.h 11 KB

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  1. /*
  2. * Freescale GPMI NAND Flash Driver
  3. *
  4. * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  5. * Copyright (C) 2008 Embedded Alley Solutions, Inc.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #ifndef __DRIVERS_MTD_NAND_GPMI_NAND_H
  18. #define __DRIVERS_MTD_NAND_GPMI_NAND_H
  19. #include <linux/mtd/nand.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/dma-mapping.h>
  22. #include <linux/fsl/mxs-dma.h>
  23. #define GPMI_CLK_MAX 5 /* MX6Q needs five clocks */
  24. struct resources {
  25. void __iomem *gpmi_regs;
  26. void __iomem *bch_regs;
  27. unsigned int bch_low_interrupt;
  28. unsigned int bch_high_interrupt;
  29. unsigned int dma_low_channel;
  30. unsigned int dma_high_channel;
  31. struct clk *clock[GPMI_CLK_MAX];
  32. };
  33. /**
  34. * struct bch_geometry - BCH geometry description.
  35. * @gf_len: The length of Galois Field. (e.g., 13 or 14)
  36. * @ecc_strength: A number that describes the strength of the ECC
  37. * algorithm.
  38. * @page_size: The size, in bytes, of a physical page, including
  39. * both data and OOB.
  40. * @metadata_size: The size, in bytes, of the metadata.
  41. * @ecc_chunk_size: The size, in bytes, of a single ECC chunk. Note
  42. * the first chunk in the page includes both data and
  43. * metadata, so it's a bit larger than this value.
  44. * @ecc_chunk_count: The number of ECC chunks in the page,
  45. * @payload_size: The size, in bytes, of the payload buffer.
  46. * @auxiliary_size: The size, in bytes, of the auxiliary buffer.
  47. * @auxiliary_status_offset: The offset into the auxiliary buffer at which
  48. * the ECC status appears.
  49. * @block_mark_byte_offset: The byte offset in the ECC-based page view at
  50. * which the underlying physical block mark appears.
  51. * @block_mark_bit_offset: The bit offset into the ECC-based page view at
  52. * which the underlying physical block mark appears.
  53. */
  54. struct bch_geometry {
  55. unsigned int gf_len;
  56. unsigned int ecc_strength;
  57. unsigned int page_size;
  58. unsigned int metadata_size;
  59. unsigned int ecc_chunk_size;
  60. unsigned int ecc_chunk_count;
  61. unsigned int payload_size;
  62. unsigned int auxiliary_size;
  63. unsigned int auxiliary_status_offset;
  64. unsigned int block_mark_byte_offset;
  65. unsigned int block_mark_bit_offset;
  66. };
  67. /**
  68. * struct boot_rom_geometry - Boot ROM geometry description.
  69. * @stride_size_in_pages: The size of a boot block stride, in pages.
  70. * @search_area_stride_exponent: The logarithm to base 2 of the size of a
  71. * search area in boot block strides.
  72. */
  73. struct boot_rom_geometry {
  74. unsigned int stride_size_in_pages;
  75. unsigned int search_area_stride_exponent;
  76. };
  77. /* DMA operations types */
  78. enum dma_ops_type {
  79. DMA_FOR_COMMAND = 1,
  80. DMA_FOR_READ_DATA,
  81. DMA_FOR_WRITE_DATA,
  82. DMA_FOR_READ_ECC_PAGE,
  83. DMA_FOR_WRITE_ECC_PAGE
  84. };
  85. /**
  86. * struct nand_timing - Fundamental timing attributes for NAND.
  87. * @data_setup_in_ns: The data setup time, in nanoseconds. Usually the
  88. * maximum of tDS and tWP. A negative value
  89. * indicates this characteristic isn't known.
  90. * @data_hold_in_ns: The data hold time, in nanoseconds. Usually the
  91. * maximum of tDH, tWH and tREH. A negative value
  92. * indicates this characteristic isn't known.
  93. * @address_setup_in_ns: The address setup time, in nanoseconds. Usually
  94. * the maximum of tCLS, tCS and tALS. A negative
  95. * value indicates this characteristic isn't known.
  96. * @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative value
  97. * indicates this characteristic isn't known.
  98. * @tREA_in_ns: tREA, in nanoseconds, from the data sheet. A
  99. * negative value indicates this characteristic isn't
  100. * known.
  101. * @tRLOH_in_ns: tRLOH, in nanoseconds, from the data sheet. A
  102. * negative value indicates this characteristic isn't
  103. * known.
  104. * @tRHOH_in_ns: tRHOH, in nanoseconds, from the data sheet. A
  105. * negative value indicates this characteristic isn't
  106. * known.
  107. */
  108. struct nand_timing {
  109. int8_t data_setup_in_ns;
  110. int8_t data_hold_in_ns;
  111. int8_t address_setup_in_ns;
  112. int8_t gpmi_sample_delay_in_ns;
  113. int8_t tREA_in_ns;
  114. int8_t tRLOH_in_ns;
  115. int8_t tRHOH_in_ns;
  116. };
  117. struct gpmi_nand_data {
  118. /* flags */
  119. #define GPMI_ASYNC_EDO_ENABLED (1 << 0)
  120. #define GPMI_TIMING_INIT_OK (1 << 1)
  121. int flags;
  122. /* System Interface */
  123. struct device *dev;
  124. struct platform_device *pdev;
  125. /* Resources */
  126. struct resources resources;
  127. /* Flash Hardware */
  128. struct nand_timing timing;
  129. int timing_mode;
  130. /* BCH */
  131. struct bch_geometry bch_geometry;
  132. struct completion bch_done;
  133. /* NAND Boot issue */
  134. bool swap_block_mark;
  135. struct boot_rom_geometry rom_geometry;
  136. /* MTD / NAND */
  137. struct nand_chip nand;
  138. struct mtd_info mtd;
  139. /* General-use Variables */
  140. int current_chip;
  141. unsigned int command_length;
  142. /* passed from upper layer */
  143. uint8_t *upper_buf;
  144. int upper_len;
  145. /* for DMA operations */
  146. bool direct_dma_map_ok;
  147. struct scatterlist cmd_sgl;
  148. char *cmd_buffer;
  149. struct scatterlist data_sgl;
  150. char *data_buffer_dma;
  151. void *page_buffer_virt;
  152. dma_addr_t page_buffer_phys;
  153. unsigned int page_buffer_size;
  154. void *payload_virt;
  155. dma_addr_t payload_phys;
  156. void *auxiliary_virt;
  157. dma_addr_t auxiliary_phys;
  158. /* DMA channels */
  159. #define DMA_CHANS 8
  160. struct dma_chan *dma_chans[DMA_CHANS];
  161. struct mxs_dma_data dma_data;
  162. enum dma_ops_type last_dma_type;
  163. enum dma_ops_type dma_type;
  164. struct completion dma_done;
  165. /* private */
  166. void *private;
  167. };
  168. /**
  169. * struct gpmi_nfc_hardware_timing - GPMI hardware timing parameters.
  170. * @data_setup_in_cycles: The data setup time, in cycles.
  171. * @data_hold_in_cycles: The data hold time, in cycles.
  172. * @address_setup_in_cycles: The address setup time, in cycles.
  173. * @device_busy_timeout: The timeout waiting for NAND Ready/Busy,
  174. * this value is the number of cycles multiplied
  175. * by 4096.
  176. * @use_half_periods: Indicates the clock is running slowly, so the
  177. * NFC DLL should use half-periods.
  178. * @sample_delay_factor: The sample delay factor.
  179. * @wrn_dly_sel: The delay on the GPMI write strobe.
  180. */
  181. struct gpmi_nfc_hardware_timing {
  182. /* for HW_GPMI_TIMING0 */
  183. uint8_t data_setup_in_cycles;
  184. uint8_t data_hold_in_cycles;
  185. uint8_t address_setup_in_cycles;
  186. /* for HW_GPMI_TIMING1 */
  187. uint16_t device_busy_timeout;
  188. #define GPMI_DEFAULT_BUSY_TIMEOUT 0x500 /* default busy timeout value.*/
  189. /* for HW_GPMI_CTRL1 */
  190. bool use_half_periods;
  191. uint8_t sample_delay_factor;
  192. uint8_t wrn_dly_sel;
  193. };
  194. /**
  195. * struct timing_threshod - Timing threshold
  196. * @max_data_setup_cycles: The maximum number of data setup cycles that
  197. * can be expressed in the hardware.
  198. * @internal_data_setup_in_ns: The time, in ns, that the NFC hardware requires
  199. * for data read internal setup. In the Reference
  200. * Manual, see the chapter "High-Speed NAND
  201. * Timing" for more details.
  202. * @max_sample_delay_factor: The maximum sample delay factor that can be
  203. * expressed in the hardware.
  204. * @max_dll_clock_period_in_ns: The maximum period of the GPMI clock that the
  205. * sample delay DLL hardware can possibly work
  206. * with (the DLL is unusable with longer periods).
  207. * If the full-cycle period is greater than HALF
  208. * this value, the DLL must be configured to use
  209. * half-periods.
  210. * @max_dll_delay_in_ns: The maximum amount of delay, in ns, that the
  211. * DLL can implement.
  212. * @clock_frequency_in_hz: The clock frequency, in Hz, during the current
  213. * I/O transaction. If no I/O transaction is in
  214. * progress, this is the clock frequency during
  215. * the most recent I/O transaction.
  216. */
  217. struct timing_threshod {
  218. const unsigned int max_chip_count;
  219. const unsigned int max_data_setup_cycles;
  220. const unsigned int internal_data_setup_in_ns;
  221. const unsigned int max_sample_delay_factor;
  222. const unsigned int max_dll_clock_period_in_ns;
  223. const unsigned int max_dll_delay_in_ns;
  224. unsigned long clock_frequency_in_hz;
  225. };
  226. /* Common Services */
  227. extern int common_nfc_set_geometry(struct gpmi_nand_data *);
  228. extern struct dma_chan *get_dma_chan(struct gpmi_nand_data *);
  229. extern void prepare_data_dma(struct gpmi_nand_data *,
  230. enum dma_data_direction dr);
  231. extern int start_dma_without_bch_irq(struct gpmi_nand_data *,
  232. struct dma_async_tx_descriptor *);
  233. extern int start_dma_with_bch_irq(struct gpmi_nand_data *,
  234. struct dma_async_tx_descriptor *);
  235. /* GPMI-NAND helper function library */
  236. extern int gpmi_init(struct gpmi_nand_data *);
  237. extern int gpmi_extra_init(struct gpmi_nand_data *);
  238. extern void gpmi_clear_bch(struct gpmi_nand_data *);
  239. extern void gpmi_dump_info(struct gpmi_nand_data *);
  240. extern int bch_set_geometry(struct gpmi_nand_data *);
  241. extern int gpmi_is_ready(struct gpmi_nand_data *, unsigned chip);
  242. extern int gpmi_send_command(struct gpmi_nand_data *);
  243. extern void gpmi_begin(struct gpmi_nand_data *);
  244. extern void gpmi_end(struct gpmi_nand_data *);
  245. extern int gpmi_read_data(struct gpmi_nand_data *);
  246. extern int gpmi_send_data(struct gpmi_nand_data *);
  247. extern int gpmi_send_page(struct gpmi_nand_data *,
  248. dma_addr_t payload, dma_addr_t auxiliary);
  249. extern int gpmi_read_page(struct gpmi_nand_data *,
  250. dma_addr_t payload, dma_addr_t auxiliary);
  251. /* BCH : Status Block Completion Codes */
  252. #define STATUS_GOOD 0x00
  253. #define STATUS_ERASED 0xff
  254. #define STATUS_UNCORRECTABLE 0xfe
  255. /* BCH's bit correction capability. */
  256. #define MXS_ECC_STRENGTH_MAX 20 /* mx23 and mx28 */
  257. #define MX6_ECC_STRENGTH_MAX 40
  258. /* Use the platform_id to distinguish different Archs. */
  259. #define IS_MX23 0x0
  260. #define IS_MX28 0x1
  261. #define IS_MX6Q 0x2
  262. #define GPMI_IS_MX23(x) ((x)->pdev->id_entry->driver_data == IS_MX23)
  263. #define GPMI_IS_MX28(x) ((x)->pdev->id_entry->driver_data == IS_MX28)
  264. #define GPMI_IS_MX6Q(x) ((x)->pdev->id_entry->driver_data == IS_MX6Q)
  265. #endif