twl4030-power.c 14 KB

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  1. /*
  2. * linux/drivers/i2c/chips/twl4030-power.c
  3. *
  4. * Handle TWL4030 Power initialization
  5. *
  6. * Copyright (C) 2008 Nokia Corporation
  7. * Copyright (C) 2006 Texas Instruments, Inc
  8. *
  9. * Written by Kalle Jokiniemi
  10. * Peter De Schrijver <peter.de-schrijver@nokia.com>
  11. * Several fixes by Amit Kucheria <amit.kucheria@verdurent.com>
  12. *
  13. * This file is subject to the terms and conditions of the GNU General
  14. * Public License. See the file "COPYING" in the main directory of this
  15. * archive for more details.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  25. */
  26. #include <linux/module.h>
  27. #include <linux/pm.h>
  28. #include <linux/i2c/twl.h>
  29. #include <linux/platform_device.h>
  30. #include <asm/mach-types.h>
  31. static u8 twl4030_start_script_address = 0x2b;
  32. #define PWR_P1_SW_EVENTS 0x10
  33. #define PWR_DEVOFF (1 << 0)
  34. #define SEQ_OFFSYNC (1 << 0)
  35. #define PHY_TO_OFF_PM_MASTER(p) (p - 0x36)
  36. #define PHY_TO_OFF_PM_RECEIVER(p) (p - 0x5b)
  37. /* resource - hfclk */
  38. #define R_HFCLKOUT_DEV_GRP PHY_TO_OFF_PM_RECEIVER(0xe6)
  39. /* PM events */
  40. #define R_P1_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x46)
  41. #define R_P2_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x47)
  42. #define R_P3_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x48)
  43. #define R_CFG_P1_TRANSITION PHY_TO_OFF_PM_MASTER(0x36)
  44. #define R_CFG_P2_TRANSITION PHY_TO_OFF_PM_MASTER(0x37)
  45. #define R_CFG_P3_TRANSITION PHY_TO_OFF_PM_MASTER(0x38)
  46. #define LVL_WAKEUP 0x08
  47. #define ENABLE_WARMRESET (1<<4)
  48. #define END_OF_SCRIPT 0x3f
  49. #define R_SEQ_ADD_A2S PHY_TO_OFF_PM_MASTER(0x55)
  50. #define R_SEQ_ADD_S2A12 PHY_TO_OFF_PM_MASTER(0x56)
  51. #define R_SEQ_ADD_S2A3 PHY_TO_OFF_PM_MASTER(0x57)
  52. #define R_SEQ_ADD_WARM PHY_TO_OFF_PM_MASTER(0x58)
  53. #define R_MEMORY_ADDRESS PHY_TO_OFF_PM_MASTER(0x59)
  54. #define R_MEMORY_DATA PHY_TO_OFF_PM_MASTER(0x5a)
  55. /* resource configuration registers
  56. <RESOURCE>_DEV_GRP at address 'n+0'
  57. <RESOURCE>_TYPE at address 'n+1'
  58. <RESOURCE>_REMAP at address 'n+2'
  59. <RESOURCE>_DEDICATED at address 'n+3'
  60. */
  61. #define DEV_GRP_OFFSET 0
  62. #define TYPE_OFFSET 1
  63. #define REMAP_OFFSET 2
  64. #define DEDICATED_OFFSET 3
  65. /* Bit positions in the registers */
  66. /* <RESOURCE>_DEV_GRP */
  67. #define DEV_GRP_SHIFT 5
  68. #define DEV_GRP_MASK (7 << DEV_GRP_SHIFT)
  69. /* <RESOURCE>_TYPE */
  70. #define TYPE_SHIFT 0
  71. #define TYPE_MASK (7 << TYPE_SHIFT)
  72. #define TYPE2_SHIFT 3
  73. #define TYPE2_MASK (3 << TYPE2_SHIFT)
  74. /* <RESOURCE>_REMAP */
  75. #define SLEEP_STATE_SHIFT 0
  76. #define SLEEP_STATE_MASK (0xf << SLEEP_STATE_SHIFT)
  77. #define OFF_STATE_SHIFT 4
  78. #define OFF_STATE_MASK (0xf << OFF_STATE_SHIFT)
  79. static u8 res_config_addrs[] = {
  80. [RES_VAUX1] = 0x17,
  81. [RES_VAUX2] = 0x1b,
  82. [RES_VAUX3] = 0x1f,
  83. [RES_VAUX4] = 0x23,
  84. [RES_VMMC1] = 0x27,
  85. [RES_VMMC2] = 0x2b,
  86. [RES_VPLL1] = 0x2f,
  87. [RES_VPLL2] = 0x33,
  88. [RES_VSIM] = 0x37,
  89. [RES_VDAC] = 0x3b,
  90. [RES_VINTANA1] = 0x3f,
  91. [RES_VINTANA2] = 0x43,
  92. [RES_VINTDIG] = 0x47,
  93. [RES_VIO] = 0x4b,
  94. [RES_VDD1] = 0x55,
  95. [RES_VDD2] = 0x63,
  96. [RES_VUSB_1V5] = 0x71,
  97. [RES_VUSB_1V8] = 0x74,
  98. [RES_VUSB_3V1] = 0x77,
  99. [RES_VUSBCP] = 0x7a,
  100. [RES_REGEN] = 0x7f,
  101. [RES_NRES_PWRON] = 0x82,
  102. [RES_CLKEN] = 0x85,
  103. [RES_SYSEN] = 0x88,
  104. [RES_HFCLKOUT] = 0x8b,
  105. [RES_32KCLKOUT] = 0x8e,
  106. [RES_RESET] = 0x91,
  107. [RES_MAIN_REF] = 0x94,
  108. };
  109. static int twl4030_write_script_byte(u8 address, u8 byte)
  110. {
  111. int err;
  112. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_MEMORY_ADDRESS);
  113. if (err)
  114. goto out;
  115. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, byte, R_MEMORY_DATA);
  116. out:
  117. return err;
  118. }
  119. static int twl4030_write_script_ins(u8 address, u16 pmb_message,
  120. u8 delay, u8 next)
  121. {
  122. int err;
  123. address *= 4;
  124. err = twl4030_write_script_byte(address++, pmb_message >> 8);
  125. if (err)
  126. goto out;
  127. err = twl4030_write_script_byte(address++, pmb_message & 0xff);
  128. if (err)
  129. goto out;
  130. err = twl4030_write_script_byte(address++, delay);
  131. if (err)
  132. goto out;
  133. err = twl4030_write_script_byte(address++, next);
  134. out:
  135. return err;
  136. }
  137. static int twl4030_write_script(u8 address, struct twl4030_ins *script,
  138. int len)
  139. {
  140. int err = -EINVAL;
  141. for (; len; len--, address++, script++) {
  142. if (len == 1) {
  143. err = twl4030_write_script_ins(address,
  144. script->pmb_message,
  145. script->delay,
  146. END_OF_SCRIPT);
  147. if (err)
  148. break;
  149. } else {
  150. err = twl4030_write_script_ins(address,
  151. script->pmb_message,
  152. script->delay,
  153. address + 1);
  154. if (err)
  155. break;
  156. }
  157. }
  158. return err;
  159. }
  160. static int twl4030_config_wakeup3_sequence(u8 address)
  161. {
  162. int err;
  163. u8 data;
  164. /* Set SLEEP to ACTIVE SEQ address for P3 */
  165. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_S2A3);
  166. if (err)
  167. goto out;
  168. /* P3 LVL_WAKEUP should be on LEVEL */
  169. err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P3_SW_EVENTS);
  170. if (err)
  171. goto out;
  172. data |= LVL_WAKEUP;
  173. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P3_SW_EVENTS);
  174. out:
  175. if (err)
  176. pr_err("TWL4030 wakeup sequence for P3 config error\n");
  177. return err;
  178. }
  179. static int twl4030_config_wakeup12_sequence(u8 address)
  180. {
  181. int err = 0;
  182. u8 data;
  183. /* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
  184. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_S2A12);
  185. if (err)
  186. goto out;
  187. /* P1/P2 LVL_WAKEUP should be on LEVEL */
  188. err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P1_SW_EVENTS);
  189. if (err)
  190. goto out;
  191. data |= LVL_WAKEUP;
  192. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P1_SW_EVENTS);
  193. if (err)
  194. goto out;
  195. err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P2_SW_EVENTS);
  196. if (err)
  197. goto out;
  198. data |= LVL_WAKEUP;
  199. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P2_SW_EVENTS);
  200. if (err)
  201. goto out;
  202. if (machine_is_omap_3430sdp() || machine_is_omap_ldp()) {
  203. /* Disabling AC charger effect on sleep-active transitions */
  204. err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data,
  205. R_CFG_P1_TRANSITION);
  206. if (err)
  207. goto out;
  208. data &= ~(1<<1);
  209. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data,
  210. R_CFG_P1_TRANSITION);
  211. if (err)
  212. goto out;
  213. }
  214. out:
  215. if (err)
  216. pr_err("TWL4030 wakeup sequence for P1 and P2" \
  217. "config error\n");
  218. return err;
  219. }
  220. static int twl4030_config_sleep_sequence(u8 address)
  221. {
  222. int err;
  223. /* Set ACTIVE to SLEEP SEQ address in T2 memory*/
  224. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_A2S);
  225. if (err)
  226. pr_err("TWL4030 sleep sequence config error\n");
  227. return err;
  228. }
  229. static int twl4030_config_warmreset_sequence(u8 address)
  230. {
  231. int err;
  232. u8 rd_data;
  233. /* Set WARM RESET SEQ address for P1 */
  234. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_WARM);
  235. if (err)
  236. goto out;
  237. /* P1/P2/P3 enable WARMRESET */
  238. err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P1_SW_EVENTS);
  239. if (err)
  240. goto out;
  241. rd_data |= ENABLE_WARMRESET;
  242. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P1_SW_EVENTS);
  243. if (err)
  244. goto out;
  245. err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P2_SW_EVENTS);
  246. if (err)
  247. goto out;
  248. rd_data |= ENABLE_WARMRESET;
  249. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P2_SW_EVENTS);
  250. if (err)
  251. goto out;
  252. err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P3_SW_EVENTS);
  253. if (err)
  254. goto out;
  255. rd_data |= ENABLE_WARMRESET;
  256. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P3_SW_EVENTS);
  257. out:
  258. if (err)
  259. pr_err("TWL4030 warmreset seq config error\n");
  260. return err;
  261. }
  262. static int twl4030_configure_resource(struct twl4030_resconfig *rconfig)
  263. {
  264. int rconfig_addr;
  265. int err;
  266. u8 type;
  267. u8 grp;
  268. u8 remap;
  269. if (rconfig->resource > TOTAL_RESOURCES) {
  270. pr_err("TWL4030 Resource %d does not exist\n",
  271. rconfig->resource);
  272. return -EINVAL;
  273. }
  274. rconfig_addr = res_config_addrs[rconfig->resource];
  275. /* Set resource group */
  276. err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &grp,
  277. rconfig_addr + DEV_GRP_OFFSET);
  278. if (err) {
  279. pr_err("TWL4030 Resource %d group could not be read\n",
  280. rconfig->resource);
  281. return err;
  282. }
  283. if (rconfig->devgroup != TWL4030_RESCONFIG_UNDEF) {
  284. grp &= ~DEV_GRP_MASK;
  285. grp |= rconfig->devgroup << DEV_GRP_SHIFT;
  286. err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
  287. grp, rconfig_addr + DEV_GRP_OFFSET);
  288. if (err < 0) {
  289. pr_err("TWL4030 failed to program devgroup\n");
  290. return err;
  291. }
  292. }
  293. /* Set resource types */
  294. err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &type,
  295. rconfig_addr + TYPE_OFFSET);
  296. if (err < 0) {
  297. pr_err("TWL4030 Resource %d type could not be read\n",
  298. rconfig->resource);
  299. return err;
  300. }
  301. if (rconfig->type != TWL4030_RESCONFIG_UNDEF) {
  302. type &= ~TYPE_MASK;
  303. type |= rconfig->type << TYPE_SHIFT;
  304. }
  305. if (rconfig->type2 != TWL4030_RESCONFIG_UNDEF) {
  306. type &= ~TYPE2_MASK;
  307. type |= rconfig->type2 << TYPE2_SHIFT;
  308. }
  309. err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
  310. type, rconfig_addr + TYPE_OFFSET);
  311. if (err < 0) {
  312. pr_err("TWL4030 failed to program resource type\n");
  313. return err;
  314. }
  315. /* Set remap states */
  316. err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &remap,
  317. rconfig_addr + REMAP_OFFSET);
  318. if (err < 0) {
  319. pr_err("TWL4030 Resource %d remap could not be read\n",
  320. rconfig->resource);
  321. return err;
  322. }
  323. if (rconfig->remap_off != TWL4030_RESCONFIG_UNDEF) {
  324. remap &= ~OFF_STATE_MASK;
  325. remap |= rconfig->remap_off << OFF_STATE_SHIFT;
  326. }
  327. if (rconfig->remap_sleep != TWL4030_RESCONFIG_UNDEF) {
  328. remap &= ~SLEEP_STATE_MASK;
  329. remap |= rconfig->remap_sleep << SLEEP_STATE_SHIFT;
  330. }
  331. err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
  332. remap,
  333. rconfig_addr + REMAP_OFFSET);
  334. if (err < 0) {
  335. pr_err("TWL4030 failed to program remap\n");
  336. return err;
  337. }
  338. return 0;
  339. }
  340. static int load_twl4030_script(struct twl4030_script *tscript,
  341. u8 address)
  342. {
  343. int err;
  344. static int order;
  345. /* Make sure the script isn't going beyond last valid address (0x3f) */
  346. if ((address + tscript->size) > END_OF_SCRIPT) {
  347. pr_err("TWL4030 scripts too big error\n");
  348. return -EINVAL;
  349. }
  350. err = twl4030_write_script(address, tscript->script, tscript->size);
  351. if (err)
  352. goto out;
  353. if (tscript->flags & TWL4030_WRST_SCRIPT) {
  354. err = twl4030_config_warmreset_sequence(address);
  355. if (err)
  356. goto out;
  357. }
  358. if (tscript->flags & TWL4030_WAKEUP12_SCRIPT) {
  359. err = twl4030_config_wakeup12_sequence(address);
  360. if (err)
  361. goto out;
  362. order = 1;
  363. }
  364. if (tscript->flags & TWL4030_WAKEUP3_SCRIPT) {
  365. err = twl4030_config_wakeup3_sequence(address);
  366. if (err)
  367. goto out;
  368. }
  369. if (tscript->flags & TWL4030_SLEEP_SCRIPT) {
  370. if (!order)
  371. pr_warning("TWL4030: Bad order of scripts (sleep "\
  372. "script before wakeup) Leads to boot"\
  373. "failure on some boards\n");
  374. err = twl4030_config_sleep_sequence(address);
  375. }
  376. out:
  377. return err;
  378. }
  379. int twl4030_remove_script(u8 flags)
  380. {
  381. int err = 0;
  382. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
  383. TWL4030_PM_MASTER_PROTECT_KEY);
  384. if (err) {
  385. pr_err("twl4030: unable to unlock PROTECT_KEY\n");
  386. return err;
  387. }
  388. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
  389. TWL4030_PM_MASTER_PROTECT_KEY);
  390. if (err) {
  391. pr_err("twl4030: unable to unlock PROTECT_KEY\n");
  392. return err;
  393. }
  394. if (flags & TWL4030_WRST_SCRIPT) {
  395. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
  396. R_SEQ_ADD_WARM);
  397. if (err)
  398. return err;
  399. }
  400. if (flags & TWL4030_WAKEUP12_SCRIPT) {
  401. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
  402. R_SEQ_ADD_S2A12);
  403. if (err)
  404. return err;
  405. }
  406. if (flags & TWL4030_WAKEUP3_SCRIPT) {
  407. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
  408. R_SEQ_ADD_S2A3);
  409. if (err)
  410. return err;
  411. }
  412. if (flags & TWL4030_SLEEP_SCRIPT) {
  413. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
  414. R_SEQ_ADD_A2S);
  415. if (err)
  416. return err;
  417. }
  418. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
  419. TWL4030_PM_MASTER_PROTECT_KEY);
  420. if (err)
  421. pr_err("TWL4030 Unable to relock registers\n");
  422. return err;
  423. }
  424. /*
  425. * In master mode, start the power off sequence.
  426. * After a successful execution, TWL shuts down the power to the SoC
  427. * and all peripherals connected to it.
  428. */
  429. void twl4030_power_off(void)
  430. {
  431. int err;
  432. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, PWR_DEVOFF,
  433. TWL4030_PM_MASTER_P1_SW_EVENTS);
  434. if (err)
  435. pr_err("TWL4030 Unable to power off\n");
  436. }
  437. void twl4030_power_init(struct twl4030_power_data *twl4030_scripts)
  438. {
  439. int err = 0;
  440. int i;
  441. struct twl4030_resconfig *resconfig;
  442. u8 val, address = twl4030_start_script_address;
  443. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
  444. TWL4030_PM_MASTER_PROTECT_KEY);
  445. if (err)
  446. goto unlock;
  447. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
  448. TWL4030_PM_MASTER_PROTECT_KEY);
  449. if (err)
  450. goto unlock;
  451. for (i = 0; i < twl4030_scripts->num; i++) {
  452. err = load_twl4030_script(twl4030_scripts->scripts[i], address);
  453. if (err)
  454. goto load;
  455. address += twl4030_scripts->scripts[i]->size;
  456. }
  457. resconfig = twl4030_scripts->resource_config;
  458. if (resconfig) {
  459. while (resconfig->resource) {
  460. err = twl4030_configure_resource(resconfig);
  461. if (err)
  462. goto resource;
  463. resconfig++;
  464. }
  465. }
  466. /* Board has to be wired properly to use this feature */
  467. if (twl4030_scripts->use_poweroff && !pm_power_off) {
  468. /* Default for SEQ_OFFSYNC is set, lets ensure this */
  469. err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &val,
  470. TWL4030_PM_MASTER_CFG_P123_TRANSITION);
  471. if (err) {
  472. pr_warning("TWL4030 Unable to read registers\n");
  473. } else if (!(val & SEQ_OFFSYNC)) {
  474. val |= SEQ_OFFSYNC;
  475. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, val,
  476. TWL4030_PM_MASTER_CFG_P123_TRANSITION);
  477. if (err) {
  478. pr_err("TWL4030 Unable to setup SEQ_OFFSYNC\n");
  479. goto relock;
  480. }
  481. }
  482. pm_power_off = twl4030_power_off;
  483. }
  484. relock:
  485. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
  486. TWL4030_PM_MASTER_PROTECT_KEY);
  487. if (err)
  488. pr_err("TWL4030 Unable to relock registers\n");
  489. return;
  490. unlock:
  491. if (err)
  492. pr_err("TWL4030 Unable to unlock registers\n");
  493. return;
  494. load:
  495. if (err)
  496. pr_err("TWL4030 failed to load scripts\n");
  497. return;
  498. resource:
  499. if (err)
  500. pr_err("TWL4030 failed to configure resource\n");
  501. return;
  502. }