hdmi_drv.c 26 KB

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  1. /*
  2. * Samsung HDMI interface driver
  3. *
  4. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  5. *
  6. * Tomasz Stanislawski, <t.stanislaws@samsung.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published
  10. * by the Free Software Foundiation. either version 2 of the License,
  11. * or (at your option) any later version
  12. */
  13. #define pr_fmt(fmt) "s5p-tv (hdmi_drv): " fmt
  14. #ifdef CONFIG_VIDEO_SAMSUNG_S5P_HDMI_DEBUG
  15. #define DEBUG
  16. #endif
  17. #include <linux/kernel.h>
  18. #include <linux/slab.h>
  19. #include <linux/io.h>
  20. #include <linux/i2c.h>
  21. #include <linux/platform_device.h>
  22. #include <media/v4l2-subdev.h>
  23. #include <linux/module.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/irq.h>
  26. #include <linux/delay.h>
  27. #include <linux/bug.h>
  28. #include <linux/pm_runtime.h>
  29. #include <linux/clk.h>
  30. #include <linux/regulator/consumer.h>
  31. #include <media/s5p_hdmi.h>
  32. #include <media/v4l2-common.h>
  33. #include <media/v4l2-dev.h>
  34. #include <media/v4l2-device.h>
  35. #include "regs-hdmi.h"
  36. MODULE_AUTHOR("Tomasz Stanislawski, <t.stanislaws@samsung.com>");
  37. MODULE_DESCRIPTION("Samsung HDMI");
  38. MODULE_LICENSE("GPL");
  39. /* default preset configured on probe */
  40. #define HDMI_DEFAULT_PRESET V4L2_DV_480P59_94
  41. struct hdmi_pulse {
  42. u32 beg;
  43. u32 end;
  44. };
  45. struct hdmi_timings {
  46. struct hdmi_pulse hact;
  47. u32 hsyn_pol; /* 0 - high, 1 - low */
  48. struct hdmi_pulse hsyn;
  49. u32 interlaced;
  50. struct hdmi_pulse vact[2];
  51. u32 vsyn_pol; /* 0 - high, 1 - low */
  52. u32 vsyn_off;
  53. struct hdmi_pulse vsyn[2];
  54. };
  55. struct hdmi_resources {
  56. struct clk *hdmi;
  57. struct clk *sclk_hdmi;
  58. struct clk *sclk_pixel;
  59. struct clk *sclk_hdmiphy;
  60. struct clk *hdmiphy;
  61. struct regulator_bulk_data *regul_bulk;
  62. int regul_count;
  63. };
  64. struct hdmi_device {
  65. /** base address of HDMI registers */
  66. void __iomem *regs;
  67. /** HDMI interrupt */
  68. unsigned int irq;
  69. /** pointer to device parent */
  70. struct device *dev;
  71. /** subdev generated by HDMI device */
  72. struct v4l2_subdev sd;
  73. /** V4L2 device structure */
  74. struct v4l2_device v4l2_dev;
  75. /** subdev of HDMIPHY interface */
  76. struct v4l2_subdev *phy_sd;
  77. /** subdev of MHL interface */
  78. struct v4l2_subdev *mhl_sd;
  79. /** configuration of current graphic mode */
  80. const struct hdmi_timings *cur_conf;
  81. /** flag indicating that timings are dirty */
  82. int cur_conf_dirty;
  83. /** current preset */
  84. u32 cur_preset;
  85. /** other resources */
  86. struct hdmi_resources res;
  87. };
  88. static struct platform_device_id hdmi_driver_types[] = {
  89. {
  90. .name = "s5pv210-hdmi",
  91. }, {
  92. .name = "exynos4-hdmi",
  93. }, {
  94. /* end node */
  95. }
  96. };
  97. static const struct v4l2_subdev_ops hdmi_sd_ops;
  98. static struct hdmi_device *sd_to_hdmi_dev(struct v4l2_subdev *sd)
  99. {
  100. return container_of(sd, struct hdmi_device, sd);
  101. }
  102. static inline
  103. void hdmi_write(struct hdmi_device *hdev, u32 reg_id, u32 value)
  104. {
  105. writel(value, hdev->regs + reg_id);
  106. }
  107. static inline
  108. void hdmi_write_mask(struct hdmi_device *hdev, u32 reg_id, u32 value, u32 mask)
  109. {
  110. u32 old = readl(hdev->regs + reg_id);
  111. value = (value & mask) | (old & ~mask);
  112. writel(value, hdev->regs + reg_id);
  113. }
  114. static inline
  115. void hdmi_writeb(struct hdmi_device *hdev, u32 reg_id, u8 value)
  116. {
  117. writeb(value, hdev->regs + reg_id);
  118. }
  119. static inline
  120. void hdmi_writebn(struct hdmi_device *hdev, u32 reg_id, int n, u32 value)
  121. {
  122. switch (n) {
  123. default:
  124. writeb(value >> 24, hdev->regs + reg_id + 12);
  125. case 3:
  126. writeb(value >> 16, hdev->regs + reg_id + 8);
  127. case 2:
  128. writeb(value >> 8, hdev->regs + reg_id + 4);
  129. case 1:
  130. writeb(value >> 0, hdev->regs + reg_id + 0);
  131. }
  132. }
  133. static inline u32 hdmi_read(struct hdmi_device *hdev, u32 reg_id)
  134. {
  135. return readl(hdev->regs + reg_id);
  136. }
  137. static irqreturn_t hdmi_irq_handler(int irq, void *dev_data)
  138. {
  139. struct hdmi_device *hdev = dev_data;
  140. u32 intc_flag;
  141. (void)irq;
  142. intc_flag = hdmi_read(hdev, HDMI_INTC_FLAG);
  143. /* clearing flags for HPD plug/unplug */
  144. if (intc_flag & HDMI_INTC_FLAG_HPD_UNPLUG) {
  145. pr_info("unplugged\n");
  146. hdmi_write_mask(hdev, HDMI_INTC_FLAG, ~0,
  147. HDMI_INTC_FLAG_HPD_UNPLUG);
  148. }
  149. if (intc_flag & HDMI_INTC_FLAG_HPD_PLUG) {
  150. pr_info("plugged\n");
  151. hdmi_write_mask(hdev, HDMI_INTC_FLAG, ~0,
  152. HDMI_INTC_FLAG_HPD_PLUG);
  153. }
  154. return IRQ_HANDLED;
  155. }
  156. static void hdmi_reg_init(struct hdmi_device *hdev)
  157. {
  158. /* enable HPD interrupts */
  159. hdmi_write_mask(hdev, HDMI_INTC_CON, ~0, HDMI_INTC_EN_GLOBAL |
  160. HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
  161. /* choose DVI mode */
  162. hdmi_write_mask(hdev, HDMI_MODE_SEL,
  163. HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
  164. hdmi_write_mask(hdev, HDMI_CON_2, ~0,
  165. HDMI_DVI_PERAMBLE_EN | HDMI_DVI_BAND_EN);
  166. /* disable bluescreen */
  167. hdmi_write_mask(hdev, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
  168. /* choose bluescreen (fecal) color */
  169. hdmi_writeb(hdev, HDMI_BLUE_SCREEN_0, 0x12);
  170. hdmi_writeb(hdev, HDMI_BLUE_SCREEN_1, 0x34);
  171. hdmi_writeb(hdev, HDMI_BLUE_SCREEN_2, 0x56);
  172. }
  173. static void hdmi_timing_apply(struct hdmi_device *hdev,
  174. const struct hdmi_timings *t)
  175. {
  176. /* setting core registers */
  177. hdmi_writebn(hdev, HDMI_H_BLANK_0, 2, t->hact.beg);
  178. hdmi_writebn(hdev, HDMI_H_SYNC_GEN_0, 3,
  179. (t->hsyn_pol << 20) | (t->hsyn.end << 10) | t->hsyn.beg);
  180. hdmi_writeb(hdev, HDMI_VSYNC_POL, t->vsyn_pol);
  181. hdmi_writebn(hdev, HDMI_V_BLANK_0, 3,
  182. (t->vact[0].beg << 11) | t->vact[0].end);
  183. hdmi_writebn(hdev, HDMI_V_SYNC_GEN_1_0, 3,
  184. (t->vsyn[0].beg << 12) | t->vsyn[0].end);
  185. if (t->interlaced) {
  186. u32 vsyn_trans = t->hsyn.beg + t->vsyn_off;
  187. hdmi_writeb(hdev, HDMI_INT_PRO_MODE, 1);
  188. hdmi_writebn(hdev, HDMI_H_V_LINE_0, 3,
  189. (t->hact.end << 12) | t->vact[1].end);
  190. hdmi_writebn(hdev, HDMI_V_BLANK_F_0, 3,
  191. (t->vact[1].end << 11) | t->vact[1].beg);
  192. hdmi_writebn(hdev, HDMI_V_SYNC_GEN_2_0, 3,
  193. (t->vsyn[1].beg << 12) | t->vsyn[1].end);
  194. hdmi_writebn(hdev, HDMI_V_SYNC_GEN_3_0, 3,
  195. (vsyn_trans << 12) | vsyn_trans);
  196. } else {
  197. hdmi_writeb(hdev, HDMI_INT_PRO_MODE, 0);
  198. hdmi_writebn(hdev, HDMI_H_V_LINE_0, 3,
  199. (t->hact.end << 12) | t->vact[0].end);
  200. }
  201. /* Timing generator registers */
  202. hdmi_writebn(hdev, HDMI_TG_H_FSZ_L, 2, t->hact.end);
  203. hdmi_writebn(hdev, HDMI_TG_HACT_ST_L, 2, t->hact.beg);
  204. hdmi_writebn(hdev, HDMI_TG_HACT_SZ_L, 2, t->hact.end - t->hact.beg);
  205. hdmi_writebn(hdev, HDMI_TG_VSYNC_L, 2, t->vsyn[0].beg);
  206. hdmi_writebn(hdev, HDMI_TG_VACT_ST_L, 2, t->vact[0].beg);
  207. hdmi_writebn(hdev, HDMI_TG_VACT_SZ_L, 2,
  208. t->vact[0].end - t->vact[0].beg);
  209. hdmi_writebn(hdev, HDMI_TG_VSYNC_TOP_HDMI_L, 2, t->vsyn[0].beg);
  210. hdmi_writebn(hdev, HDMI_TG_FIELD_TOP_HDMI_L, 2, t->vsyn[0].beg);
  211. if (t->interlaced) {
  212. hdmi_write_mask(hdev, HDMI_TG_CMD, ~0, HDMI_TG_FIELD_EN);
  213. hdmi_writebn(hdev, HDMI_TG_V_FSZ_L, 2, t->vact[1].end);
  214. hdmi_writebn(hdev, HDMI_TG_VSYNC2_L, 2, t->vsyn[1].beg);
  215. hdmi_writebn(hdev, HDMI_TG_FIELD_CHG_L, 2, t->vact[0].end);
  216. hdmi_writebn(hdev, HDMI_TG_VACT_ST2_L, 2, t->vact[1].beg);
  217. hdmi_writebn(hdev, HDMI_TG_VSYNC_BOT_HDMI_L, 2, t->vsyn[1].beg);
  218. hdmi_writebn(hdev, HDMI_TG_FIELD_BOT_HDMI_L, 2, t->vsyn[1].beg);
  219. } else {
  220. hdmi_write_mask(hdev, HDMI_TG_CMD, 0, HDMI_TG_FIELD_EN);
  221. hdmi_writebn(hdev, HDMI_TG_V_FSZ_L, 2, t->vact[0].end);
  222. }
  223. }
  224. static int hdmi_conf_apply(struct hdmi_device *hdmi_dev)
  225. {
  226. struct device *dev = hdmi_dev->dev;
  227. const struct hdmi_timings *conf = hdmi_dev->cur_conf;
  228. struct v4l2_dv_preset preset;
  229. int ret;
  230. dev_dbg(dev, "%s\n", __func__);
  231. /* skip if conf is already synchronized with HW */
  232. if (!hdmi_dev->cur_conf_dirty)
  233. return 0;
  234. /* reset hdmiphy */
  235. hdmi_write_mask(hdmi_dev, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT);
  236. mdelay(10);
  237. hdmi_write_mask(hdmi_dev, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT);
  238. mdelay(10);
  239. /* configure presets */
  240. preset.preset = hdmi_dev->cur_preset;
  241. ret = v4l2_subdev_call(hdmi_dev->phy_sd, video, s_dv_preset, &preset);
  242. if (ret) {
  243. dev_err(dev, "failed to set preset (%u)\n", preset.preset);
  244. return ret;
  245. }
  246. /* resetting HDMI core */
  247. hdmi_write_mask(hdmi_dev, HDMI_CORE_RSTOUT, 0, HDMI_CORE_SW_RSTOUT);
  248. mdelay(10);
  249. hdmi_write_mask(hdmi_dev, HDMI_CORE_RSTOUT, ~0, HDMI_CORE_SW_RSTOUT);
  250. mdelay(10);
  251. hdmi_reg_init(hdmi_dev);
  252. /* setting core registers */
  253. hdmi_timing_apply(hdmi_dev, conf);
  254. hdmi_dev->cur_conf_dirty = 0;
  255. return 0;
  256. }
  257. static void hdmi_dumpregs(struct hdmi_device *hdev, char *prefix)
  258. {
  259. #define DUMPREG(reg_id) \
  260. dev_dbg(hdev->dev, "%s:" #reg_id " = %08x\n", prefix, \
  261. readl(hdev->regs + reg_id))
  262. dev_dbg(hdev->dev, "%s: ---- CONTROL REGISTERS ----\n", prefix);
  263. DUMPREG(HDMI_INTC_FLAG);
  264. DUMPREG(HDMI_INTC_CON);
  265. DUMPREG(HDMI_HPD_STATUS);
  266. DUMPREG(HDMI_PHY_RSTOUT);
  267. DUMPREG(HDMI_PHY_VPLL);
  268. DUMPREG(HDMI_PHY_CMU);
  269. DUMPREG(HDMI_CORE_RSTOUT);
  270. dev_dbg(hdev->dev, "%s: ---- CORE REGISTERS ----\n", prefix);
  271. DUMPREG(HDMI_CON_0);
  272. DUMPREG(HDMI_CON_1);
  273. DUMPREG(HDMI_CON_2);
  274. DUMPREG(HDMI_SYS_STATUS);
  275. DUMPREG(HDMI_PHY_STATUS);
  276. DUMPREG(HDMI_STATUS_EN);
  277. DUMPREG(HDMI_HPD);
  278. DUMPREG(HDMI_MODE_SEL);
  279. DUMPREG(HDMI_HPD_GEN);
  280. DUMPREG(HDMI_DC_CONTROL);
  281. DUMPREG(HDMI_VIDEO_PATTERN_GEN);
  282. dev_dbg(hdev->dev, "%s: ---- CORE SYNC REGISTERS ----\n", prefix);
  283. DUMPREG(HDMI_H_BLANK_0);
  284. DUMPREG(HDMI_H_BLANK_1);
  285. DUMPREG(HDMI_V_BLANK_0);
  286. DUMPREG(HDMI_V_BLANK_1);
  287. DUMPREG(HDMI_V_BLANK_2);
  288. DUMPREG(HDMI_H_V_LINE_0);
  289. DUMPREG(HDMI_H_V_LINE_1);
  290. DUMPREG(HDMI_H_V_LINE_2);
  291. DUMPREG(HDMI_VSYNC_POL);
  292. DUMPREG(HDMI_INT_PRO_MODE);
  293. DUMPREG(HDMI_V_BLANK_F_0);
  294. DUMPREG(HDMI_V_BLANK_F_1);
  295. DUMPREG(HDMI_V_BLANK_F_2);
  296. DUMPREG(HDMI_H_SYNC_GEN_0);
  297. DUMPREG(HDMI_H_SYNC_GEN_1);
  298. DUMPREG(HDMI_H_SYNC_GEN_2);
  299. DUMPREG(HDMI_V_SYNC_GEN_1_0);
  300. DUMPREG(HDMI_V_SYNC_GEN_1_1);
  301. DUMPREG(HDMI_V_SYNC_GEN_1_2);
  302. DUMPREG(HDMI_V_SYNC_GEN_2_0);
  303. DUMPREG(HDMI_V_SYNC_GEN_2_1);
  304. DUMPREG(HDMI_V_SYNC_GEN_2_2);
  305. DUMPREG(HDMI_V_SYNC_GEN_3_0);
  306. DUMPREG(HDMI_V_SYNC_GEN_3_1);
  307. DUMPREG(HDMI_V_SYNC_GEN_3_2);
  308. dev_dbg(hdev->dev, "%s: ---- TG REGISTERS ----\n", prefix);
  309. DUMPREG(HDMI_TG_CMD);
  310. DUMPREG(HDMI_TG_H_FSZ_L);
  311. DUMPREG(HDMI_TG_H_FSZ_H);
  312. DUMPREG(HDMI_TG_HACT_ST_L);
  313. DUMPREG(HDMI_TG_HACT_ST_H);
  314. DUMPREG(HDMI_TG_HACT_SZ_L);
  315. DUMPREG(HDMI_TG_HACT_SZ_H);
  316. DUMPREG(HDMI_TG_V_FSZ_L);
  317. DUMPREG(HDMI_TG_V_FSZ_H);
  318. DUMPREG(HDMI_TG_VSYNC_L);
  319. DUMPREG(HDMI_TG_VSYNC_H);
  320. DUMPREG(HDMI_TG_VSYNC2_L);
  321. DUMPREG(HDMI_TG_VSYNC2_H);
  322. DUMPREG(HDMI_TG_VACT_ST_L);
  323. DUMPREG(HDMI_TG_VACT_ST_H);
  324. DUMPREG(HDMI_TG_VACT_SZ_L);
  325. DUMPREG(HDMI_TG_VACT_SZ_H);
  326. DUMPREG(HDMI_TG_FIELD_CHG_L);
  327. DUMPREG(HDMI_TG_FIELD_CHG_H);
  328. DUMPREG(HDMI_TG_VACT_ST2_L);
  329. DUMPREG(HDMI_TG_VACT_ST2_H);
  330. DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
  331. DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
  332. DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
  333. DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
  334. DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
  335. DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
  336. DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
  337. DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
  338. #undef DUMPREG
  339. }
  340. static const struct hdmi_timings hdmi_timings_480p = {
  341. .hact = { .beg = 138, .end = 858 },
  342. .hsyn_pol = 1,
  343. .hsyn = { .beg = 16, .end = 16 + 62 },
  344. .interlaced = 0,
  345. .vact[0] = { .beg = 42 + 3, .end = 522 + 3 },
  346. .vsyn_pol = 1,
  347. .vsyn[0] = { .beg = 6 + 3, .end = 12 + 3},
  348. };
  349. static const struct hdmi_timings hdmi_timings_576p50 = {
  350. .hact = { .beg = 144, .end = 864 },
  351. .hsyn_pol = 1,
  352. .hsyn = { .beg = 12, .end = 12 + 64 },
  353. .interlaced = 0,
  354. .vact[0] = { .beg = 44 + 5, .end = 620 + 5 },
  355. .vsyn_pol = 1,
  356. .vsyn[0] = { .beg = 0 + 5, .end = 5 + 5},
  357. };
  358. static const struct hdmi_timings hdmi_timings_720p60 = {
  359. .hact = { .beg = 370, .end = 1650 },
  360. .hsyn_pol = 0,
  361. .hsyn = { .beg = 110, .end = 110 + 40 },
  362. .interlaced = 0,
  363. .vact[0] = { .beg = 25 + 5, .end = 745 + 5 },
  364. .vsyn_pol = 0,
  365. .vsyn[0] = { .beg = 0 + 5, .end = 5 + 5},
  366. };
  367. static const struct hdmi_timings hdmi_timings_720p50 = {
  368. .hact = { .beg = 700, .end = 1980 },
  369. .hsyn_pol = 0,
  370. .hsyn = { .beg = 440, .end = 440 + 40 },
  371. .interlaced = 0,
  372. .vact[0] = { .beg = 25 + 5, .end = 745 + 5 },
  373. .vsyn_pol = 0,
  374. .vsyn[0] = { .beg = 0 + 5, .end = 5 + 5},
  375. };
  376. static const struct hdmi_timings hdmi_timings_1080p24 = {
  377. .hact = { .beg = 830, .end = 2750 },
  378. .hsyn_pol = 0,
  379. .hsyn = { .beg = 638, .end = 638 + 44 },
  380. .interlaced = 0,
  381. .vact[0] = { .beg = 41 + 4, .end = 1121 + 4 },
  382. .vsyn_pol = 0,
  383. .vsyn[0] = { .beg = 0 + 4, .end = 5 + 4},
  384. };
  385. static const struct hdmi_timings hdmi_timings_1080p60 = {
  386. .hact = { .beg = 280, .end = 2200 },
  387. .hsyn_pol = 0,
  388. .hsyn = { .beg = 88, .end = 88 + 44 },
  389. .interlaced = 0,
  390. .vact[0] = { .beg = 41 + 4, .end = 1121 + 4 },
  391. .vsyn_pol = 0,
  392. .vsyn[0] = { .beg = 0 + 4, .end = 5 + 4},
  393. };
  394. static const struct hdmi_timings hdmi_timings_1080i60 = {
  395. .hact = { .beg = 280, .end = 2200 },
  396. .hsyn_pol = 0,
  397. .hsyn = { .beg = 88, .end = 88 + 44 },
  398. .interlaced = 1,
  399. .vact[0] = { .beg = 20 + 2, .end = 560 + 2 },
  400. .vact[1] = { .beg = 583 + 2, .end = 1123 + 2 },
  401. .vsyn_pol = 0,
  402. .vsyn_off = 1100,
  403. .vsyn[0] = { .beg = 0 + 2, .end = 5 + 2},
  404. .vsyn[1] = { .beg = 562 + 2, .end = 567 + 2},
  405. };
  406. static const struct hdmi_timings hdmi_timings_1080i50 = {
  407. .hact = { .beg = 720, .end = 2640 },
  408. .hsyn_pol = 0,
  409. .hsyn = { .beg = 528, .end = 528 + 44 },
  410. .interlaced = 1,
  411. .vact[0] = { .beg = 20 + 2, .end = 560 + 2 },
  412. .vact[1] = { .beg = 583 + 2, .end = 1123 + 2 },
  413. .vsyn_pol = 0,
  414. .vsyn_off = 1320,
  415. .vsyn[0] = { .beg = 0 + 2, .end = 5 + 2},
  416. .vsyn[1] = { .beg = 562 + 2, .end = 567 + 2},
  417. };
  418. static const struct hdmi_timings hdmi_timings_1080p50 = {
  419. .hact = { .beg = 720, .end = 2640 },
  420. .hsyn_pol = 0,
  421. .hsyn = { .beg = 528, .end = 528 + 44 },
  422. .interlaced = 0,
  423. .vact[0] = { .beg = 41 + 4, .end = 1121 + 4 },
  424. .vsyn_pol = 0,
  425. .vsyn[0] = { .beg = 0 + 4, .end = 5 + 4},
  426. };
  427. static const struct {
  428. u32 preset;
  429. const struct hdmi_timings *timings;
  430. } hdmi_timings[] = {
  431. { V4L2_DV_480P59_94, &hdmi_timings_480p },
  432. { V4L2_DV_576P50, &hdmi_timings_576p50 },
  433. { V4L2_DV_720P50, &hdmi_timings_720p50 },
  434. { V4L2_DV_720P59_94, &hdmi_timings_720p60 },
  435. { V4L2_DV_720P60, &hdmi_timings_720p60 },
  436. { V4L2_DV_1080P24, &hdmi_timings_1080p24 },
  437. { V4L2_DV_1080P30, &hdmi_timings_1080p60 },
  438. { V4L2_DV_1080P50, &hdmi_timings_1080p50 },
  439. { V4L2_DV_1080I50, &hdmi_timings_1080i50 },
  440. { V4L2_DV_1080I60, &hdmi_timings_1080i60 },
  441. { V4L2_DV_1080P60, &hdmi_timings_1080p60 },
  442. };
  443. static const struct hdmi_timings *hdmi_preset2timings(u32 preset)
  444. {
  445. int i;
  446. for (i = 0; i < ARRAY_SIZE(hdmi_timings); ++i)
  447. if (hdmi_timings[i].preset == preset)
  448. return hdmi_timings[i].timings;
  449. return NULL;
  450. }
  451. static int hdmi_streamon(struct hdmi_device *hdev)
  452. {
  453. struct device *dev = hdev->dev;
  454. struct hdmi_resources *res = &hdev->res;
  455. int ret, tries;
  456. dev_dbg(dev, "%s\n", __func__);
  457. ret = hdmi_conf_apply(hdev);
  458. if (ret)
  459. return ret;
  460. ret = v4l2_subdev_call(hdev->phy_sd, video, s_stream, 1);
  461. if (ret)
  462. return ret;
  463. /* waiting for HDMIPHY's PLL to get to steady state */
  464. for (tries = 100; tries; --tries) {
  465. u32 val = hdmi_read(hdev, HDMI_PHY_STATUS);
  466. if (val & HDMI_PHY_STATUS_READY)
  467. break;
  468. mdelay(1);
  469. }
  470. /* steady state not achieved */
  471. if (tries == 0) {
  472. dev_err(dev, "hdmiphy's pll could not reach steady state.\n");
  473. v4l2_subdev_call(hdev->phy_sd, video, s_stream, 0);
  474. hdmi_dumpregs(hdev, "hdmiphy - s_stream");
  475. return -EIO;
  476. }
  477. /* starting MHL */
  478. ret = v4l2_subdev_call(hdev->mhl_sd, video, s_stream, 1);
  479. if (hdev->mhl_sd && ret) {
  480. v4l2_subdev_call(hdev->phy_sd, video, s_stream, 0);
  481. hdmi_dumpregs(hdev, "mhl - s_stream");
  482. return -EIO;
  483. }
  484. /* hdmiphy clock is used for HDMI in streaming mode */
  485. clk_disable(res->sclk_hdmi);
  486. clk_set_parent(res->sclk_hdmi, res->sclk_hdmiphy);
  487. clk_enable(res->sclk_hdmi);
  488. /* enable HDMI and timing generator */
  489. hdmi_write_mask(hdev, HDMI_CON_0, ~0, HDMI_EN);
  490. hdmi_write_mask(hdev, HDMI_TG_CMD, ~0, HDMI_TG_EN);
  491. hdmi_dumpregs(hdev, "streamon");
  492. return 0;
  493. }
  494. static int hdmi_streamoff(struct hdmi_device *hdev)
  495. {
  496. struct device *dev = hdev->dev;
  497. struct hdmi_resources *res = &hdev->res;
  498. dev_dbg(dev, "%s\n", __func__);
  499. hdmi_write_mask(hdev, HDMI_CON_0, 0, HDMI_EN);
  500. hdmi_write_mask(hdev, HDMI_TG_CMD, 0, HDMI_TG_EN);
  501. /* pixel(vpll) clock is used for HDMI in config mode */
  502. clk_disable(res->sclk_hdmi);
  503. clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
  504. clk_enable(res->sclk_hdmi);
  505. v4l2_subdev_call(hdev->mhl_sd, video, s_stream, 0);
  506. v4l2_subdev_call(hdev->phy_sd, video, s_stream, 0);
  507. hdmi_dumpregs(hdev, "streamoff");
  508. return 0;
  509. }
  510. static int hdmi_s_stream(struct v4l2_subdev *sd, int enable)
  511. {
  512. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  513. struct device *dev = hdev->dev;
  514. dev_dbg(dev, "%s(%d)\n", __func__, enable);
  515. if (enable)
  516. return hdmi_streamon(hdev);
  517. return hdmi_streamoff(hdev);
  518. }
  519. static void hdmi_resource_poweron(struct hdmi_resources *res)
  520. {
  521. /* turn HDMI power on */
  522. regulator_bulk_enable(res->regul_count, res->regul_bulk);
  523. /* power-on hdmi physical interface */
  524. clk_enable(res->hdmiphy);
  525. /* use VPP as parent clock; HDMIPHY is not working yet */
  526. clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
  527. /* turn clocks on */
  528. clk_enable(res->sclk_hdmi);
  529. }
  530. static void hdmi_resource_poweroff(struct hdmi_resources *res)
  531. {
  532. /* turn clocks off */
  533. clk_disable(res->sclk_hdmi);
  534. /* power-off hdmiphy */
  535. clk_disable(res->hdmiphy);
  536. /* turn HDMI power off */
  537. regulator_bulk_disable(res->regul_count, res->regul_bulk);
  538. }
  539. static int hdmi_s_power(struct v4l2_subdev *sd, int on)
  540. {
  541. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  542. int ret;
  543. if (on)
  544. ret = pm_runtime_get_sync(hdev->dev);
  545. else
  546. ret = pm_runtime_put_sync(hdev->dev);
  547. /* only values < 0 indicate errors */
  548. return IS_ERR_VALUE(ret) ? ret : 0;
  549. }
  550. static int hdmi_s_dv_preset(struct v4l2_subdev *sd,
  551. struct v4l2_dv_preset *preset)
  552. {
  553. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  554. struct device *dev = hdev->dev;
  555. const struct hdmi_timings *conf;
  556. conf = hdmi_preset2timings(preset->preset);
  557. if (conf == NULL) {
  558. dev_err(dev, "preset (%u) not supported\n", preset->preset);
  559. return -EINVAL;
  560. }
  561. hdev->cur_conf = conf;
  562. hdev->cur_conf_dirty = 1;
  563. hdev->cur_preset = preset->preset;
  564. return 0;
  565. }
  566. static int hdmi_g_dv_preset(struct v4l2_subdev *sd,
  567. struct v4l2_dv_preset *preset)
  568. {
  569. memset(preset, 0, sizeof(*preset));
  570. preset->preset = sd_to_hdmi_dev(sd)->cur_preset;
  571. return 0;
  572. }
  573. static int hdmi_g_mbus_fmt(struct v4l2_subdev *sd,
  574. struct v4l2_mbus_framefmt *fmt)
  575. {
  576. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  577. const struct hdmi_timings *t = hdev->cur_conf;
  578. dev_dbg(hdev->dev, "%s\n", __func__);
  579. if (!hdev->cur_conf)
  580. return -EINVAL;
  581. memset(fmt, 0, sizeof(*fmt));
  582. fmt->width = t->hact.end - t->hact.beg;
  583. fmt->height = t->vact[0].end - t->vact[0].beg;
  584. fmt->code = V4L2_MBUS_FMT_FIXED; /* means RGB888 */
  585. fmt->colorspace = V4L2_COLORSPACE_SRGB;
  586. if (t->interlaced) {
  587. fmt->field = V4L2_FIELD_INTERLACED;
  588. fmt->height *= 2;
  589. } else {
  590. fmt->field = V4L2_FIELD_NONE;
  591. }
  592. return 0;
  593. }
  594. static int hdmi_enum_dv_presets(struct v4l2_subdev *sd,
  595. struct v4l2_dv_enum_preset *preset)
  596. {
  597. if (preset->index >= ARRAY_SIZE(hdmi_timings))
  598. return -EINVAL;
  599. return v4l_fill_dv_preset_info(hdmi_timings[preset->index].preset,
  600. preset);
  601. }
  602. static const struct v4l2_subdev_core_ops hdmi_sd_core_ops = {
  603. .s_power = hdmi_s_power,
  604. };
  605. static const struct v4l2_subdev_video_ops hdmi_sd_video_ops = {
  606. .s_dv_preset = hdmi_s_dv_preset,
  607. .g_dv_preset = hdmi_g_dv_preset,
  608. .enum_dv_presets = hdmi_enum_dv_presets,
  609. .g_mbus_fmt = hdmi_g_mbus_fmt,
  610. .s_stream = hdmi_s_stream,
  611. };
  612. static const struct v4l2_subdev_ops hdmi_sd_ops = {
  613. .core = &hdmi_sd_core_ops,
  614. .video = &hdmi_sd_video_ops,
  615. };
  616. static int hdmi_runtime_suspend(struct device *dev)
  617. {
  618. struct v4l2_subdev *sd = dev_get_drvdata(dev);
  619. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  620. dev_dbg(dev, "%s\n", __func__);
  621. v4l2_subdev_call(hdev->mhl_sd, core, s_power, 0);
  622. hdmi_resource_poweroff(&hdev->res);
  623. /* flag that device context is lost */
  624. hdev->cur_conf_dirty = 1;
  625. return 0;
  626. }
  627. static int hdmi_runtime_resume(struct device *dev)
  628. {
  629. struct v4l2_subdev *sd = dev_get_drvdata(dev);
  630. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  631. int ret = 0;
  632. dev_dbg(dev, "%s\n", __func__);
  633. hdmi_resource_poweron(&hdev->res);
  634. /* starting MHL */
  635. ret = v4l2_subdev_call(hdev->mhl_sd, core, s_power, 1);
  636. if (hdev->mhl_sd && ret)
  637. goto fail;
  638. dev_dbg(dev, "poweron succeed\n");
  639. return 0;
  640. fail:
  641. hdmi_resource_poweroff(&hdev->res);
  642. dev_err(dev, "poweron failed\n");
  643. return ret;
  644. }
  645. static const struct dev_pm_ops hdmi_pm_ops = {
  646. .runtime_suspend = hdmi_runtime_suspend,
  647. .runtime_resume = hdmi_runtime_resume,
  648. };
  649. static void hdmi_resources_cleanup(struct hdmi_device *hdev)
  650. {
  651. struct hdmi_resources *res = &hdev->res;
  652. dev_dbg(hdev->dev, "HDMI resource cleanup\n");
  653. /* put clocks, power */
  654. if (res->regul_count)
  655. regulator_bulk_free(res->regul_count, res->regul_bulk);
  656. /* kfree is NULL-safe */
  657. kfree(res->regul_bulk);
  658. if (!IS_ERR_OR_NULL(res->hdmiphy))
  659. clk_put(res->hdmiphy);
  660. if (!IS_ERR_OR_NULL(res->sclk_hdmiphy))
  661. clk_put(res->sclk_hdmiphy);
  662. if (!IS_ERR_OR_NULL(res->sclk_pixel))
  663. clk_put(res->sclk_pixel);
  664. if (!IS_ERR_OR_NULL(res->sclk_hdmi))
  665. clk_put(res->sclk_hdmi);
  666. if (!IS_ERR_OR_NULL(res->hdmi))
  667. clk_put(res->hdmi);
  668. memset(res, 0, sizeof(*res));
  669. }
  670. static int hdmi_resources_init(struct hdmi_device *hdev)
  671. {
  672. struct device *dev = hdev->dev;
  673. struct hdmi_resources *res = &hdev->res;
  674. static char *supply[] = {
  675. "hdmi-en",
  676. "vdd",
  677. "vdd_osc",
  678. "vdd_pll",
  679. };
  680. int i, ret;
  681. dev_dbg(dev, "HDMI resource init\n");
  682. memset(res, 0, sizeof(*res));
  683. /* get clocks, power */
  684. res->hdmi = clk_get(dev, "hdmi");
  685. if (IS_ERR(res->hdmi)) {
  686. dev_err(dev, "failed to get clock 'hdmi'\n");
  687. goto fail;
  688. }
  689. res->sclk_hdmi = clk_get(dev, "sclk_hdmi");
  690. if (IS_ERR(res->sclk_hdmi)) {
  691. dev_err(dev, "failed to get clock 'sclk_hdmi'\n");
  692. goto fail;
  693. }
  694. res->sclk_pixel = clk_get(dev, "sclk_pixel");
  695. if (IS_ERR(res->sclk_pixel)) {
  696. dev_err(dev, "failed to get clock 'sclk_pixel'\n");
  697. goto fail;
  698. }
  699. res->sclk_hdmiphy = clk_get(dev, "sclk_hdmiphy");
  700. if (IS_ERR(res->sclk_hdmiphy)) {
  701. dev_err(dev, "failed to get clock 'sclk_hdmiphy'\n");
  702. goto fail;
  703. }
  704. res->hdmiphy = clk_get(dev, "hdmiphy");
  705. if (IS_ERR(res->hdmiphy)) {
  706. dev_err(dev, "failed to get clock 'hdmiphy'\n");
  707. goto fail;
  708. }
  709. res->regul_bulk = kcalloc(ARRAY_SIZE(supply),
  710. sizeof(res->regul_bulk[0]), GFP_KERNEL);
  711. if (!res->regul_bulk) {
  712. dev_err(dev, "failed to get memory for regulators\n");
  713. goto fail;
  714. }
  715. for (i = 0; i < ARRAY_SIZE(supply); ++i) {
  716. res->regul_bulk[i].supply = supply[i];
  717. res->regul_bulk[i].consumer = NULL;
  718. }
  719. ret = regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
  720. if (ret) {
  721. dev_err(dev, "failed to get regulators\n");
  722. goto fail;
  723. }
  724. res->regul_count = ARRAY_SIZE(supply);
  725. return 0;
  726. fail:
  727. dev_err(dev, "HDMI resource init - failed\n");
  728. hdmi_resources_cleanup(hdev);
  729. return -ENODEV;
  730. }
  731. static int hdmi_probe(struct platform_device *pdev)
  732. {
  733. struct device *dev = &pdev->dev;
  734. struct resource *res;
  735. struct i2c_adapter *adapter;
  736. struct v4l2_subdev *sd;
  737. struct hdmi_device *hdmi_dev = NULL;
  738. struct s5p_hdmi_platform_data *pdata = dev->platform_data;
  739. int ret;
  740. dev_dbg(dev, "probe start\n");
  741. if (!pdata) {
  742. dev_err(dev, "platform data is missing\n");
  743. ret = -ENODEV;
  744. goto fail;
  745. }
  746. hdmi_dev = devm_kzalloc(&pdev->dev, sizeof(*hdmi_dev), GFP_KERNEL);
  747. if (!hdmi_dev) {
  748. dev_err(dev, "out of memory\n");
  749. ret = -ENOMEM;
  750. goto fail;
  751. }
  752. hdmi_dev->dev = dev;
  753. ret = hdmi_resources_init(hdmi_dev);
  754. if (ret)
  755. goto fail;
  756. /* mapping HDMI registers */
  757. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  758. if (res == NULL) {
  759. dev_err(dev, "get memory resource failed.\n");
  760. ret = -ENXIO;
  761. goto fail_init;
  762. }
  763. hdmi_dev->regs = devm_ioremap(&pdev->dev, res->start,
  764. resource_size(res));
  765. if (hdmi_dev->regs == NULL) {
  766. dev_err(dev, "register mapping failed.\n");
  767. ret = -ENXIO;
  768. goto fail_init;
  769. }
  770. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  771. if (res == NULL) {
  772. dev_err(dev, "get interrupt resource failed.\n");
  773. ret = -ENXIO;
  774. goto fail_init;
  775. }
  776. ret = devm_request_irq(&pdev->dev, res->start, hdmi_irq_handler, 0,
  777. "hdmi", hdmi_dev);
  778. if (ret) {
  779. dev_err(dev, "request interrupt failed.\n");
  780. goto fail_init;
  781. }
  782. hdmi_dev->irq = res->start;
  783. /* setting v4l2 name to prevent WARN_ON in v4l2_device_register */
  784. strlcpy(hdmi_dev->v4l2_dev.name, dev_name(dev),
  785. sizeof(hdmi_dev->v4l2_dev.name));
  786. /* passing NULL owner prevents driver from erasing drvdata */
  787. ret = v4l2_device_register(NULL, &hdmi_dev->v4l2_dev);
  788. if (ret) {
  789. dev_err(dev, "could not register v4l2 device.\n");
  790. goto fail_init;
  791. }
  792. /* testing if hdmiphy info is present */
  793. if (!pdata->hdmiphy_info) {
  794. dev_err(dev, "hdmiphy info is missing in platform data\n");
  795. ret = -ENXIO;
  796. goto fail_vdev;
  797. }
  798. adapter = i2c_get_adapter(pdata->hdmiphy_bus);
  799. if (adapter == NULL) {
  800. dev_err(dev, "hdmiphy adapter request failed\n");
  801. ret = -ENXIO;
  802. goto fail_vdev;
  803. }
  804. hdmi_dev->phy_sd = v4l2_i2c_new_subdev_board(&hdmi_dev->v4l2_dev,
  805. adapter, pdata->hdmiphy_info, NULL);
  806. /* on failure or not adapter is no longer useful */
  807. i2c_put_adapter(adapter);
  808. if (hdmi_dev->phy_sd == NULL) {
  809. dev_err(dev, "missing subdev for hdmiphy\n");
  810. ret = -ENODEV;
  811. goto fail_vdev;
  812. }
  813. /* initialization of MHL interface if present */
  814. if (pdata->mhl_info) {
  815. adapter = i2c_get_adapter(pdata->mhl_bus);
  816. if (adapter == NULL) {
  817. dev_err(dev, "MHL adapter request failed\n");
  818. ret = -ENXIO;
  819. goto fail_vdev;
  820. }
  821. hdmi_dev->mhl_sd = v4l2_i2c_new_subdev_board(
  822. &hdmi_dev->v4l2_dev, adapter,
  823. pdata->mhl_info, NULL);
  824. /* on failure or not adapter is no longer useful */
  825. i2c_put_adapter(adapter);
  826. if (hdmi_dev->mhl_sd == NULL) {
  827. dev_err(dev, "missing subdev for MHL\n");
  828. ret = -ENODEV;
  829. goto fail_vdev;
  830. }
  831. }
  832. clk_enable(hdmi_dev->res.hdmi);
  833. pm_runtime_enable(dev);
  834. sd = &hdmi_dev->sd;
  835. v4l2_subdev_init(sd, &hdmi_sd_ops);
  836. sd->owner = THIS_MODULE;
  837. strlcpy(sd->name, "s5p-hdmi", sizeof(sd->name));
  838. hdmi_dev->cur_preset = HDMI_DEFAULT_PRESET;
  839. /* FIXME: missing fail preset is not supported */
  840. hdmi_dev->cur_conf = hdmi_preset2timings(hdmi_dev->cur_preset);
  841. hdmi_dev->cur_conf_dirty = 1;
  842. /* storing subdev for call that have only access to struct device */
  843. dev_set_drvdata(dev, sd);
  844. dev_info(dev, "probe successful\n");
  845. return 0;
  846. fail_vdev:
  847. v4l2_device_unregister(&hdmi_dev->v4l2_dev);
  848. fail_init:
  849. hdmi_resources_cleanup(hdmi_dev);
  850. fail:
  851. dev_err(dev, "probe failed\n");
  852. return ret;
  853. }
  854. static int hdmi_remove(struct platform_device *pdev)
  855. {
  856. struct device *dev = &pdev->dev;
  857. struct v4l2_subdev *sd = dev_get_drvdata(dev);
  858. struct hdmi_device *hdmi_dev = sd_to_hdmi_dev(sd);
  859. pm_runtime_disable(dev);
  860. clk_disable(hdmi_dev->res.hdmi);
  861. v4l2_device_unregister(&hdmi_dev->v4l2_dev);
  862. disable_irq(hdmi_dev->irq);
  863. hdmi_resources_cleanup(hdmi_dev);
  864. dev_info(dev, "remove successful\n");
  865. return 0;
  866. }
  867. static struct platform_driver hdmi_driver __refdata = {
  868. .probe = hdmi_probe,
  869. .remove = hdmi_remove,
  870. .id_table = hdmi_driver_types,
  871. .driver = {
  872. .name = "s5p-hdmi",
  873. .owner = THIS_MODULE,
  874. .pm = &hdmi_pm_ops,
  875. }
  876. };
  877. module_platform_driver(hdmi_driver);