cx23885-dvb.c 39 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448
  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/init.h>
  23. #include <linux/device.h>
  24. #include <linux/fs.h>
  25. #include <linux/kthread.h>
  26. #include <linux/file.h>
  27. #include <linux/suspend.h>
  28. #include "cx23885.h"
  29. #include <media/v4l2-common.h>
  30. #include "dvb_ca_en50221.h"
  31. #include "s5h1409.h"
  32. #include "s5h1411.h"
  33. #include "mt2131.h"
  34. #include "tda8290.h"
  35. #include "tda18271.h"
  36. #include "lgdt330x.h"
  37. #include "xc4000.h"
  38. #include "xc5000.h"
  39. #include "max2165.h"
  40. #include "tda10048.h"
  41. #include "tuner-xc2028.h"
  42. #include "tuner-simple.h"
  43. #include "dib7000p.h"
  44. #include "dibx000_common.h"
  45. #include "zl10353.h"
  46. #include "stv0900.h"
  47. #include "stv0900_reg.h"
  48. #include "stv6110.h"
  49. #include "lnbh24.h"
  50. #include "cx24116.h"
  51. #include "cimax2.h"
  52. #include "lgs8gxx.h"
  53. #include "netup-eeprom.h"
  54. #include "netup-init.h"
  55. #include "lgdt3305.h"
  56. #include "atbm8830.h"
  57. #include "ts2020.h"
  58. #include "ds3000.h"
  59. #include "cx23885-f300.h"
  60. #include "altera-ci.h"
  61. #include "stv0367.h"
  62. #include "drxk.h"
  63. #include "mt2063.h"
  64. #include "stv090x.h"
  65. #include "stb6100.h"
  66. #include "stb6100_cfg.h"
  67. #include "tda10071.h"
  68. #include "a8293.h"
  69. static unsigned int debug;
  70. #define dprintk(level, fmt, arg...)\
  71. do { if (debug >= level)\
  72. printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  73. } while (0)
  74. /* ------------------------------------------------------------------ */
  75. static unsigned int alt_tuner;
  76. module_param(alt_tuner, int, 0644);
  77. MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
  78. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  79. /* ------------------------------------------------------------------ */
  80. static int dvb_buf_setup(struct videobuf_queue *q,
  81. unsigned int *count, unsigned int *size)
  82. {
  83. struct cx23885_tsport *port = q->priv_data;
  84. port->ts_packet_size = 188 * 4;
  85. port->ts_packet_count = 32;
  86. *size = port->ts_packet_size * port->ts_packet_count;
  87. *count = 32;
  88. return 0;
  89. }
  90. static int dvb_buf_prepare(struct videobuf_queue *q,
  91. struct videobuf_buffer *vb, enum v4l2_field field)
  92. {
  93. struct cx23885_tsport *port = q->priv_data;
  94. return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
  95. }
  96. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  97. {
  98. struct cx23885_tsport *port = q->priv_data;
  99. cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
  100. }
  101. static void dvb_buf_release(struct videobuf_queue *q,
  102. struct videobuf_buffer *vb)
  103. {
  104. cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
  105. }
  106. static int cx23885_dvb_set_frontend(struct dvb_frontend *fe);
  107. static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
  108. {
  109. struct videobuf_dvb_frontends *f;
  110. struct videobuf_dvb_frontend *fe;
  111. f = &port->frontends;
  112. if (f->gate <= 1) /* undefined or fe0 */
  113. fe = videobuf_dvb_get_frontend(f, 1);
  114. else
  115. fe = videobuf_dvb_get_frontend(f, f->gate);
  116. if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
  117. fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
  118. /*
  119. * FIXME: Improve this path to avoid calling the
  120. * cx23885_dvb_set_frontend() every time it passes here.
  121. */
  122. cx23885_dvb_set_frontend(fe->dvb.frontend);
  123. }
  124. static struct videobuf_queue_ops dvb_qops = {
  125. .buf_setup = dvb_buf_setup,
  126. .buf_prepare = dvb_buf_prepare,
  127. .buf_queue = dvb_buf_queue,
  128. .buf_release = dvb_buf_release,
  129. };
  130. static struct s5h1409_config hauppauge_generic_config = {
  131. .demod_address = 0x32 >> 1,
  132. .output_mode = S5H1409_SERIAL_OUTPUT,
  133. .gpio = S5H1409_GPIO_ON,
  134. .qam_if = 44000,
  135. .inversion = S5H1409_INVERSION_OFF,
  136. .status_mode = S5H1409_DEMODLOCKING,
  137. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  138. };
  139. static struct tda10048_config hauppauge_hvr1200_config = {
  140. .demod_address = 0x10 >> 1,
  141. .output_mode = TDA10048_SERIAL_OUTPUT,
  142. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  143. .inversion = TDA10048_INVERSION_ON,
  144. .dtv6_if_freq_khz = TDA10048_IF_3300,
  145. .dtv7_if_freq_khz = TDA10048_IF_3800,
  146. .dtv8_if_freq_khz = TDA10048_IF_4300,
  147. .clk_freq_khz = TDA10048_CLK_16000,
  148. };
  149. static struct tda10048_config hauppauge_hvr1210_config = {
  150. .demod_address = 0x10 >> 1,
  151. .output_mode = TDA10048_SERIAL_OUTPUT,
  152. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  153. .inversion = TDA10048_INVERSION_ON,
  154. .dtv6_if_freq_khz = TDA10048_IF_3300,
  155. .dtv7_if_freq_khz = TDA10048_IF_3500,
  156. .dtv8_if_freq_khz = TDA10048_IF_4000,
  157. .clk_freq_khz = TDA10048_CLK_16000,
  158. };
  159. static struct s5h1409_config hauppauge_ezqam_config = {
  160. .demod_address = 0x32 >> 1,
  161. .output_mode = S5H1409_SERIAL_OUTPUT,
  162. .gpio = S5H1409_GPIO_OFF,
  163. .qam_if = 4000,
  164. .inversion = S5H1409_INVERSION_ON,
  165. .status_mode = S5H1409_DEMODLOCKING,
  166. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  167. };
  168. static struct s5h1409_config hauppauge_hvr1800lp_config = {
  169. .demod_address = 0x32 >> 1,
  170. .output_mode = S5H1409_SERIAL_OUTPUT,
  171. .gpio = S5H1409_GPIO_OFF,
  172. .qam_if = 44000,
  173. .inversion = S5H1409_INVERSION_OFF,
  174. .status_mode = S5H1409_DEMODLOCKING,
  175. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  176. };
  177. static struct s5h1409_config hauppauge_hvr1500_config = {
  178. .demod_address = 0x32 >> 1,
  179. .output_mode = S5H1409_SERIAL_OUTPUT,
  180. .gpio = S5H1409_GPIO_OFF,
  181. .inversion = S5H1409_INVERSION_OFF,
  182. .status_mode = S5H1409_DEMODLOCKING,
  183. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  184. };
  185. static struct mt2131_config hauppauge_generic_tunerconfig = {
  186. 0x61
  187. };
  188. static struct lgdt330x_config fusionhdtv_5_express = {
  189. .demod_address = 0x0e,
  190. .demod_chip = LGDT3303,
  191. .serial_mpeg = 0x40,
  192. };
  193. static struct s5h1409_config hauppauge_hvr1500q_config = {
  194. .demod_address = 0x32 >> 1,
  195. .output_mode = S5H1409_SERIAL_OUTPUT,
  196. .gpio = S5H1409_GPIO_ON,
  197. .qam_if = 44000,
  198. .inversion = S5H1409_INVERSION_OFF,
  199. .status_mode = S5H1409_DEMODLOCKING,
  200. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  201. };
  202. static struct s5h1409_config dvico_s5h1409_config = {
  203. .demod_address = 0x32 >> 1,
  204. .output_mode = S5H1409_SERIAL_OUTPUT,
  205. .gpio = S5H1409_GPIO_ON,
  206. .qam_if = 44000,
  207. .inversion = S5H1409_INVERSION_OFF,
  208. .status_mode = S5H1409_DEMODLOCKING,
  209. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  210. };
  211. static struct s5h1411_config dvico_s5h1411_config = {
  212. .output_mode = S5H1411_SERIAL_OUTPUT,
  213. .gpio = S5H1411_GPIO_ON,
  214. .qam_if = S5H1411_IF_44000,
  215. .vsb_if = S5H1411_IF_44000,
  216. .inversion = S5H1411_INVERSION_OFF,
  217. .status_mode = S5H1411_DEMODLOCKING,
  218. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  219. };
  220. static struct s5h1411_config hcw_s5h1411_config = {
  221. .output_mode = S5H1411_SERIAL_OUTPUT,
  222. .gpio = S5H1411_GPIO_OFF,
  223. .vsb_if = S5H1411_IF_44000,
  224. .qam_if = S5H1411_IF_4000,
  225. .inversion = S5H1411_INVERSION_ON,
  226. .status_mode = S5H1411_DEMODLOCKING,
  227. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  228. };
  229. static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
  230. .i2c_address = 0x61,
  231. .if_khz = 5380,
  232. };
  233. static struct xc5000_config dvico_xc5000_tunerconfig = {
  234. .i2c_address = 0x64,
  235. .if_khz = 5380,
  236. };
  237. static struct tda829x_config tda829x_no_probe = {
  238. .probe_tuner = TDA829X_DONT_PROBE,
  239. };
  240. static struct tda18271_std_map hauppauge_tda18271_std_map = {
  241. .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
  242. .if_lvl = 6, .rfagc_top = 0x37 },
  243. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
  244. .if_lvl = 6, .rfagc_top = 0x37 },
  245. };
  246. static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
  247. .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
  248. .if_lvl = 1, .rfagc_top = 0x37, },
  249. .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
  250. .if_lvl = 1, .rfagc_top = 0x37, },
  251. .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
  252. .if_lvl = 1, .rfagc_top = 0x37, },
  253. };
  254. static struct tda18271_config hauppauge_tda18271_config = {
  255. .std_map = &hauppauge_tda18271_std_map,
  256. .gate = TDA18271_GATE_ANALOG,
  257. .output_opt = TDA18271_OUTPUT_LT_OFF,
  258. };
  259. static struct tda18271_config hauppauge_hvr1200_tuner_config = {
  260. .std_map = &hauppauge_hvr1200_tda18271_std_map,
  261. .gate = TDA18271_GATE_ANALOG,
  262. .output_opt = TDA18271_OUTPUT_LT_OFF,
  263. };
  264. static struct tda18271_config hauppauge_hvr1210_tuner_config = {
  265. .gate = TDA18271_GATE_DIGITAL,
  266. .output_opt = TDA18271_OUTPUT_LT_OFF,
  267. };
  268. static struct tda18271_std_map hauppauge_hvr127x_std_map = {
  269. .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
  270. .if_lvl = 1, .rfagc_top = 0x58 },
  271. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
  272. .if_lvl = 1, .rfagc_top = 0x58 },
  273. };
  274. static struct tda18271_config hauppauge_hvr127x_config = {
  275. .std_map = &hauppauge_hvr127x_std_map,
  276. .output_opt = TDA18271_OUTPUT_LT_OFF,
  277. };
  278. static struct lgdt3305_config hauppauge_lgdt3305_config = {
  279. .i2c_addr = 0x0e,
  280. .mpeg_mode = LGDT3305_MPEG_SERIAL,
  281. .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
  282. .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
  283. .deny_i2c_rptr = 1,
  284. .spectral_inversion = 1,
  285. .qam_if_khz = 4000,
  286. .vsb_if_khz = 3250,
  287. };
  288. static struct dibx000_agc_config xc3028_agc_config = {
  289. BAND_VHF | BAND_UHF, /* band_caps */
  290. /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
  291. * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
  292. * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
  293. * P_agc_nb_est=2, P_agc_write=0
  294. */
  295. (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
  296. (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
  297. 712, /* inv_gain */
  298. 21, /* time_stabiliz */
  299. 0, /* alpha_level */
  300. 118, /* thlock */
  301. 0, /* wbd_inv */
  302. 2867, /* wbd_ref */
  303. 0, /* wbd_sel */
  304. 2, /* wbd_alpha */
  305. 0, /* agc1_max */
  306. 0, /* agc1_min */
  307. 39718, /* agc2_max */
  308. 9930, /* agc2_min */
  309. 0, /* agc1_pt1 */
  310. 0, /* agc1_pt2 */
  311. 0, /* agc1_pt3 */
  312. 0, /* agc1_slope1 */
  313. 0, /* agc1_slope2 */
  314. 0, /* agc2_pt1 */
  315. 128, /* agc2_pt2 */
  316. 29, /* agc2_slope1 */
  317. 29, /* agc2_slope2 */
  318. 17, /* alpha_mant */
  319. 27, /* alpha_exp */
  320. 23, /* beta_mant */
  321. 51, /* beta_exp */
  322. 1, /* perform_agc_softsplit */
  323. };
  324. /* PLL Configuration for COFDM BW_MHz = 8.000000
  325. * With external clock = 30.000000 */
  326. static struct dibx000_bandwidth_config xc3028_bw_config = {
  327. 60000, /* internal */
  328. 30000, /* sampling */
  329. 1, /* pll_cfg: prediv */
  330. 8, /* pll_cfg: ratio */
  331. 3, /* pll_cfg: range */
  332. 1, /* pll_cfg: reset */
  333. 0, /* pll_cfg: bypass */
  334. 0, /* misc: refdiv */
  335. 0, /* misc: bypclk_div */
  336. 1, /* misc: IO_CLK_en_core */
  337. 1, /* misc: ADClkSrc */
  338. 0, /* misc: modulo */
  339. (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
  340. (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
  341. 20452225, /* timf */
  342. 30000000 /* xtal_hz */
  343. };
  344. static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
  345. .output_mpeg2_in_188_bytes = 1,
  346. .hostbus_diversity = 1,
  347. .tuner_is_baseband = 0,
  348. .update_lna = NULL,
  349. .agc_config_count = 1,
  350. .agc = &xc3028_agc_config,
  351. .bw = &xc3028_bw_config,
  352. .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
  353. .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
  354. .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
  355. .pwm_freq_div = 0,
  356. .agc_control = NULL,
  357. .spur_protect = 0,
  358. .output_mode = OUTMODE_MPEG2_SERIAL,
  359. };
  360. static struct zl10353_config dvico_fusionhdtv_xc3028 = {
  361. .demod_address = 0x0f,
  362. .if2 = 45600,
  363. .no_tuner = 1,
  364. .disable_i2c_gate_ctrl = 1,
  365. };
  366. static struct stv0900_reg stv0900_ts_regs[] = {
  367. { R0900_TSGENERAL, 0x00 },
  368. { R0900_P1_TSSPEED, 0x40 },
  369. { R0900_P2_TSSPEED, 0x40 },
  370. { R0900_P1_TSCFGM, 0xc0 },
  371. { R0900_P2_TSCFGM, 0xc0 },
  372. { R0900_P1_TSCFGH, 0xe0 },
  373. { R0900_P2_TSCFGH, 0xe0 },
  374. { R0900_P1_TSCFGL, 0x20 },
  375. { R0900_P2_TSCFGL, 0x20 },
  376. { 0xffff, 0xff }, /* terminate */
  377. };
  378. static struct stv0900_config netup_stv0900_config = {
  379. .demod_address = 0x68,
  380. .demod_mode = 1, /* dual */
  381. .xtal = 8000000,
  382. .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
  383. .diseqc_mode = 2,/* 2/3 PWM */
  384. .ts_config_regs = stv0900_ts_regs,
  385. .tun1_maddress = 0,/* 0x60 */
  386. .tun2_maddress = 3,/* 0x63 */
  387. .tun1_adc = 1,/* 1 Vpp */
  388. .tun2_adc = 1,/* 1 Vpp */
  389. };
  390. static struct stv6110_config netup_stv6110_tunerconfig_a = {
  391. .i2c_address = 0x60,
  392. .mclk = 16000000,
  393. .clk_div = 1,
  394. .gain = 8, /* +16 dB - maximum gain */
  395. };
  396. static struct stv6110_config netup_stv6110_tunerconfig_b = {
  397. .i2c_address = 0x63,
  398. .mclk = 16000000,
  399. .clk_div = 1,
  400. .gain = 8, /* +16 dB - maximum gain */
  401. };
  402. static struct cx24116_config tbs_cx24116_config = {
  403. .demod_address = 0x55,
  404. };
  405. static struct ds3000_config tevii_ds3000_config = {
  406. .demod_address = 0x68,
  407. };
  408. static struct ts2020_config tevii_ts2020_config = {
  409. .tuner_address = 0x60,
  410. .clk_out_div = 1,
  411. };
  412. static struct cx24116_config dvbworld_cx24116_config = {
  413. .demod_address = 0x05,
  414. };
  415. static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
  416. .prod = LGS8GXX_PROD_LGS8GL5,
  417. .demod_address = 0x19,
  418. .serial_ts = 0,
  419. .ts_clk_pol = 1,
  420. .ts_clk_gated = 1,
  421. .if_clk_freq = 30400, /* 30.4 MHz */
  422. .if_freq = 5380, /* 5.38 MHz */
  423. .if_neg_center = 1,
  424. .ext_adc = 0,
  425. .adc_signed = 0,
  426. .if_neg_edge = 0,
  427. };
  428. static struct xc5000_config mygica_x8506_xc5000_config = {
  429. .i2c_address = 0x61,
  430. .if_khz = 5380,
  431. };
  432. static struct stv090x_config prof_8000_stv090x_config = {
  433. .device = STV0903,
  434. .demod_mode = STV090x_SINGLE,
  435. .clk_mode = STV090x_CLK_EXT,
  436. .xtal = 27000000,
  437. .address = 0x6A,
  438. .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED,
  439. .repeater_level = STV090x_RPTLEVEL_64,
  440. .adc1_range = STV090x_ADC_2Vpp,
  441. .diseqc_envelope_mode = false,
  442. .tuner_get_frequency = stb6100_get_frequency,
  443. .tuner_set_frequency = stb6100_set_frequency,
  444. .tuner_set_bandwidth = stb6100_set_bandwidth,
  445. .tuner_get_bandwidth = stb6100_get_bandwidth,
  446. };
  447. static struct stb6100_config prof_8000_stb6100_config = {
  448. .tuner_address = 0x60,
  449. .refclock = 27000000,
  450. };
  451. static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
  452. {
  453. struct cx23885_tsport *port = fe->dvb->priv;
  454. struct cx23885_dev *dev = port->dev;
  455. if (voltage == SEC_VOLTAGE_18)
  456. cx_write(MC417_RWD, 0x00001e00);
  457. else if (voltage == SEC_VOLTAGE_13)
  458. cx_write(MC417_RWD, 0x00001a00);
  459. else
  460. cx_write(MC417_RWD, 0x00001800);
  461. return 0;
  462. }
  463. static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
  464. {
  465. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  466. struct cx23885_tsport *port = fe->dvb->priv;
  467. struct cx23885_dev *dev = port->dev;
  468. switch (dev->board) {
  469. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  470. switch (p->modulation) {
  471. case VSB_8:
  472. cx23885_gpio_clear(dev, GPIO_5);
  473. break;
  474. case QAM_64:
  475. case QAM_256:
  476. default:
  477. cx23885_gpio_set(dev, GPIO_5);
  478. break;
  479. }
  480. break;
  481. case CX23885_BOARD_MYGICA_X8506:
  482. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  483. /* Select Digital TV */
  484. cx23885_gpio_set(dev, GPIO_0);
  485. break;
  486. }
  487. return 0;
  488. }
  489. static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
  490. .prod = LGS8GXX_PROD_LGS8G75,
  491. .demod_address = 0x19,
  492. .serial_ts = 0,
  493. .ts_clk_pol = 1,
  494. .ts_clk_gated = 1,
  495. .if_clk_freq = 30400, /* 30.4 MHz */
  496. .if_freq = 6500, /* 6.50 MHz */
  497. .if_neg_center = 1,
  498. .ext_adc = 0,
  499. .adc_signed = 1,
  500. .adc_vpp = 2, /* 1.6 Vpp */
  501. .if_neg_edge = 1,
  502. };
  503. static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
  504. .i2c_address = 0x61,
  505. .if_khz = 6500,
  506. };
  507. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
  508. .prod = ATBM8830_PROD_8830,
  509. .demod_address = 0x44,
  510. .serial_ts = 0,
  511. .ts_sampling_edge = 1,
  512. .ts_clk_gated = 0,
  513. .osc_clk_freq = 30400, /* in kHz */
  514. .if_freq = 0, /* zero IF */
  515. .zif_swap_iq = 1,
  516. .agc_min = 0x2E,
  517. .agc_max = 0xFF,
  518. .agc_hold_loop = 0,
  519. };
  520. static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
  521. .i2c_address = 0x60,
  522. .osc_clk = 20
  523. };
  524. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
  525. .prod = ATBM8830_PROD_8830,
  526. .demod_address = 0x44,
  527. .serial_ts = 1,
  528. .ts_sampling_edge = 1,
  529. .ts_clk_gated = 0,
  530. .osc_clk_freq = 30400, /* in kHz */
  531. .if_freq = 0, /* zero IF */
  532. .zif_swap_iq = 1,
  533. .agc_min = 0x2E,
  534. .agc_max = 0xFF,
  535. .agc_hold_loop = 0,
  536. };
  537. static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
  538. .i2c_address = 0x60,
  539. .osc_clk = 20
  540. };
  541. static struct stv0367_config netup_stv0367_config[] = {
  542. {
  543. .demod_address = 0x1c,
  544. .xtal = 27000000,
  545. .if_khz = 4500,
  546. .if_iq_mode = 0,
  547. .ts_mode = 1,
  548. .clk_pol = 0,
  549. }, {
  550. .demod_address = 0x1d,
  551. .xtal = 27000000,
  552. .if_khz = 4500,
  553. .if_iq_mode = 0,
  554. .ts_mode = 1,
  555. .clk_pol = 0,
  556. },
  557. };
  558. static struct xc5000_config netup_xc5000_config[] = {
  559. {
  560. .i2c_address = 0x61,
  561. .if_khz = 4500,
  562. }, {
  563. .i2c_address = 0x64,
  564. .if_khz = 4500,
  565. },
  566. };
  567. static struct drxk_config terratec_drxk_config[] = {
  568. {
  569. .adr = 0x29,
  570. .no_i2c_bridge = 1,
  571. }, {
  572. .adr = 0x2a,
  573. .no_i2c_bridge = 1,
  574. },
  575. };
  576. static struct mt2063_config terratec_mt2063_config[] = {
  577. {
  578. .tuner_address = 0x60,
  579. }, {
  580. .tuner_address = 0x67,
  581. },
  582. };
  583. static const struct tda10071_config hauppauge_tda10071_config = {
  584. .demod_i2c_addr = 0x05,
  585. .tuner_i2c_addr = 0x54,
  586. .i2c_wr_max = 64,
  587. .ts_mode = TDA10071_TS_SERIAL,
  588. .spec_inv = 0,
  589. .xtal = 40444000, /* 40.444 MHz */
  590. .pll_multiplier = 20,
  591. };
  592. static const struct a8293_config hauppauge_a8293_config = {
  593. .i2c_addr = 0x0b,
  594. };
  595. static int netup_altera_fpga_rw(void *device, int flag, int data, int read)
  596. {
  597. struct cx23885_dev *dev = (struct cx23885_dev *)device;
  598. unsigned long timeout = jiffies + msecs_to_jiffies(1);
  599. uint32_t mem = 0;
  600. mem = cx_read(MC417_RWD);
  601. if (read)
  602. cx_set(MC417_OEN, ALT_DATA);
  603. else {
  604. cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
  605. mem &= ~ALT_DATA;
  606. mem |= (data & ALT_DATA);
  607. }
  608. if (flag)
  609. mem |= ALT_AD_RG;
  610. else
  611. mem &= ~ALT_AD_RG;
  612. mem &= ~ALT_CS;
  613. if (read)
  614. mem = (mem & ~ALT_RD) | ALT_WR;
  615. else
  616. mem = (mem & ~ALT_WR) | ALT_RD;
  617. cx_write(MC417_RWD, mem); /* start RW cycle */
  618. for (;;) {
  619. mem = cx_read(MC417_RWD);
  620. if ((mem & ALT_RDY) == 0)
  621. break;
  622. if (time_after(jiffies, timeout))
  623. break;
  624. udelay(1);
  625. }
  626. cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
  627. if (read)
  628. return mem & ALT_DATA;
  629. return 0;
  630. };
  631. static int dvb_register(struct cx23885_tsport *port)
  632. {
  633. struct cx23885_dev *dev = port->dev;
  634. struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
  635. struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
  636. int mfe_shared = 0; /* bus not shared by default */
  637. int ret;
  638. /* Get the first frontend */
  639. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  640. if (!fe0)
  641. return -EINVAL;
  642. /* init struct videobuf_dvb */
  643. fe0->dvb.name = dev->name;
  644. /* multi-frontend gate control is undefined or defaults to fe0 */
  645. port->frontends.gate = 0;
  646. /* Sets the gate control callback to be used by i2c command calls */
  647. port->gate_ctrl = cx23885_dvb_gate_ctrl;
  648. /* init frontend */
  649. switch (dev->board) {
  650. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  651. i2c_bus = &dev->i2c_bus[0];
  652. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  653. &hauppauge_generic_config,
  654. &i2c_bus->i2c_adap);
  655. if (fe0->dvb.frontend != NULL) {
  656. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  657. &i2c_bus->i2c_adap,
  658. &hauppauge_generic_tunerconfig, 0);
  659. }
  660. break;
  661. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  662. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  663. i2c_bus = &dev->i2c_bus[0];
  664. fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
  665. &hauppauge_lgdt3305_config,
  666. &i2c_bus->i2c_adap);
  667. if (fe0->dvb.frontend != NULL) {
  668. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  669. 0x60, &dev->i2c_bus[1].i2c_adap,
  670. &hauppauge_hvr127x_config);
  671. }
  672. break;
  673. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  674. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  675. i2c_bus = &dev->i2c_bus[0];
  676. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  677. &hcw_s5h1411_config,
  678. &i2c_bus->i2c_adap);
  679. if (fe0->dvb.frontend != NULL) {
  680. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  681. 0x60, &dev->i2c_bus[1].i2c_adap,
  682. &hauppauge_tda18271_config);
  683. }
  684. tda18271_attach(&dev->ts1.analog_fe,
  685. 0x60, &dev->i2c_bus[1].i2c_adap,
  686. &hauppauge_tda18271_config);
  687. break;
  688. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  689. i2c_bus = &dev->i2c_bus[0];
  690. switch (alt_tuner) {
  691. case 1:
  692. fe0->dvb.frontend =
  693. dvb_attach(s5h1409_attach,
  694. &hauppauge_ezqam_config,
  695. &i2c_bus->i2c_adap);
  696. if (fe0->dvb.frontend != NULL) {
  697. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  698. &dev->i2c_bus[1].i2c_adap, 0x42,
  699. &tda829x_no_probe);
  700. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  701. 0x60, &dev->i2c_bus[1].i2c_adap,
  702. &hauppauge_tda18271_config);
  703. }
  704. break;
  705. case 0:
  706. default:
  707. fe0->dvb.frontend =
  708. dvb_attach(s5h1409_attach,
  709. &hauppauge_generic_config,
  710. &i2c_bus->i2c_adap);
  711. if (fe0->dvb.frontend != NULL)
  712. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  713. &i2c_bus->i2c_adap,
  714. &hauppauge_generic_tunerconfig, 0);
  715. break;
  716. }
  717. break;
  718. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  719. i2c_bus = &dev->i2c_bus[0];
  720. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  721. &hauppauge_hvr1800lp_config,
  722. &i2c_bus->i2c_adap);
  723. if (fe0->dvb.frontend != NULL) {
  724. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  725. &i2c_bus->i2c_adap,
  726. &hauppauge_generic_tunerconfig, 0);
  727. }
  728. break;
  729. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  730. i2c_bus = &dev->i2c_bus[0];
  731. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  732. &fusionhdtv_5_express,
  733. &i2c_bus->i2c_adap);
  734. if (fe0->dvb.frontend != NULL) {
  735. dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  736. &i2c_bus->i2c_adap, 0x61,
  737. TUNER_LG_TDVS_H06XF);
  738. }
  739. break;
  740. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  741. i2c_bus = &dev->i2c_bus[1];
  742. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  743. &hauppauge_hvr1500q_config,
  744. &dev->i2c_bus[0].i2c_adap);
  745. if (fe0->dvb.frontend != NULL)
  746. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  747. &i2c_bus->i2c_adap,
  748. &hauppauge_hvr1500q_tunerconfig);
  749. break;
  750. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  751. i2c_bus = &dev->i2c_bus[1];
  752. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  753. &hauppauge_hvr1500_config,
  754. &dev->i2c_bus[0].i2c_adap);
  755. if (fe0->dvb.frontend != NULL) {
  756. struct dvb_frontend *fe;
  757. struct xc2028_config cfg = {
  758. .i2c_adap = &i2c_bus->i2c_adap,
  759. .i2c_addr = 0x61,
  760. };
  761. static struct xc2028_ctrl ctl = {
  762. .fname = XC2028_DEFAULT_FIRMWARE,
  763. .max_len = 64,
  764. .demod = XC3028_FE_OREN538,
  765. };
  766. fe = dvb_attach(xc2028_attach,
  767. fe0->dvb.frontend, &cfg);
  768. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  769. fe->ops.tuner_ops.set_config(fe, &ctl);
  770. }
  771. break;
  772. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  773. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  774. i2c_bus = &dev->i2c_bus[0];
  775. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  776. &hauppauge_hvr1200_config,
  777. &i2c_bus->i2c_adap);
  778. if (fe0->dvb.frontend != NULL) {
  779. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  780. &dev->i2c_bus[1].i2c_adap, 0x42,
  781. &tda829x_no_probe);
  782. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  783. 0x60, &dev->i2c_bus[1].i2c_adap,
  784. &hauppauge_hvr1200_tuner_config);
  785. }
  786. break;
  787. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  788. i2c_bus = &dev->i2c_bus[0];
  789. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  790. &hauppauge_hvr1210_config,
  791. &i2c_bus->i2c_adap);
  792. if (fe0->dvb.frontend != NULL) {
  793. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  794. 0x60, &dev->i2c_bus[1].i2c_adap,
  795. &hauppauge_hvr1210_tuner_config);
  796. }
  797. break;
  798. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  799. i2c_bus = &dev->i2c_bus[0];
  800. fe0->dvb.frontend = dvb_attach(dib7000p_attach,
  801. &i2c_bus->i2c_adap,
  802. 0x12, &hauppauge_hvr1400_dib7000_config);
  803. if (fe0->dvb.frontend != NULL) {
  804. struct dvb_frontend *fe;
  805. struct xc2028_config cfg = {
  806. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  807. .i2c_addr = 0x64,
  808. };
  809. static struct xc2028_ctrl ctl = {
  810. .fname = XC3028L_DEFAULT_FIRMWARE,
  811. .max_len = 64,
  812. .demod = XC3028_FE_DIBCOM52,
  813. /* This is true for all demods with
  814. v36 firmware? */
  815. .type = XC2028_D2633,
  816. };
  817. fe = dvb_attach(xc2028_attach,
  818. fe0->dvb.frontend, &cfg);
  819. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  820. fe->ops.tuner_ops.set_config(fe, &ctl);
  821. }
  822. break;
  823. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  824. i2c_bus = &dev->i2c_bus[port->nr - 1];
  825. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  826. &dvico_s5h1409_config,
  827. &i2c_bus->i2c_adap);
  828. if (fe0->dvb.frontend == NULL)
  829. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  830. &dvico_s5h1411_config,
  831. &i2c_bus->i2c_adap);
  832. if (fe0->dvb.frontend != NULL)
  833. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  834. &i2c_bus->i2c_adap,
  835. &dvico_xc5000_tunerconfig);
  836. break;
  837. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
  838. i2c_bus = &dev->i2c_bus[port->nr - 1];
  839. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  840. &dvico_fusionhdtv_xc3028,
  841. &i2c_bus->i2c_adap);
  842. if (fe0->dvb.frontend != NULL) {
  843. struct dvb_frontend *fe;
  844. struct xc2028_config cfg = {
  845. .i2c_adap = &i2c_bus->i2c_adap,
  846. .i2c_addr = 0x61,
  847. };
  848. static struct xc2028_ctrl ctl = {
  849. .fname = XC2028_DEFAULT_FIRMWARE,
  850. .max_len = 64,
  851. .demod = XC3028_FE_ZARLINK456,
  852. };
  853. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  854. &cfg);
  855. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  856. fe->ops.tuner_ops.set_config(fe, &ctl);
  857. }
  858. break;
  859. }
  860. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  861. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  862. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  863. i2c_bus = &dev->i2c_bus[0];
  864. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  865. &dvico_fusionhdtv_xc3028,
  866. &i2c_bus->i2c_adap);
  867. if (fe0->dvb.frontend != NULL) {
  868. struct dvb_frontend *fe;
  869. struct xc2028_config cfg = {
  870. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  871. .i2c_addr = 0x61,
  872. };
  873. static struct xc2028_ctrl ctl = {
  874. .fname = XC2028_DEFAULT_FIRMWARE,
  875. .max_len = 64,
  876. .demod = XC3028_FE_ZARLINK456,
  877. };
  878. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  879. &cfg);
  880. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  881. fe->ops.tuner_ops.set_config(fe, &ctl);
  882. }
  883. break;
  884. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  885. i2c_bus = &dev->i2c_bus[0];
  886. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  887. &dvico_fusionhdtv_xc3028,
  888. &i2c_bus->i2c_adap);
  889. if (fe0->dvb.frontend != NULL) {
  890. struct dvb_frontend *fe;
  891. struct xc4000_config cfg = {
  892. .i2c_address = 0x61,
  893. .default_pm = 0,
  894. .dvb_amplitude = 134,
  895. .set_smoothedcvbs = 1,
  896. .if_khz = 4560
  897. };
  898. fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
  899. &dev->i2c_bus[1].i2c_adap, &cfg);
  900. if (!fe) {
  901. printk(KERN_ERR "%s/2: xc4000 attach failed\n",
  902. dev->name);
  903. goto frontend_detach;
  904. }
  905. }
  906. break;
  907. case CX23885_BOARD_TBS_6920:
  908. i2c_bus = &dev->i2c_bus[1];
  909. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  910. &tbs_cx24116_config,
  911. &i2c_bus->i2c_adap);
  912. if (fe0->dvb.frontend != NULL)
  913. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  914. break;
  915. case CX23885_BOARD_TEVII_S470:
  916. i2c_bus = &dev->i2c_bus[1];
  917. fe0->dvb.frontend = dvb_attach(ds3000_attach,
  918. &tevii_ds3000_config,
  919. &i2c_bus->i2c_adap);
  920. if (fe0->dvb.frontend != NULL) {
  921. dvb_attach(ts2020_attach, fe0->dvb.frontend,
  922. &tevii_ts2020_config, &i2c_bus->i2c_adap);
  923. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  924. }
  925. break;
  926. case CX23885_BOARD_DVBWORLD_2005:
  927. i2c_bus = &dev->i2c_bus[1];
  928. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  929. &dvbworld_cx24116_config,
  930. &i2c_bus->i2c_adap);
  931. break;
  932. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  933. i2c_bus = &dev->i2c_bus[0];
  934. switch (port->nr) {
  935. /* port B */
  936. case 1:
  937. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  938. &netup_stv0900_config,
  939. &i2c_bus->i2c_adap, 0);
  940. if (fe0->dvb.frontend != NULL) {
  941. if (dvb_attach(stv6110_attach,
  942. fe0->dvb.frontend,
  943. &netup_stv6110_tunerconfig_a,
  944. &i2c_bus->i2c_adap)) {
  945. if (!dvb_attach(lnbh24_attach,
  946. fe0->dvb.frontend,
  947. &i2c_bus->i2c_adap,
  948. LNBH24_PCL | LNBH24_TTX,
  949. LNBH24_TEN, 0x09))
  950. printk(KERN_ERR
  951. "No LNBH24 found!\n");
  952. }
  953. }
  954. break;
  955. /* port C */
  956. case 2:
  957. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  958. &netup_stv0900_config,
  959. &i2c_bus->i2c_adap, 1);
  960. if (fe0->dvb.frontend != NULL) {
  961. if (dvb_attach(stv6110_attach,
  962. fe0->dvb.frontend,
  963. &netup_stv6110_tunerconfig_b,
  964. &i2c_bus->i2c_adap)) {
  965. if (!dvb_attach(lnbh24_attach,
  966. fe0->dvb.frontend,
  967. &i2c_bus->i2c_adap,
  968. LNBH24_PCL | LNBH24_TTX,
  969. LNBH24_TEN, 0x0a))
  970. printk(KERN_ERR
  971. "No LNBH24 found!\n");
  972. }
  973. }
  974. break;
  975. }
  976. break;
  977. case CX23885_BOARD_MYGICA_X8506:
  978. i2c_bus = &dev->i2c_bus[0];
  979. i2c_bus2 = &dev->i2c_bus[1];
  980. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  981. &mygica_x8506_lgs8gl5_config,
  982. &i2c_bus->i2c_adap);
  983. if (fe0->dvb.frontend != NULL) {
  984. dvb_attach(xc5000_attach,
  985. fe0->dvb.frontend,
  986. &i2c_bus2->i2c_adap,
  987. &mygica_x8506_xc5000_config);
  988. }
  989. break;
  990. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  991. i2c_bus = &dev->i2c_bus[0];
  992. i2c_bus2 = &dev->i2c_bus[1];
  993. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  994. &magicpro_prohdtve2_lgs8g75_config,
  995. &i2c_bus->i2c_adap);
  996. if (fe0->dvb.frontend != NULL) {
  997. dvb_attach(xc5000_attach,
  998. fe0->dvb.frontend,
  999. &i2c_bus2->i2c_adap,
  1000. &magicpro_prohdtve2_xc5000_config);
  1001. }
  1002. break;
  1003. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1004. i2c_bus = &dev->i2c_bus[0];
  1005. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  1006. &hcw_s5h1411_config,
  1007. &i2c_bus->i2c_adap);
  1008. if (fe0->dvb.frontend != NULL)
  1009. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  1010. 0x60, &dev->i2c_bus[0].i2c_adap,
  1011. &hauppauge_tda18271_config);
  1012. tda18271_attach(&dev->ts1.analog_fe,
  1013. 0x60, &dev->i2c_bus[1].i2c_adap,
  1014. &hauppauge_tda18271_config);
  1015. break;
  1016. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1017. i2c_bus = &dev->i2c_bus[0];
  1018. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  1019. &hcw_s5h1411_config,
  1020. &i2c_bus->i2c_adap);
  1021. if (fe0->dvb.frontend != NULL)
  1022. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  1023. 0x60, &dev->i2c_bus[0].i2c_adap,
  1024. &hauppauge_tda18271_config);
  1025. break;
  1026. case CX23885_BOARD_MYGICA_X8558PRO:
  1027. switch (port->nr) {
  1028. /* port B */
  1029. case 1:
  1030. i2c_bus = &dev->i2c_bus[0];
  1031. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  1032. &mygica_x8558pro_atbm8830_cfg1,
  1033. &i2c_bus->i2c_adap);
  1034. if (fe0->dvb.frontend != NULL) {
  1035. dvb_attach(max2165_attach,
  1036. fe0->dvb.frontend,
  1037. &i2c_bus->i2c_adap,
  1038. &mygic_x8558pro_max2165_cfg1);
  1039. }
  1040. break;
  1041. /* port C */
  1042. case 2:
  1043. i2c_bus = &dev->i2c_bus[1];
  1044. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  1045. &mygica_x8558pro_atbm8830_cfg2,
  1046. &i2c_bus->i2c_adap);
  1047. if (fe0->dvb.frontend != NULL) {
  1048. dvb_attach(max2165_attach,
  1049. fe0->dvb.frontend,
  1050. &i2c_bus->i2c_adap,
  1051. &mygic_x8558pro_max2165_cfg2);
  1052. }
  1053. break;
  1054. }
  1055. break;
  1056. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1057. i2c_bus = &dev->i2c_bus[0];
  1058. mfe_shared = 1;/* MFE */
  1059. port->frontends.gate = 0;/* not clear for me yet */
  1060. /* ports B, C */
  1061. /* MFE frontend 1 DVB-T */
  1062. fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
  1063. &netup_stv0367_config[port->nr - 1],
  1064. &i2c_bus->i2c_adap);
  1065. if (fe0->dvb.frontend != NULL) {
  1066. if (NULL == dvb_attach(xc5000_attach,
  1067. fe0->dvb.frontend,
  1068. &i2c_bus->i2c_adap,
  1069. &netup_xc5000_config[port->nr - 1]))
  1070. goto frontend_detach;
  1071. /* load xc5000 firmware */
  1072. fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
  1073. }
  1074. /* MFE frontend 2 */
  1075. fe1 = videobuf_dvb_get_frontend(&port->frontends, 2);
  1076. if (fe1 == NULL)
  1077. goto frontend_detach;
  1078. /* DVB-C init */
  1079. fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
  1080. &netup_stv0367_config[port->nr - 1],
  1081. &i2c_bus->i2c_adap);
  1082. if (fe1->dvb.frontend != NULL) {
  1083. fe1->dvb.frontend->id = 1;
  1084. if (NULL == dvb_attach(xc5000_attach,
  1085. fe1->dvb.frontend,
  1086. &i2c_bus->i2c_adap,
  1087. &netup_xc5000_config[port->nr - 1]))
  1088. goto frontend_detach;
  1089. }
  1090. break;
  1091. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1092. i2c_bus = &dev->i2c_bus[0];
  1093. i2c_bus2 = &dev->i2c_bus[1];
  1094. switch (port->nr) {
  1095. /* port b */
  1096. case 1:
  1097. fe0->dvb.frontend = dvb_attach(drxk_attach,
  1098. &terratec_drxk_config[0],
  1099. &i2c_bus->i2c_adap);
  1100. if (fe0->dvb.frontend != NULL) {
  1101. if (!dvb_attach(mt2063_attach,
  1102. fe0->dvb.frontend,
  1103. &terratec_mt2063_config[0],
  1104. &i2c_bus2->i2c_adap))
  1105. goto frontend_detach;
  1106. }
  1107. break;
  1108. /* port c */
  1109. case 2:
  1110. fe0->dvb.frontend = dvb_attach(drxk_attach,
  1111. &terratec_drxk_config[1],
  1112. &i2c_bus->i2c_adap);
  1113. if (fe0->dvb.frontend != NULL) {
  1114. if (!dvb_attach(mt2063_attach,
  1115. fe0->dvb.frontend,
  1116. &terratec_mt2063_config[1],
  1117. &i2c_bus2->i2c_adap))
  1118. goto frontend_detach;
  1119. }
  1120. break;
  1121. }
  1122. break;
  1123. case CX23885_BOARD_TEVII_S471:
  1124. i2c_bus = &dev->i2c_bus[1];
  1125. fe0->dvb.frontend = dvb_attach(ds3000_attach,
  1126. &tevii_ds3000_config,
  1127. &i2c_bus->i2c_adap);
  1128. break;
  1129. case CX23885_BOARD_PROF_8000:
  1130. i2c_bus = &dev->i2c_bus[0];
  1131. fe0->dvb.frontend = dvb_attach(stv090x_attach,
  1132. &prof_8000_stv090x_config,
  1133. &i2c_bus->i2c_adap,
  1134. STV090x_DEMODULATOR_0);
  1135. if (fe0->dvb.frontend != NULL) {
  1136. if (!dvb_attach(stb6100_attach,
  1137. fe0->dvb.frontend,
  1138. &prof_8000_stb6100_config,
  1139. &i2c_bus->i2c_adap))
  1140. goto frontend_detach;
  1141. fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage;
  1142. }
  1143. break;
  1144. case CX23885_BOARD_HAUPPAUGE_HVR4400:
  1145. i2c_bus = &dev->i2c_bus[0];
  1146. fe0->dvb.frontend = dvb_attach(tda10071_attach,
  1147. &hauppauge_tda10071_config,
  1148. &i2c_bus->i2c_adap);
  1149. if (fe0->dvb.frontend != NULL) {
  1150. dvb_attach(a8293_attach, fe0->dvb.frontend,
  1151. &i2c_bus->i2c_adap,
  1152. &hauppauge_a8293_config);
  1153. }
  1154. break;
  1155. default:
  1156. printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
  1157. " isn't supported yet\n",
  1158. dev->name);
  1159. break;
  1160. }
  1161. if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
  1162. printk(KERN_ERR "%s: frontend initialization failed\n",
  1163. dev->name);
  1164. goto frontend_detach;
  1165. }
  1166. /* define general-purpose callback pointer */
  1167. fe0->dvb.frontend->callback = cx23885_tuner_callback;
  1168. if (fe1)
  1169. fe1->dvb.frontend->callback = cx23885_tuner_callback;
  1170. #if 0
  1171. /* Ensure all frontends negotiate bus access */
  1172. fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
  1173. if (fe1)
  1174. fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
  1175. #endif
  1176. /* Put the analog decoder in standby to keep it quiet */
  1177. call_all(dev, core, s_power, 0);
  1178. if (fe0->dvb.frontend->ops.analog_ops.standby)
  1179. fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
  1180. /* register everything */
  1181. ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
  1182. &dev->pci->dev, adapter_nr, mfe_shared);
  1183. if (ret)
  1184. goto frontend_detach;
  1185. /* init CI & MAC */
  1186. switch (dev->board) {
  1187. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
  1188. static struct netup_card_info cinfo;
  1189. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  1190. memcpy(port->frontends.adapter.proposed_mac,
  1191. cinfo.port[port->nr - 1].mac, 6);
  1192. printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
  1193. port->nr, port->frontends.adapter.proposed_mac);
  1194. netup_ci_init(port);
  1195. break;
  1196. }
  1197. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
  1198. struct altera_ci_config netup_ci_cfg = {
  1199. .dev = dev,/* magic number to identify*/
  1200. .adapter = &port->frontends.adapter,/* for CI */
  1201. .demux = &fe0->dvb.demux,/* for hw pid filter */
  1202. .fpga_rw = netup_altera_fpga_rw,
  1203. };
  1204. altera_ci_init(&netup_ci_cfg, port->nr);
  1205. break;
  1206. }
  1207. case CX23885_BOARD_TEVII_S470: {
  1208. u8 eeprom[256]; /* 24C02 i2c eeprom */
  1209. if (port->nr != 1)
  1210. break;
  1211. /* Read entire EEPROM */
  1212. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  1213. tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
  1214. printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
  1215. memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
  1216. break;
  1217. }
  1218. }
  1219. return ret;
  1220. frontend_detach:
  1221. port->gate_ctrl = NULL;
  1222. videobuf_dvb_dealloc_frontends(&port->frontends);
  1223. return -EINVAL;
  1224. }
  1225. int cx23885_dvb_register(struct cx23885_tsport *port)
  1226. {
  1227. struct videobuf_dvb_frontend *fe0;
  1228. struct cx23885_dev *dev = port->dev;
  1229. int err, i;
  1230. /* Here we need to allocate the correct number of frontends,
  1231. * as reflected in the cards struct. The reality is that currently
  1232. * no cx23885 boards support this - yet. But, if we don't modify this
  1233. * code then the second frontend would never be allocated (later)
  1234. * and fail with error before the attach in dvb_register().
  1235. * Without these changes we risk an OOPS later. The changes here
  1236. * are for safety, and should provide a good foundation for the
  1237. * future addition of any multi-frontend cx23885 based boards.
  1238. */
  1239. printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
  1240. port->num_frontends);
  1241. for (i = 1; i <= port->num_frontends; i++) {
  1242. if (videobuf_dvb_alloc_frontend(
  1243. &port->frontends, i) == NULL) {
  1244. printk(KERN_ERR "%s() failed to alloc\n", __func__);
  1245. return -ENOMEM;
  1246. }
  1247. fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
  1248. if (!fe0)
  1249. err = -EINVAL;
  1250. dprintk(1, "%s\n", __func__);
  1251. dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
  1252. dev->board,
  1253. dev->name,
  1254. dev->pci_bus,
  1255. dev->pci_slot);
  1256. err = -ENODEV;
  1257. /* dvb stuff */
  1258. /* We have to init the queue for each frontend on a port. */
  1259. printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
  1260. videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
  1261. &dev->pci->dev, &port->slock,
  1262. V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
  1263. sizeof(struct cx23885_buffer), port, NULL);
  1264. }
  1265. err = dvb_register(port);
  1266. if (err != 0)
  1267. printk(KERN_ERR "%s() dvb_register failed err = %d\n",
  1268. __func__, err);
  1269. return err;
  1270. }
  1271. int cx23885_dvb_unregister(struct cx23885_tsport *port)
  1272. {
  1273. struct videobuf_dvb_frontend *fe0;
  1274. /* FIXME: in an error condition where the we have
  1275. * an expected number of frontends (attach problem)
  1276. * then this might not clean up correctly, if 1
  1277. * is invalid.
  1278. * This comment only applies to future boards IF they
  1279. * implement MFE support.
  1280. */
  1281. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  1282. if (fe0 && fe0->dvb.frontend)
  1283. videobuf_dvb_unregister_bus(&port->frontends);
  1284. switch (port->dev->board) {
  1285. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1286. netup_ci_exit(port);
  1287. break;
  1288. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1289. altera_ci_release(port->dev, port->nr);
  1290. break;
  1291. }
  1292. port->gate_ctrl = NULL;
  1293. return 0;
  1294. }