cx23885-cards.c 51 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/pci.h>
  24. #include <linux/delay.h>
  25. #include <media/cx25840.h>
  26. #include <linux/firmware.h>
  27. #include <misc/altera.h>
  28. #include "cx23885.h"
  29. #include "tuner-xc2028.h"
  30. #include "netup-eeprom.h"
  31. #include "netup-init.h"
  32. #include "altera-ci.h"
  33. #include "xc4000.h"
  34. #include "xc5000.h"
  35. #include "cx23888-ir.h"
  36. static unsigned int netup_card_rev = 4;
  37. module_param(netup_card_rev, int, 0644);
  38. MODULE_PARM_DESC(netup_card_rev,
  39. "NetUP Dual DVB-T/C CI card revision");
  40. static unsigned int enable_885_ir;
  41. module_param(enable_885_ir, int, 0644);
  42. MODULE_PARM_DESC(enable_885_ir,
  43. "Enable integrated IR controller for supported\n"
  44. "\t\t CX2388[57] boards that are wired for it:\n"
  45. "\t\t\tHVR-1250 (reported safe)\n"
  46. "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n"
  47. "\t\t\tTeVii S470 (reported unsafe)\n"
  48. "\t\t This can cause an interrupt storm with some cards.\n"
  49. "\t\t Default: 0 [Disabled]");
  50. /* ------------------------------------------------------------------ */
  51. /* board config info */
  52. struct cx23885_board cx23885_boards[] = {
  53. [CX23885_BOARD_UNKNOWN] = {
  54. .name = "UNKNOWN/GENERIC",
  55. /* Ensure safe default for unknown boards */
  56. .clk_freq = 0,
  57. .input = {{
  58. .type = CX23885_VMUX_COMPOSITE1,
  59. .vmux = 0,
  60. }, {
  61. .type = CX23885_VMUX_COMPOSITE2,
  62. .vmux = 1,
  63. }, {
  64. .type = CX23885_VMUX_COMPOSITE3,
  65. .vmux = 2,
  66. }, {
  67. .type = CX23885_VMUX_COMPOSITE4,
  68. .vmux = 3,
  69. } },
  70. },
  71. [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
  72. .name = "Hauppauge WinTV-HVR1800lp",
  73. .portc = CX23885_MPEG_DVB,
  74. .input = {{
  75. .type = CX23885_VMUX_TELEVISION,
  76. .vmux = 0,
  77. .gpio0 = 0xff00,
  78. }, {
  79. .type = CX23885_VMUX_DEBUG,
  80. .vmux = 0,
  81. .gpio0 = 0xff01,
  82. }, {
  83. .type = CX23885_VMUX_COMPOSITE1,
  84. .vmux = 1,
  85. .gpio0 = 0xff02,
  86. }, {
  87. .type = CX23885_VMUX_SVIDEO,
  88. .vmux = 2,
  89. .gpio0 = 0xff02,
  90. } },
  91. },
  92. [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
  93. .name = "Hauppauge WinTV-HVR1800",
  94. .porta = CX23885_ANALOG_VIDEO,
  95. .portb = CX23885_MPEG_ENCODER,
  96. .portc = CX23885_MPEG_DVB,
  97. .tuner_type = TUNER_PHILIPS_TDA8290,
  98. .tuner_addr = 0x42, /* 0x84 >> 1 */
  99. .tuner_bus = 1,
  100. .input = {{
  101. .type = CX23885_VMUX_TELEVISION,
  102. .vmux = CX25840_VIN7_CH3 |
  103. CX25840_VIN5_CH2 |
  104. CX25840_VIN2_CH1,
  105. .amux = CX25840_AUDIO8,
  106. .gpio0 = 0,
  107. }, {
  108. .type = CX23885_VMUX_COMPOSITE1,
  109. .vmux = CX25840_VIN7_CH3 |
  110. CX25840_VIN4_CH2 |
  111. CX25840_VIN6_CH1,
  112. .amux = CX25840_AUDIO7,
  113. .gpio0 = 0,
  114. }, {
  115. .type = CX23885_VMUX_SVIDEO,
  116. .vmux = CX25840_VIN7_CH3 |
  117. CX25840_VIN4_CH2 |
  118. CX25840_VIN8_CH1 |
  119. CX25840_SVIDEO_ON,
  120. .amux = CX25840_AUDIO7,
  121. .gpio0 = 0,
  122. } },
  123. },
  124. [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
  125. .name = "Hauppauge WinTV-HVR1250",
  126. .porta = CX23885_ANALOG_VIDEO,
  127. .portc = CX23885_MPEG_DVB,
  128. #ifdef MT2131_NO_ANALOG_SUPPORT_YET
  129. .tuner_type = TUNER_PHILIPS_TDA8290,
  130. .tuner_addr = 0x42, /* 0x84 >> 1 */
  131. .tuner_bus = 1,
  132. #endif
  133. .force_bff = 1,
  134. .input = {{
  135. #ifdef MT2131_NO_ANALOG_SUPPORT_YET
  136. .type = CX23885_VMUX_TELEVISION,
  137. .vmux = CX25840_VIN7_CH3 |
  138. CX25840_VIN5_CH2 |
  139. CX25840_VIN2_CH1,
  140. .amux = CX25840_AUDIO8,
  141. .gpio0 = 0xff00,
  142. }, {
  143. #endif
  144. .type = CX23885_VMUX_COMPOSITE1,
  145. .vmux = CX25840_VIN7_CH3 |
  146. CX25840_VIN4_CH2 |
  147. CX25840_VIN6_CH1,
  148. .amux = CX25840_AUDIO7,
  149. .gpio0 = 0xff02,
  150. }, {
  151. .type = CX23885_VMUX_SVIDEO,
  152. .vmux = CX25840_VIN7_CH3 |
  153. CX25840_VIN4_CH2 |
  154. CX25840_VIN8_CH1 |
  155. CX25840_SVIDEO_ON,
  156. .amux = CX25840_AUDIO7,
  157. .gpio0 = 0xff02,
  158. } },
  159. },
  160. [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
  161. .name = "DViCO FusionHDTV5 Express",
  162. .portb = CX23885_MPEG_DVB,
  163. },
  164. [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
  165. .name = "Hauppauge WinTV-HVR1500Q",
  166. .portc = CX23885_MPEG_DVB,
  167. },
  168. [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
  169. .name = "Hauppauge WinTV-HVR1500",
  170. .porta = CX23885_ANALOG_VIDEO,
  171. .portc = CX23885_MPEG_DVB,
  172. .tuner_type = TUNER_XC2028,
  173. .tuner_addr = 0x61, /* 0xc2 >> 1 */
  174. .input = {{
  175. .type = CX23885_VMUX_TELEVISION,
  176. .vmux = CX25840_VIN7_CH3 |
  177. CX25840_VIN5_CH2 |
  178. CX25840_VIN2_CH1,
  179. .gpio0 = 0,
  180. }, {
  181. .type = CX23885_VMUX_COMPOSITE1,
  182. .vmux = CX25840_VIN7_CH3 |
  183. CX25840_VIN4_CH2 |
  184. CX25840_VIN6_CH1,
  185. .gpio0 = 0,
  186. }, {
  187. .type = CX23885_VMUX_SVIDEO,
  188. .vmux = CX25840_VIN7_CH3 |
  189. CX25840_VIN4_CH2 |
  190. CX25840_VIN8_CH1 |
  191. CX25840_SVIDEO_ON,
  192. .gpio0 = 0,
  193. } },
  194. },
  195. [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
  196. .name = "Hauppauge WinTV-HVR1200",
  197. .portc = CX23885_MPEG_DVB,
  198. },
  199. [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
  200. .name = "Hauppauge WinTV-HVR1700",
  201. .portc = CX23885_MPEG_DVB,
  202. },
  203. [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
  204. .name = "Hauppauge WinTV-HVR1400",
  205. .portc = CX23885_MPEG_DVB,
  206. },
  207. [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
  208. .name = "DViCO FusionHDTV7 Dual Express",
  209. .portb = CX23885_MPEG_DVB,
  210. .portc = CX23885_MPEG_DVB,
  211. },
  212. [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
  213. .name = "DViCO FusionHDTV DVB-T Dual Express",
  214. .portb = CX23885_MPEG_DVB,
  215. .portc = CX23885_MPEG_DVB,
  216. },
  217. [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
  218. .name = "Leadtek Winfast PxDVR3200 H",
  219. .portc = CX23885_MPEG_DVB,
  220. },
  221. [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
  222. .name = "Leadtek Winfast PxDVR3200 H XC4000",
  223. .porta = CX23885_ANALOG_VIDEO,
  224. .portc = CX23885_MPEG_DVB,
  225. .tuner_type = TUNER_XC4000,
  226. .tuner_addr = 0x61,
  227. .radio_type = UNSET,
  228. .radio_addr = ADDR_UNSET,
  229. .input = {{
  230. .type = CX23885_VMUX_TELEVISION,
  231. .vmux = CX25840_VIN2_CH1 |
  232. CX25840_VIN5_CH2 |
  233. CX25840_NONE0_CH3,
  234. }, {
  235. .type = CX23885_VMUX_COMPOSITE1,
  236. .vmux = CX25840_COMPOSITE1,
  237. }, {
  238. .type = CX23885_VMUX_SVIDEO,
  239. .vmux = CX25840_SVIDEO_LUMA3 |
  240. CX25840_SVIDEO_CHROMA4,
  241. }, {
  242. .type = CX23885_VMUX_COMPONENT,
  243. .vmux = CX25840_VIN7_CH1 |
  244. CX25840_VIN6_CH2 |
  245. CX25840_VIN8_CH3 |
  246. CX25840_COMPONENT_ON,
  247. } },
  248. },
  249. [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
  250. .name = "Compro VideoMate E650F",
  251. .portc = CX23885_MPEG_DVB,
  252. },
  253. [CX23885_BOARD_TBS_6920] = {
  254. .name = "TurboSight TBS 6920",
  255. .portb = CX23885_MPEG_DVB,
  256. },
  257. [CX23885_BOARD_TEVII_S470] = {
  258. .name = "TeVii S470",
  259. .portb = CX23885_MPEG_DVB,
  260. },
  261. [CX23885_BOARD_DVBWORLD_2005] = {
  262. .name = "DVBWorld DVB-S2 2005",
  263. .portb = CX23885_MPEG_DVB,
  264. },
  265. [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
  266. .ci_type = 1,
  267. .name = "NetUP Dual DVB-S2 CI",
  268. .portb = CX23885_MPEG_DVB,
  269. .portc = CX23885_MPEG_DVB,
  270. },
  271. [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
  272. .name = "Hauppauge WinTV-HVR1270",
  273. .portc = CX23885_MPEG_DVB,
  274. },
  275. [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
  276. .name = "Hauppauge WinTV-HVR1275",
  277. .portc = CX23885_MPEG_DVB,
  278. },
  279. [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
  280. .name = "Hauppauge WinTV-HVR1255",
  281. .porta = CX23885_ANALOG_VIDEO,
  282. .portc = CX23885_MPEG_DVB,
  283. .tuner_type = TUNER_ABSENT,
  284. .tuner_addr = 0x42, /* 0x84 >> 1 */
  285. .force_bff = 1,
  286. .input = {{
  287. .type = CX23885_VMUX_TELEVISION,
  288. .vmux = CX25840_VIN7_CH3 |
  289. CX25840_VIN5_CH2 |
  290. CX25840_VIN2_CH1 |
  291. CX25840_DIF_ON,
  292. .amux = CX25840_AUDIO8,
  293. }, {
  294. .type = CX23885_VMUX_COMPOSITE1,
  295. .vmux = CX25840_VIN7_CH3 |
  296. CX25840_VIN4_CH2 |
  297. CX25840_VIN6_CH1,
  298. .amux = CX25840_AUDIO7,
  299. }, {
  300. .type = CX23885_VMUX_SVIDEO,
  301. .vmux = CX25840_VIN7_CH3 |
  302. CX25840_VIN4_CH2 |
  303. CX25840_VIN8_CH1 |
  304. CX25840_SVIDEO_ON,
  305. .amux = CX25840_AUDIO7,
  306. } },
  307. },
  308. [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = {
  309. .name = "Hauppauge WinTV-HVR1255",
  310. .porta = CX23885_ANALOG_VIDEO,
  311. .portc = CX23885_MPEG_DVB,
  312. .tuner_type = TUNER_ABSENT,
  313. .tuner_addr = 0x42, /* 0x84 >> 1 */
  314. .force_bff = 1,
  315. .input = {{
  316. .type = CX23885_VMUX_TELEVISION,
  317. .vmux = CX25840_VIN7_CH3 |
  318. CX25840_VIN5_CH2 |
  319. CX25840_VIN2_CH1 |
  320. CX25840_DIF_ON,
  321. .amux = CX25840_AUDIO8,
  322. }, {
  323. .type = CX23885_VMUX_SVIDEO,
  324. .vmux = CX25840_VIN7_CH3 |
  325. CX25840_VIN4_CH2 |
  326. CX25840_VIN8_CH1 |
  327. CX25840_SVIDEO_ON,
  328. .amux = CX25840_AUDIO7,
  329. } },
  330. },
  331. [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
  332. .name = "Hauppauge WinTV-HVR1210",
  333. .portc = CX23885_MPEG_DVB,
  334. },
  335. [CX23885_BOARD_MYGICA_X8506] = {
  336. .name = "Mygica X8506 DMB-TH",
  337. .tuner_type = TUNER_XC5000,
  338. .tuner_addr = 0x61,
  339. .tuner_bus = 1,
  340. .porta = CX23885_ANALOG_VIDEO,
  341. .portb = CX23885_MPEG_DVB,
  342. .input = {
  343. {
  344. .type = CX23885_VMUX_TELEVISION,
  345. .vmux = CX25840_COMPOSITE2,
  346. },
  347. {
  348. .type = CX23885_VMUX_COMPOSITE1,
  349. .vmux = CX25840_COMPOSITE8,
  350. },
  351. {
  352. .type = CX23885_VMUX_SVIDEO,
  353. .vmux = CX25840_SVIDEO_LUMA3 |
  354. CX25840_SVIDEO_CHROMA4,
  355. },
  356. {
  357. .type = CX23885_VMUX_COMPONENT,
  358. .vmux = CX25840_COMPONENT_ON |
  359. CX25840_VIN1_CH1 |
  360. CX25840_VIN6_CH2 |
  361. CX25840_VIN7_CH3,
  362. },
  363. },
  364. },
  365. [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
  366. .name = "Magic-Pro ProHDTV Extreme 2",
  367. .tuner_type = TUNER_XC5000,
  368. .tuner_addr = 0x61,
  369. .tuner_bus = 1,
  370. .porta = CX23885_ANALOG_VIDEO,
  371. .portb = CX23885_MPEG_DVB,
  372. .input = {
  373. {
  374. .type = CX23885_VMUX_TELEVISION,
  375. .vmux = CX25840_COMPOSITE2,
  376. },
  377. {
  378. .type = CX23885_VMUX_COMPOSITE1,
  379. .vmux = CX25840_COMPOSITE8,
  380. },
  381. {
  382. .type = CX23885_VMUX_SVIDEO,
  383. .vmux = CX25840_SVIDEO_LUMA3 |
  384. CX25840_SVIDEO_CHROMA4,
  385. },
  386. {
  387. .type = CX23885_VMUX_COMPONENT,
  388. .vmux = CX25840_COMPONENT_ON |
  389. CX25840_VIN1_CH1 |
  390. CX25840_VIN6_CH2 |
  391. CX25840_VIN7_CH3,
  392. },
  393. },
  394. },
  395. [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
  396. .name = "Hauppauge WinTV-HVR1850",
  397. .porta = CX23885_ANALOG_VIDEO,
  398. .portb = CX23885_MPEG_ENCODER,
  399. .portc = CX23885_MPEG_DVB,
  400. .tuner_type = TUNER_ABSENT,
  401. .tuner_addr = 0x42, /* 0x84 >> 1 */
  402. .force_bff = 1,
  403. .input = {{
  404. .type = CX23885_VMUX_TELEVISION,
  405. .vmux = CX25840_VIN7_CH3 |
  406. CX25840_VIN5_CH2 |
  407. CX25840_VIN2_CH1 |
  408. CX25840_DIF_ON,
  409. .amux = CX25840_AUDIO8,
  410. }, {
  411. .type = CX23885_VMUX_COMPOSITE1,
  412. .vmux = CX25840_VIN7_CH3 |
  413. CX25840_VIN4_CH2 |
  414. CX25840_VIN6_CH1,
  415. .amux = CX25840_AUDIO7,
  416. }, {
  417. .type = CX23885_VMUX_SVIDEO,
  418. .vmux = CX25840_VIN7_CH3 |
  419. CX25840_VIN4_CH2 |
  420. CX25840_VIN8_CH1 |
  421. CX25840_SVIDEO_ON,
  422. .amux = CX25840_AUDIO7,
  423. } },
  424. },
  425. [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
  426. .name = "Compro VideoMate E800",
  427. .portc = CX23885_MPEG_DVB,
  428. },
  429. [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
  430. .name = "Hauppauge WinTV-HVR1290",
  431. .portc = CX23885_MPEG_DVB,
  432. },
  433. [CX23885_BOARD_MYGICA_X8558PRO] = {
  434. .name = "Mygica X8558 PRO DMB-TH",
  435. .portb = CX23885_MPEG_DVB,
  436. .portc = CX23885_MPEG_DVB,
  437. },
  438. [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
  439. .name = "LEADTEK WinFast PxTV1200",
  440. .porta = CX23885_ANALOG_VIDEO,
  441. .tuner_type = TUNER_XC2028,
  442. .tuner_addr = 0x61,
  443. .tuner_bus = 1,
  444. .input = {{
  445. .type = CX23885_VMUX_TELEVISION,
  446. .vmux = CX25840_VIN2_CH1 |
  447. CX25840_VIN5_CH2 |
  448. CX25840_NONE0_CH3,
  449. }, {
  450. .type = CX23885_VMUX_COMPOSITE1,
  451. .vmux = CX25840_COMPOSITE1,
  452. }, {
  453. .type = CX23885_VMUX_SVIDEO,
  454. .vmux = CX25840_SVIDEO_LUMA3 |
  455. CX25840_SVIDEO_CHROMA4,
  456. }, {
  457. .type = CX23885_VMUX_COMPONENT,
  458. .vmux = CX25840_VIN7_CH1 |
  459. CX25840_VIN6_CH2 |
  460. CX25840_VIN8_CH3 |
  461. CX25840_COMPONENT_ON,
  462. } },
  463. },
  464. [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
  465. .name = "GoTView X5 3D Hybrid",
  466. .tuner_type = TUNER_XC5000,
  467. .tuner_addr = 0x64,
  468. .tuner_bus = 1,
  469. .porta = CX23885_ANALOG_VIDEO,
  470. .portb = CX23885_MPEG_DVB,
  471. .input = {{
  472. .type = CX23885_VMUX_TELEVISION,
  473. .vmux = CX25840_VIN2_CH1 |
  474. CX25840_VIN5_CH2,
  475. .gpio0 = 0x02,
  476. }, {
  477. .type = CX23885_VMUX_COMPOSITE1,
  478. .vmux = CX23885_VMUX_COMPOSITE1,
  479. }, {
  480. .type = CX23885_VMUX_SVIDEO,
  481. .vmux = CX25840_SVIDEO_LUMA3 |
  482. CX25840_SVIDEO_CHROMA4,
  483. } },
  484. },
  485. [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
  486. .ci_type = 2,
  487. .name = "NetUP Dual DVB-T/C-CI RF",
  488. .porta = CX23885_ANALOG_VIDEO,
  489. .portb = CX23885_MPEG_DVB,
  490. .portc = CX23885_MPEG_DVB,
  491. .num_fds_portb = 2,
  492. .num_fds_portc = 2,
  493. .tuner_type = TUNER_XC5000,
  494. .tuner_addr = 0x64,
  495. .input = { {
  496. .type = CX23885_VMUX_TELEVISION,
  497. .vmux = CX25840_COMPOSITE1,
  498. } },
  499. },
  500. [CX23885_BOARD_MPX885] = {
  501. .name = "MPX-885",
  502. .porta = CX23885_ANALOG_VIDEO,
  503. .input = {{
  504. .type = CX23885_VMUX_COMPOSITE1,
  505. .vmux = CX25840_COMPOSITE1,
  506. .amux = CX25840_AUDIO6,
  507. .gpio0 = 0,
  508. }, {
  509. .type = CX23885_VMUX_COMPOSITE2,
  510. .vmux = CX25840_COMPOSITE2,
  511. .amux = CX25840_AUDIO6,
  512. .gpio0 = 0,
  513. }, {
  514. .type = CX23885_VMUX_COMPOSITE3,
  515. .vmux = CX25840_COMPOSITE3,
  516. .amux = CX25840_AUDIO7,
  517. .gpio0 = 0,
  518. }, {
  519. .type = CX23885_VMUX_COMPOSITE4,
  520. .vmux = CX25840_COMPOSITE4,
  521. .amux = CX25840_AUDIO7,
  522. .gpio0 = 0,
  523. } },
  524. },
  525. [CX23885_BOARD_MYGICA_X8507] = {
  526. .name = "Mygica X8507",
  527. .tuner_type = TUNER_XC5000,
  528. .tuner_addr = 0x61,
  529. .tuner_bus = 1,
  530. .porta = CX23885_ANALOG_VIDEO,
  531. .input = {
  532. {
  533. .type = CX23885_VMUX_TELEVISION,
  534. .vmux = CX25840_COMPOSITE2,
  535. .amux = CX25840_AUDIO8,
  536. },
  537. {
  538. .type = CX23885_VMUX_COMPOSITE1,
  539. .vmux = CX25840_COMPOSITE8,
  540. .amux = CX25840_AUDIO7,
  541. },
  542. {
  543. .type = CX23885_VMUX_SVIDEO,
  544. .vmux = CX25840_SVIDEO_LUMA3 |
  545. CX25840_SVIDEO_CHROMA4,
  546. .amux = CX25840_AUDIO7,
  547. },
  548. {
  549. .type = CX23885_VMUX_COMPONENT,
  550. .vmux = CX25840_COMPONENT_ON |
  551. CX25840_VIN1_CH1 |
  552. CX25840_VIN6_CH2 |
  553. CX25840_VIN7_CH3,
  554. .amux = CX25840_AUDIO7,
  555. },
  556. },
  557. },
  558. [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = {
  559. .name = "TerraTec Cinergy T PCIe Dual",
  560. .portb = CX23885_MPEG_DVB,
  561. .portc = CX23885_MPEG_DVB,
  562. },
  563. [CX23885_BOARD_TEVII_S471] = {
  564. .name = "TeVii S471",
  565. .portb = CX23885_MPEG_DVB,
  566. },
  567. [CX23885_BOARD_PROF_8000] = {
  568. .name = "Prof Revolution DVB-S2 8000",
  569. .portb = CX23885_MPEG_DVB,
  570. },
  571. [CX23885_BOARD_HAUPPAUGE_HVR4400] = {
  572. .name = "Hauppauge WinTV-HVR4400",
  573. .portb = CX23885_MPEG_DVB,
  574. },
  575. [CX23885_BOARD_AVERMEDIA_HC81R] = {
  576. .name = "AVerTV Hybrid Express Slim HC81R",
  577. .tuner_type = TUNER_XC2028,
  578. .tuner_addr = 0x61, /* 0xc2 >> 1 */
  579. .tuner_bus = 1,
  580. .porta = CX23885_ANALOG_VIDEO,
  581. .input = {{
  582. .type = CX23885_VMUX_TELEVISION,
  583. .vmux = CX25840_VIN2_CH1 |
  584. CX25840_VIN5_CH2 |
  585. CX25840_NONE0_CH3 |
  586. CX25840_NONE1_CH3,
  587. .amux = CX25840_AUDIO8,
  588. }, {
  589. .type = CX23885_VMUX_SVIDEO,
  590. .vmux = CX25840_VIN8_CH1 |
  591. CX25840_NONE_CH2 |
  592. CX25840_VIN7_CH3 |
  593. CX25840_SVIDEO_ON,
  594. .amux = CX25840_AUDIO6,
  595. }, {
  596. .type = CX23885_VMUX_COMPONENT,
  597. .vmux = CX25840_VIN1_CH1 |
  598. CX25840_NONE_CH2 |
  599. CX25840_NONE0_CH3 |
  600. CX25840_NONE1_CH3,
  601. .amux = CX25840_AUDIO6,
  602. } },
  603. }
  604. };
  605. const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
  606. /* ------------------------------------------------------------------ */
  607. /* PCI subsystem IDs */
  608. struct cx23885_subid cx23885_subids[] = {
  609. {
  610. .subvendor = 0x0070,
  611. .subdevice = 0x3400,
  612. .card = CX23885_BOARD_UNKNOWN,
  613. }, {
  614. .subvendor = 0x0070,
  615. .subdevice = 0x7600,
  616. .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
  617. }, {
  618. .subvendor = 0x0070,
  619. .subdevice = 0x7800,
  620. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  621. }, {
  622. .subvendor = 0x0070,
  623. .subdevice = 0x7801,
  624. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  625. }, {
  626. .subvendor = 0x0070,
  627. .subdevice = 0x7809,
  628. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  629. }, {
  630. .subvendor = 0x0070,
  631. .subdevice = 0x7911,
  632. .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
  633. }, {
  634. .subvendor = 0x18ac,
  635. .subdevice = 0xd500,
  636. .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
  637. }, {
  638. .subvendor = 0x0070,
  639. .subdevice = 0x7790,
  640. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  641. }, {
  642. .subvendor = 0x0070,
  643. .subdevice = 0x7797,
  644. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  645. }, {
  646. .subvendor = 0x0070,
  647. .subdevice = 0x7710,
  648. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  649. }, {
  650. .subvendor = 0x0070,
  651. .subdevice = 0x7717,
  652. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  653. }, {
  654. .subvendor = 0x0070,
  655. .subdevice = 0x71d1,
  656. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  657. }, {
  658. .subvendor = 0x0070,
  659. .subdevice = 0x71d3,
  660. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  661. }, {
  662. .subvendor = 0x0070,
  663. .subdevice = 0x8101,
  664. .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
  665. }, {
  666. .subvendor = 0x0070,
  667. .subdevice = 0x8010,
  668. .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
  669. }, {
  670. .subvendor = 0x18ac,
  671. .subdevice = 0xd618,
  672. .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
  673. }, {
  674. .subvendor = 0x18ac,
  675. .subdevice = 0xdb78,
  676. .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
  677. }, {
  678. .subvendor = 0x107d,
  679. .subdevice = 0x6681,
  680. .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
  681. }, {
  682. .subvendor = 0x107d,
  683. .subdevice = 0x6f39,
  684. .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
  685. }, {
  686. .subvendor = 0x185b,
  687. .subdevice = 0xe800,
  688. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
  689. }, {
  690. .subvendor = 0x6920,
  691. .subdevice = 0x8888,
  692. .card = CX23885_BOARD_TBS_6920,
  693. }, {
  694. .subvendor = 0xd470,
  695. .subdevice = 0x9022,
  696. .card = CX23885_BOARD_TEVII_S470,
  697. }, {
  698. .subvendor = 0x0001,
  699. .subdevice = 0x2005,
  700. .card = CX23885_BOARD_DVBWORLD_2005,
  701. }, {
  702. .subvendor = 0x1b55,
  703. .subdevice = 0x2a2c,
  704. .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
  705. }, {
  706. .subvendor = 0x0070,
  707. .subdevice = 0x2211,
  708. .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
  709. }, {
  710. .subvendor = 0x0070,
  711. .subdevice = 0x2215,
  712. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  713. }, {
  714. .subvendor = 0x0070,
  715. .subdevice = 0x221d,
  716. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  717. }, {
  718. .subvendor = 0x0070,
  719. .subdevice = 0x2251,
  720. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  721. }, {
  722. .subvendor = 0x0070,
  723. .subdevice = 0x2259,
  724. .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111,
  725. }, {
  726. .subvendor = 0x0070,
  727. .subdevice = 0x2291,
  728. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  729. }, {
  730. .subvendor = 0x0070,
  731. .subdevice = 0x2295,
  732. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  733. }, {
  734. .subvendor = 0x0070,
  735. .subdevice = 0x2299,
  736. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  737. }, {
  738. .subvendor = 0x0070,
  739. .subdevice = 0x229d,
  740. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  741. }, {
  742. .subvendor = 0x0070,
  743. .subdevice = 0x22f0,
  744. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  745. }, {
  746. .subvendor = 0x0070,
  747. .subdevice = 0x22f1,
  748. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  749. }, {
  750. .subvendor = 0x0070,
  751. .subdevice = 0x22f2,
  752. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  753. }, {
  754. .subvendor = 0x0070,
  755. .subdevice = 0x22f3,
  756. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  757. }, {
  758. .subvendor = 0x0070,
  759. .subdevice = 0x22f4,
  760. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  761. }, {
  762. .subvendor = 0x0070,
  763. .subdevice = 0x22f5,
  764. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  765. }, {
  766. .subvendor = 0x14f1,
  767. .subdevice = 0x8651,
  768. .card = CX23885_BOARD_MYGICA_X8506,
  769. }, {
  770. .subvendor = 0x14f1,
  771. .subdevice = 0x8657,
  772. .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
  773. }, {
  774. .subvendor = 0x0070,
  775. .subdevice = 0x8541,
  776. .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
  777. }, {
  778. .subvendor = 0x1858,
  779. .subdevice = 0xe800,
  780. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
  781. }, {
  782. .subvendor = 0x0070,
  783. .subdevice = 0x8551,
  784. .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
  785. }, {
  786. .subvendor = 0x14f1,
  787. .subdevice = 0x8578,
  788. .card = CX23885_BOARD_MYGICA_X8558PRO,
  789. }, {
  790. .subvendor = 0x107d,
  791. .subdevice = 0x6f22,
  792. .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
  793. }, {
  794. .subvendor = 0x5654,
  795. .subdevice = 0x2390,
  796. .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
  797. }, {
  798. .subvendor = 0x1b55,
  799. .subdevice = 0xe2e4,
  800. .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
  801. }, {
  802. .subvendor = 0x14f1,
  803. .subdevice = 0x8502,
  804. .card = CX23885_BOARD_MYGICA_X8507,
  805. }, {
  806. .subvendor = 0x153b,
  807. .subdevice = 0x117e,
  808. .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL,
  809. }, {
  810. .subvendor = 0xd471,
  811. .subdevice = 0x9022,
  812. .card = CX23885_BOARD_TEVII_S471,
  813. }, {
  814. .subvendor = 0x8000,
  815. .subdevice = 0x3034,
  816. .card = CX23885_BOARD_PROF_8000,
  817. }, {
  818. .subvendor = 0x0070,
  819. .subdevice = 0xc108,
  820. .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
  821. }, {
  822. .subvendor = 0x0070,
  823. .subdevice = 0xc138,
  824. .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
  825. }, {
  826. .subvendor = 0x0070,
  827. .subdevice = 0xc12a,
  828. .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
  829. }, {
  830. .subvendor = 0x0070,
  831. .subdevice = 0xc1f8,
  832. .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
  833. }, {
  834. .subvendor = 0x1461,
  835. .subdevice = 0xd939,
  836. .card = CX23885_BOARD_AVERMEDIA_HC81R,
  837. },
  838. };
  839. const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
  840. void cx23885_card_list(struct cx23885_dev *dev)
  841. {
  842. int i;
  843. if (0 == dev->pci->subsystem_vendor &&
  844. 0 == dev->pci->subsystem_device) {
  845. printk(KERN_INFO
  846. "%s: Board has no valid PCIe Subsystem ID and can't\n"
  847. "%s: be autodetected. Pass card=<n> insmod option\n"
  848. "%s: to workaround that. Redirect complaints to the\n"
  849. "%s: vendor of the TV card. Best regards,\n"
  850. "%s: -- tux\n",
  851. dev->name, dev->name, dev->name, dev->name, dev->name);
  852. } else {
  853. printk(KERN_INFO
  854. "%s: Your board isn't known (yet) to the driver.\n"
  855. "%s: Try to pick one of the existing card configs via\n"
  856. "%s: card=<n> insmod option. Updating to the latest\n"
  857. "%s: version might help as well.\n",
  858. dev->name, dev->name, dev->name, dev->name);
  859. }
  860. printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
  861. dev->name);
  862. for (i = 0; i < cx23885_bcount; i++)
  863. printk(KERN_INFO "%s: card=%d -> %s\n",
  864. dev->name, i, cx23885_boards[i].name);
  865. }
  866. static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
  867. {
  868. struct tveeprom tv;
  869. tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
  870. eeprom_data);
  871. /* Make sure we support the board model */
  872. switch (tv.model) {
  873. case 22001:
  874. /* WinTV-HVR1270 (PCIe, Retail, half height)
  875. * ATSC/QAM and basic analog, IR Blast */
  876. case 22009:
  877. /* WinTV-HVR1210 (PCIe, Retail, half height)
  878. * DVB-T and basic analog, IR Blast */
  879. case 22011:
  880. /* WinTV-HVR1270 (PCIe, Retail, half height)
  881. * ATSC/QAM and basic analog, IR Recv */
  882. case 22019:
  883. /* WinTV-HVR1210 (PCIe, Retail, half height)
  884. * DVB-T and basic analog, IR Recv */
  885. case 22021:
  886. /* WinTV-HVR1275 (PCIe, Retail, half height)
  887. * ATSC/QAM and basic analog, IR Recv */
  888. case 22029:
  889. /* WinTV-HVR1210 (PCIe, Retail, half height)
  890. * DVB-T and basic analog, IR Recv */
  891. case 22101:
  892. /* WinTV-HVR1270 (PCIe, Retail, full height)
  893. * ATSC/QAM and basic analog, IR Blast */
  894. case 22109:
  895. /* WinTV-HVR1210 (PCIe, Retail, full height)
  896. * DVB-T and basic analog, IR Blast */
  897. case 22111:
  898. /* WinTV-HVR1270 (PCIe, Retail, full height)
  899. * ATSC/QAM and basic analog, IR Recv */
  900. case 22119:
  901. /* WinTV-HVR1210 (PCIe, Retail, full height)
  902. * DVB-T and basic analog, IR Recv */
  903. case 22121:
  904. /* WinTV-HVR1275 (PCIe, Retail, full height)
  905. * ATSC/QAM and basic analog, IR Recv */
  906. case 22129:
  907. /* WinTV-HVR1210 (PCIe, Retail, full height)
  908. * DVB-T and basic analog, IR Recv */
  909. case 71009:
  910. /* WinTV-HVR1200 (PCIe, Retail, full height)
  911. * DVB-T and basic analog */
  912. case 71359:
  913. /* WinTV-HVR1200 (PCIe, OEM, half height)
  914. * DVB-T and basic analog */
  915. case 71439:
  916. /* WinTV-HVR1200 (PCIe, OEM, half height)
  917. * DVB-T and basic analog */
  918. case 71449:
  919. /* WinTV-HVR1200 (PCIe, OEM, full height)
  920. * DVB-T and basic analog */
  921. case 71939:
  922. /* WinTV-HVR1200 (PCIe, OEM, half height)
  923. * DVB-T and basic analog */
  924. case 71949:
  925. /* WinTV-HVR1200 (PCIe, OEM, full height)
  926. * DVB-T and basic analog */
  927. case 71959:
  928. /* WinTV-HVR1200 (PCIe, OEM, full height)
  929. * DVB-T and basic analog */
  930. case 71979:
  931. /* WinTV-HVR1200 (PCIe, OEM, half height)
  932. * DVB-T and basic analog */
  933. case 71999:
  934. /* WinTV-HVR1200 (PCIe, OEM, full height)
  935. * DVB-T and basic analog */
  936. case 76601:
  937. /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
  938. channel ATSC and MPEG2 HW Encoder */
  939. case 77001:
  940. /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
  941. and Basic analog */
  942. case 77011:
  943. /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
  944. and Basic analog */
  945. case 77041:
  946. /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
  947. and Basic analog */
  948. case 77051:
  949. /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
  950. and Basic analog */
  951. case 78011:
  952. /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
  953. Dual channel ATSC and MPEG2 HW Encoder */
  954. case 78501:
  955. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  956. Dual channel ATSC and MPEG2 HW Encoder */
  957. case 78521:
  958. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  959. Dual channel ATSC and MPEG2 HW Encoder */
  960. case 78531:
  961. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
  962. Dual channel ATSC and MPEG2 HW Encoder */
  963. case 78631:
  964. /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
  965. Dual channel ATSC and MPEG2 HW Encoder */
  966. case 79001:
  967. /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
  968. ATSC and Basic analog */
  969. case 79101:
  970. /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
  971. ATSC and Basic analog */
  972. case 79501:
  973. /* WinTV-HVR1250 (PCIe, No IR, half height,
  974. ATSC [at least] and Basic analog) */
  975. case 79561:
  976. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  977. ATSC and Basic analog */
  978. case 79571:
  979. /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
  980. ATSC and Basic analog */
  981. case 79671:
  982. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  983. ATSC and Basic analog */
  984. case 80019:
  985. /* WinTV-HVR1400 (Express Card, Retail, IR,
  986. * DVB-T and Basic analog */
  987. case 81509:
  988. /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
  989. * DVB-T and MPEG2 HW Encoder */
  990. case 81519:
  991. /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
  992. * DVB-T and MPEG2 HW Encoder */
  993. break;
  994. case 85021:
  995. /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
  996. Dual channel ATSC and MPEG2 HW Encoder */
  997. break;
  998. case 85721:
  999. /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
  1000. Dual channel ATSC and Basic analog */
  1001. break;
  1002. default:
  1003. printk(KERN_WARNING "%s: warning: "
  1004. "unknown hauppauge model #%d\n",
  1005. dev->name, tv.model);
  1006. break;
  1007. }
  1008. printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
  1009. dev->name, tv.model);
  1010. }
  1011. int cx23885_tuner_callback(void *priv, int component, int command, int arg)
  1012. {
  1013. struct cx23885_tsport *port = priv;
  1014. struct cx23885_dev *dev = port->dev;
  1015. u32 bitmask = 0;
  1016. if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH))
  1017. return 0;
  1018. if (command != 0) {
  1019. printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
  1020. __func__, command);
  1021. return -EINVAL;
  1022. }
  1023. switch (dev->board) {
  1024. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1025. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1026. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1027. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1028. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1029. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1030. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1031. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  1032. /* Tuner Reset Command */
  1033. bitmask = 0x04;
  1034. break;
  1035. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  1036. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1037. /* Two identical tuners on two different i2c buses,
  1038. * we need to reset the correct gpio. */
  1039. if (port->nr == 1)
  1040. bitmask = 0x01;
  1041. else if (port->nr == 2)
  1042. bitmask = 0x04;
  1043. break;
  1044. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1045. /* Tuner Reset Command */
  1046. bitmask = 0x02;
  1047. break;
  1048. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1049. altera_ci_tuner_reset(dev, port->nr);
  1050. break;
  1051. case CX23885_BOARD_AVERMEDIA_HC81R:
  1052. /* XC3028L Reset Command */
  1053. bitmask = 1 << 2;
  1054. break;
  1055. }
  1056. if (bitmask) {
  1057. /* Drive the tuner into reset and back out */
  1058. cx_clear(GP0_IO, bitmask);
  1059. mdelay(200);
  1060. cx_set(GP0_IO, bitmask);
  1061. }
  1062. return 0;
  1063. }
  1064. void cx23885_gpio_setup(struct cx23885_dev *dev)
  1065. {
  1066. switch (dev->board) {
  1067. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1068. /* GPIO-0 cx24227 demodulator reset */
  1069. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  1070. break;
  1071. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1072. /* GPIO-0 cx24227 demodulator */
  1073. /* GPIO-2 xc3028 tuner */
  1074. /* Put the parts into reset */
  1075. cx_set(GP0_IO, 0x00050000);
  1076. cx_clear(GP0_IO, 0x00000005);
  1077. msleep(5);
  1078. /* Bring the parts out of reset */
  1079. cx_set(GP0_IO, 0x00050005);
  1080. break;
  1081. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1082. /* GPIO-0 cx24227 demodulator reset */
  1083. /* GPIO-2 xc5000 tuner reset */
  1084. cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
  1085. break;
  1086. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1087. /* GPIO-0 656_CLK */
  1088. /* GPIO-1 656_D0 */
  1089. /* GPIO-2 8295A Reset */
  1090. /* GPIO-3-10 cx23417 data0-7 */
  1091. /* GPIO-11-14 cx23417 addr0-3 */
  1092. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  1093. /* GPIO-19 IR_RX */
  1094. /* CX23417 GPIO's */
  1095. /* EIO15 Zilog Reset */
  1096. /* EIO14 S5H1409/CX24227 Reset */
  1097. mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
  1098. /* Put the demod into reset and protect the eeprom */
  1099. mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
  1100. mdelay(100);
  1101. /* Bring the demod and blaster out of reset */
  1102. mc417_gpio_set(dev, GPIO_15 | GPIO_14);
  1103. mdelay(100);
  1104. /* Force the TDA8295A into reset and back */
  1105. cx23885_gpio_enable(dev, GPIO_2, 1);
  1106. cx23885_gpio_set(dev, GPIO_2);
  1107. mdelay(20);
  1108. cx23885_gpio_clear(dev, GPIO_2);
  1109. mdelay(20);
  1110. cx23885_gpio_set(dev, GPIO_2);
  1111. mdelay(20);
  1112. break;
  1113. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1114. /* GPIO-0 tda10048 demodulator reset */
  1115. /* GPIO-2 tda18271 tuner reset */
  1116. /* Put the parts into reset and back */
  1117. cx_set(GP0_IO, 0x00050000);
  1118. mdelay(20);
  1119. cx_clear(GP0_IO, 0x00000005);
  1120. mdelay(20);
  1121. cx_set(GP0_IO, 0x00050005);
  1122. break;
  1123. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1124. /* GPIO-0 TDA10048 demodulator reset */
  1125. /* GPIO-2 TDA8295A Reset */
  1126. /* GPIO-3-10 cx23417 data0-7 */
  1127. /* GPIO-11-14 cx23417 addr0-3 */
  1128. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  1129. /* The following GPIO's are on the interna AVCore (cx25840) */
  1130. /* GPIO-19 IR_RX */
  1131. /* GPIO-20 IR_TX 416/DVBT Select */
  1132. /* GPIO-21 IIS DAT */
  1133. /* GPIO-22 IIS WCLK */
  1134. /* GPIO-23 IIS BCLK */
  1135. /* Put the parts into reset and back */
  1136. cx_set(GP0_IO, 0x00050000);
  1137. mdelay(20);
  1138. cx_clear(GP0_IO, 0x00000005);
  1139. mdelay(20);
  1140. cx_set(GP0_IO, 0x00050005);
  1141. break;
  1142. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1143. /* GPIO-0 Dibcom7000p demodulator reset */
  1144. /* GPIO-2 xc3028L tuner reset */
  1145. /* GPIO-13 LED */
  1146. /* Put the parts into reset and back */
  1147. cx_set(GP0_IO, 0x00050000);
  1148. mdelay(20);
  1149. cx_clear(GP0_IO, 0x00000005);
  1150. mdelay(20);
  1151. cx_set(GP0_IO, 0x00050005);
  1152. break;
  1153. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  1154. /* GPIO-0 xc5000 tuner reset i2c bus 0 */
  1155. /* GPIO-1 s5h1409 demod reset i2c bus 0 */
  1156. /* GPIO-2 xc5000 tuner reset i2c bus 1 */
  1157. /* GPIO-3 s5h1409 demod reset i2c bus 0 */
  1158. /* Put the parts into reset and back */
  1159. cx_set(GP0_IO, 0x000f0000);
  1160. mdelay(20);
  1161. cx_clear(GP0_IO, 0x0000000f);
  1162. mdelay(20);
  1163. cx_set(GP0_IO, 0x000f000f);
  1164. break;
  1165. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1166. /* GPIO-0 portb xc3028 reset */
  1167. /* GPIO-1 portb zl10353 reset */
  1168. /* GPIO-2 portc xc3028 reset */
  1169. /* GPIO-3 portc zl10353 reset */
  1170. /* Put the parts into reset and back */
  1171. cx_set(GP0_IO, 0x000f0000);
  1172. mdelay(20);
  1173. cx_clear(GP0_IO, 0x0000000f);
  1174. mdelay(20);
  1175. cx_set(GP0_IO, 0x000f000f);
  1176. break;
  1177. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1178. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1179. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1180. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1181. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  1182. /* GPIO-2 xc3028 tuner reset */
  1183. /* The following GPIO's are on the internal AVCore (cx25840) */
  1184. /* GPIO-? zl10353 demod reset */
  1185. /* Put the parts into reset and back */
  1186. cx_set(GP0_IO, 0x00040000);
  1187. mdelay(20);
  1188. cx_clear(GP0_IO, 0x00000004);
  1189. mdelay(20);
  1190. cx_set(GP0_IO, 0x00040004);
  1191. break;
  1192. case CX23885_BOARD_TBS_6920:
  1193. case CX23885_BOARD_PROF_8000:
  1194. cx_write(MC417_CTL, 0x00000036);
  1195. cx_write(MC417_OEN, 0x00001000);
  1196. cx_set(MC417_RWD, 0x00000002);
  1197. mdelay(200);
  1198. cx_clear(MC417_RWD, 0x00000800);
  1199. mdelay(200);
  1200. cx_set(MC417_RWD, 0x00000800);
  1201. mdelay(200);
  1202. break;
  1203. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1204. /* GPIO-0 INTA from CiMax1
  1205. GPIO-1 INTB from CiMax2
  1206. GPIO-2 reset chips
  1207. GPIO-3 to GPIO-10 data/addr for CA
  1208. GPIO-11 ~CS0 to CiMax1
  1209. GPIO-12 ~CS1 to CiMax2
  1210. GPIO-13 ADL0 load LSB addr
  1211. GPIO-14 ADL1 load MSB addr
  1212. GPIO-15 ~RDY from CiMax
  1213. GPIO-17 ~RD to CiMax
  1214. GPIO-18 ~WR to CiMax
  1215. */
  1216. cx_set(GP0_IO, 0x00040000); /* GPIO as out */
  1217. /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
  1218. cx_clear(GP0_IO, 0x00030004);
  1219. mdelay(100);/* reset delay */
  1220. cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
  1221. cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
  1222. /* GPIO-15 IN as ~ACK, rest as OUT */
  1223. cx_write(MC417_OEN, 0x00001000);
  1224. /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
  1225. cx_write(MC417_RWD, 0x0000c300);
  1226. /* enable irq */
  1227. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  1228. break;
  1229. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1230. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1231. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1232. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  1233. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1234. /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
  1235. /* GPIO-6 I2C Gate which can isolate the demod from the bus */
  1236. /* GPIO-9 Demod reset */
  1237. /* Put the parts into reset and back */
  1238. cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
  1239. cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
  1240. cx23885_gpio_clear(dev, GPIO_9);
  1241. mdelay(20);
  1242. cx23885_gpio_set(dev, GPIO_9);
  1243. break;
  1244. case CX23885_BOARD_MYGICA_X8506:
  1245. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1246. case CX23885_BOARD_MYGICA_X8507:
  1247. /* GPIO-0 (0)Analog / (1)Digital TV */
  1248. /* GPIO-1 reset XC5000 */
  1249. /* GPIO-2 reset LGS8GL5 / LGS8G75 */
  1250. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
  1251. cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
  1252. mdelay(100);
  1253. cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
  1254. mdelay(100);
  1255. break;
  1256. case CX23885_BOARD_MYGICA_X8558PRO:
  1257. /* GPIO-0 reset first ATBM8830 */
  1258. /* GPIO-1 reset second ATBM8830 */
  1259. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
  1260. cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
  1261. mdelay(100);
  1262. cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
  1263. mdelay(100);
  1264. break;
  1265. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1266. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1267. /* GPIO-0 656_CLK */
  1268. /* GPIO-1 656_D0 */
  1269. /* GPIO-2 Wake# */
  1270. /* GPIO-3-10 cx23417 data0-7 */
  1271. /* GPIO-11-14 cx23417 addr0-3 */
  1272. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  1273. /* GPIO-19 IR_RX */
  1274. /* GPIO-20 C_IR_TX */
  1275. /* GPIO-21 I2S DAT */
  1276. /* GPIO-22 I2S WCLK */
  1277. /* GPIO-23 I2S BCLK */
  1278. /* ALT GPIO: EXP GPIO LATCH */
  1279. /* CX23417 GPIO's */
  1280. /* GPIO-14 S5H1411/CX24228 Reset */
  1281. /* GPIO-13 EEPROM write protect */
  1282. mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
  1283. /* Put the demod into reset and protect the eeprom */
  1284. mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
  1285. mdelay(100);
  1286. /* Bring the demod out of reset */
  1287. mc417_gpio_set(dev, GPIO_14);
  1288. mdelay(100);
  1289. /* CX24228 GPIO */
  1290. /* Connected to IF / Mux */
  1291. break;
  1292. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1293. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  1294. break;
  1295. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1296. /* GPIO-0 ~INT in
  1297. GPIO-1 TMS out
  1298. GPIO-2 ~reset chips out
  1299. GPIO-3 to GPIO-10 data/addr for CA in/out
  1300. GPIO-11 ~CS out
  1301. GPIO-12 ADDR out
  1302. GPIO-13 ~WR out
  1303. GPIO-14 ~RD out
  1304. GPIO-15 ~RDY in
  1305. GPIO-16 TCK out
  1306. GPIO-17 TDO in
  1307. GPIO-18 TDI out
  1308. */
  1309. cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
  1310. /* GPIO-0 as INT, reset & TMS low */
  1311. cx_clear(GP0_IO, 0x00010006);
  1312. mdelay(100);/* reset delay */
  1313. cx_set(GP0_IO, 0x00000004); /* reset high */
  1314. cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
  1315. /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
  1316. cx_write(MC417_OEN, 0x00005000);
  1317. /* ~RD, ~WR high; ADDR low; ~CS high */
  1318. cx_write(MC417_RWD, 0x00000d00);
  1319. /* enable irq */
  1320. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  1321. break;
  1322. case CX23885_BOARD_HAUPPAUGE_HVR4400:
  1323. /* GPIO-8 tda10071 demod reset */
  1324. /* Put the parts into reset and back */
  1325. cx23885_gpio_enable(dev, GPIO_8, 1);
  1326. cx23885_gpio_clear(dev, GPIO_8);
  1327. mdelay(100);
  1328. cx23885_gpio_set(dev, GPIO_8);
  1329. mdelay(100);
  1330. break;
  1331. case CX23885_BOARD_AVERMEDIA_HC81R:
  1332. cx_clear(MC417_CTL, 1);
  1333. /* GPIO-0,1,2 setup direction as output */
  1334. cx_set(GP0_IO, 0x00070000);
  1335. mdelay(10);
  1336. /* AF9013 demod reset */
  1337. cx_set(GP0_IO, 0x00010001);
  1338. mdelay(10);
  1339. cx_clear(GP0_IO, 0x00010001);
  1340. mdelay(10);
  1341. cx_set(GP0_IO, 0x00010001);
  1342. mdelay(10);
  1343. /* demod tune? */
  1344. cx_clear(GP0_IO, 0x00030003);
  1345. mdelay(10);
  1346. cx_set(GP0_IO, 0x00020002);
  1347. mdelay(10);
  1348. cx_set(GP0_IO, 0x00010001);
  1349. mdelay(10);
  1350. cx_clear(GP0_IO, 0x00020002);
  1351. /* XC3028L tuner reset */
  1352. cx_set(GP0_IO, 0x00040004);
  1353. cx_clear(GP0_IO, 0x00040004);
  1354. cx_set(GP0_IO, 0x00040004);
  1355. mdelay(60);
  1356. break;
  1357. }
  1358. }
  1359. int cx23885_ir_init(struct cx23885_dev *dev)
  1360. {
  1361. static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
  1362. {
  1363. .flags = V4L2_SUBDEV_IO_PIN_INPUT,
  1364. .pin = CX23885_PIN_IR_RX_GPIO19,
  1365. .function = CX23885_PAD_IR_RX,
  1366. .value = 0,
  1367. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1368. }, {
  1369. .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
  1370. .pin = CX23885_PIN_IR_TX_GPIO20,
  1371. .function = CX23885_PAD_IR_TX,
  1372. .value = 0,
  1373. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1374. }
  1375. };
  1376. const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
  1377. static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
  1378. {
  1379. .flags = V4L2_SUBDEV_IO_PIN_INPUT,
  1380. .pin = CX23885_PIN_IR_RX_GPIO19,
  1381. .function = CX23885_PAD_IR_RX,
  1382. .value = 0,
  1383. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1384. }
  1385. };
  1386. const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
  1387. struct v4l2_subdev_ir_parameters params;
  1388. int ret = 0;
  1389. switch (dev->board) {
  1390. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1391. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1392. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1393. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1394. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1395. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1396. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1397. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  1398. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1399. /* FIXME: Implement me */
  1400. break;
  1401. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1402. ret = cx23888_ir_probe(dev);
  1403. if (ret)
  1404. break;
  1405. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
  1406. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1407. ir_rx_pin_cfg_count, ir_rx_pin_cfg);
  1408. break;
  1409. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1410. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1411. ret = cx23888_ir_probe(dev);
  1412. if (ret)
  1413. break;
  1414. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
  1415. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1416. ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
  1417. /*
  1418. * For these boards we need to invert the Tx output via the
  1419. * IR controller to have the LED off while idle
  1420. */
  1421. v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
  1422. params.enable = false;
  1423. params.shutdown = false;
  1424. params.invert_level = true;
  1425. v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
  1426. params.shutdown = true;
  1427. v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
  1428. break;
  1429. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1430. case CX23885_BOARD_TEVII_S470:
  1431. case CX23885_BOARD_MYGICA_X8507:
  1432. if (!enable_885_ir)
  1433. break;
  1434. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
  1435. if (dev->sd_ir == NULL) {
  1436. ret = -ENODEV;
  1437. break;
  1438. }
  1439. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1440. ir_rx_pin_cfg_count, ir_rx_pin_cfg);
  1441. break;
  1442. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1443. if (!enable_885_ir)
  1444. break;
  1445. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
  1446. if (dev->sd_ir == NULL) {
  1447. ret = -ENODEV;
  1448. break;
  1449. }
  1450. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1451. ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
  1452. break;
  1453. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1454. request_module("ir-kbd-i2c");
  1455. break;
  1456. }
  1457. return ret;
  1458. }
  1459. void cx23885_ir_fini(struct cx23885_dev *dev)
  1460. {
  1461. switch (dev->board) {
  1462. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1463. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1464. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1465. cx23885_irq_remove(dev, PCI_MSK_IR);
  1466. cx23888_ir_remove(dev);
  1467. dev->sd_ir = NULL;
  1468. break;
  1469. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1470. case CX23885_BOARD_TEVII_S470:
  1471. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1472. case CX23885_BOARD_MYGICA_X8507:
  1473. cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
  1474. /* sd_ir is a duplicate pointer to the AV Core, just clear it */
  1475. dev->sd_ir = NULL;
  1476. break;
  1477. }
  1478. }
  1479. static int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
  1480. {
  1481. int data;
  1482. int tdo = 0;
  1483. struct cx23885_dev *dev = (struct cx23885_dev *)device;
  1484. /*TMS*/
  1485. data = ((cx_read(GP0_IO)) & (~0x00000002));
  1486. data |= (tms ? 0x00020002 : 0x00020000);
  1487. cx_write(GP0_IO, data);
  1488. /*TDI*/
  1489. data = ((cx_read(MC417_RWD)) & (~0x0000a000));
  1490. data |= (tdi ? 0x00008000 : 0);
  1491. cx_write(MC417_RWD, data);
  1492. if (read_tdo)
  1493. tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
  1494. cx_write(MC417_RWD, data | 0x00002000);
  1495. udelay(1);
  1496. /*TCK*/
  1497. cx_write(MC417_RWD, data);
  1498. return tdo;
  1499. }
  1500. void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
  1501. {
  1502. switch (dev->board) {
  1503. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1504. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1505. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1506. if (dev->sd_ir)
  1507. cx23885_irq_add_enable(dev, PCI_MSK_IR);
  1508. break;
  1509. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1510. case CX23885_BOARD_TEVII_S470:
  1511. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1512. case CX23885_BOARD_MYGICA_X8507:
  1513. if (dev->sd_ir)
  1514. cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
  1515. break;
  1516. }
  1517. }
  1518. void cx23885_card_setup(struct cx23885_dev *dev)
  1519. {
  1520. struct cx23885_tsport *ts1 = &dev->ts1;
  1521. struct cx23885_tsport *ts2 = &dev->ts2;
  1522. static u8 eeprom[256];
  1523. if (dev->i2c_bus[0].i2c_rc == 0) {
  1524. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  1525. tveeprom_read(&dev->i2c_bus[0].i2c_client,
  1526. eeprom, sizeof(eeprom));
  1527. }
  1528. switch (dev->board) {
  1529. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1530. if (dev->i2c_bus[0].i2c_rc == 0) {
  1531. if (eeprom[0x80] != 0x84)
  1532. hauppauge_eeprom(dev, eeprom+0xc0);
  1533. else
  1534. hauppauge_eeprom(dev, eeprom+0x80);
  1535. }
  1536. break;
  1537. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1538. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1539. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1540. if (dev->i2c_bus[0].i2c_rc == 0)
  1541. hauppauge_eeprom(dev, eeprom+0x80);
  1542. break;
  1543. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1544. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1545. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1546. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1547. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1548. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1549. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1550. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  1551. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1552. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1553. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1554. case CX23885_BOARD_HAUPPAUGE_HVR4400:
  1555. if (dev->i2c_bus[0].i2c_rc == 0)
  1556. hauppauge_eeprom(dev, eeprom+0xc0);
  1557. break;
  1558. }
  1559. switch (dev->board) {
  1560. case CX23885_BOARD_AVERMEDIA_HC81R:
  1561. /* Defaults for VID B */
  1562. ts1->gen_ctrl_val = 0x4; /* Parallel */
  1563. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1564. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1565. /* Defaults for VID C */
  1566. /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
  1567. ts2->gen_ctrl_val = 0x10e;
  1568. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1569. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1570. break;
  1571. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  1572. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1573. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1574. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1575. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1576. /* break omitted intentionally */
  1577. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  1578. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1579. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1580. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1581. break;
  1582. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1583. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1584. /* Defaults for VID B - Analog encoder */
  1585. /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
  1586. ts1->gen_ctrl_val = 0x10e;
  1587. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1588. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1589. /* APB_TSVALERR_POL (active low)*/
  1590. ts1->vld_misc_val = 0x2000;
  1591. ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
  1592. cx_write(0x130184, 0xc);
  1593. /* Defaults for VID C */
  1594. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1595. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1596. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1597. break;
  1598. case CX23885_BOARD_TBS_6920:
  1599. ts1->gen_ctrl_val = 0x4; /* Parallel */
  1600. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1601. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1602. break;
  1603. case CX23885_BOARD_TEVII_S470:
  1604. case CX23885_BOARD_TEVII_S471:
  1605. case CX23885_BOARD_DVBWORLD_2005:
  1606. case CX23885_BOARD_PROF_8000:
  1607. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1608. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1609. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1610. break;
  1611. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1612. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1613. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1614. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1615. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1616. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1617. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1618. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1619. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1620. break;
  1621. case CX23885_BOARD_MYGICA_X8506:
  1622. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1623. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1624. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1625. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1626. break;
  1627. case CX23885_BOARD_MYGICA_X8558PRO:
  1628. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1629. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1630. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1631. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1632. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1633. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1634. break;
  1635. case CX23885_BOARD_HAUPPAUGE_HVR4400:
  1636. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1637. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1638. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1639. break;
  1640. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1641. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1642. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1643. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1644. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1645. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1646. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1647. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1648. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1649. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1650. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1651. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1652. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1653. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  1654. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1655. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1656. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1657. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1658. default:
  1659. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1660. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1661. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1662. }
  1663. /* Certain boards support analog, or require the avcore to be
  1664. * loaded, ensure this happens.
  1665. */
  1666. switch (dev->board) {
  1667. case CX23885_BOARD_TEVII_S470:
  1668. /* Currently only enabled for the integrated IR controller */
  1669. if (!enable_885_ir)
  1670. break;
  1671. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1672. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1673. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1674. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1675. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1676. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1677. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1678. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1679. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1680. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1681. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1682. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  1683. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1684. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1685. case CX23885_BOARD_MYGICA_X8506:
  1686. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1687. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1688. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  1689. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1690. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1691. case CX23885_BOARD_MPX885:
  1692. case CX23885_BOARD_MYGICA_X8507:
  1693. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1694. case CX23885_BOARD_AVERMEDIA_HC81R:
  1695. dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
  1696. &dev->i2c_bus[2].i2c_adap,
  1697. "cx25840", 0x88 >> 1, NULL);
  1698. if (dev->sd_cx25840) {
  1699. dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
  1700. v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
  1701. }
  1702. break;
  1703. }
  1704. /* AUX-PLL 27MHz CLK */
  1705. switch (dev->board) {
  1706. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1707. netup_initialize(dev);
  1708. break;
  1709. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
  1710. int ret;
  1711. const struct firmware *fw;
  1712. const char *filename = "dvb-netup-altera-01.fw";
  1713. char *action = "configure";
  1714. static struct netup_card_info cinfo;
  1715. struct altera_config netup_config = {
  1716. .dev = dev,
  1717. .action = action,
  1718. .jtag_io = netup_jtag_io,
  1719. };
  1720. netup_initialize(dev);
  1721. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  1722. if (netup_card_rev)
  1723. cinfo.rev = netup_card_rev;
  1724. switch (cinfo.rev) {
  1725. case 0x4:
  1726. filename = "dvb-netup-altera-04.fw";
  1727. break;
  1728. default:
  1729. filename = "dvb-netup-altera-01.fw";
  1730. break;
  1731. }
  1732. printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n",
  1733. cinfo.rev, filename);
  1734. ret = request_firmware(&fw, filename, &dev->pci->dev);
  1735. if (ret != 0)
  1736. printk(KERN_ERR "did not find the firmware file. (%s) "
  1737. "Please see linux/Documentation/dvb/ for more details "
  1738. "on firmware-problems.", filename);
  1739. else
  1740. altera_init(&netup_config, fw);
  1741. release_firmware(fw);
  1742. break;
  1743. }
  1744. }
  1745. }
  1746. /* ------------------------------------------------------------------ */