clk-div.c 2.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110
  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/clk-provider.h>
  13. #include <linux/err.h>
  14. #include <linux/slab.h>
  15. #include "clk.h"
  16. /**
  17. * struct clk_div - mxs integer divider clock
  18. * @divider: the parent class
  19. * @ops: pointer to clk_ops of parent class
  20. * @reg: register address
  21. * @busy: busy bit shift
  22. *
  23. * The mxs divider clock is a subclass of basic clk_divider with an
  24. * addtional busy bit.
  25. */
  26. struct clk_div {
  27. struct clk_divider divider;
  28. const struct clk_ops *ops;
  29. void __iomem *reg;
  30. u8 busy;
  31. };
  32. static inline struct clk_div *to_clk_div(struct clk_hw *hw)
  33. {
  34. struct clk_divider *divider = container_of(hw, struct clk_divider, hw);
  35. return container_of(divider, struct clk_div, divider);
  36. }
  37. static unsigned long clk_div_recalc_rate(struct clk_hw *hw,
  38. unsigned long parent_rate)
  39. {
  40. struct clk_div *div = to_clk_div(hw);
  41. return div->ops->recalc_rate(&div->divider.hw, parent_rate);
  42. }
  43. static long clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
  44. unsigned long *prate)
  45. {
  46. struct clk_div *div = to_clk_div(hw);
  47. return div->ops->round_rate(&div->divider.hw, rate, prate);
  48. }
  49. static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
  50. unsigned long parent_rate)
  51. {
  52. struct clk_div *div = to_clk_div(hw);
  53. int ret;
  54. ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate);
  55. if (!ret)
  56. ret = mxs_clk_wait(div->reg, div->busy);
  57. return ret;
  58. }
  59. static struct clk_ops clk_div_ops = {
  60. .recalc_rate = clk_div_recalc_rate,
  61. .round_rate = clk_div_round_rate,
  62. .set_rate = clk_div_set_rate,
  63. };
  64. struct clk *mxs_clk_div(const char *name, const char *parent_name,
  65. void __iomem *reg, u8 shift, u8 width, u8 busy)
  66. {
  67. struct clk_div *div;
  68. struct clk *clk;
  69. struct clk_init_data init;
  70. div = kzalloc(sizeof(*div), GFP_KERNEL);
  71. if (!div)
  72. return ERR_PTR(-ENOMEM);
  73. init.name = name;
  74. init.ops = &clk_div_ops;
  75. init.flags = CLK_SET_RATE_PARENT;
  76. init.parent_names = (parent_name ? &parent_name: NULL);
  77. init.num_parents = (parent_name ? 1 : 0);
  78. div->reg = reg;
  79. div->busy = busy;
  80. div->divider.reg = reg;
  81. div->divider.shift = shift;
  82. div->divider.width = width;
  83. div->divider.flags = CLK_DIVIDER_ONE_BASED;
  84. div->divider.lock = &mxs_lock;
  85. div->divider.hw.init = &init;
  86. div->ops = &clk_divider_ops;
  87. clk = clk_register(NULL, &div->divider.hw);
  88. if (IS_ERR(clk))
  89. kfree(div);
  90. return clk;
  91. }