hardware.h 1.9 KB

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  1. /*
  2. * arch/xtensa/platform/xtavnet/include/platform/hardware.h
  3. *
  4. * This file is subject to the terms and conditions of the GNU General Public
  5. * License. See the file "COPYING" in the main directory of this archive
  6. * for more details.
  7. *
  8. * Copyright (C) 2006 Tensilica Inc.
  9. */
  10. /*
  11. * This file contains the hardware configuration of the XTAVNET boards.
  12. */
  13. #ifndef __XTENSA_XTAVNET_HARDWARE_H
  14. #define __XTENSA_XTAVNET_HARDWARE_H
  15. /* By default NO_IRQ is defined to 0 in Linux, but we use the
  16. interrupt 0 for UART... */
  17. #define NO_IRQ -1
  18. /* Memory configuration. */
  19. #define PLATFORM_DEFAULT_MEM_START 0x00000000
  20. #define PLATFORM_DEFAULT_MEM_SIZE 0x04000000
  21. /* Interrupt configuration. */
  22. #define PLATFORM_NR_IRQS 10
  23. /* Default assignment of LX60 devices to external interrupts. */
  24. #ifdef CONFIG_ARCH_HAS_SMP
  25. #define DUART16552_INTNUM XCHAL_EXTINT3_NUM
  26. #define OETH_IRQ XCHAL_EXTINT4_NUM
  27. #else
  28. #define DUART16552_INTNUM XCHAL_EXTINT0_NUM
  29. #define OETH_IRQ XCHAL_EXTINT1_NUM
  30. #endif
  31. /*
  32. * Device addresses and parameters.
  33. */
  34. /* UART */
  35. #define DUART16552_PADDR (XCHAL_KIO_PADDR + 0x0D050020)
  36. /* LCD instruction and data addresses. */
  37. #define LCD_INSTR_ADDR ((char *)IOADDR(0x0D040000))
  38. #define LCD_DATA_ADDR ((char *)IOADDR(0x0D040004))
  39. /* Misc. */
  40. #define XTFPGA_FPGAREGS_VADDR IOADDR(0x0D020000)
  41. /* Clock frequency in Hz (read-only): */
  42. #define XTFPGA_CLKFRQ_VADDR (XTFPGA_FPGAREGS_VADDR + 0x04)
  43. /* Setting of 8 DIP switches: */
  44. #define DIP_SWITCHES_VADDR (XTFPGA_FPGAREGS_VADDR + 0x0C)
  45. /* Software reset (write 0xdead): */
  46. #define XTFPGA_SWRST_VADDR (XTFPGA_FPGAREGS_VADDR + 0x10)
  47. /* OpenCores Ethernet controller: */
  48. /* regs + RX/TX descriptors */
  49. #define OETH_REGS_PADDR (XCHAL_KIO_PADDR + 0x0D030000)
  50. #define OETH_REGS_SIZE 0x1000
  51. #define OETH_SRAMBUFF_PADDR (XCHAL_KIO_PADDR + 0x0D800000)
  52. /* 5*rx buffs + 5*tx buffs */
  53. #define OETH_SRAMBUFF_SIZE (5 * 0x600 + 5 * 0x600)
  54. #endif /* __XTENSA_XTAVNET_HARDWARE_H */