qoriq-sec4.2-0.dtsi 3.5 KB

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  1. /*
  2. * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
  3. *
  4. * Copyright 2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. crypto: crypto@300000 {
  35. compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
  36. #address-cells = <1>;
  37. #size-cells = <1>;
  38. reg = <0x300000 0x10000>;
  39. ranges = <0 0x300000 0x10000>;
  40. interrupts = <92 2 0 0>;
  41. sec_jr0: jr@1000 {
  42. compatible = "fsl,sec-v4.2-job-ring",
  43. "fsl,sec-v4.0-job-ring";
  44. reg = <0x1000 0x1000>;
  45. interrupts = <88 2 0 0>;
  46. };
  47. sec_jr1: jr@2000 {
  48. compatible = "fsl,sec-v4.2-job-ring",
  49. "fsl,sec-v4.0-job-ring";
  50. reg = <0x2000 0x1000>;
  51. interrupts = <89 2 0 0>;
  52. };
  53. sec_jr2: jr@3000 {
  54. compatible = "fsl,sec-v4.2-job-ring",
  55. "fsl,sec-v4.0-job-ring";
  56. reg = <0x3000 0x1000>;
  57. interrupts = <90 2 0 0>;
  58. };
  59. sec_jr3: jr@4000 {
  60. compatible = "fsl,sec-v4.2-job-ring",
  61. "fsl,sec-v4.0-job-ring";
  62. reg = <0x4000 0x1000>;
  63. interrupts = <91 2 0 0>;
  64. };
  65. rtic@6000 {
  66. compatible = "fsl,sec-v4.2-rtic",
  67. "fsl,sec-v4.0-rtic";
  68. #address-cells = <1>;
  69. #size-cells = <1>;
  70. reg = <0x6000 0x100>;
  71. ranges = <0x0 0x6100 0xe00>;
  72. rtic_a: rtic-a@0 {
  73. compatible = "fsl,sec-v4.2-rtic-memory",
  74. "fsl,sec-v4.0-rtic-memory";
  75. reg = <0x00 0x20 0x100 0x80>;
  76. };
  77. rtic_b: rtic-b@20 {
  78. compatible = "fsl,sec-v4.2-rtic-memory",
  79. "fsl,sec-v4.0-rtic-memory";
  80. reg = <0x20 0x20 0x200 0x80>;
  81. };
  82. rtic_c: rtic-c@40 {
  83. compatible = "fsl,sec-v4.2-rtic-memory",
  84. "fsl,sec-v4.0-rtic-memory";
  85. reg = <0x40 0x20 0x300 0x80>;
  86. };
  87. rtic_d: rtic-d@60 {
  88. compatible = "fsl,sec-v4.2-rtic-memory",
  89. "fsl,sec-v4.0-rtic-memory";
  90. reg = <0x60 0x20 0x500 0x80>;
  91. };
  92. };
  93. };
  94. sec_mon: sec_mon@314000 {
  95. compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
  96. reg = <0x314000 0x1000>;
  97. interrupts = <93 2 0 0>;
  98. };