p5040si-post.dtsi 9.7 KB

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  1. /*
  2. * P5040 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2012 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * This software is provided by Freescale Semiconductor "as is" and any
  24. * express or implied warranties, including, but not limited to, the implied
  25. * warranties of merchantability and fitness for a particular purpose are
  26. * disclaimed. In no event shall Freescale Semiconductor be liable for any
  27. * direct, indirect, incidental, special, exemplary, or consequential damages
  28. * (including, but not limited to, procurement of substitute goods or services;
  29. * loss of use, data, or profits; or business interruption) however caused and
  30. * on any theory of liability, whether in contract, strict liability, or tort
  31. * (including negligence or otherwise) arising in any way out of the use of this
  32. * software, even if advised of the possibility of such damage.
  33. */
  34. &lbc {
  35. compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
  36. interrupts = <25 2 0 0>;
  37. #address-cells = <2>;
  38. #size-cells = <1>;
  39. };
  40. /* controller at 0x200000 */
  41. &pci0 {
  42. compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
  43. device_type = "pci";
  44. #size-cells = <2>;
  45. #address-cells = <3>;
  46. bus-range = <0x0 0xff>;
  47. clock-frequency = <33333333>;
  48. interrupts = <16 2 1 15>;
  49. fsl,iommu-parent = <&pamu0>;
  50. pcie@0 {
  51. reg = <0 0 0 0 0>;
  52. #interrupt-cells = <1>;
  53. #size-cells = <2>;
  54. #address-cells = <3>;
  55. device_type = "pci";
  56. interrupts = <16 2 1 15>;
  57. interrupt-map-mask = <0xf800 0 0 7>;
  58. interrupt-map = <
  59. /* IDSEL 0x0 */
  60. 0000 0 0 1 &mpic 40 1 0 0
  61. 0000 0 0 2 &mpic 1 1 0 0
  62. 0000 0 0 3 &mpic 2 1 0 0
  63. 0000 0 0 4 &mpic 3 1 0 0
  64. >;
  65. };
  66. };
  67. /* controller at 0x201000 */
  68. &pci1 {
  69. compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
  70. device_type = "pci";
  71. #size-cells = <2>;
  72. #address-cells = <3>;
  73. bus-range = <0 0xff>;
  74. clock-frequency = <33333333>;
  75. interrupts = <16 2 1 14>;
  76. fsl,iommu-parent = <&pamu0>;
  77. pcie@0 {
  78. reg = <0 0 0 0 0>;
  79. #interrupt-cells = <1>;
  80. #size-cells = <2>;
  81. #address-cells = <3>;
  82. device_type = "pci";
  83. interrupts = <16 2 1 14>;
  84. interrupt-map-mask = <0xf800 0 0 7>;
  85. interrupt-map = <
  86. /* IDSEL 0x0 */
  87. 0000 0 0 1 &mpic 41 1 0 0
  88. 0000 0 0 2 &mpic 5 1 0 0
  89. 0000 0 0 3 &mpic 6 1 0 0
  90. 0000 0 0 4 &mpic 7 1 0 0
  91. >;
  92. };
  93. };
  94. /* controller at 0x202000 */
  95. &pci2 {
  96. compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
  97. device_type = "pci";
  98. #size-cells = <2>;
  99. #address-cells = <3>;
  100. bus-range = <0x0 0xff>;
  101. clock-frequency = <33333333>;
  102. interrupts = <16 2 1 13>;
  103. fsl,iommu-parent = <&pamu0>;
  104. pcie@0 {
  105. reg = <0 0 0 0 0>;
  106. #interrupt-cells = <1>;
  107. #size-cells = <2>;
  108. #address-cells = <3>;
  109. device_type = "pci";
  110. interrupts = <16 2 1 13>;
  111. interrupt-map-mask = <0xf800 0 0 7>;
  112. interrupt-map = <
  113. /* IDSEL 0x0 */
  114. 0000 0 0 1 &mpic 42 1 0 0
  115. 0000 0 0 2 &mpic 9 1 0 0
  116. 0000 0 0 3 &mpic 10 1 0 0
  117. 0000 0 0 4 &mpic 11 1 0 0
  118. >;
  119. };
  120. };
  121. &dcsr {
  122. #address-cells = <1>;
  123. #size-cells = <1>;
  124. compatible = "fsl,dcsr", "simple-bus";
  125. dcsr-epu@0 {
  126. compatible = "fsl,dcsr-epu";
  127. interrupts = <52 2 0 0
  128. 84 2 0 0
  129. 85 2 0 0>;
  130. reg = <0x0 0x1000>;
  131. };
  132. dcsr-npc {
  133. compatible = "fsl,dcsr-npc";
  134. reg = <0x1000 0x1000 0x1000000 0x8000>;
  135. };
  136. dcsr-nxc@2000 {
  137. compatible = "fsl,dcsr-nxc";
  138. reg = <0x2000 0x1000>;
  139. };
  140. dcsr-corenet {
  141. compatible = "fsl,dcsr-corenet";
  142. reg = <0x8000 0x1000 0xB0000 0x1000>;
  143. };
  144. dcsr-dpaa@9000 {
  145. compatible = "fsl,p5040-dcsr-dpaa", "fsl,dcsr-dpaa";
  146. reg = <0x9000 0x1000>;
  147. };
  148. dcsr-ocn@11000 {
  149. compatible = "fsl,p5040-dcsr-ocn", "fsl,dcsr-ocn";
  150. reg = <0x11000 0x1000>;
  151. };
  152. dcsr-ddr@12000 {
  153. compatible = "fsl,dcsr-ddr";
  154. dev-handle = <&ddr1>;
  155. reg = <0x12000 0x1000>;
  156. };
  157. dcsr-ddr@13000 {
  158. compatible = "fsl,dcsr-ddr";
  159. dev-handle = <&ddr2>;
  160. reg = <0x13000 0x1000>;
  161. };
  162. dcsr-nal@18000 {
  163. compatible = "fsl,p5040-dcsr-nal", "fsl,dcsr-nal";
  164. reg = <0x18000 0x1000>;
  165. };
  166. dcsr-rcpm@22000 {
  167. compatible = "fsl,p5040-dcsr-rcpm", "fsl,dcsr-rcpm";
  168. reg = <0x22000 0x1000>;
  169. };
  170. dcsr-cpu-sb-proxy@40000 {
  171. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  172. cpu-handle = <&cpu0>;
  173. reg = <0x40000 0x1000>;
  174. };
  175. dcsr-cpu-sb-proxy@41000 {
  176. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  177. cpu-handle = <&cpu1>;
  178. reg = <0x41000 0x1000>;
  179. };
  180. dcsr-cpu-sb-proxy@42000 {
  181. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  182. cpu-handle = <&cpu2>;
  183. reg = <0x42000 0x1000>;
  184. };
  185. dcsr-cpu-sb-proxy@43000 {
  186. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  187. cpu-handle = <&cpu3>;
  188. reg = <0x43000 0x1000>;
  189. };
  190. };
  191. &soc {
  192. #address-cells = <1>;
  193. #size-cells = <1>;
  194. device_type = "soc";
  195. compatible = "simple-bus";
  196. soc-sram-error {
  197. compatible = "fsl,soc-sram-error";
  198. interrupts = <16 2 1 29>;
  199. };
  200. corenet-law@0 {
  201. compatible = "fsl,corenet-law";
  202. reg = <0x0 0x1000>;
  203. fsl,num-laws = <32>;
  204. };
  205. ddr1: memory-controller@8000 {
  206. compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
  207. reg = <0x8000 0x1000>;
  208. interrupts = <16 2 1 23>;
  209. };
  210. ddr2: memory-controller@9000 {
  211. compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
  212. reg = <0x9000 0x1000>;
  213. interrupts = <16 2 1 22>;
  214. };
  215. cpc: l3-cache-controller@10000 {
  216. compatible = "fsl,p5040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
  217. reg = <0x10000 0x1000
  218. 0x11000 0x1000>;
  219. interrupts = <16 2 1 27
  220. 16 2 1 26>;
  221. };
  222. corenet-cf@18000 {
  223. compatible = "fsl,corenet-cf";
  224. reg = <0x18000 0x1000>;
  225. interrupts = <16 2 1 31>;
  226. fsl,ccf-num-csdids = <32>;
  227. fsl,ccf-num-snoopids = <32>;
  228. };
  229. iommu@20000 {
  230. compatible = "fsl,pamu-v1.0", "fsl,pamu";
  231. reg = <0x20000 0x5000>; /* for compatibility with older PAMU drivers */
  232. ranges = <0 0x20000 0x5000>;
  233. #address-cells = <1>;
  234. #size-cells = <1>;
  235. interrupts = <24 2 0 0
  236. 16 2 1 30>;
  237. pamu0: pamu@0 {
  238. reg = <0 0x1000>;
  239. fsl,primary-cache-geometry = <32 1>;
  240. fsl,secondary-cache-geometry = <128 2>;
  241. };
  242. pamu1: pamu@1000 {
  243. reg = <0x1000 0x1000>;
  244. fsl,primary-cache-geometry = <32 1>;
  245. fsl,secondary-cache-geometry = <128 2>;
  246. };
  247. pamu2: pamu@2000 {
  248. reg = <0x2000 0x1000>;
  249. fsl,primary-cache-geometry = <32 1>;
  250. fsl,secondary-cache-geometry = <128 2>;
  251. };
  252. pamu3: pamu@3000 {
  253. reg = <0x3000 0x1000>;
  254. fsl,primary-cache-geometry = <32 1>;
  255. fsl,secondary-cache-geometry = <128 2>;
  256. };
  257. pamu4: pamu@4000 {
  258. reg = <0x4000 0x1000>;
  259. fsl,primary-cache-geometry = <32 1>;
  260. fsl,secondary-cache-geometry = <128 2>;
  261. };
  262. };
  263. /include/ "qoriq-mpic.dtsi"
  264. guts: global-utilities@e0000 {
  265. compatible = "fsl,p5040-device-config", "fsl,qoriq-device-config-1.0";
  266. reg = <0xe0000 0xe00>;
  267. fsl,has-rstcr;
  268. #sleep-cells = <1>;
  269. fsl,liodn-bits = <12>;
  270. };
  271. pins: global-utilities@e0e00 {
  272. compatible = "fsl,p5040-pin-control", "fsl,qoriq-pin-control-1.0";
  273. reg = <0xe0e00 0x200>;
  274. #sleep-cells = <2>;
  275. };
  276. clockgen: global-utilities@e1000 {
  277. compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
  278. reg = <0xe1000 0x1000>;
  279. clock-frequency = <0>;
  280. };
  281. rcpm: global-utilities@e2000 {
  282. compatible = "fsl,p5040-rcpm", "fsl,qoriq-rcpm-1.0";
  283. reg = <0xe2000 0x1000>;
  284. #sleep-cells = <1>;
  285. };
  286. sfp: sfp@e8000 {
  287. compatible = "fsl,p5040-sfp", "fsl,qoriq-sfp-1.0";
  288. reg = <0xe8000 0x1000>;
  289. };
  290. serdes: serdes@ea000 {
  291. compatible = "fsl,p5040-serdes";
  292. reg = <0xea000 0x1000>;
  293. };
  294. /include/ "qoriq-dma-0.dtsi"
  295. dma@100300 {
  296. fsl,iommu-parent = <&pamu0>;
  297. fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
  298. };
  299. /include/ "qoriq-dma-1.dtsi"
  300. dma@101300 {
  301. fsl,iommu-parent = <&pamu0>;
  302. fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
  303. };
  304. /include/ "qoriq-espi-0.dtsi"
  305. spi@110000 {
  306. fsl,espi-num-chipselects = <4>;
  307. };
  308. /include/ "qoriq-esdhc-0.dtsi"
  309. sdhc@114000 {
  310. fsl,iommu-parent = <&pamu2>;
  311. fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
  312. sdhci,auto-cmd12;
  313. };
  314. /include/ "qoriq-i2c-0.dtsi"
  315. /include/ "qoriq-i2c-1.dtsi"
  316. /include/ "qoriq-duart-0.dtsi"
  317. /include/ "qoriq-duart-1.dtsi"
  318. /include/ "qoriq-gpio-0.dtsi"
  319. /include/ "qoriq-usb2-mph-0.dtsi"
  320. usb0: usb@210000 {
  321. compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
  322. fsl,iommu-parent = <&pamu4>;
  323. fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
  324. phy_type = "utmi";
  325. port0;
  326. };
  327. /include/ "qoriq-usb2-dr-0.dtsi"
  328. usb1: usb@211000 {
  329. compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
  330. fsl,iommu-parent = <&pamu4>;
  331. fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
  332. dr_mode = "host";
  333. phy_type = "utmi";
  334. };
  335. /include/ "qoriq-sata2-0.dtsi"
  336. sata@220000 {
  337. fsl,iommu-parent = <&pamu4>;
  338. fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
  339. };
  340. /include/ "qoriq-sata2-1.dtsi"
  341. sata@221000 {
  342. fsl,iommu-parent = <&pamu4>;
  343. fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
  344. };
  345. /include/ "qoriq-sec5.2-0.dtsi"
  346. crypto@300000 {
  347. fsl,iommu-parent = <&pamu4>;
  348. };
  349. };