p5020si-post.dtsi 10 KB

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  1. /*
  2. * P5020/5010 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &lbc {
  35. compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
  36. interrupts = <25 2 0 0>;
  37. #address-cells = <2>;
  38. #size-cells = <1>;
  39. };
  40. /* controller at 0x200000 */
  41. &pci0 {
  42. compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
  43. device_type = "pci";
  44. #size-cells = <2>;
  45. #address-cells = <3>;
  46. bus-range = <0x0 0xff>;
  47. clock-frequency = <33333333>;
  48. interrupts = <16 2 1 15>;
  49. fsl,iommu-parent = <&pamu0>;
  50. fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
  51. pcie@0 {
  52. reg = <0 0 0 0 0>;
  53. #interrupt-cells = <1>;
  54. #size-cells = <2>;
  55. #address-cells = <3>;
  56. device_type = "pci";
  57. interrupts = <16 2 1 15>;
  58. interrupt-map-mask = <0xf800 0 0 7>;
  59. interrupt-map = <
  60. /* IDSEL 0x0 */
  61. 0000 0 0 1 &mpic 40 1 0 0
  62. 0000 0 0 2 &mpic 1 1 0 0
  63. 0000 0 0 3 &mpic 2 1 0 0
  64. 0000 0 0 4 &mpic 3 1 0 0
  65. >;
  66. };
  67. };
  68. /* controller at 0x201000 */
  69. &pci1 {
  70. compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
  71. device_type = "pci";
  72. #size-cells = <2>;
  73. #address-cells = <3>;
  74. bus-range = <0 0xff>;
  75. clock-frequency = <33333333>;
  76. interrupts = <16 2 1 14>;
  77. fsl,iommu-parent = <&pamu0>;
  78. fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
  79. pcie@0 {
  80. reg = <0 0 0 0 0>;
  81. #interrupt-cells = <1>;
  82. #size-cells = <2>;
  83. #address-cells = <3>;
  84. device_type = "pci";
  85. interrupts = <16 2 1 14>;
  86. interrupt-map-mask = <0xf800 0 0 7>;
  87. interrupt-map = <
  88. /* IDSEL 0x0 */
  89. 0000 0 0 1 &mpic 41 1 0 0
  90. 0000 0 0 2 &mpic 5 1 0 0
  91. 0000 0 0 3 &mpic 6 1 0 0
  92. 0000 0 0 4 &mpic 7 1 0 0
  93. >;
  94. };
  95. };
  96. /* controller at 0x202000 */
  97. &pci2 {
  98. compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
  99. device_type = "pci";
  100. #size-cells = <2>;
  101. #address-cells = <3>;
  102. bus-range = <0x0 0xff>;
  103. clock-frequency = <33333333>;
  104. interrupts = <16 2 1 13>;
  105. fsl,iommu-parent = <&pamu0>;
  106. fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
  107. pcie@0 {
  108. reg = <0 0 0 0 0>;
  109. #interrupt-cells = <1>;
  110. #size-cells = <2>;
  111. #address-cells = <3>;
  112. device_type = "pci";
  113. interrupts = <16 2 1 13>;
  114. interrupt-map-mask = <0xf800 0 0 7>;
  115. interrupt-map = <
  116. /* IDSEL 0x0 */
  117. 0000 0 0 1 &mpic 42 1 0 0
  118. 0000 0 0 2 &mpic 9 1 0 0
  119. 0000 0 0 3 &mpic 10 1 0 0
  120. 0000 0 0 4 &mpic 11 1 0 0
  121. >;
  122. };
  123. };
  124. /* controller at 0x203000 */
  125. &pci3 {
  126. compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
  127. device_type = "pci";
  128. #size-cells = <2>;
  129. #address-cells = <3>;
  130. bus-range = <0x0 0xff>;
  131. clock-frequency = <33333333>;
  132. interrupts = <16 2 1 12>;
  133. fsl,iommu-parent = <&pamu0>;
  134. fsl,liodn-reg = <&guts 0x50c>; /* PEX4LIODNR */
  135. pcie@0 {
  136. reg = <0 0 0 0 0>;
  137. #interrupt-cells = <1>;
  138. #size-cells = <2>;
  139. #address-cells = <3>;
  140. device_type = "pci";
  141. interrupts = <16 2 1 12>;
  142. interrupt-map-mask = <0xf800 0 0 7>;
  143. interrupt-map = <
  144. /* IDSEL 0x0 */
  145. 0000 0 0 1 &mpic 43 1 0 0
  146. 0000 0 0 2 &mpic 0 1 0 0
  147. 0000 0 0 3 &mpic 4 1 0 0
  148. 0000 0 0 4 &mpic 8 1 0 0
  149. >;
  150. };
  151. };
  152. &rio {
  153. compatible = "fsl,srio";
  154. interrupts = <16 2 1 11>;
  155. #address-cells = <2>;
  156. #size-cells = <2>;
  157. fsl,iommu-parent = <&pamu0>;
  158. ranges;
  159. port1 {
  160. #address-cells = <2>;
  161. #size-cells = <2>;
  162. cell-index = <1>;
  163. fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
  164. };
  165. port2 {
  166. #address-cells = <2>;
  167. #size-cells = <2>;
  168. cell-index = <2>;
  169. fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
  170. };
  171. };
  172. &dcsr {
  173. #address-cells = <1>;
  174. #size-cells = <1>;
  175. compatible = "fsl,dcsr", "simple-bus";
  176. dcsr-epu@0 {
  177. compatible = "fsl,dcsr-epu";
  178. interrupts = <52 2 0 0
  179. 84 2 0 0
  180. 85 2 0 0>;
  181. reg = <0x0 0x1000>;
  182. };
  183. dcsr-npc {
  184. compatible = "fsl,dcsr-npc";
  185. reg = <0x1000 0x1000 0x1000000 0x8000>;
  186. };
  187. dcsr-nxc@2000 {
  188. compatible = "fsl,dcsr-nxc";
  189. reg = <0x2000 0x1000>;
  190. };
  191. dcsr-corenet {
  192. compatible = "fsl,dcsr-corenet";
  193. reg = <0x8000 0x1000 0xB0000 0x1000>;
  194. };
  195. dcsr-dpaa@9000 {
  196. compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa";
  197. reg = <0x9000 0x1000>;
  198. };
  199. dcsr-ocn@11000 {
  200. compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn";
  201. reg = <0x11000 0x1000>;
  202. };
  203. dcsr-ddr@12000 {
  204. compatible = "fsl,dcsr-ddr";
  205. dev-handle = <&ddr1>;
  206. reg = <0x12000 0x1000>;
  207. };
  208. dcsr-ddr@13000 {
  209. compatible = "fsl,dcsr-ddr";
  210. dev-handle = <&ddr2>;
  211. reg = <0x13000 0x1000>;
  212. };
  213. dcsr-nal@18000 {
  214. compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal";
  215. reg = <0x18000 0x1000>;
  216. };
  217. dcsr-rcpm@22000 {
  218. compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm";
  219. reg = <0x22000 0x1000>;
  220. };
  221. dcsr-cpu-sb-proxy@40000 {
  222. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  223. cpu-handle = <&cpu0>;
  224. reg = <0x40000 0x1000>;
  225. };
  226. dcsr-cpu-sb-proxy@41000 {
  227. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  228. cpu-handle = <&cpu1>;
  229. reg = <0x41000 0x1000>;
  230. };
  231. };
  232. &soc {
  233. #address-cells = <1>;
  234. #size-cells = <1>;
  235. device_type = "soc";
  236. compatible = "simple-bus";
  237. soc-sram-error {
  238. compatible = "fsl,soc-sram-error";
  239. interrupts = <16 2 1 29>;
  240. };
  241. corenet-law@0 {
  242. compatible = "fsl,corenet-law";
  243. reg = <0x0 0x1000>;
  244. fsl,num-laws = <32>;
  245. };
  246. ddr1: memory-controller@8000 {
  247. compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
  248. reg = <0x8000 0x1000>;
  249. interrupts = <16 2 1 23>;
  250. };
  251. ddr2: memory-controller@9000 {
  252. compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
  253. reg = <0x9000 0x1000>;
  254. interrupts = <16 2 1 22>;
  255. };
  256. cpc: l3-cache-controller@10000 {
  257. compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
  258. reg = <0x10000 0x1000
  259. 0x11000 0x1000>;
  260. interrupts = <16 2 1 27
  261. 16 2 1 26>;
  262. };
  263. corenet-cf@18000 {
  264. compatible = "fsl,corenet-cf";
  265. reg = <0x18000 0x1000>;
  266. interrupts = <16 2 1 31>;
  267. fsl,ccf-num-csdids = <32>;
  268. fsl,ccf-num-snoopids = <32>;
  269. };
  270. iommu@20000 {
  271. compatible = "fsl,pamu-v1.0", "fsl,pamu";
  272. reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */
  273. ranges = <0 0x20000 0x4000>;
  274. #address-cells = <1>;
  275. #size-cells = <1>;
  276. interrupts = <
  277. 24 2 0 0
  278. 16 2 1 30>;
  279. pamu0: pamu@0 {
  280. reg = <0 0x1000>;
  281. fsl,primary-cache-geometry = <32 1>;
  282. fsl,secondary-cache-geometry = <128 2>;
  283. };
  284. pamu1: pamu@1000 {
  285. reg = <0x1000 0x1000>;
  286. fsl,primary-cache-geometry = <32 1>;
  287. fsl,secondary-cache-geometry = <128 2>;
  288. };
  289. pamu2: pamu@2000 {
  290. reg = <0x2000 0x1000>;
  291. fsl,primary-cache-geometry = <32 1>;
  292. fsl,secondary-cache-geometry = <128 2>;
  293. };
  294. pamu3: pamu@3000 {
  295. reg = <0x3000 0x1000>;
  296. fsl,primary-cache-geometry = <32 1>;
  297. fsl,secondary-cache-geometry = <128 2>;
  298. };
  299. };
  300. /include/ "qoriq-mpic.dtsi"
  301. guts: global-utilities@e0000 {
  302. compatible = "fsl,qoriq-device-config-1.0";
  303. reg = <0xe0000 0xe00>;
  304. fsl,has-rstcr;
  305. #sleep-cells = <1>;
  306. fsl,liodn-bits = <12>;
  307. };
  308. pins: global-utilities@e0e00 {
  309. compatible = "fsl,qoriq-pin-control-1.0";
  310. reg = <0xe0e00 0x200>;
  311. #sleep-cells = <2>;
  312. };
  313. clockgen: global-utilities@e1000 {
  314. compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
  315. reg = <0xe1000 0x1000>;
  316. clock-frequency = <0>;
  317. };
  318. rcpm: global-utilities@e2000 {
  319. compatible = "fsl,qoriq-rcpm-1.0";
  320. reg = <0xe2000 0x1000>;
  321. #sleep-cells = <1>;
  322. };
  323. sfp: sfp@e8000 {
  324. compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
  325. reg = <0xe8000 0x1000>;
  326. };
  327. serdes: serdes@ea000 {
  328. compatible = "fsl,p5020-serdes";
  329. reg = <0xea000 0x1000>;
  330. };
  331. /include/ "qoriq-dma-0.dtsi"
  332. dma@100300 {
  333. fsl,iommu-parent = <&pamu0>;
  334. fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
  335. };
  336. /include/ "qoriq-dma-1.dtsi"
  337. dma@101300 {
  338. fsl,iommu-parent = <&pamu0>;
  339. fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
  340. };
  341. /include/ "qoriq-espi-0.dtsi"
  342. spi@110000 {
  343. fsl,espi-num-chipselects = <4>;
  344. };
  345. /include/ "qoriq-esdhc-0.dtsi"
  346. sdhc@114000 {
  347. fsl,iommu-parent = <&pamu1>;
  348. fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
  349. sdhci,auto-cmd12;
  350. };
  351. /include/ "qoriq-i2c-0.dtsi"
  352. /include/ "qoriq-i2c-1.dtsi"
  353. /include/ "qoriq-duart-0.dtsi"
  354. /include/ "qoriq-duart-1.dtsi"
  355. /include/ "qoriq-gpio-0.dtsi"
  356. /include/ "qoriq-usb2-mph-0.dtsi"
  357. usb0: usb@210000 {
  358. compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
  359. fsl,iommu-parent = <&pamu1>;
  360. fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
  361. phy_type = "utmi";
  362. port0;
  363. };
  364. /include/ "qoriq-usb2-dr-0.dtsi"
  365. usb1: usb@211000 {
  366. compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
  367. fsl,iommu-parent = <&pamu1>;
  368. fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
  369. dr_mode = "host";
  370. phy_type = "utmi";
  371. };
  372. /include/ "qoriq-sata2-0.dtsi"
  373. sata@220000 {
  374. fsl,iommu-parent = <&pamu1>;
  375. fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
  376. };
  377. /include/ "qoriq-sata2-1.dtsi"
  378. sata@221000 {
  379. fsl,iommu-parent = <&pamu1>;
  380. fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
  381. };
  382. /include/ "qoriq-sec4.2-0.dtsi"
  383. crypto@300000 {
  384. fsl,iommu-parent = <&pamu1>;
  385. };
  386. /include/ "qoriq-raid1.0-0.dtsi"
  387. raideng@320000 {
  388. fsl,iommu-parent = <&pamu1>;
  389. };
  390. };