p4080si-post.dtsi 11 KB

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  1. /*
  2. * P4080/P4040 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &lbc {
  35. compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
  36. interrupts = <25 2 0 0>;
  37. #address-cells = <2>;
  38. #size-cells = <1>;
  39. };
  40. /* controller at 0x200000 */
  41. &pci0 {
  42. compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1";
  43. device_type = "pci";
  44. #size-cells = <2>;
  45. #address-cells = <3>;
  46. bus-range = <0x0 0xff>;
  47. clock-frequency = <33333333>;
  48. interrupts = <16 2 1 15>;
  49. fsl,iommu-parent = <&pamu0>;
  50. fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
  51. pcie@0 {
  52. reg = <0 0 0 0 0>;
  53. #interrupt-cells = <1>;
  54. #size-cells = <2>;
  55. #address-cells = <3>;
  56. device_type = "pci";
  57. interrupts = <16 2 1 15>;
  58. interrupt-map-mask = <0xf800 0 0 7>;
  59. interrupt-map = <
  60. /* IDSEL 0x0 */
  61. 0000 0 0 1 &mpic 40 1 0 0
  62. 0000 0 0 2 &mpic 1 1 0 0
  63. 0000 0 0 3 &mpic 2 1 0 0
  64. 0000 0 0 4 &mpic 3 1 0 0
  65. >;
  66. };
  67. };
  68. /* controller at 0x201000 */
  69. &pci1 {
  70. compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1";
  71. device_type = "pci";
  72. #size-cells = <2>;
  73. #address-cells = <3>;
  74. bus-range = <0 0xff>;
  75. clock-frequency = <33333333>;
  76. interrupts = <16 2 1 14>;
  77. fsl,iommu-parent = <&pamu0>;
  78. fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
  79. pcie@0 {
  80. reg = <0 0 0 0 0>;
  81. #interrupt-cells = <1>;
  82. #size-cells = <2>;
  83. #address-cells = <3>;
  84. device_type = "pci";
  85. interrupts = <16 2 1 14>;
  86. interrupt-map-mask = <0xf800 0 0 7>;
  87. interrupt-map = <
  88. /* IDSEL 0x0 */
  89. 0000 0 0 1 &mpic 41 1 0 0
  90. 0000 0 0 2 &mpic 5 1 0 0
  91. 0000 0 0 3 &mpic 6 1 0 0
  92. 0000 0 0 4 &mpic 7 1 0 0
  93. >;
  94. };
  95. };
  96. /* controller at 0x202000 */
  97. &pci2 {
  98. compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1";
  99. device_type = "pci";
  100. #size-cells = <2>;
  101. #address-cells = <3>;
  102. bus-range = <0x0 0xff>;
  103. clock-frequency = <33333333>;
  104. interrupts = <16 2 1 13>;
  105. fsl,iommu-parent = <&pamu0>;
  106. fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
  107. pcie@0 {
  108. reg = <0 0 0 0 0>;
  109. #interrupt-cells = <1>;
  110. #size-cells = <2>;
  111. #address-cells = <3>;
  112. device_type = "pci";
  113. interrupts = <16 2 1 13>;
  114. interrupt-map-mask = <0xf800 0 0 7>;
  115. interrupt-map = <
  116. /* IDSEL 0x0 */
  117. 0000 0 0 1 &mpic 42 1 0 0
  118. 0000 0 0 2 &mpic 9 1 0 0
  119. 0000 0 0 3 &mpic 10 1 0 0
  120. 0000 0 0 4 &mpic 11 1 0 0
  121. >;
  122. };
  123. };
  124. &rio {
  125. compatible = "fsl,srio";
  126. interrupts = <16 2 1 11>;
  127. #address-cells = <2>;
  128. #size-cells = <2>;
  129. fsl,srio-rmu-handle = <&rmu>;
  130. fsl,iommu-parent = <&pamu0>;
  131. ranges;
  132. port1 {
  133. #address-cells = <2>;
  134. #size-cells = <2>;
  135. cell-index = <1>;
  136. fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
  137. };
  138. port2 {
  139. #address-cells = <2>;
  140. #size-cells = <2>;
  141. cell-index = <2>;
  142. fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
  143. };
  144. };
  145. &dcsr {
  146. #address-cells = <1>;
  147. #size-cells = <1>;
  148. compatible = "fsl,dcsr", "simple-bus";
  149. dcsr-epu@0 {
  150. compatible = "fsl,dcsr-epu";
  151. interrupts = <52 2 0 0
  152. 84 2 0 0
  153. 85 2 0 0>;
  154. reg = <0x0 0x1000>;
  155. };
  156. dcsr-npc {
  157. compatible = "fsl,dcsr-npc";
  158. reg = <0x1000 0x1000 0x1000000 0x8000>;
  159. };
  160. dcsr-nxc@2000 {
  161. compatible = "fsl,dcsr-nxc";
  162. reg = <0x2000 0x1000>;
  163. };
  164. dcsr-corenet {
  165. compatible = "fsl,dcsr-corenet";
  166. reg = <0x8000 0x1000 0xB0000 0x1000>;
  167. };
  168. dcsr-dpaa@9000 {
  169. compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
  170. reg = <0x9000 0x1000>;
  171. };
  172. dcsr-ocn@11000 {
  173. compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
  174. reg = <0x11000 0x1000>;
  175. };
  176. dcsr-ddr@12000 {
  177. compatible = "fsl,dcsr-ddr";
  178. dev-handle = <&ddr1>;
  179. reg = <0x12000 0x1000>;
  180. };
  181. dcsr-ddr@13000 {
  182. compatible = "fsl,dcsr-ddr";
  183. dev-handle = <&ddr2>;
  184. reg = <0x13000 0x1000>;
  185. };
  186. dcsr-nal@18000 {
  187. compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
  188. reg = <0x18000 0x1000>;
  189. };
  190. dcsr-rcpm@22000 {
  191. compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
  192. reg = <0x22000 0x1000>;
  193. };
  194. dcsr-cpu-sb-proxy@40000 {
  195. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  196. cpu-handle = <&cpu0>;
  197. reg = <0x40000 0x1000>;
  198. };
  199. dcsr-cpu-sb-proxy@41000 {
  200. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  201. cpu-handle = <&cpu1>;
  202. reg = <0x41000 0x1000>;
  203. };
  204. dcsr-cpu-sb-proxy@42000 {
  205. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  206. cpu-handle = <&cpu2>;
  207. reg = <0x42000 0x1000>;
  208. };
  209. dcsr-cpu-sb-proxy@43000 {
  210. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  211. cpu-handle = <&cpu3>;
  212. reg = <0x43000 0x1000>;
  213. };
  214. dcsr-cpu-sb-proxy@44000 {
  215. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  216. cpu-handle = <&cpu4>;
  217. reg = <0x44000 0x1000>;
  218. };
  219. dcsr-cpu-sb-proxy@45000 {
  220. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  221. cpu-handle = <&cpu5>;
  222. reg = <0x45000 0x1000>;
  223. };
  224. dcsr-cpu-sb-proxy@46000 {
  225. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  226. cpu-handle = <&cpu6>;
  227. reg = <0x46000 0x1000>;
  228. };
  229. dcsr-cpu-sb-proxy@47000 {
  230. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  231. cpu-handle = <&cpu7>;
  232. reg = <0x47000 0x1000>;
  233. };
  234. };
  235. &soc {
  236. #address-cells = <1>;
  237. #size-cells = <1>;
  238. device_type = "soc";
  239. compatible = "simple-bus";
  240. soc-sram-error {
  241. compatible = "fsl,soc-sram-error";
  242. interrupts = <16 2 1 29>;
  243. };
  244. corenet-law@0 {
  245. compatible = "fsl,corenet-law";
  246. reg = <0x0 0x1000>;
  247. fsl,num-laws = <32>;
  248. };
  249. ddr1: memory-controller@8000 {
  250. compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
  251. reg = <0x8000 0x1000>;
  252. interrupts = <16 2 1 23>;
  253. };
  254. ddr2: memory-controller@9000 {
  255. compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
  256. reg = <0x9000 0x1000>;
  257. interrupts = <16 2 1 22>;
  258. };
  259. cpc: l3-cache-controller@10000 {
  260. compatible = "fsl,p4080-l3-cache-controller", "cache";
  261. reg = <0x10000 0x1000
  262. 0x11000 0x1000>;
  263. interrupts = <16 2 1 27
  264. 16 2 1 26>;
  265. };
  266. corenet-cf@18000 {
  267. compatible = "fsl,corenet-cf";
  268. reg = <0x18000 0x1000>;
  269. interrupts = <16 2 1 31>;
  270. fsl,ccf-num-csdids = <32>;
  271. fsl,ccf-num-snoopids = <32>;
  272. };
  273. iommu@20000 {
  274. compatible = "fsl,pamu-v1.0", "fsl,pamu";
  275. reg = <0x20000 0x5000>; /* for compatibility with older PAMU drivers */
  276. ranges = <0 0x20000 0x5000>;
  277. #address-cells = <1>;
  278. #size-cells = <1>;
  279. interrupts = <
  280. 24 2 0 0
  281. 16 2 1 30>;
  282. pamu0: pamu@0 {
  283. reg = <0 0x1000>;
  284. fsl,primary-cache-geometry = <32 1>;
  285. fsl,secondary-cache-geometry = <128 2>;
  286. };
  287. pamu1: pamu@1000 {
  288. reg = <0x1000 0x1000>;
  289. fsl,primary-cache-geometry = <32 1>;
  290. fsl,secondary-cache-geometry = <128 2>;
  291. };
  292. pamu2: pamu@2000 {
  293. reg = <0x2000 0x1000>;
  294. fsl,primary-cache-geometry = <32 1>;
  295. fsl,secondary-cache-geometry = <128 2>;
  296. };
  297. pamu3: pamu@3000 {
  298. reg = <0x3000 0x1000>;
  299. fsl,primary-cache-geometry = <32 1>;
  300. fsl,secondary-cache-geometry = <128 2>;
  301. };
  302. pamu4: pamu@4000 {
  303. reg = <0x4000 0x1000>;
  304. fsl,primary-cache-geometry = <32 1>;
  305. fsl,secondary-cache-geometry = <128 2>;
  306. };
  307. };
  308. /include/ "qoriq-rmu-0.dtsi"
  309. rmu@d3000 {
  310. fsl,iommu-parent = <&pamu0>;
  311. fsl,liodn-reg = <&guts 0x540>; /* RMULIODNR */
  312. };
  313. /include/ "qoriq-mpic.dtsi"
  314. guts: global-utilities@e0000 {
  315. compatible = "fsl,qoriq-device-config-1.0";
  316. reg = <0xe0000 0xe00>;
  317. fsl,has-rstcr;
  318. #sleep-cells = <1>;
  319. fsl,liodn-bits = <12>;
  320. };
  321. pins: global-utilities@e0e00 {
  322. compatible = "fsl,qoriq-pin-control-1.0";
  323. reg = <0xe0e00 0x200>;
  324. #sleep-cells = <2>;
  325. };
  326. clockgen: global-utilities@e1000 {
  327. compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
  328. reg = <0xe1000 0x1000>;
  329. clock-frequency = <0>;
  330. };
  331. rcpm: global-utilities@e2000 {
  332. compatible = "fsl,qoriq-rcpm-1.0";
  333. reg = <0xe2000 0x1000>;
  334. #sleep-cells = <1>;
  335. };
  336. sfp: sfp@e8000 {
  337. compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
  338. reg = <0xe8000 0x1000>;
  339. };
  340. serdes: serdes@ea000 {
  341. compatible = "fsl,p4080-serdes";
  342. reg = <0xea000 0x1000>;
  343. };
  344. /include/ "qoriq-dma-0.dtsi"
  345. dma@100300 {
  346. fsl,iommu-parent = <&pamu0>;
  347. fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
  348. };
  349. /include/ "qoriq-dma-1.dtsi"
  350. dma@101300 {
  351. fsl,iommu-parent = <&pamu0>;
  352. fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
  353. };
  354. /include/ "qoriq-espi-0.dtsi"
  355. spi@110000 {
  356. fsl,espi-num-chipselects = <4>;
  357. };
  358. /include/ "qoriq-esdhc-0.dtsi"
  359. sdhc@114000 {
  360. fsl,iommu-parent = <&pamu1>;
  361. fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
  362. voltage-ranges = <3300 3300>;
  363. sdhci,auto-cmd12;
  364. };
  365. /include/ "qoriq-i2c-0.dtsi"
  366. /include/ "qoriq-i2c-1.dtsi"
  367. /include/ "qoriq-duart-0.dtsi"
  368. /include/ "qoriq-duart-1.dtsi"
  369. /include/ "qoriq-gpio-0.dtsi"
  370. /include/ "qoriq-usb2-mph-0.dtsi"
  371. usb@210000 {
  372. compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
  373. fsl,iommu-parent = <&pamu1>;
  374. fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
  375. port0;
  376. };
  377. /include/ "qoriq-usb2-dr-0.dtsi"
  378. usb@211000 {
  379. compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
  380. fsl,iommu-parent = <&pamu1>;
  381. fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
  382. };
  383. /include/ "qoriq-sec4.0-0.dtsi"
  384. crypto: crypto@300000 {
  385. fsl,iommu-parent = <&pamu1>;
  386. };
  387. };