p2041si-post.dtsi 9.7 KB

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  1. /*
  2. * P2041/P2040 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &lbc {
  35. compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
  36. interrupts = <25 2 0 0>;
  37. #address-cells = <2>;
  38. #size-cells = <1>;
  39. };
  40. /* controller at 0x200000 */
  41. &pci0 {
  42. compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
  43. device_type = "pci";
  44. #size-cells = <2>;
  45. #address-cells = <3>;
  46. bus-range = <0x0 0xff>;
  47. clock-frequency = <33333333>;
  48. interrupts = <16 2 1 15>;
  49. fsl,iommu-parent = <&pamu0>;
  50. fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
  51. pcie@0 {
  52. reg = <0 0 0 0 0>;
  53. #interrupt-cells = <1>;
  54. #size-cells = <2>;
  55. #address-cells = <3>;
  56. device_type = "pci";
  57. interrupts = <16 2 1 15>;
  58. interrupt-map-mask = <0xf800 0 0 7>;
  59. interrupt-map = <
  60. /* IDSEL 0x0 */
  61. 0000 0 0 1 &mpic 40 1 0 0
  62. 0000 0 0 2 &mpic 1 1 0 0
  63. 0000 0 0 3 &mpic 2 1 0 0
  64. 0000 0 0 4 &mpic 3 1 0 0
  65. >;
  66. };
  67. };
  68. /* controller at 0x201000 */
  69. &pci1 {
  70. compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
  71. device_type = "pci";
  72. #size-cells = <2>;
  73. #address-cells = <3>;
  74. bus-range = <0 0xff>;
  75. clock-frequency = <33333333>;
  76. interrupts = <16 2 1 14>;
  77. fsl,iommu-parent = <&pamu0>;
  78. fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
  79. pcie@0 {
  80. reg = <0 0 0 0 0>;
  81. #interrupt-cells = <1>;
  82. #size-cells = <2>;
  83. #address-cells = <3>;
  84. device_type = "pci";
  85. interrupts = <16 2 1 14>;
  86. interrupt-map-mask = <0xf800 0 0 7>;
  87. interrupt-map = <
  88. /* IDSEL 0x0 */
  89. 0000 0 0 1 &mpic 41 1 0 0
  90. 0000 0 0 2 &mpic 5 1 0 0
  91. 0000 0 0 3 &mpic 6 1 0 0
  92. 0000 0 0 4 &mpic 7 1 0 0
  93. >;
  94. };
  95. };
  96. /* controller at 0x202000 */
  97. &pci2 {
  98. compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
  99. device_type = "pci";
  100. #size-cells = <2>;
  101. #address-cells = <3>;
  102. bus-range = <0x0 0xff>;
  103. clock-frequency = <33333333>;
  104. interrupts = <16 2 1 13>;
  105. fsl,iommu-parent = <&pamu0>;
  106. fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
  107. pcie@0 {
  108. reg = <0 0 0 0 0>;
  109. #interrupt-cells = <1>;
  110. #size-cells = <2>;
  111. #address-cells = <3>;
  112. device_type = "pci";
  113. interrupts = <16 2 1 13>;
  114. interrupt-map-mask = <0xf800 0 0 7>;
  115. interrupt-map = <
  116. /* IDSEL 0x0 */
  117. 0000 0 0 1 &mpic 42 1 0 0
  118. 0000 0 0 2 &mpic 9 1 0 0
  119. 0000 0 0 3 &mpic 10 1 0 0
  120. 0000 0 0 4 &mpic 11 1 0 0
  121. >;
  122. };
  123. };
  124. &rio {
  125. compatible = "fsl,srio";
  126. interrupts = <16 2 1 11>;
  127. #address-cells = <2>;
  128. #size-cells = <2>;
  129. fsl,iommu-parent = <&pamu0>;
  130. ranges;
  131. port1 {
  132. #address-cells = <2>;
  133. #size-cells = <2>;
  134. cell-index = <1>;
  135. fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
  136. };
  137. port2 {
  138. #address-cells = <2>;
  139. #size-cells = <2>;
  140. cell-index = <2>;
  141. fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
  142. };
  143. };
  144. &dcsr {
  145. #address-cells = <1>;
  146. #size-cells = <1>;
  147. compatible = "fsl,dcsr", "simple-bus";
  148. dcsr-epu@0 {
  149. compatible = "fsl,dcsr-epu";
  150. interrupts = <52 2 0 0
  151. 84 2 0 0
  152. 85 2 0 0>;
  153. reg = <0x0 0x1000>;
  154. };
  155. dcsr-npc {
  156. compatible = "fsl,dcsr-npc";
  157. reg = <0x1000 0x1000 0x1000000 0x8000>;
  158. };
  159. dcsr-nxc@2000 {
  160. compatible = "fsl,dcsr-nxc";
  161. reg = <0x2000 0x1000>;
  162. };
  163. dcsr-corenet {
  164. compatible = "fsl,dcsr-corenet";
  165. reg = <0x8000 0x1000 0xB0000 0x1000>;
  166. };
  167. dcsr-dpaa@9000 {
  168. compatible = "fsl,p2041-dcsr-dpaa", "fsl,dcsr-dpaa";
  169. reg = <0x9000 0x1000>;
  170. };
  171. dcsr-ocn@11000 {
  172. compatible = "fsl,p2041-dcsr-ocn", "fsl,dcsr-ocn";
  173. reg = <0x11000 0x1000>;
  174. };
  175. dcsr-ddr@12000 {
  176. compatible = "fsl,dcsr-ddr";
  177. dev-handle = <&ddr1>;
  178. reg = <0x12000 0x1000>;
  179. };
  180. dcsr-nal@18000 {
  181. compatible = "fsl,p2041-dcsr-nal", "fsl,dcsr-nal";
  182. reg = <0x18000 0x1000>;
  183. };
  184. dcsr-rcpm@22000 {
  185. compatible = "fsl,p2041-dcsr-rcpm", "fsl,dcsr-rcpm";
  186. reg = <0x22000 0x1000>;
  187. };
  188. dcsr-cpu-sb-proxy@40000 {
  189. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  190. cpu-handle = <&cpu0>;
  191. reg = <0x40000 0x1000>;
  192. };
  193. dcsr-cpu-sb-proxy@41000 {
  194. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  195. cpu-handle = <&cpu1>;
  196. reg = <0x41000 0x1000>;
  197. };
  198. dcsr-cpu-sb-proxy@42000 {
  199. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  200. cpu-handle = <&cpu2>;
  201. reg = <0x42000 0x1000>;
  202. };
  203. dcsr-cpu-sb-proxy@43000 {
  204. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  205. cpu-handle = <&cpu3>;
  206. reg = <0x43000 0x1000>;
  207. };
  208. };
  209. &soc {
  210. #address-cells = <1>;
  211. #size-cells = <1>;
  212. device_type = "soc";
  213. compatible = "simple-bus";
  214. soc-sram-error {
  215. compatible = "fsl,soc-sram-error";
  216. interrupts = <16 2 1 29>;
  217. };
  218. corenet-law@0 {
  219. compatible = "fsl,corenet-law";
  220. reg = <0x0 0x1000>;
  221. fsl,num-laws = <32>;
  222. };
  223. ddr1: memory-controller@8000 {
  224. compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
  225. reg = <0x8000 0x1000>;
  226. interrupts = <16 2 1 23>;
  227. };
  228. cpc: l3-cache-controller@10000 {
  229. compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
  230. reg = <0x10000 0x1000>;
  231. interrupts = <16 2 1 27>;
  232. };
  233. corenet-cf@18000 {
  234. compatible = "fsl,corenet-cf";
  235. reg = <0x18000 0x1000>;
  236. interrupts = <16 2 1 31>;
  237. fsl,ccf-num-csdids = <32>;
  238. fsl,ccf-num-snoopids = <32>;
  239. };
  240. iommu@20000 {
  241. compatible = "fsl,pamu-v1.0", "fsl,pamu";
  242. reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */
  243. ranges = <0 0x20000 0x4000>;
  244. #address-cells = <1>;
  245. #size-cells = <1>;
  246. interrupts = <
  247. 24 2 0 0
  248. 16 2 1 30>;
  249. pamu0: pamu@0 {
  250. reg = <0 0x1000>;
  251. fsl,primary-cache-geometry = <32 1>;
  252. fsl,secondary-cache-geometry = <128 2>;
  253. };
  254. pamu1: pamu@1000 {
  255. reg = <0x1000 0x1000>;
  256. fsl,primary-cache-geometry = <32 1>;
  257. fsl,secondary-cache-geometry = <128 2>;
  258. };
  259. pamu2: pamu@2000 {
  260. reg = <0x2000 0x1000>;
  261. fsl,primary-cache-geometry = <32 1>;
  262. fsl,secondary-cache-geometry = <128 2>;
  263. };
  264. pamu3: pamu@3000 {
  265. reg = <0x3000 0x1000>;
  266. fsl,primary-cache-geometry = <32 1>;
  267. fsl,secondary-cache-geometry = <128 2>;
  268. };
  269. };
  270. /include/ "qoriq-mpic.dtsi"
  271. guts: global-utilities@e0000 {
  272. compatible = "fsl,qoriq-device-config-1.0";
  273. reg = <0xe0000 0xe00>;
  274. fsl,has-rstcr;
  275. #sleep-cells = <1>;
  276. fsl,liodn-bits = <12>;
  277. };
  278. pins: global-utilities@e0e00 {
  279. compatible = "fsl,qoriq-pin-control-1.0";
  280. reg = <0xe0e00 0x200>;
  281. #sleep-cells = <2>;
  282. };
  283. clockgen: global-utilities@e1000 {
  284. compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
  285. reg = <0xe1000 0x1000>;
  286. clock-frequency = <0>;
  287. };
  288. rcpm: global-utilities@e2000 {
  289. compatible = "fsl,qoriq-rcpm-1.0";
  290. reg = <0xe2000 0x1000>;
  291. #sleep-cells = <1>;
  292. };
  293. sfp: sfp@e8000 {
  294. compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0";
  295. reg = <0xe8000 0x1000>;
  296. };
  297. serdes: serdes@ea000 {
  298. compatible = "fsl,p2041-serdes";
  299. reg = <0xea000 0x1000>;
  300. };
  301. /include/ "qoriq-dma-0.dtsi"
  302. dma@100300 {
  303. fsl,iommu-parent = <&pamu0>;
  304. fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
  305. };
  306. /include/ "qoriq-dma-1.dtsi"
  307. dma@101300 {
  308. fsl,iommu-parent = <&pamu0>;
  309. fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
  310. };
  311. /include/ "qoriq-espi-0.dtsi"
  312. spi@110000 {
  313. fsl,espi-num-chipselects = <4>;
  314. };
  315. /include/ "qoriq-esdhc-0.dtsi"
  316. sdhc@114000 {
  317. fsl,iommu-parent = <&pamu1>;
  318. fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
  319. sdhci,auto-cmd12;
  320. };
  321. /include/ "qoriq-i2c-0.dtsi"
  322. /include/ "qoriq-i2c-1.dtsi"
  323. /include/ "qoriq-duart-0.dtsi"
  324. /include/ "qoriq-duart-1.dtsi"
  325. /include/ "qoriq-gpio-0.dtsi"
  326. /include/ "qoriq-usb2-mph-0.dtsi"
  327. usb0: usb@210000 {
  328. compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
  329. phy_type = "utmi";
  330. fsl,iommu-parent = <&pamu1>;
  331. fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
  332. port0;
  333. };
  334. /include/ "qoriq-usb2-dr-0.dtsi"
  335. usb1: usb@211000 {
  336. compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
  337. fsl,iommu-parent = <&pamu1>;
  338. fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
  339. dr_mode = "host";
  340. phy_type = "utmi";
  341. };
  342. /include/ "qoriq-sata2-0.dtsi"
  343. sata@220000 {
  344. fsl,iommu-parent = <&pamu1>;
  345. fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
  346. };
  347. /include/ "qoriq-sata2-1.dtsi"
  348. sata@221000 {
  349. fsl,iommu-parent = <&pamu1>;
  350. fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
  351. };
  352. /include/ "qoriq-sec4.2-0.dtsi"
  353. crypto: crypto@300000 {
  354. fsl,iommu-parent = <&pamu1>;
  355. };
  356. };