sysctrl.c 11 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify it
  3. * under the terms of the GNU General Public License version 2 as published
  4. * by the Free Software Foundation.
  5. *
  6. * Copyright (C) 2011-2012 John Crispin <blogic@openwrt.org>
  7. */
  8. #include <linux/ioport.h>
  9. #include <linux/export.h>
  10. #include <linux/clkdev.h>
  11. #include <linux/of.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/of_address.h>
  14. #include <lantiq_soc.h>
  15. #include "../clk.h"
  16. #include "../prom.h"
  17. /* clock control register */
  18. #define CGU_IFCCR 0x0018
  19. #define CGU_IFCCR_VR9 0x0024
  20. /* system clock register */
  21. #define CGU_SYS 0x0010
  22. /* pci control register */
  23. #define CGU_PCICR 0x0034
  24. #define CGU_PCICR_VR9 0x0038
  25. /* ephy configuration register */
  26. #define CGU_EPHY 0x10
  27. /* power control register */
  28. #define PMU_PWDCR 0x1C
  29. /* power status register */
  30. #define PMU_PWDSR 0x20
  31. /* power control register */
  32. #define PMU_PWDCR1 0x24
  33. /* power status register */
  34. #define PMU_PWDSR1 0x28
  35. /* power control register */
  36. #define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
  37. /* power status register */
  38. #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
  39. /* clock gates that we can en/disable */
  40. #define PMU_USB0_P BIT(0)
  41. #define PMU_PCI BIT(4)
  42. #define PMU_DMA BIT(5)
  43. #define PMU_USB0 BIT(6)
  44. #define PMU_ASC0 BIT(7)
  45. #define PMU_EPHY BIT(7) /* ase */
  46. #define PMU_SPI BIT(8)
  47. #define PMU_DFE BIT(9)
  48. #define PMU_EBU BIT(10)
  49. #define PMU_STP BIT(11)
  50. #define PMU_GPT BIT(12)
  51. #define PMU_AHBS BIT(13) /* vr9 */
  52. #define PMU_FPI BIT(14)
  53. #define PMU_AHBM BIT(15)
  54. #define PMU_ASC1 BIT(17)
  55. #define PMU_PPE_QSB BIT(18)
  56. #define PMU_PPE_SLL01 BIT(19)
  57. #define PMU_PPE_TC BIT(21)
  58. #define PMU_PPE_EMA BIT(22)
  59. #define PMU_PPE_DPLUM BIT(23)
  60. #define PMU_PPE_DPLUS BIT(24)
  61. #define PMU_USB1_P BIT(26)
  62. #define PMU_USB1 BIT(27)
  63. #define PMU_SWITCH BIT(28)
  64. #define PMU_PPE_TOP BIT(29)
  65. #define PMU_GPHY BIT(30)
  66. #define PMU_PCIE_CLK BIT(31)
  67. #define PMU1_PCIE_PHY BIT(0)
  68. #define PMU1_PCIE_CTL BIT(1)
  69. #define PMU1_PCIE_PDI BIT(4)
  70. #define PMU1_PCIE_MSI BIT(5)
  71. #define pmu_w32(x, y) ltq_w32((x), pmu_membase + (y))
  72. #define pmu_r32(x) ltq_r32(pmu_membase + (x))
  73. static void __iomem *pmu_membase;
  74. void __iomem *ltq_cgu_membase;
  75. void __iomem *ltq_ebu_membase;
  76. static u32 ifccr = CGU_IFCCR;
  77. static u32 pcicr = CGU_PCICR;
  78. /* legacy function kept alive to ease clkdev transition */
  79. void ltq_pmu_enable(unsigned int module)
  80. {
  81. int err = 1000000;
  82. pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR);
  83. do {} while (--err && (pmu_r32(PMU_PWDSR) & module));
  84. if (!err)
  85. panic("activating PMU module failed!");
  86. }
  87. EXPORT_SYMBOL(ltq_pmu_enable);
  88. /* legacy function kept alive to ease clkdev transition */
  89. void ltq_pmu_disable(unsigned int module)
  90. {
  91. pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR);
  92. }
  93. EXPORT_SYMBOL(ltq_pmu_disable);
  94. /* enable a hw clock */
  95. static int cgu_enable(struct clk *clk)
  96. {
  97. ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr);
  98. return 0;
  99. }
  100. /* disable a hw clock */
  101. static void cgu_disable(struct clk *clk)
  102. {
  103. ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr);
  104. }
  105. /* enable a clock gate */
  106. static int pmu_enable(struct clk *clk)
  107. {
  108. int retry = 1000000;
  109. pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits,
  110. PWDCR(clk->module));
  111. do {} while (--retry && (pmu_r32(PWDSR(clk->module)) & clk->bits));
  112. if (!retry)
  113. panic("activating PMU module failed!\n");
  114. return 0;
  115. }
  116. /* disable a clock gate */
  117. static void pmu_disable(struct clk *clk)
  118. {
  119. pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits,
  120. PWDCR(clk->module));
  121. }
  122. /* the pci enable helper */
  123. static int pci_enable(struct clk *clk)
  124. {
  125. unsigned int val = ltq_cgu_r32(ifccr);
  126. /* set bus clock speed */
  127. if (of_machine_is_compatible("lantiq,ar9") ||
  128. of_machine_is_compatible("lantiq,vr9")) {
  129. val &= ~0x1f00000;
  130. if (clk->rate == CLOCK_33M)
  131. val |= 0xe00000;
  132. else
  133. val |= 0x700000; /* 62.5M */
  134. } else {
  135. val &= ~0xf00000;
  136. if (clk->rate == CLOCK_33M)
  137. val |= 0x800000;
  138. else
  139. val |= 0x400000; /* 62.5M */
  140. }
  141. ltq_cgu_w32(val, ifccr);
  142. pmu_enable(clk);
  143. return 0;
  144. }
  145. /* enable the external clock as a source */
  146. static int pci_ext_enable(struct clk *clk)
  147. {
  148. ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr);
  149. ltq_cgu_w32((1 << 30), pcicr);
  150. return 0;
  151. }
  152. /* disable the external clock as a source */
  153. static void pci_ext_disable(struct clk *clk)
  154. {
  155. ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr);
  156. ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
  157. }
  158. /* enable a clockout source */
  159. static int clkout_enable(struct clk *clk)
  160. {
  161. int i;
  162. /* get the correct rate */
  163. for (i = 0; i < 4; i++) {
  164. if (clk->rates[i] == clk->rate) {
  165. int shift = 14 - (2 * clk->module);
  166. int enable = 7 - clk->module;
  167. unsigned int val = ltq_cgu_r32(ifccr);
  168. val &= ~(3 << shift);
  169. val |= i << shift;
  170. val |= enable;
  171. ltq_cgu_w32(val, ifccr);
  172. return 0;
  173. }
  174. }
  175. return -1;
  176. }
  177. /* manage the clock gates via PMU */
  178. static void clkdev_add_pmu(const char *dev, const char *con,
  179. unsigned int module, unsigned int bits)
  180. {
  181. struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
  182. clk->cl.dev_id = dev;
  183. clk->cl.con_id = con;
  184. clk->cl.clk = clk;
  185. clk->enable = pmu_enable;
  186. clk->disable = pmu_disable;
  187. clk->module = module;
  188. clk->bits = bits;
  189. clkdev_add(&clk->cl);
  190. }
  191. /* manage the clock generator */
  192. static void clkdev_add_cgu(const char *dev, const char *con,
  193. unsigned int bits)
  194. {
  195. struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
  196. clk->cl.dev_id = dev;
  197. clk->cl.con_id = con;
  198. clk->cl.clk = clk;
  199. clk->enable = cgu_enable;
  200. clk->disable = cgu_disable;
  201. clk->bits = bits;
  202. clkdev_add(&clk->cl);
  203. }
  204. /* pci needs its own enable function as the setup is a bit more complex */
  205. static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0};
  206. static void clkdev_add_pci(void)
  207. {
  208. struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
  209. struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
  210. /* main pci clock */
  211. clk->cl.dev_id = "17000000.pci";
  212. clk->cl.con_id = NULL;
  213. clk->cl.clk = clk;
  214. clk->rate = CLOCK_33M;
  215. clk->rates = valid_pci_rates;
  216. clk->enable = pci_enable;
  217. clk->disable = pmu_disable;
  218. clk->module = 0;
  219. clk->bits = PMU_PCI;
  220. clkdev_add(&clk->cl);
  221. /* use internal/external bus clock */
  222. clk_ext->cl.dev_id = "17000000.pci";
  223. clk_ext->cl.con_id = "external";
  224. clk_ext->cl.clk = clk_ext;
  225. clk_ext->enable = pci_ext_enable;
  226. clk_ext->disable = pci_ext_disable;
  227. clkdev_add(&clk_ext->cl);
  228. }
  229. /* xway socs can generate clocks on gpio pins */
  230. static unsigned long valid_clkout_rates[4][5] = {
  231. {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0},
  232. {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0},
  233. {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0},
  234. {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0},
  235. };
  236. static void clkdev_add_clkout(void)
  237. {
  238. int i;
  239. for (i = 0; i < 4; i++) {
  240. struct clk *clk;
  241. char *name;
  242. name = kzalloc(sizeof("clkout0"), GFP_KERNEL);
  243. sprintf(name, "clkout%d", i);
  244. clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
  245. clk->cl.dev_id = "1f103000.cgu";
  246. clk->cl.con_id = name;
  247. clk->cl.clk = clk;
  248. clk->rate = 0;
  249. clk->rates = valid_clkout_rates[i];
  250. clk->enable = clkout_enable;
  251. clk->module = i;
  252. clkdev_add(&clk->cl);
  253. }
  254. }
  255. /* bring up all register ranges that we need for basic system control */
  256. void __init ltq_soc_init(void)
  257. {
  258. struct resource res_pmu, res_cgu, res_ebu;
  259. struct device_node *np_pmu =
  260. of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway");
  261. struct device_node *np_cgu =
  262. of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway");
  263. struct device_node *np_ebu =
  264. of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway");
  265. /* check if all the core register ranges are available */
  266. if (!np_pmu || !np_cgu || !np_ebu)
  267. panic("Failed to load core nodes from devicetree");
  268. if (of_address_to_resource(np_pmu, 0, &res_pmu) ||
  269. of_address_to_resource(np_cgu, 0, &res_cgu) ||
  270. of_address_to_resource(np_ebu, 0, &res_ebu))
  271. panic("Failed to get core resources");
  272. if ((request_mem_region(res_pmu.start, resource_size(&res_pmu),
  273. res_pmu.name) < 0) ||
  274. (request_mem_region(res_cgu.start, resource_size(&res_cgu),
  275. res_cgu.name) < 0) ||
  276. (request_mem_region(res_ebu.start, resource_size(&res_ebu),
  277. res_ebu.name) < 0))
  278. pr_err("Failed to request core reources");
  279. pmu_membase = ioremap_nocache(res_pmu.start, resource_size(&res_pmu));
  280. ltq_cgu_membase = ioremap_nocache(res_cgu.start,
  281. resource_size(&res_cgu));
  282. ltq_ebu_membase = ioremap_nocache(res_ebu.start,
  283. resource_size(&res_ebu));
  284. if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
  285. panic("Failed to remap core resources");
  286. /* make sure to unprotect the memory region where flash is located */
  287. ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
  288. /* add our generic xway clocks */
  289. clkdev_add_pmu("10000000.fpi", NULL, 0, PMU_FPI);
  290. clkdev_add_pmu("1e100400.serial", NULL, 0, PMU_ASC0);
  291. clkdev_add_pmu("1e100a00.gptu", NULL, 0, PMU_GPT);
  292. clkdev_add_pmu("1e100bb0.stp", NULL, 0, PMU_STP);
  293. clkdev_add_pmu("1e104100.dma", NULL, 0, PMU_DMA);
  294. clkdev_add_pmu("1e100800.spi", NULL, 0, PMU_SPI);
  295. clkdev_add_pmu("1e105300.ebu", NULL, 0, PMU_EBU);
  296. clkdev_add_clkout();
  297. /* add the soc dependent clocks */
  298. if (of_machine_is_compatible("lantiq,vr9")) {
  299. ifccr = CGU_IFCCR_VR9;
  300. pcicr = CGU_PCICR_VR9;
  301. } else {
  302. clkdev_add_pmu("1e180000.etop", NULL, 0, PMU_PPE);
  303. }
  304. if (!of_machine_is_compatible("lantiq,ase")) {
  305. clkdev_add_pmu("1e100c00.serial", NULL, 0, PMU_ASC1);
  306. clkdev_add_pci();
  307. }
  308. if (of_machine_is_compatible("lantiq,ase")) {
  309. if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
  310. clkdev_add_static(CLOCK_266M, CLOCK_133M,
  311. CLOCK_133M, CLOCK_266M);
  312. else
  313. clkdev_add_static(CLOCK_133M, CLOCK_133M,
  314. CLOCK_133M, CLOCK_133M);
  315. clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY),
  316. clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY);
  317. } else if (of_machine_is_compatible("lantiq,vr9")) {
  318. clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
  319. ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
  320. clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY);
  321. clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK);
  322. clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI);
  323. clkdev_add_pmu("1d900000.pcie", "pdi", 1, PMU1_PCIE_PDI);
  324. clkdev_add_pmu("1d900000.pcie", "ctl", 1, PMU1_PCIE_CTL);
  325. clkdev_add_pmu("1d900000.pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
  326. clkdev_add_pmu("1e108000.eth", NULL, 0,
  327. PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
  328. PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
  329. PMU_PPE_QSB | PMU_PPE_TOP);
  330. clkdev_add_pmu("1f203000.rcu", "gphy", 0, PMU_GPHY);
  331. } else if (of_machine_is_compatible("lantiq,ar9")) {
  332. clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
  333. ltq_ar9_fpi_hz(), CLOCK_250M);
  334. clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH);
  335. } else {
  336. clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
  337. ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
  338. }
  339. }