octeon-platform.c 17 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2004-2011 Cavium Networks
  7. * Copyright (C) 2008 Wind River Systems
  8. */
  9. #include <linux/init.h>
  10. #include <linux/irq.h>
  11. #include <linux/i2c.h>
  12. #include <linux/usb.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/module.h>
  15. #include <linux/slab.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/of_platform.h>
  18. #include <linux/of_fdt.h>
  19. #include <linux/libfdt.h>
  20. #include <asm/octeon/octeon.h>
  21. #include <asm/octeon/cvmx-rnm-defs.h>
  22. #include <asm/octeon/cvmx-helper.h>
  23. #include <asm/octeon/cvmx-helper-board.h>
  24. /* Octeon Random Number Generator. */
  25. static int __init octeon_rng_device_init(void)
  26. {
  27. struct platform_device *pd;
  28. int ret = 0;
  29. struct resource rng_resources[] = {
  30. {
  31. .flags = IORESOURCE_MEM,
  32. .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
  33. .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
  34. }, {
  35. .flags = IORESOURCE_MEM,
  36. .start = cvmx_build_io_address(8, 0),
  37. .end = cvmx_build_io_address(8, 0) + 0x7
  38. }
  39. };
  40. pd = platform_device_alloc("octeon_rng", -1);
  41. if (!pd) {
  42. ret = -ENOMEM;
  43. goto out;
  44. }
  45. ret = platform_device_add_resources(pd, rng_resources,
  46. ARRAY_SIZE(rng_resources));
  47. if (ret)
  48. goto fail;
  49. ret = platform_device_add(pd);
  50. if (ret)
  51. goto fail;
  52. return ret;
  53. fail:
  54. platform_device_put(pd);
  55. out:
  56. return ret;
  57. }
  58. device_initcall(octeon_rng_device_init);
  59. #ifdef CONFIG_USB
  60. static int __init octeon_ehci_device_init(void)
  61. {
  62. struct platform_device *pd;
  63. int ret = 0;
  64. struct resource usb_resources[] = {
  65. {
  66. .flags = IORESOURCE_MEM,
  67. }, {
  68. .flags = IORESOURCE_IRQ,
  69. }
  70. };
  71. /* Only Octeon2 has ehci/ohci */
  72. if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
  73. return 0;
  74. if (octeon_is_simulation() || usb_disabled())
  75. return 0; /* No USB in the simulator. */
  76. pd = platform_device_alloc("octeon-ehci", 0);
  77. if (!pd) {
  78. ret = -ENOMEM;
  79. goto out;
  80. }
  81. usb_resources[0].start = 0x00016F0000000000ULL;
  82. usb_resources[0].end = usb_resources[0].start + 0x100;
  83. usb_resources[1].start = OCTEON_IRQ_USB0;
  84. usb_resources[1].end = OCTEON_IRQ_USB0;
  85. ret = platform_device_add_resources(pd, usb_resources,
  86. ARRAY_SIZE(usb_resources));
  87. if (ret)
  88. goto fail;
  89. ret = platform_device_add(pd);
  90. if (ret)
  91. goto fail;
  92. return ret;
  93. fail:
  94. platform_device_put(pd);
  95. out:
  96. return ret;
  97. }
  98. device_initcall(octeon_ehci_device_init);
  99. static int __init octeon_ohci_device_init(void)
  100. {
  101. struct platform_device *pd;
  102. int ret = 0;
  103. struct resource usb_resources[] = {
  104. {
  105. .flags = IORESOURCE_MEM,
  106. }, {
  107. .flags = IORESOURCE_IRQ,
  108. }
  109. };
  110. /* Only Octeon2 has ehci/ohci */
  111. if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
  112. return 0;
  113. if (octeon_is_simulation() || usb_disabled())
  114. return 0; /* No USB in the simulator. */
  115. pd = platform_device_alloc("octeon-ohci", 0);
  116. if (!pd) {
  117. ret = -ENOMEM;
  118. goto out;
  119. }
  120. usb_resources[0].start = 0x00016F0000000400ULL;
  121. usb_resources[0].end = usb_resources[0].start + 0x100;
  122. usb_resources[1].start = OCTEON_IRQ_USB0;
  123. usb_resources[1].end = OCTEON_IRQ_USB0;
  124. ret = platform_device_add_resources(pd, usb_resources,
  125. ARRAY_SIZE(usb_resources));
  126. if (ret)
  127. goto fail;
  128. ret = platform_device_add(pd);
  129. if (ret)
  130. goto fail;
  131. return ret;
  132. fail:
  133. platform_device_put(pd);
  134. out:
  135. return ret;
  136. }
  137. device_initcall(octeon_ohci_device_init);
  138. #endif /* CONFIG_USB */
  139. static struct of_device_id __initdata octeon_ids[] = {
  140. { .compatible = "simple-bus", },
  141. { .compatible = "cavium,octeon-6335-uctl", },
  142. { .compatible = "cavium,octeon-3860-bootbus", },
  143. { .compatible = "cavium,mdio-mux", },
  144. { .compatible = "gpio-leds", },
  145. {},
  146. };
  147. static bool __init octeon_has_88e1145(void)
  148. {
  149. return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
  150. !OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
  151. !OCTEON_IS_MODEL(OCTEON_CN56XX);
  152. }
  153. static void __init octeon_fdt_set_phy(int eth, int phy_addr)
  154. {
  155. const __be32 *phy_handle;
  156. const __be32 *alt_phy_handle;
  157. const __be32 *reg;
  158. u32 phandle;
  159. int phy;
  160. int alt_phy;
  161. const char *p;
  162. int current_len;
  163. char new_name[20];
  164. phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
  165. if (!phy_handle)
  166. return;
  167. phandle = be32_to_cpup(phy_handle);
  168. phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);
  169. alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
  170. if (alt_phy_handle) {
  171. u32 alt_phandle = be32_to_cpup(alt_phy_handle);
  172. alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
  173. } else {
  174. alt_phy = -1;
  175. }
  176. if (phy_addr < 0 || phy < 0) {
  177. /* Delete the PHY things */
  178. fdt_nop_property(initial_boot_params, eth, "phy-handle");
  179. /* This one may fail */
  180. fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
  181. if (phy >= 0)
  182. fdt_nop_node(initial_boot_params, phy);
  183. if (alt_phy >= 0)
  184. fdt_nop_node(initial_boot_params, alt_phy);
  185. return;
  186. }
  187. if (phy_addr >= 256 && alt_phy > 0) {
  188. const struct fdt_property *phy_prop;
  189. struct fdt_property *alt_prop;
  190. u32 phy_handle_name;
  191. /* Use the alt phy node instead.*/
  192. phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
  193. phy_handle_name = phy_prop->nameoff;
  194. fdt_nop_node(initial_boot_params, phy);
  195. fdt_nop_property(initial_boot_params, eth, "phy-handle");
  196. alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
  197. alt_prop->nameoff = phy_handle_name;
  198. phy = alt_phy;
  199. }
  200. phy_addr &= 0xff;
  201. if (octeon_has_88e1145()) {
  202. fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
  203. memset(new_name, 0, sizeof(new_name));
  204. strcpy(new_name, "marvell,88e1145");
  205. p = fdt_getprop(initial_boot_params, phy, "compatible",
  206. &current_len);
  207. if (p && current_len >= strlen(new_name))
  208. fdt_setprop_inplace(initial_boot_params, phy,
  209. "compatible", new_name, current_len);
  210. }
  211. reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
  212. if (phy_addr == be32_to_cpup(reg))
  213. return;
  214. fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);
  215. snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);
  216. p = fdt_get_name(initial_boot_params, phy, &current_len);
  217. if (p && current_len == strlen(new_name))
  218. fdt_set_name(initial_boot_params, phy, new_name);
  219. else
  220. pr_err("Error: could not rename ethernet phy: <%s>", p);
  221. }
  222. static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
  223. {
  224. u8 new_mac[6];
  225. u64 mac = *pmac;
  226. int r;
  227. new_mac[0] = (mac >> 40) & 0xff;
  228. new_mac[1] = (mac >> 32) & 0xff;
  229. new_mac[2] = (mac >> 24) & 0xff;
  230. new_mac[3] = (mac >> 16) & 0xff;
  231. new_mac[4] = (mac >> 8) & 0xff;
  232. new_mac[5] = mac & 0xff;
  233. r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
  234. new_mac, sizeof(new_mac));
  235. if (r) {
  236. pr_err("Setting \"local-mac-address\" failed %d", r);
  237. return;
  238. }
  239. *pmac = mac + 1;
  240. }
  241. static void __init octeon_fdt_rm_ethernet(int node)
  242. {
  243. const __be32 *phy_handle;
  244. phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
  245. if (phy_handle) {
  246. u32 ph = be32_to_cpup(phy_handle);
  247. int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
  248. if (p >= 0)
  249. fdt_nop_node(initial_boot_params, p);
  250. }
  251. fdt_nop_node(initial_boot_params, node);
  252. }
  253. static void __init octeon_fdt_pip_port(int iface, int i, int p, int max, u64 *pmac)
  254. {
  255. char name_buffer[20];
  256. int eth;
  257. int phy_addr;
  258. int ipd_port;
  259. snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
  260. eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
  261. if (eth < 0)
  262. return;
  263. if (p > max) {
  264. pr_debug("Deleting port %x:%x\n", i, p);
  265. octeon_fdt_rm_ethernet(eth);
  266. return;
  267. }
  268. if (OCTEON_IS_MODEL(OCTEON_CN68XX))
  269. ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
  270. else
  271. ipd_port = 16 * i + p;
  272. phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
  273. octeon_fdt_set_phy(eth, phy_addr);
  274. octeon_fdt_set_mac_addr(eth, pmac);
  275. }
  276. static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac)
  277. {
  278. char name_buffer[20];
  279. int iface;
  280. int p;
  281. int count;
  282. count = cvmx_helper_interface_enumerate(idx);
  283. snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
  284. iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
  285. if (iface < 0)
  286. return;
  287. for (p = 0; p < 16; p++)
  288. octeon_fdt_pip_port(iface, idx, p, count - 1, pmac);
  289. }
  290. int __init octeon_prune_device_tree(void)
  291. {
  292. int i, max_port, uart_mask;
  293. const char *pip_path;
  294. const char *alias_prop;
  295. char name_buffer[20];
  296. int aliases;
  297. u64 mac_addr_base;
  298. if (fdt_check_header(initial_boot_params))
  299. panic("Corrupt Device Tree.");
  300. aliases = fdt_path_offset(initial_boot_params, "/aliases");
  301. if (aliases < 0) {
  302. pr_err("Error: No /aliases node in device tree.");
  303. return -EINVAL;
  304. }
  305. mac_addr_base =
  306. ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 |
  307. ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 |
  308. ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 |
  309. ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 |
  310. ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 |
  311. (octeon_bootinfo->mac_addr_base[5] & 0xffull);
  312. if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
  313. max_port = 2;
  314. else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
  315. max_port = 1;
  316. else
  317. max_port = 0;
  318. if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
  319. max_port = 0;
  320. for (i = 0; i < 2; i++) {
  321. int mgmt;
  322. snprintf(name_buffer, sizeof(name_buffer),
  323. "mix%d", i);
  324. alias_prop = fdt_getprop(initial_boot_params, aliases,
  325. name_buffer, NULL);
  326. if (alias_prop) {
  327. mgmt = fdt_path_offset(initial_boot_params, alias_prop);
  328. if (mgmt < 0)
  329. continue;
  330. if (i >= max_port) {
  331. pr_debug("Deleting mix%d\n", i);
  332. octeon_fdt_rm_ethernet(mgmt);
  333. fdt_nop_property(initial_boot_params, aliases,
  334. name_buffer);
  335. } else {
  336. int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
  337. octeon_fdt_set_phy(mgmt, phy_addr);
  338. octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
  339. }
  340. }
  341. }
  342. pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
  343. if (pip_path) {
  344. int pip = fdt_path_offset(initial_boot_params, pip_path);
  345. if (pip >= 0)
  346. for (i = 0; i <= 4; i++)
  347. octeon_fdt_pip_iface(pip, i, &mac_addr_base);
  348. }
  349. /* I2C */
  350. if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
  351. OCTEON_IS_MODEL(OCTEON_CN63XX) ||
  352. OCTEON_IS_MODEL(OCTEON_CN68XX) ||
  353. OCTEON_IS_MODEL(OCTEON_CN56XX))
  354. max_port = 2;
  355. else
  356. max_port = 1;
  357. for (i = 0; i < 2; i++) {
  358. int i2c;
  359. snprintf(name_buffer, sizeof(name_buffer),
  360. "twsi%d", i);
  361. alias_prop = fdt_getprop(initial_boot_params, aliases,
  362. name_buffer, NULL);
  363. if (alias_prop) {
  364. i2c = fdt_path_offset(initial_boot_params, alias_prop);
  365. if (i2c < 0)
  366. continue;
  367. if (i >= max_port) {
  368. pr_debug("Deleting twsi%d\n", i);
  369. fdt_nop_node(initial_boot_params, i2c);
  370. fdt_nop_property(initial_boot_params, aliases,
  371. name_buffer);
  372. }
  373. }
  374. }
  375. /* SMI/MDIO */
  376. if (OCTEON_IS_MODEL(OCTEON_CN68XX))
  377. max_port = 4;
  378. else if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
  379. OCTEON_IS_MODEL(OCTEON_CN63XX) ||
  380. OCTEON_IS_MODEL(OCTEON_CN56XX))
  381. max_port = 2;
  382. else
  383. max_port = 1;
  384. for (i = 0; i < 2; i++) {
  385. int i2c;
  386. snprintf(name_buffer, sizeof(name_buffer),
  387. "smi%d", i);
  388. alias_prop = fdt_getprop(initial_boot_params, aliases,
  389. name_buffer, NULL);
  390. if (alias_prop) {
  391. i2c = fdt_path_offset(initial_boot_params, alias_prop);
  392. if (i2c < 0)
  393. continue;
  394. if (i >= max_port) {
  395. pr_debug("Deleting smi%d\n", i);
  396. fdt_nop_node(initial_boot_params, i2c);
  397. fdt_nop_property(initial_boot_params, aliases,
  398. name_buffer);
  399. }
  400. }
  401. }
  402. /* Serial */
  403. uart_mask = 3;
  404. /* Right now CN52XX is the only chip with a third uart */
  405. if (OCTEON_IS_MODEL(OCTEON_CN52XX))
  406. uart_mask |= 4; /* uart2 */
  407. for (i = 0; i < 3; i++) {
  408. int uart;
  409. snprintf(name_buffer, sizeof(name_buffer),
  410. "uart%d", i);
  411. alias_prop = fdt_getprop(initial_boot_params, aliases,
  412. name_buffer, NULL);
  413. if (alias_prop) {
  414. uart = fdt_path_offset(initial_boot_params, alias_prop);
  415. if (uart_mask & (1 << i))
  416. continue;
  417. pr_debug("Deleting uart%d\n", i);
  418. fdt_nop_node(initial_boot_params, uart);
  419. fdt_nop_property(initial_boot_params, aliases,
  420. name_buffer);
  421. }
  422. }
  423. /* Compact Flash */
  424. alias_prop = fdt_getprop(initial_boot_params, aliases,
  425. "cf0", NULL);
  426. if (alias_prop) {
  427. union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
  428. unsigned long base_ptr, region_base, region_size;
  429. unsigned long region1_base = 0;
  430. unsigned long region1_size = 0;
  431. int cs, bootbus;
  432. bool is_16bit = false;
  433. bool is_true_ide = false;
  434. __be32 new_reg[6];
  435. __be32 *ranges;
  436. int len;
  437. int cf = fdt_path_offset(initial_boot_params, alias_prop);
  438. base_ptr = 0;
  439. if (octeon_bootinfo->major_version == 1
  440. && octeon_bootinfo->minor_version >= 1) {
  441. if (octeon_bootinfo->compact_flash_common_base_addr)
  442. base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
  443. } else {
  444. base_ptr = 0x1d000800;
  445. }
  446. if (!base_ptr)
  447. goto no_cf;
  448. /* Find CS0 region. */
  449. for (cs = 0; cs < 8; cs++) {
  450. mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
  451. region_base = mio_boot_reg_cfg.s.base << 16;
  452. region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
  453. if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
  454. && base_ptr < region_base + region_size) {
  455. is_16bit = mio_boot_reg_cfg.s.width;
  456. break;
  457. }
  458. }
  459. if (cs >= 7) {
  460. /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
  461. goto no_cf;
  462. }
  463. if (!(base_ptr & 0xfffful)) {
  464. /*
  465. * Boot loader signals availability of DMA (true_ide
  466. * mode) by setting low order bits of base_ptr to
  467. * zero.
  468. */
  469. /* Asume that CS1 immediately follows. */
  470. mio_boot_reg_cfg.u64 =
  471. cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
  472. region1_base = mio_boot_reg_cfg.s.base << 16;
  473. region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
  474. if (!mio_boot_reg_cfg.s.en)
  475. goto no_cf;
  476. is_true_ide = true;
  477. } else {
  478. fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
  479. fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
  480. if (!is_16bit) {
  481. __be32 width = cpu_to_be32(8);
  482. fdt_setprop_inplace(initial_boot_params, cf,
  483. "cavium,bus-width", &width, sizeof(width));
  484. }
  485. }
  486. new_reg[0] = cpu_to_be32(cs);
  487. new_reg[1] = cpu_to_be32(0);
  488. new_reg[2] = cpu_to_be32(0x10000);
  489. new_reg[3] = cpu_to_be32(cs + 1);
  490. new_reg[4] = cpu_to_be32(0);
  491. new_reg[5] = cpu_to_be32(0x10000);
  492. fdt_setprop_inplace(initial_boot_params, cf,
  493. "reg", new_reg, sizeof(new_reg));
  494. bootbus = fdt_parent_offset(initial_boot_params, cf);
  495. if (bootbus < 0)
  496. goto no_cf;
  497. ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
  498. if (!ranges || len < (5 * 8 * sizeof(__be32)))
  499. goto no_cf;
  500. ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
  501. ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
  502. ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
  503. if (is_true_ide) {
  504. cs++;
  505. ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
  506. ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
  507. ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
  508. }
  509. goto end_cf;
  510. no_cf:
  511. fdt_nop_node(initial_boot_params, cf);
  512. end_cf:
  513. ;
  514. }
  515. /* 8 char LED */
  516. alias_prop = fdt_getprop(initial_boot_params, aliases,
  517. "led0", NULL);
  518. if (alias_prop) {
  519. union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
  520. unsigned long base_ptr, region_base, region_size;
  521. int cs, bootbus;
  522. __be32 new_reg[6];
  523. __be32 *ranges;
  524. int len;
  525. int led = fdt_path_offset(initial_boot_params, alias_prop);
  526. base_ptr = octeon_bootinfo->led_display_base_addr;
  527. if (base_ptr == 0)
  528. goto no_led;
  529. /* Find CS0 region. */
  530. for (cs = 0; cs < 8; cs++) {
  531. mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
  532. region_base = mio_boot_reg_cfg.s.base << 16;
  533. region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
  534. if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
  535. && base_ptr < region_base + region_size)
  536. break;
  537. }
  538. if (cs > 7)
  539. goto no_led;
  540. new_reg[0] = cpu_to_be32(cs);
  541. new_reg[1] = cpu_to_be32(0x20);
  542. new_reg[2] = cpu_to_be32(0x20);
  543. new_reg[3] = cpu_to_be32(cs);
  544. new_reg[4] = cpu_to_be32(0);
  545. new_reg[5] = cpu_to_be32(0x20);
  546. fdt_setprop_inplace(initial_boot_params, led,
  547. "reg", new_reg, sizeof(new_reg));
  548. bootbus = fdt_parent_offset(initial_boot_params, led);
  549. if (bootbus < 0)
  550. goto no_led;
  551. ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
  552. if (!ranges || len < (5 * 8 * sizeof(__be32)))
  553. goto no_led;
  554. ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
  555. ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
  556. ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
  557. goto end_led;
  558. no_led:
  559. fdt_nop_node(initial_boot_params, led);
  560. end_led:
  561. ;
  562. }
  563. /* OHCI/UHCI USB */
  564. alias_prop = fdt_getprop(initial_boot_params, aliases,
  565. "uctl", NULL);
  566. if (alias_prop) {
  567. int uctl = fdt_path_offset(initial_boot_params, alias_prop);
  568. if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
  569. octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
  570. pr_debug("Deleting uctl\n");
  571. fdt_nop_node(initial_boot_params, uctl);
  572. fdt_nop_property(initial_boot_params, aliases, "uctl");
  573. } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E ||
  574. octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
  575. /* Missing "refclk-type" defaults to crystal. */
  576. fdt_nop_property(initial_boot_params, uctl, "refclk-type");
  577. }
  578. }
  579. return 0;
  580. }
  581. static int __init octeon_publish_devices(void)
  582. {
  583. return of_platform_bus_probe(NULL, octeon_ids, NULL);
  584. }
  585. device_initcall(octeon_publish_devices);
  586. MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
  587. MODULE_LICENSE("GPL");
  588. MODULE_DESCRIPTION("Platform driver for Octeon SOC");