ddr2_defs.h 9.6 KB

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  1. #ifndef __ddr2_defs_h
  2. #define __ddr2_defs_h
  3. /*
  4. * This file is autogenerated from
  5. * file: ddr2.r
  6. *
  7. * by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r
  8. * Any changes here will be lost.
  9. *
  10. * -*- buffer-read-only: t -*-
  11. */
  12. /* Main access macros */
  13. #ifndef REG_RD
  14. #define REG_RD( scope, inst, reg ) \
  15. REG_READ( reg_##scope##_##reg, \
  16. (inst) + REG_RD_ADDR_##scope##_##reg )
  17. #endif
  18. #ifndef REG_WR
  19. #define REG_WR( scope, inst, reg, val ) \
  20. REG_WRITE( reg_##scope##_##reg, \
  21. (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  22. #endif
  23. #ifndef REG_RD_VECT
  24. #define REG_RD_VECT( scope, inst, reg, index ) \
  25. REG_READ( reg_##scope##_##reg, \
  26. (inst) + REG_RD_ADDR_##scope##_##reg + \
  27. (index) * STRIDE_##scope##_##reg )
  28. #endif
  29. #ifndef REG_WR_VECT
  30. #define REG_WR_VECT( scope, inst, reg, index, val ) \
  31. REG_WRITE( reg_##scope##_##reg, \
  32. (inst) + REG_WR_ADDR_##scope##_##reg + \
  33. (index) * STRIDE_##scope##_##reg, (val) )
  34. #endif
  35. #ifndef REG_RD_INT
  36. #define REG_RD_INT( scope, inst, reg ) \
  37. REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  38. #endif
  39. #ifndef REG_WR_INT
  40. #define REG_WR_INT( scope, inst, reg, val ) \
  41. REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  42. #endif
  43. #ifndef REG_RD_INT_VECT
  44. #define REG_RD_INT_VECT( scope, inst, reg, index ) \
  45. REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  46. (index) * STRIDE_##scope##_##reg )
  47. #endif
  48. #ifndef REG_WR_INT_VECT
  49. #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  50. REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  51. (index) * STRIDE_##scope##_##reg, (val) )
  52. #endif
  53. #ifndef REG_TYPE_CONV
  54. #define REG_TYPE_CONV( type, orgtype, val ) \
  55. ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  56. #endif
  57. #ifndef reg_page_size
  58. #define reg_page_size 8192
  59. #endif
  60. #ifndef REG_ADDR
  61. #define REG_ADDR( scope, inst, reg ) \
  62. ( (inst) + REG_RD_ADDR_##scope##_##reg )
  63. #endif
  64. #ifndef REG_ADDR_VECT
  65. #define REG_ADDR_VECT( scope, inst, reg, index ) \
  66. ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  67. (index) * STRIDE_##scope##_##reg )
  68. #endif
  69. /* C-code for register scope ddr2 */
  70. /* Register rw_cfg, scope ddr2, type rw */
  71. typedef struct {
  72. unsigned int col_width : 4;
  73. unsigned int nr_banks : 1;
  74. unsigned int bw : 1;
  75. unsigned int nr_ref : 4;
  76. unsigned int ref_interval : 11;
  77. unsigned int odt_ctrl : 2;
  78. unsigned int odt_mem : 1;
  79. unsigned int imp_strength : 1;
  80. unsigned int auto_imp_cal : 1;
  81. unsigned int imp_cal_override : 1;
  82. unsigned int dll_override : 1;
  83. unsigned int dummy1 : 4;
  84. } reg_ddr2_rw_cfg;
  85. #define REG_RD_ADDR_ddr2_rw_cfg 0
  86. #define REG_WR_ADDR_ddr2_rw_cfg 0
  87. /* Register rw_timing, scope ddr2, type rw */
  88. typedef struct {
  89. unsigned int wr : 3;
  90. unsigned int rcd : 3;
  91. unsigned int rp : 3;
  92. unsigned int ras : 4;
  93. unsigned int rfc : 7;
  94. unsigned int rc : 5;
  95. unsigned int rtp : 2;
  96. unsigned int rtw : 3;
  97. unsigned int wtr : 2;
  98. } reg_ddr2_rw_timing;
  99. #define REG_RD_ADDR_ddr2_rw_timing 4
  100. #define REG_WR_ADDR_ddr2_rw_timing 4
  101. /* Register rw_latency, scope ddr2, type rw */
  102. typedef struct {
  103. unsigned int cas : 3;
  104. unsigned int additive : 3;
  105. unsigned int dummy1 : 26;
  106. } reg_ddr2_rw_latency;
  107. #define REG_RD_ADDR_ddr2_rw_latency 8
  108. #define REG_WR_ADDR_ddr2_rw_latency 8
  109. /* Register rw_phy_cfg, scope ddr2, type rw */
  110. typedef struct {
  111. unsigned int en : 1;
  112. unsigned int dummy1 : 31;
  113. } reg_ddr2_rw_phy_cfg;
  114. #define REG_RD_ADDR_ddr2_rw_phy_cfg 12
  115. #define REG_WR_ADDR_ddr2_rw_phy_cfg 12
  116. /* Register rw_phy_ctrl, scope ddr2, type rw */
  117. typedef struct {
  118. unsigned int rst : 1;
  119. unsigned int cal_rst : 1;
  120. unsigned int cal_start : 1;
  121. unsigned int dummy1 : 29;
  122. } reg_ddr2_rw_phy_ctrl;
  123. #define REG_RD_ADDR_ddr2_rw_phy_ctrl 16
  124. #define REG_WR_ADDR_ddr2_rw_phy_ctrl 16
  125. /* Register rw_ctrl, scope ddr2, type rw */
  126. typedef struct {
  127. unsigned int mrs_data : 16;
  128. unsigned int cmd : 8;
  129. unsigned int dummy1 : 8;
  130. } reg_ddr2_rw_ctrl;
  131. #define REG_RD_ADDR_ddr2_rw_ctrl 20
  132. #define REG_WR_ADDR_ddr2_rw_ctrl 20
  133. /* Register rw_pwr_down, scope ddr2, type rw */
  134. typedef struct {
  135. unsigned int self_ref : 2;
  136. unsigned int phy_en : 1;
  137. unsigned int dummy1 : 29;
  138. } reg_ddr2_rw_pwr_down;
  139. #define REG_RD_ADDR_ddr2_rw_pwr_down 24
  140. #define REG_WR_ADDR_ddr2_rw_pwr_down 24
  141. /* Register r_stat, scope ddr2, type r */
  142. typedef struct {
  143. unsigned int dll_lock : 1;
  144. unsigned int dll_delay_code : 7;
  145. unsigned int imp_cal_done : 1;
  146. unsigned int imp_cal_fault : 1;
  147. unsigned int cal_imp_pu : 4;
  148. unsigned int cal_imp_pd : 4;
  149. unsigned int dummy1 : 14;
  150. } reg_ddr2_r_stat;
  151. #define REG_RD_ADDR_ddr2_r_stat 28
  152. /* Register rw_imp_ctrl, scope ddr2, type rw */
  153. typedef struct {
  154. unsigned int imp_pu : 4;
  155. unsigned int imp_pd : 4;
  156. unsigned int dummy1 : 24;
  157. } reg_ddr2_rw_imp_ctrl;
  158. #define REG_RD_ADDR_ddr2_rw_imp_ctrl 32
  159. #define REG_WR_ADDR_ddr2_rw_imp_ctrl 32
  160. #define STRIDE_ddr2_rw_dll_ctrl 4
  161. /* Register rw_dll_ctrl, scope ddr2, type rw */
  162. typedef struct {
  163. unsigned int mode : 1;
  164. unsigned int clk_delay : 7;
  165. unsigned int dummy1 : 24;
  166. } reg_ddr2_rw_dll_ctrl;
  167. #define REG_RD_ADDR_ddr2_rw_dll_ctrl 36
  168. #define REG_WR_ADDR_ddr2_rw_dll_ctrl 36
  169. #define STRIDE_ddr2_rw_dqs_dll_ctrl 4
  170. /* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
  171. typedef struct {
  172. unsigned int dqs90_delay : 7;
  173. unsigned int dqs180_delay : 7;
  174. unsigned int dqs270_delay : 7;
  175. unsigned int dqs360_delay : 7;
  176. unsigned int dummy1 : 4;
  177. } reg_ddr2_rw_dqs_dll_ctrl;
  178. #define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52
  179. #define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52
  180. /* Constants */
  181. enum {
  182. regk_ddr2_al0 = 0x00000000,
  183. regk_ddr2_al1 = 0x00000008,
  184. regk_ddr2_al2 = 0x00000010,
  185. regk_ddr2_al3 = 0x00000018,
  186. regk_ddr2_al4 = 0x00000020,
  187. regk_ddr2_auto = 0x00000003,
  188. regk_ddr2_bank4 = 0x00000000,
  189. regk_ddr2_bank8 = 0x00000001,
  190. regk_ddr2_bl4 = 0x00000002,
  191. regk_ddr2_bl8 = 0x00000003,
  192. regk_ddr2_bt_il = 0x00000008,
  193. regk_ddr2_bt_seq = 0x00000000,
  194. regk_ddr2_bw16 = 0x00000001,
  195. regk_ddr2_bw32 = 0x00000000,
  196. regk_ddr2_cas2 = 0x00000020,
  197. regk_ddr2_cas3 = 0x00000030,
  198. regk_ddr2_cas4 = 0x00000040,
  199. regk_ddr2_cas5 = 0x00000050,
  200. regk_ddr2_deselect = 0x000000c0,
  201. regk_ddr2_dic_weak = 0x00000002,
  202. regk_ddr2_direct = 0x00000001,
  203. regk_ddr2_dis = 0x00000000,
  204. regk_ddr2_dll_dis = 0x00000001,
  205. regk_ddr2_dll_en = 0x00000000,
  206. regk_ddr2_dll_rst = 0x00000100,
  207. regk_ddr2_emrs = 0x00000081,
  208. regk_ddr2_emrs2 = 0x00000082,
  209. regk_ddr2_emrs3 = 0x00000083,
  210. regk_ddr2_full = 0x00000001,
  211. regk_ddr2_hi_ref_rate = 0x00000080,
  212. regk_ddr2_mrs = 0x00000080,
  213. regk_ddr2_no = 0x00000000,
  214. regk_ddr2_nop = 0x000000b8,
  215. regk_ddr2_ocd_adj = 0x00000200,
  216. regk_ddr2_ocd_default = 0x00000380,
  217. regk_ddr2_ocd_drive0 = 0x00000100,
  218. regk_ddr2_ocd_drive1 = 0x00000080,
  219. regk_ddr2_ocd_exit = 0x00000000,
  220. regk_ddr2_odt_dis = 0x00000000,
  221. regk_ddr2_offs = 0x00000000,
  222. regk_ddr2_pre = 0x00000090,
  223. regk_ddr2_pre_all = 0x00000400,
  224. regk_ddr2_pwr_down_fast = 0x00000000,
  225. regk_ddr2_pwr_down_slow = 0x00001000,
  226. regk_ddr2_ref = 0x00000088,
  227. regk_ddr2_rtt150 = 0x00000040,
  228. regk_ddr2_rtt50 = 0x00000044,
  229. regk_ddr2_rtt75 = 0x00000004,
  230. regk_ddr2_rw_cfg_default = 0x00186000,
  231. regk_ddr2_rw_dll_ctrl_default = 0x00000000,
  232. regk_ddr2_rw_dll_ctrl_size = 0x00000004,
  233. regk_ddr2_rw_dqs_dll_ctrl_default = 0x00000000,
  234. regk_ddr2_rw_dqs_dll_ctrl_size = 0x00000004,
  235. regk_ddr2_rw_latency_default = 0x00000000,
  236. regk_ddr2_rw_phy_cfg_default = 0x00000000,
  237. regk_ddr2_rw_pwr_down_default = 0x00000000,
  238. regk_ddr2_rw_timing_default = 0x00000000,
  239. regk_ddr2_s1Gb = 0x0000001a,
  240. regk_ddr2_s256Mb = 0x0000000f,
  241. regk_ddr2_s2Gb = 0x00000027,
  242. regk_ddr2_s4Gb = 0x00000042,
  243. regk_ddr2_s512Mb = 0x00000015,
  244. regk_ddr2_temp0_85 = 0x00000618,
  245. regk_ddr2_temp85_95 = 0x0000030c,
  246. regk_ddr2_term150 = 0x00000002,
  247. regk_ddr2_term50 = 0x00000003,
  248. regk_ddr2_term75 = 0x00000001,
  249. regk_ddr2_test = 0x00000080,
  250. regk_ddr2_weak = 0x00000000,
  251. regk_ddr2_wr2 = 0x00000200,
  252. regk_ddr2_wr3 = 0x00000400,
  253. regk_ddr2_yes = 0x00000001
  254. };
  255. #endif /* __ddr2_defs_h */