cpuidle-tegra30.c 4.3 KB

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  1. /*
  2. * CPU idle driver for Tegra CPUs
  3. *
  4. * Copyright (c) 2010-2012, NVIDIA Corporation.
  5. * Copyright (c) 2011 Google, Inc.
  6. * Author: Colin Cross <ccross@android.com>
  7. * Gary King <gking@nvidia.com>
  8. *
  9. * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful, but WITHOUT
  17. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  19. * more details.
  20. */
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/cpuidle.h>
  24. #include <linux/cpu_pm.h>
  25. #include <linux/clockchips.h>
  26. #include <linux/clk/tegra.h>
  27. #include <asm/cpuidle.h>
  28. #include <asm/proc-fns.h>
  29. #include <asm/suspend.h>
  30. #include <asm/smp_plat.h>
  31. #include "pm.h"
  32. #include "sleep.h"
  33. #ifdef CONFIG_PM_SLEEP
  34. static int tegra30_idle_lp2(struct cpuidle_device *dev,
  35. struct cpuidle_driver *drv,
  36. int index);
  37. #endif
  38. static struct cpuidle_driver tegra_idle_driver = {
  39. .name = "tegra_idle",
  40. .owner = THIS_MODULE,
  41. .en_core_tk_irqen = 1,
  42. #ifdef CONFIG_PM_SLEEP
  43. .state_count = 2,
  44. #else
  45. .state_count = 1,
  46. #endif
  47. .states = {
  48. [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
  49. #ifdef CONFIG_PM_SLEEP
  50. [1] = {
  51. .enter = tegra30_idle_lp2,
  52. .exit_latency = 2000,
  53. .target_residency = 2200,
  54. .power_usage = 0,
  55. .flags = CPUIDLE_FLAG_TIME_VALID,
  56. .name = "powered-down",
  57. .desc = "CPU power gated",
  58. },
  59. #endif
  60. },
  61. };
  62. static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
  63. #ifdef CONFIG_PM_SLEEP
  64. static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
  65. struct cpuidle_driver *drv,
  66. int index)
  67. {
  68. struct cpuidle_state *state = &drv->states[index];
  69. u32 cpu_on_time = state->exit_latency;
  70. u32 cpu_off_time = state->target_residency - state->exit_latency;
  71. /* All CPUs entering LP2 is not working.
  72. * Don't let CPU0 enter LP2 when any secondary CPU is online.
  73. */
  74. if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) {
  75. cpu_do_idle();
  76. return false;
  77. }
  78. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
  79. tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
  80. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
  81. return true;
  82. }
  83. #ifdef CONFIG_SMP
  84. static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
  85. struct cpuidle_driver *drv,
  86. int index)
  87. {
  88. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
  89. smp_wmb();
  90. save_cpu_arch_register();
  91. cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
  92. restore_cpu_arch_register();
  93. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
  94. return true;
  95. }
  96. #else
  97. static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
  98. struct cpuidle_driver *drv,
  99. int index)
  100. {
  101. return true;
  102. }
  103. #endif
  104. static int tegra30_idle_lp2(struct cpuidle_device *dev,
  105. struct cpuidle_driver *drv,
  106. int index)
  107. {
  108. u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
  109. bool entered_lp2 = false;
  110. bool last_cpu;
  111. local_fiq_disable();
  112. last_cpu = tegra_set_cpu_in_lp2(cpu);
  113. cpu_pm_enter();
  114. if (cpu == 0) {
  115. if (last_cpu)
  116. entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
  117. index);
  118. else
  119. cpu_do_idle();
  120. } else {
  121. entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
  122. }
  123. cpu_pm_exit();
  124. tegra_clear_cpu_in_lp2(cpu);
  125. local_fiq_enable();
  126. smp_rmb();
  127. return (entered_lp2) ? index : 0;
  128. }
  129. #endif
  130. int __init tegra30_cpuidle_init(void)
  131. {
  132. int ret;
  133. unsigned int cpu;
  134. struct cpuidle_device *dev;
  135. struct cpuidle_driver *drv = &tegra_idle_driver;
  136. #ifdef CONFIG_PM_SLEEP
  137. tegra_tear_down_cpu = tegra30_tear_down_cpu;
  138. #endif
  139. ret = cpuidle_register_driver(&tegra_idle_driver);
  140. if (ret) {
  141. pr_err("CPUidle driver registration failed\n");
  142. return ret;
  143. }
  144. for_each_possible_cpu(cpu) {
  145. dev = &per_cpu(tegra_idle_device, cpu);
  146. dev->cpu = cpu;
  147. dev->state_count = drv->state_count;
  148. ret = cpuidle_register_device(dev);
  149. if (ret) {
  150. pr_err("CPU%u: CPUidle device registration failed\n",
  151. cpu);
  152. return ret;
  153. }
  154. }
  155. return 0;
  156. }