spear3xx.c 3.0 KB

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  1. /*
  2. * arch/arm/mach-spear3xx/spear3xx.c
  3. *
  4. * SPEAr3XX machines common source file
  5. *
  6. * Copyright (C) 2009-2012 ST Microelectronics
  7. * Viresh Kumar <viresh.linux@gmail.com>
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without any
  11. * warranty of any kind, whether express or implied.
  12. */
  13. #define pr_fmt(fmt) "SPEAr3xx: " fmt
  14. #include <linux/amba/pl022.h>
  15. #include <linux/amba/pl08x.h>
  16. #include <linux/io.h>
  17. #include <plat/pl080.h>
  18. #include <mach/generic.h>
  19. #include <mach/spear.h>
  20. /* ssp device registration */
  21. struct pl022_ssp_controller pl022_plat_data = {
  22. .bus_id = 0,
  23. .enable_dma = 1,
  24. .dma_filter = pl08x_filter_id,
  25. .dma_tx_param = "ssp0_tx",
  26. .dma_rx_param = "ssp0_rx",
  27. /*
  28. * This is number of spi devices that can be connected to spi. There are
  29. * two type of chipselects on which slave devices can work. One is chip
  30. * select provided by spi masters other is controlled through external
  31. * gpio's. We can't use chipselect provided from spi master (because as
  32. * soon as FIFO becomes empty, CS is disabled and transfer ends). So
  33. * this number now depends on number of gpios available for spi. each
  34. * slave on each master requires a separate gpio pin.
  35. */
  36. .num_chipselect = 2,
  37. };
  38. /* dmac device registration */
  39. struct pl08x_platform_data pl080_plat_data = {
  40. .memcpy_channel = {
  41. .bus_id = "memcpy",
  42. .cctl_memcpy =
  43. (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
  44. PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
  45. PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
  46. PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
  47. PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
  48. PL080_CONTROL_PROT_SYS),
  49. },
  50. .lli_buses = PL08X_AHB1,
  51. .mem_buses = PL08X_AHB1,
  52. .get_signal = pl080_get_signal,
  53. .put_signal = pl080_put_signal,
  54. };
  55. /*
  56. * Following will create 16MB static virtual/physical mappings
  57. * PHYSICAL VIRTUAL
  58. * 0xD0000000 0xFD000000
  59. * 0xFC000000 0xFC000000
  60. */
  61. struct map_desc spear3xx_io_desc[] __initdata = {
  62. {
  63. .virtual = VA_SPEAR3XX_ICM1_2_BASE,
  64. .pfn = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
  65. .length = SZ_16M,
  66. .type = MT_DEVICE
  67. }, {
  68. .virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
  69. .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
  70. .length = SZ_16M,
  71. .type = MT_DEVICE
  72. },
  73. };
  74. /* This will create static memory mapping for selected devices */
  75. void __init spear3xx_map_io(void)
  76. {
  77. iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
  78. }
  79. void __init spear3xx_timer_init(void)
  80. {
  81. char pclk_name[] = "pll3_clk";
  82. struct clk *gpt_clk, *pclk;
  83. spear3xx_clk_init();
  84. /* get the system timer clock */
  85. gpt_clk = clk_get_sys("gpt0", NULL);
  86. if (IS_ERR(gpt_clk)) {
  87. pr_err("%s:couldn't get clk for gpt\n", __func__);
  88. BUG();
  89. }
  90. /* get the suitable parent clock for timer*/
  91. pclk = clk_get(NULL, pclk_name);
  92. if (IS_ERR(pclk)) {
  93. pr_err("%s:couldn't get %s as parent for gpt\n",
  94. __func__, pclk_name);
  95. BUG();
  96. }
  97. clk_set_parent(gpt_clk, pclk);
  98. clk_put(gpt_clk);
  99. clk_put(pclk);
  100. spear_setup_of_timer();
  101. }