setup-usb-phy.c 2.2 KB

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  1. /*
  2. * Copyright (C) 2012 Samsung Electronics Co.Ltd
  3. * Author: Joonyoung Shim <jy0922.shim@samsung.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundationr
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/err.h>
  12. #include <linux/io.h>
  13. #include <linux/platform_device.h>
  14. #include <mach/map.h>
  15. #include <plat/cpu.h>
  16. #include <plat/regs-usb-hsotg-phy.h>
  17. #include <plat/usb-phy.h>
  18. #define S5PV210_USB_PHY_CON (S3C_VA_SYS + 0xE80C)
  19. #define S5PV210_USB_PHY0_EN (1 << 0)
  20. #define S5PV210_USB_PHY1_EN (1 << 1)
  21. static int s5pv210_usb_otgphy_init(struct platform_device *pdev)
  22. {
  23. struct clk *xusbxti;
  24. u32 phyclk;
  25. writel(readl(S5PV210_USB_PHY_CON) | S5PV210_USB_PHY0_EN,
  26. S5PV210_USB_PHY_CON);
  27. /* set clock frequency for PLL */
  28. phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
  29. xusbxti = clk_get(&pdev->dev, "xusbxti");
  30. if (xusbxti && !IS_ERR(xusbxti)) {
  31. switch (clk_get_rate(xusbxti)) {
  32. case 12 * MHZ:
  33. phyclk |= S3C_PHYCLK_CLKSEL_12M;
  34. break;
  35. case 24 * MHZ:
  36. phyclk |= S3C_PHYCLK_CLKSEL_24M;
  37. break;
  38. default:
  39. case 48 * MHZ:
  40. /* default reference clock */
  41. break;
  42. }
  43. clk_put(xusbxti);
  44. }
  45. /* TODO: select external clock/oscillator */
  46. writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
  47. /* set to normal OTG PHY */
  48. writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
  49. mdelay(1);
  50. /* reset OTG PHY and Link */
  51. writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
  52. S3C_RSTCON);
  53. udelay(20); /* at-least 10uS */
  54. writel(0, S3C_RSTCON);
  55. return 0;
  56. }
  57. static int s5pv210_usb_otgphy_exit(struct platform_device *pdev)
  58. {
  59. writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
  60. S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
  61. writel(readl(S5PV210_USB_PHY_CON) & ~S5PV210_USB_PHY0_EN,
  62. S5PV210_USB_PHY_CON);
  63. return 0;
  64. }
  65. int s5p_usb_phy_init(struct platform_device *pdev, int type)
  66. {
  67. if (type == S5P_USB_PHY_DEVICE)
  68. return s5pv210_usb_otgphy_init(pdev);
  69. return -EINVAL;
  70. }
  71. int s5p_usb_phy_exit(struct platform_device *pdev, int type)
  72. {
  73. if (type == S5P_USB_PHY_DEVICE)
  74. return s5pv210_usb_otgphy_exit(pdev);
  75. return -EINVAL;
  76. }