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mach-kirkwood
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kirkwood.h

kirkwood.h 4.7 KB
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  1. /*
    2. 

  2.  * arch/arm/mach-kirkwood/include/mach/kirkwood.h
    3. 

  3.  *
    4. 

  4.  * Generic definitions for Marvell Kirkwood SoC flavors:
    5. 

  5.  *  88F6180, 88F6192 and 88F6281.
    6. 

  6.  *
    7. 

  7.  * This file is licensed under the terms of the GNU General Public
    8. 

  8.  * License version 2.  This program is licensed "as is" without any
    9. 

  9.  * warranty of any kind, whether express or implied.
    10. 

  10.  */
    11. 

  11. 

  12. #ifndef __ASM_ARCH_KIRKWOOD_H
    13. 

  13. #define __ASM_ARCH_KIRKWOOD_H
    14. 

  14. 

  15. /*
    16. 

  16.  * Marvell Kirkwood address maps.
    17. 

  17.  *
    18. 

  18.  * phys
    19. 

  19.  * e0000000	PCIe #0 Memory space
    20. 

  20.  * e8000000	PCIe #1 Memory space
    21. 

  21.  * f1000000	on-chip peripheral registers
    22. 

  22.  * f2000000	PCIe #0 I/O space
    23. 

  23.  * f3000000	PCIe #1 I/O space
    24. 

  24.  * f4000000	NAND controller address window
    25. 

  25.  * f5000000	Security Accelerator SRAM
    26. 

  26.  *
    27. 

  27.  * virt		phys		size
    28. 

  28.  * fed00000	f1000000	1M	on-chip peripheral registers
    29. 

  29.  * fee00000	f2000000	1M	PCIe #0 I/O space
    30. 

  30.  * fef00000	f3000000	1M	PCIe #1 I/O space
    31. 

  31.  */
    32. 

  32. 

  33. #define KIRKWOOD_SRAM_PHYS_BASE		0xf5000000
    34. 

  34. #define KIRKWOOD_SRAM_SIZE		SZ_2K
    35. 

  35. 

  36. #define KIRKWOOD_NAND_MEM_PHYS_BASE	0xf4000000
    37. 

  37. #define KIRKWOOD_NAND_MEM_SIZE		SZ_1K
    38. 

  38. 

  39. #define KIRKWOOD_PCIE1_IO_PHYS_BASE	0xf3000000
    40. 

  40. #define KIRKWOOD_PCIE1_IO_BUS_BASE	0x00010000
    41. 

  41. #define KIRKWOOD_PCIE1_IO_SIZE		SZ_64K
    42. 

  42. 

  43. #define KIRKWOOD_PCIE_IO_PHYS_BASE	0xf2000000
    44. 

  44. #define KIRKWOOD_PCIE_IO_BUS_BASE	0x00000000
    45. 

  45. #define KIRKWOOD_PCIE_IO_SIZE		SZ_64K
    46. 

  46. 

  47. #define KIRKWOOD_REGS_PHYS_BASE		0xf1000000
    48. 

  48. #define KIRKWOOD_REGS_VIRT_BASE		IOMEM(0xfed00000)
    49. 

  49. #define KIRKWOOD_REGS_SIZE		SZ_1M
    50. 

  50. 

  51. #define KIRKWOOD_PCIE_MEM_PHYS_BASE	0xe0000000
    52. 

  52. #define KIRKWOOD_PCIE_MEM_BUS_BASE	0xe0000000
    53. 

  53. #define KIRKWOOD_PCIE_MEM_SIZE		SZ_128M
    54. 

  54. 

  55. #define KIRKWOOD_PCIE1_MEM_PHYS_BASE	0xe8000000
    56. 

  56. #define KIRKWOOD_PCIE1_MEM_BUS_BASE	0xe8000000
    57. 

  57. #define KIRKWOOD_PCIE1_MEM_SIZE		SZ_128M
    58. 

  58. 

  59. /*
    60. 

  60.  * Register Map
    61. 

  61.  */
    62. 

  62. #define DDR_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE + 0x00000)
    63. 

  63. #define DDR_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE + 0x00000)
    64. 

  64. #define  DDR_WINDOW_CPU_BASE	(DDR_VIRT_BASE + 0x1500)
    65. 

  65. #define DDR_OPERATION_BASE	(DDR_PHYS_BASE + 0x1418)
    66. 

  66. 

  67. #define DEV_BUS_PHYS_BASE	(KIRKWOOD_REGS_PHYS_BASE + 0x10000)
    68. 

  68. #define DEV_BUS_VIRT_BASE	(KIRKWOOD_REGS_VIRT_BASE + 0x10000)
    69. 

  69. #define  SAMPLE_AT_RESET	(DEV_BUS_VIRT_BASE + 0x0030)
    70. 

  70. #define  DEVICE_ID		(DEV_BUS_VIRT_BASE + 0x0034)
    71. 

  71. #define  GPIO_LOW_VIRT_BASE	(DEV_BUS_VIRT_BASE + 0x0100)
    72. 

  72. #define  GPIO_HIGH_VIRT_BASE	(DEV_BUS_VIRT_BASE + 0x0140)
    73. 

  73. #define  RTC_PHYS_BASE		(DEV_BUS_PHYS_BASE + 0x0300)
    74. 

  74. #define  SPI_PHYS_BASE		(DEV_BUS_PHYS_BASE + 0x0600)
    75. 

  75. #define  I2C_PHYS_BASE		(DEV_BUS_PHYS_BASE + 0x1000)
    76. 

  76. #define  UART0_PHYS_BASE	(DEV_BUS_PHYS_BASE + 0x2000)
    77. 

  77. #define  UART0_VIRT_BASE	(DEV_BUS_VIRT_BASE + 0x2000)
    78. 

  78. #define  UART1_PHYS_BASE	(DEV_BUS_PHYS_BASE + 0x2100)
    79. 

  79. #define  UART1_VIRT_BASE	(DEV_BUS_VIRT_BASE + 0x2100)
    80. 

  80. 

  81. #define BRIDGE_VIRT_BASE	(KIRKWOOD_REGS_VIRT_BASE + 0x20000)
    82. 

  82. #define BRIDGE_PHYS_BASE	(KIRKWOOD_REGS_PHYS_BASE + 0x20000)
    83. 

  83. 

  84. #define CRYPTO_PHYS_BASE	(KIRKWOOD_REGS_PHYS_BASE + 0x30000)
    85. 

  85. 

  86. #define PCIE_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE + 0x40000)
    87. 

  87. #define PCIE_LINK_CTRL		(PCIE_VIRT_BASE + 0x70)
    88. 

  88. #define PCIE_STATUS		(PCIE_VIRT_BASE + 0x1a04)
    89. 

  89. #define PCIE1_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE + 0x44000)
    90. 

  90. #define PCIE1_LINK_CTRL		(PCIE1_VIRT_BASE + 0x70)
    91. 

  91. #define PCIE1_STATUS		(PCIE1_VIRT_BASE + 0x1a04)
    92. 

  92. 

  93. #define USB_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE + 0x50000)
    94. 

  94. 

  95. #define XOR0_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE + 0x60800)
    96. 

  96. #define XOR0_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE + 0x60800)
    97. 

  97. #define XOR1_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE + 0x60900)
    98. 

  98. #define XOR1_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE + 0x60900)
    99. 

  99. #define XOR0_HIGH_PHYS_BASE	(KIRKWOOD_REGS_PHYS_BASE + 0x60A00)
    100. 

  100. #define XOR0_HIGH_VIRT_BASE	(KIRKWOOD_REGS_VIRT_BASE + 0x60A00)
    101. 

  101. #define XOR1_HIGH_PHYS_BASE	(KIRKWOOD_REGS_PHYS_BASE + 0x60B00)
    102. 

  102. #define XOR1_HIGH_VIRT_BASE	(KIRKWOOD_REGS_VIRT_BASE + 0x60B00)
    103. 

  103. 

  104. #define GE00_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE + 0x70000)
    105. 

  105. #define GE01_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE + 0x74000)
    106. 

  106. 

  107. #define SATA_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE + 0x80000)
    108. 

  108. #define SATA_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE + 0x80000)
    109. 

  109. #define SATA0_IF_CTRL		(SATA_VIRT_BASE + 0x2050)
    110. 

  110. #define SATA0_PHY_MODE_2	(SATA_VIRT_BASE + 0x2330)
    111. 

  111. #define SATA1_IF_CTRL		(SATA_VIRT_BASE + 0x4050)
    112. 

  112. #define SATA1_PHY_MODE_2	(SATA_VIRT_BASE + 0x4330)
    113. 

  113. 

  114. #define SDIO_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE + 0x90000)
    115. 

  115. 

  116. #define AUDIO_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE + 0xA0000)
    117. 

  117. #define AUDIO_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE + 0xA0000)
    118. 

  118. 

  119. /*
    120. 

  120.  * Supported devices and revisions.
    121. 

  121.  */
    122. 

  122. #define MV88F6281_DEV_ID	0x6281
    123. 

  123. #define MV88F6281_REV_Z0	0
    124. 

  124. #define MV88F6281_REV_A0	2
    125. 

  125. #define MV88F6281_REV_A1	3
    126. 

  126. 

  127. #define MV88F6192_DEV_ID	0x6192
    128. 

  128. #define MV88F6192_REV_Z0	0
    129. 

  129. #define MV88F6192_REV_A0	2
    130. 

  130. #define MV88F6192_REV_A1	3
    131. 

  131. 

  132. #define MV88F6180_DEV_ID	0x6180
    133. 

  133. #define MV88F6180_REV_A0	2
    134. 

  134. #define MV88F6180_REV_A1	3
    135. 

  135. 

  136. #define MV88F6282_DEV_ID	0x6282
    137. 

  137. #define MV88F6282_REV_A0	0
    138. 

  138. #define MV88F6282_REV_A1	1
    139. 

  139. #endif
    140.