cns3420vb.c 6.2 KB

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  1. /*
  2. * Cavium Networks CNS3420 Validation Board
  3. *
  4. * Copyright 2000 Deep Blue Solutions Ltd
  5. * Copyright 2008 ARM Limited
  6. * Copyright 2008 Cavium Networks
  7. * Scott Shu
  8. * Copyright 2010 MontaVista Software, LLC.
  9. * Anton Vorontsov <avorontsov@mvista.com>
  10. *
  11. * This file is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License, Version 2, as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/kernel.h>
  17. #include <linux/compiler.h>
  18. #include <linux/io.h>
  19. #include <linux/dma-mapping.h>
  20. #include <linux/serial_core.h>
  21. #include <linux/serial_8250.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/mtd/mtd.h>
  24. #include <linux/mtd/physmap.h>
  25. #include <linux/mtd/partitions.h>
  26. #include <linux/usb/ehci_pdriver.h>
  27. #include <linux/usb/ohci_pdriver.h>
  28. #include <asm/setup.h>
  29. #include <asm/mach-types.h>
  30. #include <asm/mach/arch.h>
  31. #include <asm/mach/map.h>
  32. #include <asm/mach/time.h>
  33. #include <mach/cns3xxx.h>
  34. #include <mach/irqs.h>
  35. #include <mach/pm.h>
  36. #include "core.h"
  37. #include "devices.h"
  38. /*
  39. * NOR Flash
  40. */
  41. static struct mtd_partition cns3420_nor_partitions[] = {
  42. {
  43. .name = "uboot",
  44. .size = 0x00040000,
  45. .offset = 0,
  46. .mask_flags = MTD_WRITEABLE,
  47. }, {
  48. .name = "kernel",
  49. .size = 0x004C0000,
  50. .offset = MTDPART_OFS_APPEND,
  51. }, {
  52. .name = "filesystem",
  53. .size = 0x7000000,
  54. .offset = MTDPART_OFS_APPEND,
  55. }, {
  56. .name = "filesystem2",
  57. .size = 0x0AE0000,
  58. .offset = MTDPART_OFS_APPEND,
  59. }, {
  60. .name = "ubootenv",
  61. .size = MTDPART_SIZ_FULL,
  62. .offset = MTDPART_OFS_APPEND,
  63. },
  64. };
  65. static struct physmap_flash_data cns3420_nor_pdata = {
  66. .width = 2,
  67. .parts = cns3420_nor_partitions,
  68. .nr_parts = ARRAY_SIZE(cns3420_nor_partitions),
  69. };
  70. static struct resource cns3420_nor_res = {
  71. .start = CNS3XXX_FLASH_BASE,
  72. .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
  73. .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
  74. };
  75. static struct platform_device cns3420_nor_pdev = {
  76. .name = "physmap-flash",
  77. .id = 0,
  78. .resource = &cns3420_nor_res,
  79. .num_resources = 1,
  80. .dev = {
  81. .platform_data = &cns3420_nor_pdata,
  82. },
  83. };
  84. /*
  85. * UART
  86. */
  87. static void __init cns3420_early_serial_setup(void)
  88. {
  89. #ifdef CONFIG_SERIAL_8250_CONSOLE
  90. static struct uart_port cns3420_serial_port = {
  91. .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
  92. .mapbase = CNS3XXX_UART0_BASE,
  93. .irq = IRQ_CNS3XXX_UART0,
  94. .iotype = UPIO_MEM,
  95. .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
  96. .regshift = 2,
  97. .uartclk = 24000000,
  98. .line = 0,
  99. .type = PORT_16550A,
  100. .fifosize = 16,
  101. };
  102. early_serial_setup(&cns3420_serial_port);
  103. #endif
  104. }
  105. /*
  106. * USB
  107. */
  108. static struct resource cns3xxx_usb_ehci_resources[] = {
  109. [0] = {
  110. .start = CNS3XXX_USB_BASE,
  111. .end = CNS3XXX_USB_BASE + SZ_16M - 1,
  112. .flags = IORESOURCE_MEM,
  113. },
  114. [1] = {
  115. .start = IRQ_CNS3XXX_USB_EHCI,
  116. .flags = IORESOURCE_IRQ,
  117. },
  118. };
  119. static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
  120. static int csn3xxx_usb_power_on(struct platform_device *pdev)
  121. {
  122. /*
  123. * EHCI and OHCI share the same clock and power,
  124. * resetting twice would cause the 1st controller been reset.
  125. * Therefore only do power up at the first up device, and
  126. * power down at the last down device.
  127. *
  128. * Set USB AHB INCR length to 16
  129. */
  130. if (atomic_inc_return(&usb_pwr_ref) == 1) {
  131. cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
  132. cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
  133. cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
  134. __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
  135. MISC_CHIP_CONFIG_REG);
  136. }
  137. return 0;
  138. }
  139. static void csn3xxx_usb_power_off(struct platform_device *pdev)
  140. {
  141. /*
  142. * EHCI and OHCI share the same clock and power,
  143. * resetting twice would cause the 1st controller been reset.
  144. * Therefore only do power up at the first up device, and
  145. * power down at the last down device.
  146. */
  147. if (atomic_dec_return(&usb_pwr_ref) == 0)
  148. cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
  149. }
  150. static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
  151. .power_on = csn3xxx_usb_power_on,
  152. .power_off = csn3xxx_usb_power_off,
  153. };
  154. static struct platform_device cns3xxx_usb_ehci_device = {
  155. .name = "ehci-platform",
  156. .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
  157. .resource = cns3xxx_usb_ehci_resources,
  158. .dev = {
  159. .dma_mask = &cns3xxx_usb_ehci_dma_mask,
  160. .coherent_dma_mask = DMA_BIT_MASK(32),
  161. .platform_data = &cns3xxx_usb_ehci_pdata,
  162. },
  163. };
  164. static struct resource cns3xxx_usb_ohci_resources[] = {
  165. [0] = {
  166. .start = CNS3XXX_USB_OHCI_BASE,
  167. .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
  168. .flags = IORESOURCE_MEM,
  169. },
  170. [1] = {
  171. .start = IRQ_CNS3XXX_USB_OHCI,
  172. .flags = IORESOURCE_IRQ,
  173. },
  174. };
  175. static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
  176. static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
  177. .num_ports = 1,
  178. .power_on = csn3xxx_usb_power_on,
  179. .power_off = csn3xxx_usb_power_off,
  180. };
  181. static struct platform_device cns3xxx_usb_ohci_device = {
  182. .name = "ohci-platform",
  183. .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
  184. .resource = cns3xxx_usb_ohci_resources,
  185. .dev = {
  186. .dma_mask = &cns3xxx_usb_ohci_dma_mask,
  187. .coherent_dma_mask = DMA_BIT_MASK(32),
  188. .platform_data = &cns3xxx_usb_ohci_pdata,
  189. },
  190. };
  191. /*
  192. * Initialization
  193. */
  194. static struct platform_device *cns3420_pdevs[] __initdata = {
  195. &cns3420_nor_pdev,
  196. &cns3xxx_usb_ehci_device,
  197. &cns3xxx_usb_ohci_device,
  198. };
  199. static void __init cns3420_init(void)
  200. {
  201. cns3xxx_l2x0_init();
  202. platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
  203. cns3xxx_ahci_init();
  204. cns3xxx_sdhci_init();
  205. pm_power_off = cns3xxx_power_off;
  206. }
  207. static struct map_desc cns3420_io_desc[] __initdata = {
  208. {
  209. .virtual = CNS3XXX_UART0_BASE_VIRT,
  210. .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
  211. .length = SZ_4K,
  212. .type = MT_DEVICE,
  213. },
  214. };
  215. static void __init cns3420_map_io(void)
  216. {
  217. cns3xxx_map_io();
  218. iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
  219. cns3420_early_serial_setup();
  220. }
  221. MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
  222. .atag_offset = 0x100,
  223. .map_io = cns3420_map_io,
  224. .init_irq = cns3xxx_init_irq,
  225. .init_time = cns3xxx_timer_init,
  226. .init_machine = cns3420_init,
  227. .restart = cns3xxx_restart,
  228. MACHINE_END