tegra20-colibri-512.dtsi 12 KB

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  1. /include/ "tegra20.dtsi"
  2. / {
  3. model = "Toradex Colibri T20 512MB";
  4. compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
  5. memory {
  6. reg = <0x00000000 0x20000000>;
  7. };
  8. host1x {
  9. hdmi {
  10. vdd-supply = <&hdmi_vdd_reg>;
  11. pll-supply = <&hdmi_pll_reg>;
  12. nvidia,ddc-i2c-bus = <&i2c_ddc>;
  13. nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
  14. };
  15. };
  16. pinmux {
  17. pinctrl-names = "default";
  18. pinctrl-0 = <&state_default>;
  19. state_default: pinmux {
  20. audio_refclk {
  21. nvidia,pins = "cdev1";
  22. nvidia,function = "plla_out";
  23. nvidia,pull = <0>;
  24. nvidia,tristate = <0>;
  25. };
  26. crt {
  27. nvidia,pins = "crtp";
  28. nvidia,function = "crt";
  29. nvidia,pull = <0>;
  30. nvidia,tristate = <1>;
  31. };
  32. dap3 {
  33. nvidia,pins = "dap3";
  34. nvidia,function = "dap3";
  35. nvidia,pull = <0>;
  36. nvidia,tristate = <0>;
  37. };
  38. displaya {
  39. nvidia,pins = "ld0", "ld1", "ld2", "ld3",
  40. "ld4", "ld5", "ld6", "ld7", "ld8",
  41. "ld9", "ld10", "ld11", "ld12", "ld13",
  42. "ld14", "ld15", "ld16", "ld17",
  43. "lhs", "lpw0", "lpw2", "lsc0",
  44. "lsc1", "lsck", "lsda", "lspi", "lvs";
  45. nvidia,function = "displaya";
  46. nvidia,tristate = <1>;
  47. };
  48. gpio_dte {
  49. nvidia,pins = "dte";
  50. nvidia,function = "rsvd1";
  51. nvidia,pull = <0>;
  52. nvidia,tristate = <0>;
  53. };
  54. gpio_gmi {
  55. nvidia,pins = "ata", "atc", "atd", "ate",
  56. "dap1", "dap2", "dap4", "gpu", "irrx",
  57. "irtx", "spia", "spib", "spic";
  58. nvidia,function = "gmi";
  59. nvidia,pull = <0>;
  60. nvidia,tristate = <0>;
  61. };
  62. gpio_pta {
  63. nvidia,pins = "pta";
  64. nvidia,function = "rsvd4";
  65. nvidia,pull = <0>;
  66. nvidia,tristate = <0>;
  67. };
  68. gpio_uac {
  69. nvidia,pins = "uac";
  70. nvidia,function = "rsvd2";
  71. nvidia,pull = <0>;
  72. nvidia,tristate = <0>;
  73. };
  74. hdint {
  75. nvidia,pins = "hdint";
  76. nvidia,function = "hdmi";
  77. nvidia,tristate = <1>;
  78. };
  79. i2c1 {
  80. nvidia,pins = "rm";
  81. nvidia,function = "i2c1";
  82. nvidia,pull = <0>;
  83. nvidia,tristate = <1>;
  84. };
  85. i2c3 {
  86. nvidia,pins = "dtf";
  87. nvidia,function = "i2c3";
  88. nvidia,pull = <0>;
  89. nvidia,tristate = <1>;
  90. };
  91. i2cddc {
  92. nvidia,pins = "ddc";
  93. nvidia,function = "i2c2";
  94. nvidia,pull = <2>;
  95. nvidia,tristate = <1>;
  96. };
  97. i2cp {
  98. nvidia,pins = "i2cp";
  99. nvidia,function = "i2cp";
  100. nvidia,pull = <0>;
  101. nvidia,tristate = <0>;
  102. };
  103. irda {
  104. nvidia,pins = "uad";
  105. nvidia,function = "irda";
  106. nvidia,pull = <0>;
  107. nvidia,tristate = <1>;
  108. };
  109. nand {
  110. nvidia,pins = "kbca", "kbcc", "kbcd",
  111. "kbce", "kbcf";
  112. nvidia,function = "nand";
  113. nvidia,pull = <0>;
  114. nvidia,tristate = <0>;
  115. };
  116. owc {
  117. nvidia,pins = "owc";
  118. nvidia,function = "owr";
  119. nvidia,pull = <0>;
  120. nvidia,tristate = <1>;
  121. };
  122. pmc {
  123. nvidia,pins = "pmc";
  124. nvidia,function = "pwr_on";
  125. nvidia,tristate = <0>;
  126. };
  127. pwm {
  128. nvidia,pins = "sdb", "sdc", "sdd";
  129. nvidia,function = "pwm";
  130. nvidia,tristate = <1>;
  131. };
  132. sdio4 {
  133. nvidia,pins = "atb", "gma", "gme";
  134. nvidia,function = "sdio4";
  135. nvidia,pull = <0>;
  136. nvidia,tristate = <1>;
  137. };
  138. spi1 {
  139. nvidia,pins = "spid", "spie", "spif";
  140. nvidia,function = "spi1";
  141. nvidia,pull = <0>;
  142. nvidia,tristate = <1>;
  143. };
  144. spi4 {
  145. nvidia,pins = "slxa", "slxc", "slxd", "slxk";
  146. nvidia,function = "spi4";
  147. nvidia,pull = <0>;
  148. nvidia,tristate = <1>;
  149. };
  150. uarta {
  151. nvidia,pins = "sdio1";
  152. nvidia,function = "uarta";
  153. nvidia,pull = <0>;
  154. nvidia,tristate = <1>;
  155. };
  156. uartd {
  157. nvidia,pins = "gmc";
  158. nvidia,function = "uartd";
  159. nvidia,pull = <0>;
  160. nvidia,tristate = <1>;
  161. };
  162. ulpi {
  163. nvidia,pins = "uaa", "uab", "uda";
  164. nvidia,function = "ulpi";
  165. nvidia,pull = <0>;
  166. nvidia,tristate = <0>;
  167. };
  168. ulpi_refclk {
  169. nvidia,pins = "cdev2";
  170. nvidia,function = "pllp_out4";
  171. nvidia,pull = <0>;
  172. nvidia,tristate = <0>;
  173. };
  174. usb_gpio {
  175. nvidia,pins = "spig", "spih";
  176. nvidia,function = "spi2_alt";
  177. nvidia,pull = <0>;
  178. nvidia,tristate = <0>;
  179. };
  180. vi {
  181. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  182. nvidia,function = "vi";
  183. nvidia,pull = <0>;
  184. nvidia,tristate = <1>;
  185. };
  186. vi_sc {
  187. nvidia,pins = "csus";
  188. nvidia,function = "vi_sensor_clk";
  189. nvidia,pull = <0>;
  190. nvidia,tristate = <1>;
  191. };
  192. };
  193. };
  194. i2c@7000c000 {
  195. clock-frequency = <400000>;
  196. };
  197. i2c_ddc: i2c@7000c400 {
  198. clock-frequency = <100000>;
  199. };
  200. i2c@7000c500 {
  201. clock-frequency = <400000>;
  202. };
  203. i2c@7000d000 {
  204. status = "okay";
  205. clock-frequency = <400000>;
  206. pmic: tps6586x@34 {
  207. compatible = "ti,tps6586x";
  208. reg = <0x34>;
  209. interrupts = <0 86 0x4>;
  210. ti,system-power-controller;
  211. #gpio-cells = <2>;
  212. gpio-controller;
  213. sys-supply = <&vdd_5v0_reg>;
  214. vin-sm0-supply = <&sys_reg>;
  215. vin-sm1-supply = <&sys_reg>;
  216. vin-sm2-supply = <&sys_reg>;
  217. vinldo01-supply = <&sm2_reg>;
  218. vinldo23-supply = <&sm2_reg>;
  219. vinldo4-supply = <&sm2_reg>;
  220. vinldo678-supply = <&sm2_reg>;
  221. vinldo9-supply = <&sm2_reg>;
  222. regulators {
  223. #address-cells = <1>;
  224. #size-cells = <0>;
  225. sys_reg: regulator@0 {
  226. reg = <0>;
  227. regulator-compatible = "sys";
  228. regulator-name = "vdd_sys";
  229. regulator-always-on;
  230. };
  231. regulator@1 {
  232. reg = <1>;
  233. regulator-compatible = "sm0";
  234. regulator-name = "vdd_sm0,vdd_core";
  235. regulator-min-microvolt = <1275000>;
  236. regulator-max-microvolt = <1275000>;
  237. regulator-always-on;
  238. };
  239. regulator@2 {
  240. reg = <2>;
  241. regulator-compatible = "sm1";
  242. regulator-name = "vdd_sm1,vdd_cpu";
  243. regulator-min-microvolt = <1100000>;
  244. regulator-max-microvolt = <1100000>;
  245. regulator-always-on;
  246. };
  247. sm2_reg: regulator@3 {
  248. reg = <3>;
  249. regulator-compatible = "sm2";
  250. regulator-name = "vdd_sm2,vin_ldo*";
  251. regulator-min-microvolt = <3700000>;
  252. regulator-max-microvolt = <3700000>;
  253. regulator-always-on;
  254. };
  255. /* LDO0 is not connected to anything */
  256. regulator@5 {
  257. reg = <5>;
  258. regulator-compatible = "ldo1";
  259. regulator-name = "vdd_ldo1,avdd_pll*";
  260. regulator-min-microvolt = <1100000>;
  261. regulator-max-microvolt = <1100000>;
  262. regulator-always-on;
  263. };
  264. regulator@6 {
  265. reg = <6>;
  266. regulator-compatible = "ldo2";
  267. regulator-name = "vdd_ldo2,vdd_rtc";
  268. regulator-min-microvolt = <1200000>;
  269. regulator-max-microvolt = <1200000>;
  270. };
  271. /* LDO3 is not connected to anything */
  272. regulator@8 {
  273. reg = <8>;
  274. regulator-compatible = "ldo4";
  275. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  276. regulator-min-microvolt = <1800000>;
  277. regulator-max-microvolt = <1800000>;
  278. regulator-always-on;
  279. };
  280. ldo5_reg: regulator@9 {
  281. reg = <9>;
  282. regulator-compatible = "ldo5";
  283. regulator-name = "vdd_ldo5,vdd_fuse";
  284. regulator-min-microvolt = <3300000>;
  285. regulator-max-microvolt = <3300000>;
  286. regulator-always-on;
  287. };
  288. regulator@10 {
  289. reg = <10>;
  290. regulator-compatible = "ldo6";
  291. regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
  292. regulator-min-microvolt = <1800000>;
  293. regulator-max-microvolt = <1800000>;
  294. };
  295. hdmi_vdd_reg: regulator@11 {
  296. reg = <11>;
  297. regulator-compatible = "ldo7";
  298. regulator-name = "vdd_ldo7,avdd_hdmi";
  299. regulator-min-microvolt = <3300000>;
  300. regulator-max-microvolt = <3300000>;
  301. };
  302. hdmi_pll_reg: regulator@12 {
  303. reg = <12>;
  304. regulator-compatible = "ldo8";
  305. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  306. regulator-min-microvolt = <1800000>;
  307. regulator-max-microvolt = <1800000>;
  308. };
  309. regulator@13 {
  310. reg = <13>;
  311. regulator-compatible = "ldo9";
  312. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  313. regulator-min-microvolt = <2850000>;
  314. regulator-max-microvolt = <2850000>;
  315. regulator-always-on;
  316. };
  317. regulator@14 {
  318. reg = <14>;
  319. regulator-compatible = "ldo_rtc";
  320. regulator-name = "vdd_rtc_out,vdd_cell";
  321. regulator-min-microvolt = <3300000>;
  322. regulator-max-microvolt = <3300000>;
  323. regulator-always-on;
  324. };
  325. };
  326. };
  327. temperature-sensor@4c {
  328. compatible = "national,lm95245";
  329. reg = <0x4c>;
  330. };
  331. };
  332. memory-controller@7000f400 {
  333. emc-table@83250 {
  334. reg = <83250>;
  335. compatible = "nvidia,tegra20-emc-table";
  336. clock-frequency = <83250>;
  337. nvidia,emc-registers = <0x00000005 0x00000011
  338. 0x00000004 0x00000002 0x00000004 0x00000004
  339. 0x00000001 0x0000000a 0x00000002 0x00000002
  340. 0x00000001 0x00000001 0x00000003 0x00000004
  341. 0x00000003 0x00000009 0x0000000c 0x0000025f
  342. 0x00000000 0x00000003 0x00000003 0x00000002
  343. 0x00000002 0x00000001 0x00000008 0x000000c8
  344. 0x00000003 0x00000005 0x00000003 0x0000000c
  345. 0x00000002 0x00000000 0x00000000 0x00000002
  346. 0x00000000 0x00000000 0x00000083 0x00520006
  347. 0x00000010 0x00000008 0x00000000 0x00000000
  348. 0x00000000 0x00000000 0x00000000 0x00000000>;
  349. };
  350. emc-table@133200 {
  351. reg = <133200>;
  352. compatible = "nvidia,tegra20-emc-table";
  353. clock-frequency = <133200>;
  354. nvidia,emc-registers = <0x00000008 0x00000019
  355. 0x00000006 0x00000002 0x00000004 0x00000004
  356. 0x00000001 0x0000000a 0x00000002 0x00000002
  357. 0x00000002 0x00000001 0x00000003 0x00000004
  358. 0x00000003 0x00000009 0x0000000c 0x0000039f
  359. 0x00000000 0x00000003 0x00000003 0x00000002
  360. 0x00000002 0x00000001 0x00000008 0x000000c8
  361. 0x00000003 0x00000007 0x00000003 0x0000000c
  362. 0x00000002 0x00000000 0x00000000 0x00000002
  363. 0x00000000 0x00000000 0x00000083 0x00510006
  364. 0x00000010 0x00000008 0x00000000 0x00000000
  365. 0x00000000 0x00000000 0x00000000 0x00000000>;
  366. };
  367. emc-table@166500 {
  368. reg = <166500>;
  369. compatible = "nvidia,tegra20-emc-table";
  370. clock-frequency = <166500>;
  371. nvidia,emc-registers = <0x0000000a 0x00000021
  372. 0x00000008 0x00000003 0x00000004 0x00000004
  373. 0x00000002 0x0000000a 0x00000003 0x00000003
  374. 0x00000002 0x00000001 0x00000003 0x00000004
  375. 0x00000003 0x00000009 0x0000000c 0x000004df
  376. 0x00000000 0x00000003 0x00000003 0x00000003
  377. 0x00000003 0x00000001 0x00000009 0x000000c8
  378. 0x00000003 0x00000009 0x00000004 0x0000000c
  379. 0x00000002 0x00000000 0x00000000 0x00000002
  380. 0x00000000 0x00000000 0x00000083 0x004f0006
  381. 0x00000010 0x00000008 0x00000000 0x00000000
  382. 0x00000000 0x00000000 0x00000000 0x00000000>;
  383. };
  384. emc-table@333000 {
  385. reg = <333000>;
  386. compatible = "nvidia,tegra20-emc-table";
  387. clock-frequency = <333000>;
  388. nvidia,emc-registers = <0x00000014 0x00000041
  389. 0x0000000f 0x00000005 0x00000004 0x00000005
  390. 0x00000003 0x0000000a 0x00000005 0x00000005
  391. 0x00000004 0x00000001 0x00000003 0x00000004
  392. 0x00000003 0x00000009 0x0000000c 0x000009ff
  393. 0x00000000 0x00000003 0x00000003 0x00000005
  394. 0x00000005 0x00000001 0x0000000e 0x000000c8
  395. 0x00000003 0x00000011 0x00000006 0x0000000c
  396. 0x00000002 0x00000000 0x00000000 0x00000002
  397. 0x00000000 0x00000000 0x00000083 0x00380006
  398. 0x00000010 0x00000008 0x00000000 0x00000000
  399. 0x00000000 0x00000000 0x00000000 0x00000000>;
  400. };
  401. };
  402. ac97: ac97 {
  403. status = "okay";
  404. nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
  405. nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
  406. };
  407. usb@c5004000 {
  408. status = "okay";
  409. nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
  410. };
  411. sdhci@c8000600 {
  412. cd-gpios = <&gpio 23 0>; /* gpio PC7 */
  413. };
  414. sound {
  415. compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
  416. "nvidia,tegra-audio-wm9712";
  417. nvidia,model = "Colibri T20 AC97 Audio";
  418. nvidia,audio-routing =
  419. "Headphone", "HPOUTL",
  420. "Headphone", "HPOUTR",
  421. "LineIn", "LINEINL",
  422. "LineIn", "LINEINR",
  423. "Mic", "MIC1";
  424. nvidia,ac97-controller = <&ac97>;
  425. };
  426. regulators {
  427. compatible = "simple-bus";
  428. #address-cells = <1>;
  429. #size-cells = <0>;
  430. vdd_5v0_reg: regulator@100 {
  431. compatible = "regulator-fixed";
  432. reg = <100>;
  433. regulator-name = "vdd_5v0";
  434. regulator-min-microvolt = <5000000>;
  435. regulator-max-microvolt = <5000000>;
  436. regulator-always-on;
  437. };
  438. regulator@101 {
  439. compatible = "regulator-fixed";
  440. reg = <101>;
  441. regulator-name = "internal_usb";
  442. regulator-min-microvolt = <5000000>;
  443. regulator-max-microvolt = <5000000>;
  444. enable-active-high;
  445. regulator-boot-on;
  446. regulator-always-on;
  447. gpio = <&gpio 217 0>;
  448. };
  449. };
  450. };