spear13xx.dtsi 6.6 KB

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  1. /*
  2. * DTS file for all SPEAr13xx SoCs
  3. *
  4. * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
  5. *
  6. * The code contained herein is licensed under the GNU General Public
  7. * License. You may obtain a copy of the GNU General Public License
  8. * Version 2 or later at the following locations:
  9. *
  10. * http://www.opensource.org/licenses/gpl-license.html
  11. * http://www.gnu.org/copyleft/gpl.html
  12. */
  13. /include/ "skeleton.dtsi"
  14. / {
  15. interrupt-parent = <&gic>;
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. cpu@0 {
  20. compatible = "arm,cortex-a9";
  21. reg = <0>;
  22. next-level-cache = <&L2>;
  23. };
  24. cpu@1 {
  25. compatible = "arm,cortex-a9";
  26. reg = <1>;
  27. next-level-cache = <&L2>;
  28. };
  29. };
  30. gic: interrupt-controller@ec801000 {
  31. compatible = "arm,cortex-a9-gic";
  32. interrupt-controller;
  33. #interrupt-cells = <3>;
  34. reg = < 0xec801000 0x1000 >,
  35. < 0xec800100 0x0100 >;
  36. };
  37. pmu {
  38. compatible = "arm,cortex-a9-pmu";
  39. interrupts = <0 6 0x04
  40. 0 7 0x04>;
  41. };
  42. L2: l2-cache {
  43. compatible = "arm,pl310-cache";
  44. reg = <0xed000000 0x1000>;
  45. cache-unified;
  46. cache-level = <2>;
  47. };
  48. memory {
  49. name = "memory";
  50. device_type = "memory";
  51. reg = <0 0x40000000>;
  52. };
  53. chosen {
  54. bootargs = "console=ttyAMA0,115200";
  55. };
  56. cpufreq {
  57. compatible = "st,cpufreq-spear";
  58. cpufreq_tbl = < 166000
  59. 200000
  60. 250000
  61. 300000
  62. 400000
  63. 500000
  64. 600000 >;
  65. status = "disabled";
  66. };
  67. ahb {
  68. #address-cells = <1>;
  69. #size-cells = <1>;
  70. compatible = "simple-bus";
  71. ranges = <0x50000000 0x50000000 0x10000000
  72. 0xb0000000 0xb0000000 0x10000000
  73. 0xd0000000 0xd0000000 0x02000000
  74. 0xd8000000 0xd8000000 0x01000000
  75. 0xe0000000 0xe0000000 0x10000000>;
  76. sdhci@b3000000 {
  77. compatible = "st,sdhci-spear";
  78. reg = <0xb3000000 0x100>;
  79. interrupts = <0 28 0x4>;
  80. status = "disabled";
  81. };
  82. cf@b2800000 {
  83. compatible = "arasan,cf-spear1340";
  84. reg = <0xb2800000 0x1000>;
  85. interrupts = <0 29 0x4>;
  86. status = "disabled";
  87. };
  88. dma@ea800000 {
  89. compatible = "snps,dma-spear1340";
  90. reg = <0xea800000 0x1000>;
  91. interrupts = <0 19 0x4>;
  92. status = "disabled";
  93. };
  94. dma@eb000000 {
  95. compatible = "snps,dma-spear1340";
  96. reg = <0xeb000000 0x1000>;
  97. interrupts = <0 59 0x4>;
  98. status = "disabled";
  99. };
  100. fsmc: flash@b0000000 {
  101. compatible = "st,spear600-fsmc-nand";
  102. #address-cells = <1>;
  103. #size-cells = <1>;
  104. reg = <0xb0000000 0x1000 /* FSMC Register*/
  105. 0xb0800000 0x0010 /* NAND Base DATA */
  106. 0xb0820000 0x0010 /* NAND Base ADDR */
  107. 0xb0810000 0x0010>; /* NAND Base CMD */
  108. reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
  109. interrupts = <0 20 0x4
  110. 0 21 0x4
  111. 0 22 0x4
  112. 0 23 0x4>;
  113. st,mode = <2>;
  114. status = "disabled";
  115. };
  116. gmac0: eth@e2000000 {
  117. compatible = "st,spear600-gmac";
  118. reg = <0xe2000000 0x8000>;
  119. interrupts = <0 33 0x4
  120. 0 34 0x4>;
  121. interrupt-names = "macirq", "eth_wake_irq";
  122. status = "disabled";
  123. };
  124. pcm {
  125. compatible = "st,pcm-audio";
  126. #address-cells = <0>;
  127. #size-cells = <0>;
  128. status = "disabled";
  129. };
  130. smi: flash@ea000000 {
  131. compatible = "st,spear600-smi";
  132. #address-cells = <1>;
  133. #size-cells = <1>;
  134. reg = <0xea000000 0x1000>;
  135. interrupts = <0 30 0x4>;
  136. status = "disabled";
  137. };
  138. ehci@e4800000 {
  139. compatible = "st,spear600-ehci", "usb-ehci";
  140. reg = <0xe4800000 0x1000>;
  141. interrupts = <0 64 0x4>;
  142. usbh0_id = <0>;
  143. status = "disabled";
  144. };
  145. ehci@e5800000 {
  146. compatible = "st,spear600-ehci", "usb-ehci";
  147. reg = <0xe5800000 0x1000>;
  148. interrupts = <0 66 0x4>;
  149. usbh1_id = <1>;
  150. status = "disabled";
  151. };
  152. ohci@e4000000 {
  153. compatible = "st,spear600-ohci", "usb-ohci";
  154. reg = <0xe4000000 0x1000>;
  155. interrupts = <0 65 0x4>;
  156. usbh0_id = <0>;
  157. status = "disabled";
  158. };
  159. ohci@e5000000 {
  160. compatible = "st,spear600-ohci", "usb-ohci";
  161. reg = <0xe5000000 0x1000>;
  162. interrupts = <0 67 0x4>;
  163. usbh1_id = <1>;
  164. status = "disabled";
  165. };
  166. apb {
  167. #address-cells = <1>;
  168. #size-cells = <1>;
  169. compatible = "simple-bus";
  170. ranges = <0x50000000 0x50000000 0x10000000
  171. 0xb0000000 0xb0000000 0x10000000
  172. 0xd0000000 0xd0000000 0x02000000
  173. 0xd8000000 0xd8000000 0x01000000
  174. 0xe0000000 0xe0000000 0x10000000>;
  175. gpio0: gpio@e0600000 {
  176. compatible = "arm,pl061", "arm,primecell";
  177. reg = <0xe0600000 0x1000>;
  178. interrupts = <0 24 0x4>;
  179. gpio-controller;
  180. #gpio-cells = <2>;
  181. interrupt-controller;
  182. #interrupt-cells = <2>;
  183. status = "disabled";
  184. };
  185. gpio1: gpio@e0680000 {
  186. compatible = "arm,pl061", "arm,primecell";
  187. reg = <0xe0680000 0x1000>;
  188. interrupts = <0 25 0x4>;
  189. gpio-controller;
  190. #gpio-cells = <2>;
  191. interrupt-controller;
  192. #interrupt-cells = <2>;
  193. status = "disabled";
  194. };
  195. kbd@e0300000 {
  196. compatible = "st,spear300-kbd";
  197. reg = <0xe0300000 0x1000>;
  198. interrupts = <0 52 0x4>;
  199. status = "disabled";
  200. };
  201. i2c0: i2c@e0280000 {
  202. #address-cells = <1>;
  203. #size-cells = <0>;
  204. compatible = "snps,designware-i2c";
  205. reg = <0xe0280000 0x1000>;
  206. interrupts = <0 41 0x4>;
  207. status = "disabled";
  208. };
  209. i2s@e0180000 {
  210. compatible = "st,designware-i2s";
  211. reg = <0xe0180000 0x1000>;
  212. interrupt-names = "play_irq", "record_irq";
  213. interrupts = <0 10 0x4
  214. 0 11 0x4 >;
  215. status = "disabled";
  216. };
  217. i2s@e0200000 {
  218. compatible = "st,designware-i2s";
  219. reg = <0xe0200000 0x1000>;
  220. interrupt-names = "play_irq", "record_irq";
  221. interrupts = <0 26 0x4
  222. 0 53 0x4>;
  223. status = "disabled";
  224. };
  225. spi0: spi@e0100000 {
  226. compatible = "arm,pl022", "arm,primecell";
  227. reg = <0xe0100000 0x1000>;
  228. #address-cells = <1>;
  229. #size-cells = <0>;
  230. interrupts = <0 31 0x4>;
  231. status = "disabled";
  232. };
  233. rtc@e0580000 {
  234. compatible = "st,spear600-rtc";
  235. reg = <0xe0580000 0x1000>;
  236. interrupts = <0 36 0x4>;
  237. status = "disabled";
  238. };
  239. serial@e0000000 {
  240. compatible = "arm,pl011", "arm,primecell";
  241. reg = <0xe0000000 0x1000>;
  242. interrupts = <0 35 0x4>;
  243. status = "disabled";
  244. };
  245. adc@e0080000 {
  246. compatible = "st,spear600-adc";
  247. reg = <0xe0080000 0x1000>;
  248. interrupts = <0 12 0x4>;
  249. status = "disabled";
  250. };
  251. timer@e0380000 {
  252. compatible = "st,spear-timer";
  253. reg = <0xe0380000 0x400>;
  254. interrupts = <0 37 0x4>;
  255. };
  256. timer@ec800600 {
  257. compatible = "arm,cortex-a9-twd-timer";
  258. reg = <0xec800600 0x20>;
  259. interrupts = <1 13 0x4>;
  260. status = "disabled";
  261. };
  262. wdt@ec800620 {
  263. compatible = "arm,cortex-a9-twd-wdt";
  264. reg = <0xec800620 0x20>;
  265. status = "disabled";
  266. };
  267. thermal@e07008c4 {
  268. compatible = "st,thermal-spear1340";
  269. reg = <0xe07008c4 0x4>;
  270. thermal_flags = <0x7000>;
  271. };
  272. };
  273. };
  274. };