imx6qdl.dtsi 19 KB

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  1. /*
  2. * Copyright 2011 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12. /include/ "skeleton.dtsi"
  13. / {
  14. aliases {
  15. serial0 = &uart1;
  16. serial1 = &uart2;
  17. serial2 = &uart3;
  18. serial3 = &uart4;
  19. serial4 = &uart5;
  20. gpio0 = &gpio1;
  21. gpio1 = &gpio2;
  22. gpio2 = &gpio3;
  23. gpio3 = &gpio4;
  24. gpio4 = &gpio5;
  25. gpio5 = &gpio6;
  26. gpio6 = &gpio7;
  27. };
  28. intc: interrupt-controller@00a01000 {
  29. compatible = "arm,cortex-a9-gic";
  30. #interrupt-cells = <3>;
  31. #address-cells = <1>;
  32. #size-cells = <1>;
  33. interrupt-controller;
  34. reg = <0x00a01000 0x1000>,
  35. <0x00a00100 0x100>;
  36. };
  37. clocks {
  38. #address-cells = <1>;
  39. #size-cells = <0>;
  40. ckil {
  41. compatible = "fsl,imx-ckil", "fixed-clock";
  42. clock-frequency = <32768>;
  43. };
  44. ckih1 {
  45. compatible = "fsl,imx-ckih1", "fixed-clock";
  46. clock-frequency = <0>;
  47. };
  48. osc {
  49. compatible = "fsl,imx-osc", "fixed-clock";
  50. clock-frequency = <24000000>;
  51. };
  52. };
  53. soc {
  54. #address-cells = <1>;
  55. #size-cells = <1>;
  56. compatible = "simple-bus";
  57. interrupt-parent = <&intc>;
  58. ranges;
  59. dma-apbh@00110000 {
  60. compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  61. reg = <0x00110000 0x2000>;
  62. clocks = <&clks 106>;
  63. };
  64. gpmi: gpmi-nand@00112000 {
  65. compatible = "fsl,imx6q-gpmi-nand";
  66. #address-cells = <1>;
  67. #size-cells = <1>;
  68. reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
  69. reg-names = "gpmi-nand", "bch";
  70. interrupts = <0 13 0x04>, <0 15 0x04>;
  71. interrupt-names = "gpmi-dma", "bch";
  72. clocks = <&clks 152>, <&clks 153>, <&clks 151>,
  73. <&clks 150>, <&clks 149>;
  74. clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
  75. "gpmi_bch_apb", "per1_bch";
  76. fsl,gpmi-dma-channel = <0>;
  77. status = "disabled";
  78. };
  79. timer@00a00600 {
  80. compatible = "arm,cortex-a9-twd-timer";
  81. reg = <0x00a00600 0x20>;
  82. interrupts = <1 13 0xf01>;
  83. };
  84. L2: l2-cache@00a02000 {
  85. compatible = "arm,pl310-cache";
  86. reg = <0x00a02000 0x1000>;
  87. interrupts = <0 92 0x04>;
  88. cache-unified;
  89. cache-level = <2>;
  90. };
  91. aips-bus@02000000 { /* AIPS1 */
  92. compatible = "fsl,aips-bus", "simple-bus";
  93. #address-cells = <1>;
  94. #size-cells = <1>;
  95. reg = <0x02000000 0x100000>;
  96. ranges;
  97. spba-bus@02000000 {
  98. compatible = "fsl,spba-bus", "simple-bus";
  99. #address-cells = <1>;
  100. #size-cells = <1>;
  101. reg = <0x02000000 0x40000>;
  102. ranges;
  103. spdif: spdif@02004000 {
  104. reg = <0x02004000 0x4000>;
  105. interrupts = <0 52 0x04>;
  106. };
  107. ecspi1: ecspi@02008000 {
  108. #address-cells = <1>;
  109. #size-cells = <0>;
  110. compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
  111. reg = <0x02008000 0x4000>;
  112. interrupts = <0 31 0x04>;
  113. clocks = <&clks 112>, <&clks 112>;
  114. clock-names = "ipg", "per";
  115. status = "disabled";
  116. };
  117. ecspi2: ecspi@0200c000 {
  118. #address-cells = <1>;
  119. #size-cells = <0>;
  120. compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
  121. reg = <0x0200c000 0x4000>;
  122. interrupts = <0 32 0x04>;
  123. clocks = <&clks 113>, <&clks 113>;
  124. clock-names = "ipg", "per";
  125. status = "disabled";
  126. };
  127. ecspi3: ecspi@02010000 {
  128. #address-cells = <1>;
  129. #size-cells = <0>;
  130. compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
  131. reg = <0x02010000 0x4000>;
  132. interrupts = <0 33 0x04>;
  133. clocks = <&clks 114>, <&clks 114>;
  134. clock-names = "ipg", "per";
  135. status = "disabled";
  136. };
  137. ecspi4: ecspi@02014000 {
  138. #address-cells = <1>;
  139. #size-cells = <0>;
  140. compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
  141. reg = <0x02014000 0x4000>;
  142. interrupts = <0 34 0x04>;
  143. clocks = <&clks 115>, <&clks 115>;
  144. clock-names = "ipg", "per";
  145. status = "disabled";
  146. };
  147. uart1: serial@02020000 {
  148. compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
  149. reg = <0x02020000 0x4000>;
  150. interrupts = <0 26 0x04>;
  151. clocks = <&clks 160>, <&clks 161>;
  152. clock-names = "ipg", "per";
  153. status = "disabled";
  154. };
  155. esai: esai@02024000 {
  156. reg = <0x02024000 0x4000>;
  157. interrupts = <0 51 0x04>;
  158. };
  159. ssi1: ssi@02028000 {
  160. compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
  161. reg = <0x02028000 0x4000>;
  162. interrupts = <0 46 0x04>;
  163. clocks = <&clks 178>;
  164. fsl,fifo-depth = <15>;
  165. fsl,ssi-dma-events = <38 37>;
  166. status = "disabled";
  167. };
  168. ssi2: ssi@0202c000 {
  169. compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
  170. reg = <0x0202c000 0x4000>;
  171. interrupts = <0 47 0x04>;
  172. clocks = <&clks 179>;
  173. fsl,fifo-depth = <15>;
  174. fsl,ssi-dma-events = <42 41>;
  175. status = "disabled";
  176. };
  177. ssi3: ssi@02030000 {
  178. compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
  179. reg = <0x02030000 0x4000>;
  180. interrupts = <0 48 0x04>;
  181. clocks = <&clks 180>;
  182. fsl,fifo-depth = <15>;
  183. fsl,ssi-dma-events = <46 45>;
  184. status = "disabled";
  185. };
  186. asrc: asrc@02034000 {
  187. reg = <0x02034000 0x4000>;
  188. interrupts = <0 50 0x04>;
  189. };
  190. spba@0203c000 {
  191. reg = <0x0203c000 0x4000>;
  192. };
  193. };
  194. vpu: vpu@02040000 {
  195. reg = <0x02040000 0x3c000>;
  196. interrupts = <0 3 0x04 0 12 0x04>;
  197. };
  198. aipstz@0207c000 { /* AIPSTZ1 */
  199. reg = <0x0207c000 0x4000>;
  200. };
  201. pwm1: pwm@02080000 {
  202. #pwm-cells = <2>;
  203. compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
  204. reg = <0x02080000 0x4000>;
  205. interrupts = <0 83 0x04>;
  206. clocks = <&clks 62>, <&clks 145>;
  207. clock-names = "ipg", "per";
  208. };
  209. pwm2: pwm@02084000 {
  210. #pwm-cells = <2>;
  211. compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
  212. reg = <0x02084000 0x4000>;
  213. interrupts = <0 84 0x04>;
  214. clocks = <&clks 62>, <&clks 146>;
  215. clock-names = "ipg", "per";
  216. };
  217. pwm3: pwm@02088000 {
  218. #pwm-cells = <2>;
  219. compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
  220. reg = <0x02088000 0x4000>;
  221. interrupts = <0 85 0x04>;
  222. clocks = <&clks 62>, <&clks 147>;
  223. clock-names = "ipg", "per";
  224. };
  225. pwm4: pwm@0208c000 {
  226. #pwm-cells = <2>;
  227. compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
  228. reg = <0x0208c000 0x4000>;
  229. interrupts = <0 86 0x04>;
  230. clocks = <&clks 62>, <&clks 148>;
  231. clock-names = "ipg", "per";
  232. };
  233. can1: flexcan@02090000 {
  234. reg = <0x02090000 0x4000>;
  235. interrupts = <0 110 0x04>;
  236. };
  237. can2: flexcan@02094000 {
  238. reg = <0x02094000 0x4000>;
  239. interrupts = <0 111 0x04>;
  240. };
  241. gpt: gpt@02098000 {
  242. compatible = "fsl,imx6q-gpt";
  243. reg = <0x02098000 0x4000>;
  244. interrupts = <0 55 0x04>;
  245. };
  246. gpio1: gpio@0209c000 {
  247. compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
  248. reg = <0x0209c000 0x4000>;
  249. interrupts = <0 66 0x04 0 67 0x04>;
  250. gpio-controller;
  251. #gpio-cells = <2>;
  252. interrupt-controller;
  253. #interrupt-cells = <2>;
  254. };
  255. gpio2: gpio@020a0000 {
  256. compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
  257. reg = <0x020a0000 0x4000>;
  258. interrupts = <0 68 0x04 0 69 0x04>;
  259. gpio-controller;
  260. #gpio-cells = <2>;
  261. interrupt-controller;
  262. #interrupt-cells = <2>;
  263. };
  264. gpio3: gpio@020a4000 {
  265. compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
  266. reg = <0x020a4000 0x4000>;
  267. interrupts = <0 70 0x04 0 71 0x04>;
  268. gpio-controller;
  269. #gpio-cells = <2>;
  270. interrupt-controller;
  271. #interrupt-cells = <2>;
  272. };
  273. gpio4: gpio@020a8000 {
  274. compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
  275. reg = <0x020a8000 0x4000>;
  276. interrupts = <0 72 0x04 0 73 0x04>;
  277. gpio-controller;
  278. #gpio-cells = <2>;
  279. interrupt-controller;
  280. #interrupt-cells = <2>;
  281. };
  282. gpio5: gpio@020ac000 {
  283. compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
  284. reg = <0x020ac000 0x4000>;
  285. interrupts = <0 74 0x04 0 75 0x04>;
  286. gpio-controller;
  287. #gpio-cells = <2>;
  288. interrupt-controller;
  289. #interrupt-cells = <2>;
  290. };
  291. gpio6: gpio@020b0000 {
  292. compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
  293. reg = <0x020b0000 0x4000>;
  294. interrupts = <0 76 0x04 0 77 0x04>;
  295. gpio-controller;
  296. #gpio-cells = <2>;
  297. interrupt-controller;
  298. #interrupt-cells = <2>;
  299. };
  300. gpio7: gpio@020b4000 {
  301. compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
  302. reg = <0x020b4000 0x4000>;
  303. interrupts = <0 78 0x04 0 79 0x04>;
  304. gpio-controller;
  305. #gpio-cells = <2>;
  306. interrupt-controller;
  307. #interrupt-cells = <2>;
  308. };
  309. kpp: kpp@020b8000 {
  310. reg = <0x020b8000 0x4000>;
  311. interrupts = <0 82 0x04>;
  312. };
  313. wdog1: wdog@020bc000 {
  314. compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
  315. reg = <0x020bc000 0x4000>;
  316. interrupts = <0 80 0x04>;
  317. clocks = <&clks 0>;
  318. };
  319. wdog2: wdog@020c0000 {
  320. compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
  321. reg = <0x020c0000 0x4000>;
  322. interrupts = <0 81 0x04>;
  323. clocks = <&clks 0>;
  324. status = "disabled";
  325. };
  326. clks: ccm@020c4000 {
  327. compatible = "fsl,imx6q-ccm";
  328. reg = <0x020c4000 0x4000>;
  329. interrupts = <0 87 0x04 0 88 0x04>;
  330. #clock-cells = <1>;
  331. };
  332. anatop: anatop@020c8000 {
  333. compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
  334. reg = <0x020c8000 0x1000>;
  335. interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
  336. regulator-1p1@110 {
  337. compatible = "fsl,anatop-regulator";
  338. regulator-name = "vdd1p1";
  339. regulator-min-microvolt = <800000>;
  340. regulator-max-microvolt = <1375000>;
  341. regulator-always-on;
  342. anatop-reg-offset = <0x110>;
  343. anatop-vol-bit-shift = <8>;
  344. anatop-vol-bit-width = <5>;
  345. anatop-min-bit-val = <4>;
  346. anatop-min-voltage = <800000>;
  347. anatop-max-voltage = <1375000>;
  348. };
  349. regulator-3p0@120 {
  350. compatible = "fsl,anatop-regulator";
  351. regulator-name = "vdd3p0";
  352. regulator-min-microvolt = <2800000>;
  353. regulator-max-microvolt = <3150000>;
  354. regulator-always-on;
  355. anatop-reg-offset = <0x120>;
  356. anatop-vol-bit-shift = <8>;
  357. anatop-vol-bit-width = <5>;
  358. anatop-min-bit-val = <0>;
  359. anatop-min-voltage = <2625000>;
  360. anatop-max-voltage = <3400000>;
  361. };
  362. regulator-2p5@130 {
  363. compatible = "fsl,anatop-regulator";
  364. regulator-name = "vdd2p5";
  365. regulator-min-microvolt = <2000000>;
  366. regulator-max-microvolt = <2750000>;
  367. regulator-always-on;
  368. anatop-reg-offset = <0x130>;
  369. anatop-vol-bit-shift = <8>;
  370. anatop-vol-bit-width = <5>;
  371. anatop-min-bit-val = <0>;
  372. anatop-min-voltage = <2000000>;
  373. anatop-max-voltage = <2750000>;
  374. };
  375. reg_arm: regulator-vddcore@140 {
  376. compatible = "fsl,anatop-regulator";
  377. regulator-name = "cpu";
  378. regulator-min-microvolt = <725000>;
  379. regulator-max-microvolt = <1450000>;
  380. regulator-always-on;
  381. anatop-reg-offset = <0x140>;
  382. anatop-vol-bit-shift = <0>;
  383. anatop-vol-bit-width = <5>;
  384. anatop-delay-reg-offset = <0x170>;
  385. anatop-delay-bit-shift = <24>;
  386. anatop-delay-bit-width = <2>;
  387. anatop-min-bit-val = <1>;
  388. anatop-min-voltage = <725000>;
  389. anatop-max-voltage = <1450000>;
  390. };
  391. reg_pu: regulator-vddpu@140 {
  392. compatible = "fsl,anatop-regulator";
  393. regulator-name = "vddpu";
  394. regulator-min-microvolt = <725000>;
  395. regulator-max-microvolt = <1450000>;
  396. regulator-always-on;
  397. anatop-reg-offset = <0x140>;
  398. anatop-vol-bit-shift = <9>;
  399. anatop-vol-bit-width = <5>;
  400. anatop-delay-reg-offset = <0x170>;
  401. anatop-delay-bit-shift = <26>;
  402. anatop-delay-bit-width = <2>;
  403. anatop-min-bit-val = <1>;
  404. anatop-min-voltage = <725000>;
  405. anatop-max-voltage = <1450000>;
  406. };
  407. reg_soc: regulator-vddsoc@140 {
  408. compatible = "fsl,anatop-regulator";
  409. regulator-name = "vddsoc";
  410. regulator-min-microvolt = <725000>;
  411. regulator-max-microvolt = <1450000>;
  412. regulator-always-on;
  413. anatop-reg-offset = <0x140>;
  414. anatop-vol-bit-shift = <18>;
  415. anatop-vol-bit-width = <5>;
  416. anatop-delay-reg-offset = <0x170>;
  417. anatop-delay-bit-shift = <28>;
  418. anatop-delay-bit-width = <2>;
  419. anatop-min-bit-val = <1>;
  420. anatop-min-voltage = <725000>;
  421. anatop-max-voltage = <1450000>;
  422. };
  423. };
  424. usbphy1: usbphy@020c9000 {
  425. compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
  426. reg = <0x020c9000 0x1000>;
  427. interrupts = <0 44 0x04>;
  428. clocks = <&clks 182>;
  429. };
  430. usbphy2: usbphy@020ca000 {
  431. compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
  432. reg = <0x020ca000 0x1000>;
  433. interrupts = <0 45 0x04>;
  434. clocks = <&clks 183>;
  435. };
  436. snvs@020cc000 {
  437. compatible = "fsl,sec-v4.0-mon", "simple-bus";
  438. #address-cells = <1>;
  439. #size-cells = <1>;
  440. ranges = <0 0x020cc000 0x4000>;
  441. snvs-rtc-lp@34 {
  442. compatible = "fsl,sec-v4.0-mon-rtc-lp";
  443. reg = <0x34 0x58>;
  444. interrupts = <0 19 0x04 0 20 0x04>;
  445. };
  446. };
  447. epit1: epit@020d0000 { /* EPIT1 */
  448. reg = <0x020d0000 0x4000>;
  449. interrupts = <0 56 0x04>;
  450. };
  451. epit2: epit@020d4000 { /* EPIT2 */
  452. reg = <0x020d4000 0x4000>;
  453. interrupts = <0 57 0x04>;
  454. };
  455. src: src@020d8000 {
  456. compatible = "fsl,imx6q-src";
  457. reg = <0x020d8000 0x4000>;
  458. interrupts = <0 91 0x04 0 96 0x04>;
  459. };
  460. gpc: gpc@020dc000 {
  461. compatible = "fsl,imx6q-gpc";
  462. reg = <0x020dc000 0x4000>;
  463. interrupts = <0 89 0x04 0 90 0x04>;
  464. };
  465. gpr: iomuxc-gpr@020e0000 {
  466. compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
  467. reg = <0x020e0000 0x38>;
  468. };
  469. dcic1: dcic@020e4000 {
  470. reg = <0x020e4000 0x4000>;
  471. interrupts = <0 124 0x04>;
  472. };
  473. dcic2: dcic@020e8000 {
  474. reg = <0x020e8000 0x4000>;
  475. interrupts = <0 125 0x04>;
  476. };
  477. sdma: sdma@020ec000 {
  478. compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
  479. reg = <0x020ec000 0x4000>;
  480. interrupts = <0 2 0x04>;
  481. clocks = <&clks 155>, <&clks 155>;
  482. clock-names = "ipg", "ahb";
  483. fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
  484. };
  485. };
  486. aips-bus@02100000 { /* AIPS2 */
  487. compatible = "fsl,aips-bus", "simple-bus";
  488. #address-cells = <1>;
  489. #size-cells = <1>;
  490. reg = <0x02100000 0x100000>;
  491. ranges;
  492. caam@02100000 {
  493. reg = <0x02100000 0x40000>;
  494. interrupts = <0 105 0x04 0 106 0x04>;
  495. };
  496. aipstz@0217c000 { /* AIPSTZ2 */
  497. reg = <0x0217c000 0x4000>;
  498. };
  499. usbotg: usb@02184000 {
  500. compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
  501. reg = <0x02184000 0x200>;
  502. interrupts = <0 43 0x04>;
  503. clocks = <&clks 162>;
  504. fsl,usbphy = <&usbphy1>;
  505. fsl,usbmisc = <&usbmisc 0>;
  506. status = "disabled";
  507. };
  508. usbh1: usb@02184200 {
  509. compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
  510. reg = <0x02184200 0x200>;
  511. interrupts = <0 40 0x04>;
  512. clocks = <&clks 162>;
  513. fsl,usbphy = <&usbphy2>;
  514. fsl,usbmisc = <&usbmisc 1>;
  515. status = "disabled";
  516. };
  517. usbh2: usb@02184400 {
  518. compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
  519. reg = <0x02184400 0x200>;
  520. interrupts = <0 41 0x04>;
  521. clocks = <&clks 162>;
  522. fsl,usbmisc = <&usbmisc 2>;
  523. status = "disabled";
  524. };
  525. usbh3: usb@02184600 {
  526. compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
  527. reg = <0x02184600 0x200>;
  528. interrupts = <0 42 0x04>;
  529. clocks = <&clks 162>;
  530. fsl,usbmisc = <&usbmisc 3>;
  531. status = "disabled";
  532. };
  533. usbmisc: usbmisc: usbmisc@02184800 {
  534. #index-cells = <1>;
  535. compatible = "fsl,imx6q-usbmisc";
  536. reg = <0x02184800 0x200>;
  537. clocks = <&clks 162>;
  538. };
  539. fec: ethernet@02188000 {
  540. compatible = "fsl,imx6q-fec";
  541. reg = <0x02188000 0x4000>;
  542. interrupts = <0 118 0x04 0 119 0x04>;
  543. clocks = <&clks 117>, <&clks 117>, <&clks 190>;
  544. clock-names = "ipg", "ahb", "ptp";
  545. status = "disabled";
  546. };
  547. mlb@0218c000 {
  548. reg = <0x0218c000 0x4000>;
  549. interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
  550. };
  551. usdhc1: usdhc@02190000 {
  552. compatible = "fsl,imx6q-usdhc";
  553. reg = <0x02190000 0x4000>;
  554. interrupts = <0 22 0x04>;
  555. clocks = <&clks 163>, <&clks 163>, <&clks 163>;
  556. clock-names = "ipg", "ahb", "per";
  557. bus-width = <4>;
  558. status = "disabled";
  559. };
  560. usdhc2: usdhc@02194000 {
  561. compatible = "fsl,imx6q-usdhc";
  562. reg = <0x02194000 0x4000>;
  563. interrupts = <0 23 0x04>;
  564. clocks = <&clks 164>, <&clks 164>, <&clks 164>;
  565. clock-names = "ipg", "ahb", "per";
  566. bus-width = <4>;
  567. status = "disabled";
  568. };
  569. usdhc3: usdhc@02198000 {
  570. compatible = "fsl,imx6q-usdhc";
  571. reg = <0x02198000 0x4000>;
  572. interrupts = <0 24 0x04>;
  573. clocks = <&clks 165>, <&clks 165>, <&clks 165>;
  574. clock-names = "ipg", "ahb", "per";
  575. bus-width = <4>;
  576. status = "disabled";
  577. };
  578. usdhc4: usdhc@0219c000 {
  579. compatible = "fsl,imx6q-usdhc";
  580. reg = <0x0219c000 0x4000>;
  581. interrupts = <0 25 0x04>;
  582. clocks = <&clks 166>, <&clks 166>, <&clks 166>;
  583. clock-names = "ipg", "ahb", "per";
  584. bus-width = <4>;
  585. status = "disabled";
  586. };
  587. i2c1: i2c@021a0000 {
  588. #address-cells = <1>;
  589. #size-cells = <0>;
  590. compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
  591. reg = <0x021a0000 0x4000>;
  592. interrupts = <0 36 0x04>;
  593. clocks = <&clks 125>;
  594. status = "disabled";
  595. };
  596. i2c2: i2c@021a4000 {
  597. #address-cells = <1>;
  598. #size-cells = <0>;
  599. compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
  600. reg = <0x021a4000 0x4000>;
  601. interrupts = <0 37 0x04>;
  602. clocks = <&clks 126>;
  603. status = "disabled";
  604. };
  605. i2c3: i2c@021a8000 {
  606. #address-cells = <1>;
  607. #size-cells = <0>;
  608. compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
  609. reg = <0x021a8000 0x4000>;
  610. interrupts = <0 38 0x04>;
  611. clocks = <&clks 127>;
  612. status = "disabled";
  613. };
  614. romcp@021ac000 {
  615. reg = <0x021ac000 0x4000>;
  616. };
  617. mmdc0: mmdc@021b0000 { /* MMDC0 */
  618. compatible = "fsl,imx6q-mmdc";
  619. reg = <0x021b0000 0x4000>;
  620. };
  621. mmdc1: mmdc@021b4000 { /* MMDC1 */
  622. reg = <0x021b4000 0x4000>;
  623. };
  624. weim@021b8000 {
  625. reg = <0x021b8000 0x4000>;
  626. interrupts = <0 14 0x04>;
  627. };
  628. ocotp@021bc000 {
  629. compatible = "fsl,imx6q-ocotp";
  630. reg = <0x021bc000 0x4000>;
  631. };
  632. ocotp@021c0000 {
  633. reg = <0x021c0000 0x4000>;
  634. interrupts = <0 21 0x04>;
  635. };
  636. tzasc@021d0000 { /* TZASC1 */
  637. reg = <0x021d0000 0x4000>;
  638. interrupts = <0 108 0x04>;
  639. };
  640. tzasc@021d4000 { /* TZASC2 */
  641. reg = <0x021d4000 0x4000>;
  642. interrupts = <0 109 0x04>;
  643. };
  644. audmux: audmux@021d8000 {
  645. compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
  646. reg = <0x021d8000 0x4000>;
  647. status = "disabled";
  648. };
  649. mipi@021dc000 { /* MIPI-CSI */
  650. reg = <0x021dc000 0x4000>;
  651. };
  652. mipi@021e0000 { /* MIPI-DSI */
  653. reg = <0x021e0000 0x4000>;
  654. };
  655. vdoa@021e4000 {
  656. reg = <0x021e4000 0x4000>;
  657. interrupts = <0 18 0x04>;
  658. };
  659. uart2: serial@021e8000 {
  660. compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
  661. reg = <0x021e8000 0x4000>;
  662. interrupts = <0 27 0x04>;
  663. clocks = <&clks 160>, <&clks 161>;
  664. clock-names = "ipg", "per";
  665. status = "disabled";
  666. };
  667. uart3: serial@021ec000 {
  668. compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
  669. reg = <0x021ec000 0x4000>;
  670. interrupts = <0 28 0x04>;
  671. clocks = <&clks 160>, <&clks 161>;
  672. clock-names = "ipg", "per";
  673. status = "disabled";
  674. };
  675. uart4: serial@021f0000 {
  676. compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
  677. reg = <0x021f0000 0x4000>;
  678. interrupts = <0 29 0x04>;
  679. clocks = <&clks 160>, <&clks 161>;
  680. clock-names = "ipg", "per";
  681. status = "disabled";
  682. };
  683. uart5: serial@021f4000 {
  684. compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
  685. reg = <0x021f4000 0x4000>;
  686. interrupts = <0 30 0x04>;
  687. clocks = <&clks 160>, <&clks 161>;
  688. clock-names = "ipg", "per";
  689. status = "disabled";
  690. };
  691. };
  692. ipu1: ipu@02400000 {
  693. #crtc-cells = <1>;
  694. compatible = "fsl,imx6q-ipu";
  695. reg = <0x02400000 0x400000>;
  696. interrupts = <0 6 0x4 0 5 0x4>;
  697. clocks = <&clks 130>, <&clks 131>, <&clks 132>;
  698. clock-names = "bus", "di0", "di1";
  699. };
  700. };
  701. };