at91sam9x5.dtsi 13 KB

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  1. /*
  2. * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
  3. * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
  4. * AT91SAM9X25, AT91SAM9X35 SoC
  5. *
  6. * Copyright (C) 2012 Atmel,
  7. * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9x5 family SoC";
  14. compatible = "atmel,at91sam9x5";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. gpio0 = &pioA;
  22. gpio1 = &pioB;
  23. gpio2 = &pioC;
  24. gpio3 = &pioD;
  25. tcb0 = &tcb0;
  26. tcb1 = &tcb1;
  27. i2c0 = &i2c0;
  28. i2c1 = &i2c1;
  29. i2c2 = &i2c2;
  30. ssc0 = &ssc0;
  31. };
  32. cpus {
  33. cpu@0 {
  34. compatible = "arm,arm926ejs";
  35. };
  36. };
  37. memory {
  38. reg = <0x20000000 0x10000000>;
  39. };
  40. ahb {
  41. compatible = "simple-bus";
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. ranges;
  45. apb {
  46. compatible = "simple-bus";
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. ranges;
  50. aic: interrupt-controller@fffff000 {
  51. #interrupt-cells = <3>;
  52. compatible = "atmel,at91rm9200-aic";
  53. interrupt-controller;
  54. reg = <0xfffff000 0x200>;
  55. atmel,external-irqs = <31>;
  56. };
  57. ramc0: ramc@ffffe800 {
  58. compatible = "atmel,at91sam9g45-ddramc";
  59. reg = <0xffffe800 0x200>;
  60. };
  61. pmc: pmc@fffffc00 {
  62. compatible = "atmel,at91rm9200-pmc";
  63. reg = <0xfffffc00 0x100>;
  64. };
  65. rstc@fffffe00 {
  66. compatible = "atmel,at91sam9g45-rstc";
  67. reg = <0xfffffe00 0x10>;
  68. };
  69. shdwc@fffffe10 {
  70. compatible = "atmel,at91sam9x5-shdwc";
  71. reg = <0xfffffe10 0x10>;
  72. };
  73. pit: timer@fffffe30 {
  74. compatible = "atmel,at91sam9260-pit";
  75. reg = <0xfffffe30 0xf>;
  76. interrupts = <1 4 7>;
  77. };
  78. tcb0: timer@f8008000 {
  79. compatible = "atmel,at91sam9x5-tcb";
  80. reg = <0xf8008000 0x100>;
  81. interrupts = <17 4 0>;
  82. };
  83. tcb1: timer@f800c000 {
  84. compatible = "atmel,at91sam9x5-tcb";
  85. reg = <0xf800c000 0x100>;
  86. interrupts = <17 4 0>;
  87. };
  88. dma0: dma-controller@ffffec00 {
  89. compatible = "atmel,at91sam9g45-dma";
  90. reg = <0xffffec00 0x200>;
  91. interrupts = <20 4 0>;
  92. };
  93. dma1: dma-controller@ffffee00 {
  94. compatible = "atmel,at91sam9g45-dma";
  95. reg = <0xffffee00 0x200>;
  96. interrupts = <21 4 0>;
  97. };
  98. pinctrl@fffff400 {
  99. #address-cells = <1>;
  100. #size-cells = <1>;
  101. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  102. ranges = <0xfffff400 0xfffff400 0x800>;
  103. /* shared pinctrl settings */
  104. dbgu {
  105. pinctrl_dbgu: dbgu-0 {
  106. atmel,pins =
  107. <0 9 0x1 0x0 /* PA9 periph A */
  108. 0 10 0x1 0x1>; /* PA10 periph A with pullup */
  109. };
  110. };
  111. usart0 {
  112. pinctrl_usart0: usart0-0 {
  113. atmel,pins =
  114. <0 0 0x1 0x1 /* PA0 periph A with pullup */
  115. 0 1 0x1 0x0>; /* PA1 periph A */
  116. };
  117. pinctrl_usart0_rts: usart0_rts-0 {
  118. atmel,pins =
  119. <0 2 0x1 0x0>; /* PA2 periph A */
  120. };
  121. pinctrl_usart0_cts: usart0_cts-0 {
  122. atmel,pins =
  123. <0 3 0x1 0x0>; /* PA3 periph A */
  124. };
  125. pinctrl_usart0_sck: usart0_sck-0 {
  126. atmel,pins =
  127. <0 4 0x1 0x0>; /* PA4 periph A */
  128. };
  129. };
  130. usart1 {
  131. pinctrl_usart1: usart1-0 {
  132. atmel,pins =
  133. <0 5 0x1 0x1 /* PA5 periph A with pullup */
  134. 0 6 0x1 0x0>; /* PA6 periph A */
  135. };
  136. pinctrl_usart1_rts: usart1_rts-0 {
  137. atmel,pins =
  138. <2 27 0x3 0x0>; /* PC27 periph C */
  139. };
  140. pinctrl_usart1_cts: usart1_cts-0 {
  141. atmel,pins =
  142. <2 28 0x3 0x0>; /* PC28 periph C */
  143. };
  144. pinctrl_usart1_sck: usart1_sck-0 {
  145. atmel,pins =
  146. <2 28 0x3 0x0>; /* PC29 periph C */
  147. };
  148. };
  149. usart2 {
  150. pinctrl_usart2: usart2-0 {
  151. atmel,pins =
  152. <0 7 0x1 0x1 /* PA7 periph A with pullup */
  153. 0 8 0x1 0x0>; /* PA8 periph A */
  154. };
  155. pinctrl_uart2_rts: uart2_rts-0 {
  156. atmel,pins =
  157. <1 0 0x2 0x0>; /* PB0 periph B */
  158. };
  159. pinctrl_uart2_cts: uart2_cts-0 {
  160. atmel,pins =
  161. <1 1 0x2 0x0>; /* PB1 periph B */
  162. };
  163. pinctrl_usart2_sck: usart2_sck-0 {
  164. atmel,pins =
  165. <1 2 0x2 0x0>; /* PB2 periph B */
  166. };
  167. };
  168. usart3 {
  169. pinctrl_usart3: usart3-0 {
  170. atmel,pins =
  171. <2 22 0x2 0x1 /* PC22 periph B with pullup */
  172. 2 23 0x2 0x0>; /* PC23 periph B */
  173. };
  174. pinctrl_usart3_rts: usart3_rts-0 {
  175. atmel,pins =
  176. <2 24 0x2 0x0>; /* PC24 periph B */
  177. };
  178. pinctrl_usart3_cts: usart3_cts-0 {
  179. atmel,pins =
  180. <2 25 0x2 0x0>; /* PC25 periph B */
  181. };
  182. pinctrl_usart3_sck: usart3_sck-0 {
  183. atmel,pins =
  184. <2 26 0x2 0x0>; /* PC26 periph B */
  185. };
  186. };
  187. uart0 {
  188. pinctrl_uart0: uart0-0 {
  189. atmel,pins =
  190. <2 8 0x3 0x0 /* PC8 periph C */
  191. 2 9 0x3 0x1>; /* PC9 periph C with pullup */
  192. };
  193. };
  194. uart1 {
  195. pinctrl_uart1: uart1-0 {
  196. atmel,pins =
  197. <2 16 0x3 0x0 /* PC16 periph C */
  198. 2 17 0x3 0x1>; /* PC17 periph C with pullup */
  199. };
  200. };
  201. nand {
  202. pinctrl_nand: nand-0 {
  203. atmel,pins =
  204. <3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */
  205. 3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */
  206. };
  207. };
  208. macb0 {
  209. pinctrl_macb0_rmii: macb0_rmii-0 {
  210. atmel,pins =
  211. <1 0 0x1 0x0 /* PB0 periph A */
  212. 1 1 0x1 0x0 /* PB1 periph A */
  213. 1 2 0x1 0x0 /* PB2 periph A */
  214. 1 3 0x1 0x0 /* PB3 periph A */
  215. 1 4 0x1 0x0 /* PB4 periph A */
  216. 1 5 0x1 0x0 /* PB5 periph A */
  217. 1 6 0x1 0x0 /* PB6 periph A */
  218. 1 7 0x1 0x0 /* PB7 periph A */
  219. 1 9 0x1 0x0 /* PB9 periph A */
  220. 1 10 0x1 0x0>; /* PB10 periph A */
  221. };
  222. pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
  223. atmel,pins =
  224. <1 8 0x1 0x0 /* PB8 periph A */
  225. 1 11 0x1 0x0 /* PB11 periph A */
  226. 1 12 0x1 0x0 /* PB12 periph A */
  227. 1 13 0x1 0x0 /* PB13 periph A */
  228. 1 14 0x1 0x0 /* PB14 periph A */
  229. 1 15 0x1 0x0 /* PB15 periph A */
  230. 1 16 0x1 0x0 /* PB16 periph A */
  231. 1 17 0x1 0x0>; /* PB17 periph A */
  232. };
  233. };
  234. mmc0 {
  235. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  236. atmel,pins =
  237. <0 17 0x1 0x0 /* PA17 periph A */
  238. 0 16 0x1 0x1 /* PA16 periph A with pullup */
  239. 0 15 0x1 0x1>; /* PA15 periph A with pullup */
  240. };
  241. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  242. atmel,pins =
  243. <0 18 0x1 0x1 /* PA18 periph A with pullup */
  244. 0 19 0x1 0x1 /* PA19 periph A with pullup */
  245. 0 20 0x1 0x1>; /* PA20 periph A with pullup */
  246. };
  247. };
  248. mmc1 {
  249. pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
  250. atmel,pins =
  251. <0 13 0x2 0x0 /* PA13 periph B */
  252. 0 12 0x2 0x1 /* PA12 periph B with pullup */
  253. 0 11 0x2 0x1>; /* PA11 periph B with pullup */
  254. };
  255. pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
  256. atmel,pins =
  257. <0 2 0x2 0x1 /* PA2 periph B with pullup */
  258. 0 3 0x2 0x1 /* PA3 periph B with pullup */
  259. 0 4 0x2 0x1>; /* PA4 periph B with pullup */
  260. };
  261. };
  262. ssc0 {
  263. pinctrl_ssc0_tx: ssc0_tx-0 {
  264. atmel,pins =
  265. <0 24 0x2 0x0 /* PA24 periph B */
  266. 0 25 0x2 0x0 /* PA25 periph B */
  267. 0 26 0x2 0x0>; /* PA26 periph B */
  268. };
  269. pinctrl_ssc0_rx: ssc0_rx-0 {
  270. atmel,pins =
  271. <0 27 0x2 0x0 /* PA27 periph B */
  272. 0 28 0x2 0x0 /* PA28 periph B */
  273. 0 29 0x2 0x0>; /* PA29 periph B */
  274. };
  275. };
  276. pioA: gpio@fffff400 {
  277. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  278. reg = <0xfffff400 0x200>;
  279. interrupts = <2 4 1>;
  280. #gpio-cells = <2>;
  281. gpio-controller;
  282. interrupt-controller;
  283. #interrupt-cells = <2>;
  284. };
  285. pioB: gpio@fffff600 {
  286. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  287. reg = <0xfffff600 0x200>;
  288. interrupts = <2 4 1>;
  289. #gpio-cells = <2>;
  290. gpio-controller;
  291. #gpio-lines = <19>;
  292. interrupt-controller;
  293. #interrupt-cells = <2>;
  294. };
  295. pioC: gpio@fffff800 {
  296. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  297. reg = <0xfffff800 0x200>;
  298. interrupts = <3 4 1>;
  299. #gpio-cells = <2>;
  300. gpio-controller;
  301. interrupt-controller;
  302. #interrupt-cells = <2>;
  303. };
  304. pioD: gpio@fffffa00 {
  305. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  306. reg = <0xfffffa00 0x200>;
  307. interrupts = <3 4 1>;
  308. #gpio-cells = <2>;
  309. gpio-controller;
  310. #gpio-lines = <22>;
  311. interrupt-controller;
  312. #interrupt-cells = <2>;
  313. };
  314. };
  315. ssc0: ssc@f0010000 {
  316. compatible = "atmel,at91sam9g45-ssc";
  317. reg = <0xf0010000 0x4000>;
  318. interrupts = <28 4 5>;
  319. pinctrl-names = "default";
  320. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  321. status = "disabled";
  322. };
  323. mmc0: mmc@f0008000 {
  324. compatible = "atmel,hsmci";
  325. reg = <0xf0008000 0x600>;
  326. interrupts = <12 4 0>;
  327. #address-cells = <1>;
  328. #size-cells = <0>;
  329. status = "disabled";
  330. };
  331. mmc1: mmc@f000c000 {
  332. compatible = "atmel,hsmci";
  333. reg = <0xf000c000 0x600>;
  334. interrupts = <26 4 0>;
  335. #address-cells = <1>;
  336. #size-cells = <0>;
  337. status = "disabled";
  338. };
  339. dbgu: serial@fffff200 {
  340. compatible = "atmel,at91sam9260-usart";
  341. reg = <0xfffff200 0x200>;
  342. interrupts = <1 4 7>;
  343. pinctrl-names = "default";
  344. pinctrl-0 = <&pinctrl_dbgu>;
  345. status = "disabled";
  346. };
  347. usart0: serial@f801c000 {
  348. compatible = "atmel,at91sam9260-usart";
  349. reg = <0xf801c000 0x200>;
  350. interrupts = <5 4 5>;
  351. pinctrl-names = "default";
  352. pinctrl-0 = <&pinctrl_usart0>;
  353. status = "disabled";
  354. };
  355. usart1: serial@f8020000 {
  356. compatible = "atmel,at91sam9260-usart";
  357. reg = <0xf8020000 0x200>;
  358. interrupts = <6 4 5>;
  359. pinctrl-names = "default";
  360. pinctrl-0 = <&pinctrl_usart1>;
  361. status = "disabled";
  362. };
  363. usart2: serial@f8024000 {
  364. compatible = "atmel,at91sam9260-usart";
  365. reg = <0xf8024000 0x200>;
  366. interrupts = <7 4 5>;
  367. pinctrl-names = "default";
  368. pinctrl-0 = <&pinctrl_usart2>;
  369. status = "disabled";
  370. };
  371. macb0: ethernet@f802c000 {
  372. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  373. reg = <0xf802c000 0x100>;
  374. interrupts = <24 4 3>;
  375. pinctrl-names = "default";
  376. pinctrl-0 = <&pinctrl_macb0_rmii>;
  377. status = "disabled";
  378. };
  379. macb1: ethernet@f8030000 {
  380. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  381. reg = <0xf8030000 0x100>;
  382. interrupts = <27 4 3>;
  383. status = "disabled";
  384. };
  385. i2c0: i2c@f8010000 {
  386. compatible = "atmel,at91sam9x5-i2c";
  387. reg = <0xf8010000 0x100>;
  388. interrupts = <9 4 6>;
  389. #address-cells = <1>;
  390. #size-cells = <0>;
  391. status = "disabled";
  392. };
  393. i2c1: i2c@f8014000 {
  394. compatible = "atmel,at91sam9x5-i2c";
  395. reg = <0xf8014000 0x100>;
  396. interrupts = <10 4 6>;
  397. #address-cells = <1>;
  398. #size-cells = <0>;
  399. status = "disabled";
  400. };
  401. i2c2: i2c@f8018000 {
  402. compatible = "atmel,at91sam9x5-i2c";
  403. reg = <0xf8018000 0x100>;
  404. interrupts = <11 4 6>;
  405. #address-cells = <1>;
  406. #size-cells = <0>;
  407. status = "disabled";
  408. };
  409. adc0: adc@f804c000 {
  410. compatible = "atmel,at91sam9260-adc";
  411. reg = <0xf804c000 0x100>;
  412. interrupts = <19 4 0>;
  413. atmel,adc-use-external;
  414. atmel,adc-channels-used = <0xffff>;
  415. atmel,adc-vref = <3300>;
  416. atmel,adc-num-channels = <12>;
  417. atmel,adc-startup-time = <40>;
  418. atmel,adc-channel-base = <0x50>;
  419. atmel,adc-drdy-mask = <0x1000000>;
  420. atmel,adc-status-register = <0x30>;
  421. atmel,adc-trigger-register = <0xc0>;
  422. trigger@0 {
  423. trigger-name = "external-rising";
  424. trigger-value = <0x1>;
  425. trigger-external;
  426. };
  427. trigger@1 {
  428. trigger-name = "external-falling";
  429. trigger-value = <0x2>;
  430. trigger-external;
  431. };
  432. trigger@2 {
  433. trigger-name = "external-any";
  434. trigger-value = <0x3>;
  435. trigger-external;
  436. };
  437. trigger@3 {
  438. trigger-name = "continuous";
  439. trigger-value = <0x6>;
  440. };
  441. };
  442. };
  443. nand0: nand@40000000 {
  444. compatible = "atmel,at91rm9200-nand";
  445. #address-cells = <1>;
  446. #size-cells = <1>;
  447. reg = <0x40000000 0x10000000
  448. 0xffffe000 0x600 /* PMECC Registers */
  449. 0xffffe600 0x200 /* PMECC Error Location Registers */
  450. 0x00108000 0x18000 /* PMECC looup table in ROM code */
  451. >;
  452. atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
  453. atmel,nand-addr-offset = <21>;
  454. atmel,nand-cmd-offset = <22>;
  455. pinctrl-names = "default";
  456. pinctrl-0 = <&pinctrl_nand>;
  457. gpios = <&pioD 5 0
  458. &pioD 4 0
  459. 0
  460. >;
  461. status = "disabled";
  462. };
  463. usb0: ohci@00600000 {
  464. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  465. reg = <0x00600000 0x100000>;
  466. interrupts = <22 4 2>;
  467. status = "disabled";
  468. };
  469. usb1: ehci@00700000 {
  470. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  471. reg = <0x00700000 0x100000>;
  472. interrupts = <22 4 2>;
  473. status = "disabled";
  474. };
  475. };
  476. i2c@0 {
  477. compatible = "i2c-gpio";
  478. gpios = <&pioA 30 0 /* sda */
  479. &pioA 31 0 /* scl */
  480. >;
  481. i2c-gpio,sda-open-drain;
  482. i2c-gpio,scl-open-drain;
  483. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  484. #address-cells = <1>;
  485. #size-cells = <0>;
  486. status = "disabled";
  487. };
  488. i2c@1 {
  489. compatible = "i2c-gpio";
  490. gpios = <&pioC 0 0 /* sda */
  491. &pioC 1 0 /* scl */
  492. >;
  493. i2c-gpio,sda-open-drain;
  494. i2c-gpio,scl-open-drain;
  495. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  496. #address-cells = <1>;
  497. #size-cells = <0>;
  498. status = "disabled";
  499. };
  500. i2c@2 {
  501. compatible = "i2c-gpio";
  502. gpios = <&pioB 4 0 /* sda */
  503. &pioB 5 0 /* scl */
  504. >;
  505. i2c-gpio,sda-open-drain;
  506. i2c-gpio,scl-open-drain;
  507. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  508. #address-cells = <1>;
  509. #size-cells = <0>;
  510. status = "disabled";
  511. };
  512. };