armada-xp-gp.dts 2.2 KB

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  1. /*
  2. * Device Tree file for Marvell Armada XP development board
  3. * (DB-MV784MP-GP)
  4. *
  5. * Copyright (C) 2013 Marvell
  6. *
  7. * Lior Amsalem <alior@marvell.com>
  8. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  9. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. */
  15. /dts-v1/;
  16. /include/ "armada-xp-mv78460.dtsi"
  17. / {
  18. model = "Marvell Armada XP Development Board DB-MV784MP-GP";
  19. compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
  20. chosen {
  21. bootargs = "console=ttyS0,115200 earlyprintk";
  22. };
  23. memory {
  24. device_type = "memory";
  25. /*
  26. * 4 GB of plug-in RAM modules by default but only 3GB
  27. * are visible, the amount of memory available can be
  28. * changed by the bootloader according the size of the
  29. * module actually plugged
  30. */
  31. reg = <0x00000000 0xC0000000>;
  32. };
  33. soc {
  34. serial@d0012000 {
  35. clock-frequency = <250000000>;
  36. status = "okay";
  37. };
  38. serial@d0012100 {
  39. clock-frequency = <250000000>;
  40. status = "okay";
  41. };
  42. serial@d0012200 {
  43. clock-frequency = <250000000>;
  44. status = "okay";
  45. };
  46. serial@d0012300 {
  47. clock-frequency = <250000000>;
  48. status = "okay";
  49. };
  50. sata@d00a0000 {
  51. nr-ports = <2>;
  52. status = "okay";
  53. };
  54. mdio {
  55. phy0: ethernet-phy@0 {
  56. reg = <16>;
  57. };
  58. phy1: ethernet-phy@1 {
  59. reg = <17>;
  60. };
  61. phy2: ethernet-phy@2 {
  62. reg = <18>;
  63. };
  64. phy3: ethernet-phy@3 {
  65. reg = <19>;
  66. };
  67. };
  68. ethernet@d0070000 {
  69. status = "okay";
  70. phy = <&phy0>;
  71. phy-mode = "rgmii-id";
  72. };
  73. ethernet@d0074000 {
  74. status = "okay";
  75. phy = <&phy1>;
  76. phy-mode = "rgmii-id";
  77. };
  78. ethernet@d0030000 {
  79. status = "okay";
  80. phy = <&phy2>;
  81. phy-mode = "rgmii-id";
  82. };
  83. ethernet@d0034000 {
  84. status = "okay";
  85. phy = <&phy3>;
  86. phy-mode = "rgmii-id";
  87. };
  88. spi0: spi@d0010600 {
  89. status = "okay";
  90. spi-flash@0 {
  91. #address-cells = <1>;
  92. #size-cells = <1>;
  93. compatible = "n25q128a13";
  94. reg = <0>; /* Chip select 0 */
  95. spi-max-frequency = <108000000>;
  96. };
  97. };
  98. };
  99. };