am33xx.dtsi 8.6 KB

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  1. /*
  2. * Device Tree Source for AM33XX SoC
  3. *
  4. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. /include/ "skeleton.dtsi"
  11. / {
  12. compatible = "ti,am33xx";
  13. interrupt-parent = <&intc>;
  14. aliases {
  15. serial0 = &uart1;
  16. serial1 = &uart2;
  17. serial2 = &uart3;
  18. serial3 = &uart4;
  19. serial4 = &uart5;
  20. serial5 = &uart6;
  21. };
  22. cpus {
  23. cpu@0 {
  24. compatible = "arm,cortex-a8";
  25. /*
  26. * To consider voltage drop between PMIC and SoC,
  27. * tolerance value is reduced to 2% from 4% and
  28. * voltage value is increased as a precaution.
  29. */
  30. operating-points = <
  31. /* kHz uV */
  32. 720000 1285000
  33. 600000 1225000
  34. 500000 1125000
  35. 275000 1125000
  36. >;
  37. voltage-tolerance = <2>; /* 2 percentage */
  38. clock-latency = <300000>; /* From omap-cpufreq driver */
  39. };
  40. };
  41. /*
  42. * The soc node represents the soc top level view. It is uses for IPs
  43. * that are not memory mapped in the MPU view or for the MPU itself.
  44. */
  45. soc {
  46. compatible = "ti,omap-infra";
  47. mpu {
  48. compatible = "ti,omap3-mpu";
  49. ti,hwmods = "mpu";
  50. };
  51. };
  52. am33xx_pinmux: pinmux@44e10800 {
  53. compatible = "pinctrl-single";
  54. reg = <0x44e10800 0x0238>;
  55. #address-cells = <1>;
  56. #size-cells = <0>;
  57. pinctrl-single,register-width = <32>;
  58. pinctrl-single,function-mask = <0x7f>;
  59. };
  60. /*
  61. * XXX: Use a flat representation of the AM33XX interconnect.
  62. * The real AM33XX interconnect network is quite complex.Since
  63. * that will not bring real advantage to represent that in DT
  64. * for the moment, just use a fake OCP bus entry to represent
  65. * the whole bus hierarchy.
  66. */
  67. ocp {
  68. compatible = "simple-bus";
  69. #address-cells = <1>;
  70. #size-cells = <1>;
  71. ranges;
  72. ti,hwmods = "l3_main";
  73. intc: interrupt-controller@48200000 {
  74. compatible = "ti,omap2-intc";
  75. interrupt-controller;
  76. #interrupt-cells = <1>;
  77. ti,intc-size = <128>;
  78. reg = <0x48200000 0x1000>;
  79. };
  80. gpio1: gpio@44e07000 {
  81. compatible = "ti,omap4-gpio";
  82. ti,hwmods = "gpio1";
  83. gpio-controller;
  84. #gpio-cells = <2>;
  85. interrupt-controller;
  86. #interrupt-cells = <1>;
  87. reg = <0x44e07000 0x1000>;
  88. interrupts = <96>;
  89. };
  90. gpio2: gpio@4804c000 {
  91. compatible = "ti,omap4-gpio";
  92. ti,hwmods = "gpio2";
  93. gpio-controller;
  94. #gpio-cells = <2>;
  95. interrupt-controller;
  96. #interrupt-cells = <1>;
  97. reg = <0x4804c000 0x1000>;
  98. interrupts = <98>;
  99. };
  100. gpio3: gpio@481ac000 {
  101. compatible = "ti,omap4-gpio";
  102. ti,hwmods = "gpio3";
  103. gpio-controller;
  104. #gpio-cells = <2>;
  105. interrupt-controller;
  106. #interrupt-cells = <1>;
  107. reg = <0x481ac000 0x1000>;
  108. interrupts = <32>;
  109. };
  110. gpio4: gpio@481ae000 {
  111. compatible = "ti,omap4-gpio";
  112. ti,hwmods = "gpio4";
  113. gpio-controller;
  114. #gpio-cells = <2>;
  115. interrupt-controller;
  116. #interrupt-cells = <1>;
  117. reg = <0x481ae000 0x1000>;
  118. interrupts = <62>;
  119. };
  120. uart1: serial@44e09000 {
  121. compatible = "ti,omap3-uart";
  122. ti,hwmods = "uart1";
  123. clock-frequency = <48000000>;
  124. reg = <0x44e09000 0x2000>;
  125. interrupts = <72>;
  126. status = "disabled";
  127. };
  128. uart2: serial@48022000 {
  129. compatible = "ti,omap3-uart";
  130. ti,hwmods = "uart2";
  131. clock-frequency = <48000000>;
  132. reg = <0x48022000 0x2000>;
  133. interrupts = <73>;
  134. status = "disabled";
  135. };
  136. uart3: serial@48024000 {
  137. compatible = "ti,omap3-uart";
  138. ti,hwmods = "uart3";
  139. clock-frequency = <48000000>;
  140. reg = <0x48024000 0x2000>;
  141. interrupts = <74>;
  142. status = "disabled";
  143. };
  144. uart4: serial@481a6000 {
  145. compatible = "ti,omap3-uart";
  146. ti,hwmods = "uart4";
  147. clock-frequency = <48000000>;
  148. reg = <0x481a6000 0x2000>;
  149. interrupts = <44>;
  150. status = "disabled";
  151. };
  152. uart5: serial@481a8000 {
  153. compatible = "ti,omap3-uart";
  154. ti,hwmods = "uart5";
  155. clock-frequency = <48000000>;
  156. reg = <0x481a8000 0x2000>;
  157. interrupts = <45>;
  158. status = "disabled";
  159. };
  160. uart6: serial@481aa000 {
  161. compatible = "ti,omap3-uart";
  162. ti,hwmods = "uart6";
  163. clock-frequency = <48000000>;
  164. reg = <0x481aa000 0x2000>;
  165. interrupts = <46>;
  166. status = "disabled";
  167. };
  168. i2c1: i2c@44e0b000 {
  169. compatible = "ti,omap4-i2c";
  170. #address-cells = <1>;
  171. #size-cells = <0>;
  172. ti,hwmods = "i2c1";
  173. reg = <0x44e0b000 0x1000>;
  174. interrupts = <70>;
  175. status = "disabled";
  176. };
  177. i2c2: i2c@4802a000 {
  178. compatible = "ti,omap4-i2c";
  179. #address-cells = <1>;
  180. #size-cells = <0>;
  181. ti,hwmods = "i2c2";
  182. reg = <0x4802a000 0x1000>;
  183. interrupts = <71>;
  184. status = "disabled";
  185. };
  186. i2c3: i2c@4819c000 {
  187. compatible = "ti,omap4-i2c";
  188. #address-cells = <1>;
  189. #size-cells = <0>;
  190. ti,hwmods = "i2c3";
  191. reg = <0x4819c000 0x1000>;
  192. interrupts = <30>;
  193. status = "disabled";
  194. };
  195. wdt2: wdt@44e35000 {
  196. compatible = "ti,omap3-wdt";
  197. ti,hwmods = "wd_timer2";
  198. reg = <0x44e35000 0x1000>;
  199. interrupts = <91>;
  200. };
  201. dcan0: d_can@481cc000 {
  202. compatible = "bosch,d_can";
  203. ti,hwmods = "d_can0";
  204. reg = <0x481cc000 0x2000>;
  205. interrupts = <52>;
  206. status = "disabled";
  207. };
  208. dcan1: d_can@481d0000 {
  209. compatible = "bosch,d_can";
  210. ti,hwmods = "d_can1";
  211. reg = <0x481d0000 0x2000>;
  212. interrupts = <55>;
  213. status = "disabled";
  214. };
  215. timer1: timer@44e31000 {
  216. compatible = "ti,omap2-timer";
  217. reg = <0x44e31000 0x400>;
  218. interrupts = <67>;
  219. ti,hwmods = "timer1";
  220. ti,timer-alwon;
  221. };
  222. timer2: timer@48040000 {
  223. compatible = "ti,omap2-timer";
  224. reg = <0x48040000 0x400>;
  225. interrupts = <68>;
  226. ti,hwmods = "timer2";
  227. };
  228. timer3: timer@48042000 {
  229. compatible = "ti,omap2-timer";
  230. reg = <0x48042000 0x400>;
  231. interrupts = <69>;
  232. ti,hwmods = "timer3";
  233. };
  234. timer4: timer@48044000 {
  235. compatible = "ti,omap2-timer";
  236. reg = <0x48044000 0x400>;
  237. interrupts = <92>;
  238. ti,hwmods = "timer4";
  239. ti,timer-pwm;
  240. };
  241. timer5: timer@48046000 {
  242. compatible = "ti,omap2-timer";
  243. reg = <0x48046000 0x400>;
  244. interrupts = <93>;
  245. ti,hwmods = "timer5";
  246. ti,timer-pwm;
  247. };
  248. timer6: timer@48048000 {
  249. compatible = "ti,omap2-timer";
  250. reg = <0x48048000 0x400>;
  251. interrupts = <94>;
  252. ti,hwmods = "timer6";
  253. ti,timer-pwm;
  254. };
  255. timer7: timer@4804a000 {
  256. compatible = "ti,omap2-timer";
  257. reg = <0x4804a000 0x400>;
  258. interrupts = <95>;
  259. ti,hwmods = "timer7";
  260. ti,timer-pwm;
  261. };
  262. rtc@44e3e000 {
  263. compatible = "ti,da830-rtc";
  264. reg = <0x44e3e000 0x1000>;
  265. interrupts = <75
  266. 76>;
  267. ti,hwmods = "rtc";
  268. };
  269. spi0: spi@48030000 {
  270. compatible = "ti,omap4-mcspi";
  271. #address-cells = <1>;
  272. #size-cells = <0>;
  273. reg = <0x48030000 0x400>;
  274. interrupt = <65>;
  275. ti,spi-num-cs = <2>;
  276. ti,hwmods = "spi0";
  277. status = "disabled";
  278. };
  279. spi1: spi@481a0000 {
  280. compatible = "ti,omap4-mcspi";
  281. #address-cells = <1>;
  282. #size-cells = <0>;
  283. reg = <0x481a0000 0x400>;
  284. interrupt = <125>;
  285. ti,spi-num-cs = <2>;
  286. ti,hwmods = "spi1";
  287. status = "disabled";
  288. };
  289. usb@47400000 {
  290. compatible = "ti,musb-am33xx";
  291. reg = <0x47400000 0x1000 /* usbss */
  292. 0x47401000 0x800 /* musb instance 0 */
  293. 0x47401800 0x800>; /* musb instance 1 */
  294. interrupts = <17 /* usbss */
  295. 18 /* musb instance 0 */
  296. 19>; /* musb instance 1 */
  297. multipoint = <1>;
  298. num-eps = <16>;
  299. ram-bits = <12>;
  300. port0-mode = <3>;
  301. port1-mode = <3>;
  302. power = <250>;
  303. ti,hwmods = "usb_otg_hs";
  304. };
  305. mac: ethernet@4a100000 {
  306. compatible = "ti,cpsw";
  307. ti,hwmods = "cpgmac0";
  308. cpdma_channels = <8>;
  309. ale_entries = <1024>;
  310. bd_ram_size = <0x2000>;
  311. no_bd_ram = <0>;
  312. rx_descs = <64>;
  313. mac_control = <0x20>;
  314. slaves = <2>;
  315. cpts_active_slave = <0>;
  316. cpts_clock_mult = <0x80000000>;
  317. cpts_clock_shift = <29>;
  318. reg = <0x4a100000 0x800
  319. 0x4a101200 0x100>;
  320. #address-cells = <1>;
  321. #size-cells = <1>;
  322. interrupt-parent = <&intc>;
  323. /*
  324. * c0_rx_thresh_pend
  325. * c0_rx_pend
  326. * c0_tx_pend
  327. * c0_misc_pend
  328. */
  329. interrupts = <40 41 42 43>;
  330. ranges;
  331. davinci_mdio: mdio@4a101000 {
  332. compatible = "ti,davinci_mdio";
  333. #address-cells = <1>;
  334. #size-cells = <0>;
  335. ti,hwmods = "davinci_mdio";
  336. bus_freq = <1000000>;
  337. reg = <0x4a101000 0x100>;
  338. };
  339. cpsw_emac0: slave@4a100200 {
  340. /* Filled in by U-Boot */
  341. mac-address = [ 00 00 00 00 00 00 ];
  342. };
  343. cpsw_emac1: slave@4a100300 {
  344. /* Filled in by U-Boot */
  345. mac-address = [ 00 00 00 00 00 00 ];
  346. };
  347. };
  348. ocmcram: ocmcram@40300000 {
  349. compatible = "ti,am3352-ocmcram";
  350. reg = <0x40300000 0x10000>;
  351. ti,hwmods = "ocmcram";
  352. ti,no_idle_on_suspend;
  353. };
  354. wkup_m3: wkup_m3@44d00000 {
  355. compatible = "ti,am3353-wkup-m3";
  356. reg = <0x44d00000 0x4000 /* M3 UMEM */
  357. 0x44d80000 0x2000>; /* M3 DMEM */
  358. ti,hwmods = "wkup_m3";
  359. };
  360. };
  361. };