vmwgfx_execbuf.c 37 KB

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  1. /**************************************************************************
  2. *
  3. * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. **************************************************************************/
  27. #include "vmwgfx_drv.h"
  28. #include "vmwgfx_reg.h"
  29. #include <drm/ttm/ttm_bo_api.h>
  30. #include <drm/ttm/ttm_placement.h>
  31. static int vmw_cmd_invalid(struct vmw_private *dev_priv,
  32. struct vmw_sw_context *sw_context,
  33. SVGA3dCmdHeader *header)
  34. {
  35. return capable(CAP_SYS_ADMIN) ? : -EINVAL;
  36. }
  37. static int vmw_cmd_ok(struct vmw_private *dev_priv,
  38. struct vmw_sw_context *sw_context,
  39. SVGA3dCmdHeader *header)
  40. {
  41. return 0;
  42. }
  43. static void vmw_resource_to_validate_list(struct vmw_sw_context *sw_context,
  44. struct vmw_resource **p_res)
  45. {
  46. struct vmw_resource *res = *p_res;
  47. if (list_empty(&res->validate_head)) {
  48. list_add_tail(&res->validate_head, &sw_context->resource_list);
  49. *p_res = NULL;
  50. } else
  51. vmw_resource_unreference(p_res);
  52. }
  53. /**
  54. * vmw_bo_to_validate_list - add a bo to a validate list
  55. *
  56. * @sw_context: The software context used for this command submission batch.
  57. * @bo: The buffer object to add.
  58. * @fence_flags: Fence flags to be or'ed with any other fence flags for
  59. * this buffer on this submission batch.
  60. * @p_val_node: If non-NULL Will be updated with the validate node number
  61. * on return.
  62. *
  63. * Returns -EINVAL if the limit of number of buffer objects per command
  64. * submission is reached.
  65. */
  66. static int vmw_bo_to_validate_list(struct vmw_sw_context *sw_context,
  67. struct ttm_buffer_object *bo,
  68. uint32_t *p_val_node)
  69. {
  70. uint32_t val_node;
  71. struct ttm_validate_buffer *val_buf;
  72. val_node = vmw_dmabuf_validate_node(bo, sw_context->cur_val_buf);
  73. if (unlikely(val_node >= VMWGFX_MAX_VALIDATIONS)) {
  74. DRM_ERROR("Max number of DMA buffers per submission"
  75. " exceeded.\n");
  76. return -EINVAL;
  77. }
  78. val_buf = &sw_context->val_bufs[val_node];
  79. if (unlikely(val_node == sw_context->cur_val_buf)) {
  80. val_buf->bo = ttm_bo_reference(bo);
  81. list_add_tail(&val_buf->head, &sw_context->validate_nodes);
  82. ++sw_context->cur_val_buf;
  83. }
  84. sw_context->fence_flags |= DRM_VMW_FENCE_FLAG_EXEC;
  85. if (p_val_node)
  86. *p_val_node = val_node;
  87. return 0;
  88. }
  89. static int vmw_cmd_cid_check(struct vmw_private *dev_priv,
  90. struct vmw_sw_context *sw_context,
  91. SVGA3dCmdHeader *header)
  92. {
  93. struct vmw_resource *ctx;
  94. struct vmw_cid_cmd {
  95. SVGA3dCmdHeader header;
  96. __le32 cid;
  97. } *cmd;
  98. int ret;
  99. cmd = container_of(header, struct vmw_cid_cmd, header);
  100. if (likely(sw_context->cid_valid && cmd->cid == sw_context->last_cid))
  101. return 0;
  102. ret = vmw_context_check(dev_priv, sw_context->tfile, cmd->cid,
  103. &ctx);
  104. if (unlikely(ret != 0)) {
  105. DRM_ERROR("Could not find or use context %u\n",
  106. (unsigned) cmd->cid);
  107. return ret;
  108. }
  109. sw_context->last_cid = cmd->cid;
  110. sw_context->cid_valid = true;
  111. sw_context->cur_ctx = ctx;
  112. vmw_resource_to_validate_list(sw_context, &ctx);
  113. return 0;
  114. }
  115. static int vmw_cmd_sid_check(struct vmw_private *dev_priv,
  116. struct vmw_sw_context *sw_context,
  117. uint32_t *sid)
  118. {
  119. struct vmw_surface *srf;
  120. int ret;
  121. struct vmw_resource *res;
  122. if (*sid == SVGA3D_INVALID_ID)
  123. return 0;
  124. if (likely((sw_context->sid_valid &&
  125. *sid == sw_context->last_sid))) {
  126. *sid = sw_context->sid_translation;
  127. return 0;
  128. }
  129. ret = vmw_user_surface_lookup_handle(dev_priv,
  130. sw_context->tfile,
  131. *sid, &srf);
  132. if (unlikely(ret != 0)) {
  133. DRM_ERROR("Could ot find or use surface 0x%08x "
  134. "address 0x%08lx\n",
  135. (unsigned int) *sid,
  136. (unsigned long) sid);
  137. return ret;
  138. }
  139. ret = vmw_surface_validate(dev_priv, srf);
  140. if (unlikely(ret != 0)) {
  141. if (ret != -ERESTARTSYS)
  142. DRM_ERROR("Could not validate surface.\n");
  143. vmw_surface_unreference(&srf);
  144. return ret;
  145. }
  146. sw_context->last_sid = *sid;
  147. sw_context->sid_valid = true;
  148. sw_context->sid_translation = srf->res.id;
  149. *sid = sw_context->sid_translation;
  150. res = &srf->res;
  151. vmw_resource_to_validate_list(sw_context, &res);
  152. return 0;
  153. }
  154. static int vmw_cmd_set_render_target_check(struct vmw_private *dev_priv,
  155. struct vmw_sw_context *sw_context,
  156. SVGA3dCmdHeader *header)
  157. {
  158. struct vmw_sid_cmd {
  159. SVGA3dCmdHeader header;
  160. SVGA3dCmdSetRenderTarget body;
  161. } *cmd;
  162. int ret;
  163. ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
  164. if (unlikely(ret != 0))
  165. return ret;
  166. cmd = container_of(header, struct vmw_sid_cmd, header);
  167. ret = vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.target.sid);
  168. return ret;
  169. }
  170. static int vmw_cmd_surface_copy_check(struct vmw_private *dev_priv,
  171. struct vmw_sw_context *sw_context,
  172. SVGA3dCmdHeader *header)
  173. {
  174. struct vmw_sid_cmd {
  175. SVGA3dCmdHeader header;
  176. SVGA3dCmdSurfaceCopy body;
  177. } *cmd;
  178. int ret;
  179. cmd = container_of(header, struct vmw_sid_cmd, header);
  180. ret = vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.src.sid);
  181. if (unlikely(ret != 0))
  182. return ret;
  183. return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.dest.sid);
  184. }
  185. static int vmw_cmd_stretch_blt_check(struct vmw_private *dev_priv,
  186. struct vmw_sw_context *sw_context,
  187. SVGA3dCmdHeader *header)
  188. {
  189. struct vmw_sid_cmd {
  190. SVGA3dCmdHeader header;
  191. SVGA3dCmdSurfaceStretchBlt body;
  192. } *cmd;
  193. int ret;
  194. cmd = container_of(header, struct vmw_sid_cmd, header);
  195. ret = vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.src.sid);
  196. if (unlikely(ret != 0))
  197. return ret;
  198. return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.dest.sid);
  199. }
  200. static int vmw_cmd_blt_surf_screen_check(struct vmw_private *dev_priv,
  201. struct vmw_sw_context *sw_context,
  202. SVGA3dCmdHeader *header)
  203. {
  204. struct vmw_sid_cmd {
  205. SVGA3dCmdHeader header;
  206. SVGA3dCmdBlitSurfaceToScreen body;
  207. } *cmd;
  208. cmd = container_of(header, struct vmw_sid_cmd, header);
  209. if (unlikely(!sw_context->kernel)) {
  210. DRM_ERROR("Kernel only SVGA3d command: %u.\n", cmd->header.id);
  211. return -EPERM;
  212. }
  213. return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.srcImage.sid);
  214. }
  215. static int vmw_cmd_present_check(struct vmw_private *dev_priv,
  216. struct vmw_sw_context *sw_context,
  217. SVGA3dCmdHeader *header)
  218. {
  219. struct vmw_sid_cmd {
  220. SVGA3dCmdHeader header;
  221. SVGA3dCmdPresent body;
  222. } *cmd;
  223. cmd = container_of(header, struct vmw_sid_cmd, header);
  224. if (unlikely(!sw_context->kernel)) {
  225. DRM_ERROR("Kernel only SVGA3d command: %u.\n", cmd->header.id);
  226. return -EPERM;
  227. }
  228. return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.sid);
  229. }
  230. /**
  231. * vmw_query_bo_switch_prepare - Prepare to switch pinned buffer for queries.
  232. *
  233. * @dev_priv: The device private structure.
  234. * @cid: The hardware context for the next query.
  235. * @new_query_bo: The new buffer holding query results.
  236. * @sw_context: The software context used for this command submission.
  237. *
  238. * This function checks whether @new_query_bo is suitable for holding
  239. * query results, and if another buffer currently is pinned for query
  240. * results. If so, the function prepares the state of @sw_context for
  241. * switching pinned buffers after successful submission of the current
  242. * command batch. It also checks whether we're using a new query context.
  243. * In that case, it makes sure we emit a query barrier for the old
  244. * context before the current query buffer is fenced.
  245. */
  246. static int vmw_query_bo_switch_prepare(struct vmw_private *dev_priv,
  247. uint32_t cid,
  248. struct ttm_buffer_object *new_query_bo,
  249. struct vmw_sw_context *sw_context)
  250. {
  251. int ret;
  252. bool add_cid = false;
  253. uint32_t cid_to_add;
  254. if (unlikely(new_query_bo != sw_context->cur_query_bo)) {
  255. if (unlikely(new_query_bo->num_pages > 4)) {
  256. DRM_ERROR("Query buffer too large.\n");
  257. return -EINVAL;
  258. }
  259. if (unlikely(sw_context->cur_query_bo != NULL)) {
  260. BUG_ON(!sw_context->query_cid_valid);
  261. add_cid = true;
  262. cid_to_add = sw_context->cur_query_cid;
  263. ret = vmw_bo_to_validate_list(sw_context,
  264. sw_context->cur_query_bo,
  265. NULL);
  266. if (unlikely(ret != 0))
  267. return ret;
  268. }
  269. sw_context->cur_query_bo = new_query_bo;
  270. ret = vmw_bo_to_validate_list(sw_context,
  271. dev_priv->dummy_query_bo,
  272. NULL);
  273. if (unlikely(ret != 0))
  274. return ret;
  275. }
  276. if (unlikely(cid != sw_context->cur_query_cid &&
  277. sw_context->query_cid_valid)) {
  278. add_cid = true;
  279. cid_to_add = sw_context->cur_query_cid;
  280. }
  281. sw_context->cur_query_cid = cid;
  282. sw_context->query_cid_valid = true;
  283. if (add_cid) {
  284. struct vmw_resource *ctx = sw_context->cur_ctx;
  285. if (list_empty(&ctx->query_head))
  286. list_add_tail(&ctx->query_head,
  287. &sw_context->query_list);
  288. ret = vmw_bo_to_validate_list(sw_context,
  289. dev_priv->dummy_query_bo,
  290. NULL);
  291. if (unlikely(ret != 0))
  292. return ret;
  293. }
  294. return 0;
  295. }
  296. /**
  297. * vmw_query_bo_switch_commit - Finalize switching pinned query buffer
  298. *
  299. * @dev_priv: The device private structure.
  300. * @sw_context: The software context used for this command submission batch.
  301. *
  302. * This function will check if we're switching query buffers, and will then,
  303. * if no other query waits are issued this command submission batch,
  304. * issue a dummy occlusion query wait used as a query barrier. When the fence
  305. * object following that query wait has signaled, we are sure that all
  306. * preseding queries have finished, and the old query buffer can be unpinned.
  307. * However, since both the new query buffer and the old one are fenced with
  308. * that fence, we can do an asynchronus unpin now, and be sure that the
  309. * old query buffer won't be moved until the fence has signaled.
  310. *
  311. * As mentioned above, both the new - and old query buffers need to be fenced
  312. * using a sequence emitted *after* calling this function.
  313. */
  314. static void vmw_query_bo_switch_commit(struct vmw_private *dev_priv,
  315. struct vmw_sw_context *sw_context)
  316. {
  317. struct vmw_resource *ctx, *next_ctx;
  318. int ret;
  319. /*
  320. * The validate list should still hold references to all
  321. * contexts here.
  322. */
  323. list_for_each_entry_safe(ctx, next_ctx, &sw_context->query_list,
  324. query_head) {
  325. list_del_init(&ctx->query_head);
  326. BUG_ON(list_empty(&ctx->validate_head));
  327. ret = vmw_fifo_emit_dummy_query(dev_priv, ctx->id);
  328. if (unlikely(ret != 0))
  329. DRM_ERROR("Out of fifo space for dummy query.\n");
  330. }
  331. if (dev_priv->pinned_bo != sw_context->cur_query_bo) {
  332. if (dev_priv->pinned_bo) {
  333. vmw_bo_pin(dev_priv->pinned_bo, false);
  334. ttm_bo_unref(&dev_priv->pinned_bo);
  335. }
  336. vmw_bo_pin(sw_context->cur_query_bo, true);
  337. /*
  338. * We pin also the dummy_query_bo buffer so that we
  339. * don't need to validate it when emitting
  340. * dummy queries in context destroy paths.
  341. */
  342. vmw_bo_pin(dev_priv->dummy_query_bo, true);
  343. dev_priv->dummy_query_bo_pinned = true;
  344. dev_priv->query_cid = sw_context->cur_query_cid;
  345. dev_priv->pinned_bo =
  346. ttm_bo_reference(sw_context->cur_query_bo);
  347. }
  348. }
  349. /**
  350. * vmw_query_switch_backoff - clear query barrier list
  351. * @sw_context: The sw context used for this submission batch.
  352. *
  353. * This function is used as part of an error path, where a previously
  354. * set up list of query barriers needs to be cleared.
  355. *
  356. */
  357. static void vmw_query_switch_backoff(struct vmw_sw_context *sw_context)
  358. {
  359. struct list_head *list, *next;
  360. list_for_each_safe(list, next, &sw_context->query_list) {
  361. list_del_init(list);
  362. }
  363. }
  364. static int vmw_translate_guest_ptr(struct vmw_private *dev_priv,
  365. struct vmw_sw_context *sw_context,
  366. SVGAGuestPtr *ptr,
  367. struct vmw_dma_buffer **vmw_bo_p)
  368. {
  369. struct vmw_dma_buffer *vmw_bo = NULL;
  370. struct ttm_buffer_object *bo;
  371. uint32_t handle = ptr->gmrId;
  372. struct vmw_relocation *reloc;
  373. int ret;
  374. ret = vmw_user_dmabuf_lookup(sw_context->tfile, handle, &vmw_bo);
  375. if (unlikely(ret != 0)) {
  376. DRM_ERROR("Could not find or use GMR region.\n");
  377. return -EINVAL;
  378. }
  379. bo = &vmw_bo->base;
  380. if (unlikely(sw_context->cur_reloc >= VMWGFX_MAX_RELOCATIONS)) {
  381. DRM_ERROR("Max number relocations per submission"
  382. " exceeded\n");
  383. ret = -EINVAL;
  384. goto out_no_reloc;
  385. }
  386. reloc = &sw_context->relocs[sw_context->cur_reloc++];
  387. reloc->location = ptr;
  388. ret = vmw_bo_to_validate_list(sw_context, bo, &reloc->index);
  389. if (unlikely(ret != 0))
  390. goto out_no_reloc;
  391. *vmw_bo_p = vmw_bo;
  392. return 0;
  393. out_no_reloc:
  394. vmw_dmabuf_unreference(&vmw_bo);
  395. vmw_bo_p = NULL;
  396. return ret;
  397. }
  398. static int vmw_cmd_end_query(struct vmw_private *dev_priv,
  399. struct vmw_sw_context *sw_context,
  400. SVGA3dCmdHeader *header)
  401. {
  402. struct vmw_dma_buffer *vmw_bo;
  403. struct vmw_query_cmd {
  404. SVGA3dCmdHeader header;
  405. SVGA3dCmdEndQuery q;
  406. } *cmd;
  407. int ret;
  408. cmd = container_of(header, struct vmw_query_cmd, header);
  409. ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
  410. if (unlikely(ret != 0))
  411. return ret;
  412. ret = vmw_translate_guest_ptr(dev_priv, sw_context,
  413. &cmd->q.guestResult,
  414. &vmw_bo);
  415. if (unlikely(ret != 0))
  416. return ret;
  417. ret = vmw_query_bo_switch_prepare(dev_priv, cmd->q.cid,
  418. &vmw_bo->base, sw_context);
  419. vmw_dmabuf_unreference(&vmw_bo);
  420. return ret;
  421. }
  422. static int vmw_cmd_wait_query(struct vmw_private *dev_priv,
  423. struct vmw_sw_context *sw_context,
  424. SVGA3dCmdHeader *header)
  425. {
  426. struct vmw_dma_buffer *vmw_bo;
  427. struct vmw_query_cmd {
  428. SVGA3dCmdHeader header;
  429. SVGA3dCmdWaitForQuery q;
  430. } *cmd;
  431. int ret;
  432. struct vmw_resource *ctx;
  433. cmd = container_of(header, struct vmw_query_cmd, header);
  434. ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
  435. if (unlikely(ret != 0))
  436. return ret;
  437. ret = vmw_translate_guest_ptr(dev_priv, sw_context,
  438. &cmd->q.guestResult,
  439. &vmw_bo);
  440. if (unlikely(ret != 0))
  441. return ret;
  442. vmw_dmabuf_unreference(&vmw_bo);
  443. /*
  444. * This wait will act as a barrier for previous waits for this
  445. * context.
  446. */
  447. ctx = sw_context->cur_ctx;
  448. if (!list_empty(&ctx->query_head))
  449. list_del_init(&ctx->query_head);
  450. return 0;
  451. }
  452. static int vmw_cmd_dma(struct vmw_private *dev_priv,
  453. struct vmw_sw_context *sw_context,
  454. SVGA3dCmdHeader *header)
  455. {
  456. struct vmw_dma_buffer *vmw_bo = NULL;
  457. struct ttm_buffer_object *bo;
  458. struct vmw_surface *srf = NULL;
  459. struct vmw_dma_cmd {
  460. SVGA3dCmdHeader header;
  461. SVGA3dCmdSurfaceDMA dma;
  462. } *cmd;
  463. int ret;
  464. struct vmw_resource *res;
  465. cmd = container_of(header, struct vmw_dma_cmd, header);
  466. ret = vmw_translate_guest_ptr(dev_priv, sw_context,
  467. &cmd->dma.guest.ptr,
  468. &vmw_bo);
  469. if (unlikely(ret != 0))
  470. return ret;
  471. bo = &vmw_bo->base;
  472. ret = vmw_user_surface_lookup_handle(dev_priv, sw_context->tfile,
  473. cmd->dma.host.sid, &srf);
  474. if (ret) {
  475. DRM_ERROR("could not find surface\n");
  476. goto out_no_reloc;
  477. }
  478. ret = vmw_surface_validate(dev_priv, srf);
  479. if (unlikely(ret != 0)) {
  480. if (ret != -ERESTARTSYS)
  481. DRM_ERROR("Culd not validate surface.\n");
  482. goto out_no_validate;
  483. }
  484. /*
  485. * Patch command stream with device SID.
  486. */
  487. cmd->dma.host.sid = srf->res.id;
  488. vmw_kms_cursor_snoop(srf, sw_context->tfile, bo, header);
  489. vmw_dmabuf_unreference(&vmw_bo);
  490. res = &srf->res;
  491. vmw_resource_to_validate_list(sw_context, &res);
  492. return 0;
  493. out_no_validate:
  494. vmw_surface_unreference(&srf);
  495. out_no_reloc:
  496. vmw_dmabuf_unreference(&vmw_bo);
  497. return ret;
  498. }
  499. static int vmw_cmd_draw(struct vmw_private *dev_priv,
  500. struct vmw_sw_context *sw_context,
  501. SVGA3dCmdHeader *header)
  502. {
  503. struct vmw_draw_cmd {
  504. SVGA3dCmdHeader header;
  505. SVGA3dCmdDrawPrimitives body;
  506. } *cmd;
  507. SVGA3dVertexDecl *decl = (SVGA3dVertexDecl *)(
  508. (unsigned long)header + sizeof(*cmd));
  509. SVGA3dPrimitiveRange *range;
  510. uint32_t i;
  511. uint32_t maxnum;
  512. int ret;
  513. ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
  514. if (unlikely(ret != 0))
  515. return ret;
  516. cmd = container_of(header, struct vmw_draw_cmd, header);
  517. maxnum = (header->size - sizeof(cmd->body)) / sizeof(*decl);
  518. if (unlikely(cmd->body.numVertexDecls > maxnum)) {
  519. DRM_ERROR("Illegal number of vertex declarations.\n");
  520. return -EINVAL;
  521. }
  522. for (i = 0; i < cmd->body.numVertexDecls; ++i, ++decl) {
  523. ret = vmw_cmd_sid_check(dev_priv, sw_context,
  524. &decl->array.surfaceId);
  525. if (unlikely(ret != 0))
  526. return ret;
  527. }
  528. maxnum = (header->size - sizeof(cmd->body) -
  529. cmd->body.numVertexDecls * sizeof(*decl)) / sizeof(*range);
  530. if (unlikely(cmd->body.numRanges > maxnum)) {
  531. DRM_ERROR("Illegal number of index ranges.\n");
  532. return -EINVAL;
  533. }
  534. range = (SVGA3dPrimitiveRange *) decl;
  535. for (i = 0; i < cmd->body.numRanges; ++i, ++range) {
  536. ret = vmw_cmd_sid_check(dev_priv, sw_context,
  537. &range->indexArray.surfaceId);
  538. if (unlikely(ret != 0))
  539. return ret;
  540. }
  541. return 0;
  542. }
  543. static int vmw_cmd_tex_state(struct vmw_private *dev_priv,
  544. struct vmw_sw_context *sw_context,
  545. SVGA3dCmdHeader *header)
  546. {
  547. struct vmw_tex_state_cmd {
  548. SVGA3dCmdHeader header;
  549. SVGA3dCmdSetTextureState state;
  550. };
  551. SVGA3dTextureState *last_state = (SVGA3dTextureState *)
  552. ((unsigned long) header + header->size + sizeof(header));
  553. SVGA3dTextureState *cur_state = (SVGA3dTextureState *)
  554. ((unsigned long) header + sizeof(struct vmw_tex_state_cmd));
  555. int ret;
  556. ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
  557. if (unlikely(ret != 0))
  558. return ret;
  559. for (; cur_state < last_state; ++cur_state) {
  560. if (likely(cur_state->name != SVGA3D_TS_BIND_TEXTURE))
  561. continue;
  562. ret = vmw_cmd_sid_check(dev_priv, sw_context,
  563. &cur_state->value);
  564. if (unlikely(ret != 0))
  565. return ret;
  566. }
  567. return 0;
  568. }
  569. static int vmw_cmd_check_define_gmrfb(struct vmw_private *dev_priv,
  570. struct vmw_sw_context *sw_context,
  571. void *buf)
  572. {
  573. struct vmw_dma_buffer *vmw_bo;
  574. int ret;
  575. struct {
  576. uint32_t header;
  577. SVGAFifoCmdDefineGMRFB body;
  578. } *cmd = buf;
  579. ret = vmw_translate_guest_ptr(dev_priv, sw_context,
  580. &cmd->body.ptr,
  581. &vmw_bo);
  582. if (unlikely(ret != 0))
  583. return ret;
  584. vmw_dmabuf_unreference(&vmw_bo);
  585. return ret;
  586. }
  587. static int vmw_cmd_check_not_3d(struct vmw_private *dev_priv,
  588. struct vmw_sw_context *sw_context,
  589. void *buf, uint32_t *size)
  590. {
  591. uint32_t size_remaining = *size;
  592. uint32_t cmd_id;
  593. cmd_id = le32_to_cpu(((uint32_t *)buf)[0]);
  594. switch (cmd_id) {
  595. case SVGA_CMD_UPDATE:
  596. *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdUpdate);
  597. break;
  598. case SVGA_CMD_DEFINE_GMRFB:
  599. *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdDefineGMRFB);
  600. break;
  601. case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
  602. *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdBlitGMRFBToScreen);
  603. break;
  604. case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
  605. *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdBlitGMRFBToScreen);
  606. break;
  607. default:
  608. DRM_ERROR("Unsupported SVGA command: %u.\n", cmd_id);
  609. return -EINVAL;
  610. }
  611. if (*size > size_remaining) {
  612. DRM_ERROR("Invalid SVGA command (size mismatch):"
  613. " %u.\n", cmd_id);
  614. return -EINVAL;
  615. }
  616. if (unlikely(!sw_context->kernel)) {
  617. DRM_ERROR("Kernel only SVGA command: %u.\n", cmd_id);
  618. return -EPERM;
  619. }
  620. if (cmd_id == SVGA_CMD_DEFINE_GMRFB)
  621. return vmw_cmd_check_define_gmrfb(dev_priv, sw_context, buf);
  622. return 0;
  623. }
  624. typedef int (*vmw_cmd_func) (struct vmw_private *,
  625. struct vmw_sw_context *,
  626. SVGA3dCmdHeader *);
  627. #define VMW_CMD_DEF(cmd, func) \
  628. [cmd - SVGA_3D_CMD_BASE] = func
  629. static vmw_cmd_func vmw_cmd_funcs[SVGA_3D_CMD_MAX] = {
  630. VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DEFINE, &vmw_cmd_invalid),
  631. VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DESTROY, &vmw_cmd_invalid),
  632. VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_COPY, &vmw_cmd_surface_copy_check),
  633. VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_STRETCHBLT, &vmw_cmd_stretch_blt_check),
  634. VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DMA, &vmw_cmd_dma),
  635. VMW_CMD_DEF(SVGA_3D_CMD_CONTEXT_DEFINE, &vmw_cmd_invalid),
  636. VMW_CMD_DEF(SVGA_3D_CMD_CONTEXT_DESTROY, &vmw_cmd_invalid),
  637. VMW_CMD_DEF(SVGA_3D_CMD_SETTRANSFORM, &vmw_cmd_cid_check),
  638. VMW_CMD_DEF(SVGA_3D_CMD_SETZRANGE, &vmw_cmd_cid_check),
  639. VMW_CMD_DEF(SVGA_3D_CMD_SETRENDERSTATE, &vmw_cmd_cid_check),
  640. VMW_CMD_DEF(SVGA_3D_CMD_SETRENDERTARGET,
  641. &vmw_cmd_set_render_target_check),
  642. VMW_CMD_DEF(SVGA_3D_CMD_SETTEXTURESTATE, &vmw_cmd_tex_state),
  643. VMW_CMD_DEF(SVGA_3D_CMD_SETMATERIAL, &vmw_cmd_cid_check),
  644. VMW_CMD_DEF(SVGA_3D_CMD_SETLIGHTDATA, &vmw_cmd_cid_check),
  645. VMW_CMD_DEF(SVGA_3D_CMD_SETLIGHTENABLED, &vmw_cmd_cid_check),
  646. VMW_CMD_DEF(SVGA_3D_CMD_SETVIEWPORT, &vmw_cmd_cid_check),
  647. VMW_CMD_DEF(SVGA_3D_CMD_SETCLIPPLANE, &vmw_cmd_cid_check),
  648. VMW_CMD_DEF(SVGA_3D_CMD_CLEAR, &vmw_cmd_cid_check),
  649. VMW_CMD_DEF(SVGA_3D_CMD_PRESENT, &vmw_cmd_present_check),
  650. VMW_CMD_DEF(SVGA_3D_CMD_SHADER_DEFINE, &vmw_cmd_cid_check),
  651. VMW_CMD_DEF(SVGA_3D_CMD_SHADER_DESTROY, &vmw_cmd_cid_check),
  652. VMW_CMD_DEF(SVGA_3D_CMD_SET_SHADER, &vmw_cmd_cid_check),
  653. VMW_CMD_DEF(SVGA_3D_CMD_SET_SHADER_CONST, &vmw_cmd_cid_check),
  654. VMW_CMD_DEF(SVGA_3D_CMD_DRAW_PRIMITIVES, &vmw_cmd_draw),
  655. VMW_CMD_DEF(SVGA_3D_CMD_SETSCISSORRECT, &vmw_cmd_cid_check),
  656. VMW_CMD_DEF(SVGA_3D_CMD_BEGIN_QUERY, &vmw_cmd_cid_check),
  657. VMW_CMD_DEF(SVGA_3D_CMD_END_QUERY, &vmw_cmd_end_query),
  658. VMW_CMD_DEF(SVGA_3D_CMD_WAIT_FOR_QUERY, &vmw_cmd_wait_query),
  659. VMW_CMD_DEF(SVGA_3D_CMD_PRESENT_READBACK, &vmw_cmd_ok),
  660. VMW_CMD_DEF(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN,
  661. &vmw_cmd_blt_surf_screen_check)
  662. };
  663. static int vmw_cmd_check(struct vmw_private *dev_priv,
  664. struct vmw_sw_context *sw_context,
  665. void *buf, uint32_t *size)
  666. {
  667. uint32_t cmd_id;
  668. uint32_t size_remaining = *size;
  669. SVGA3dCmdHeader *header = (SVGA3dCmdHeader *) buf;
  670. int ret;
  671. cmd_id = le32_to_cpu(((uint32_t *)buf)[0]);
  672. /* Handle any none 3D commands */
  673. if (unlikely(cmd_id < SVGA_CMD_MAX))
  674. return vmw_cmd_check_not_3d(dev_priv, sw_context, buf, size);
  675. cmd_id = le32_to_cpu(header->id);
  676. *size = le32_to_cpu(header->size) + sizeof(SVGA3dCmdHeader);
  677. cmd_id -= SVGA_3D_CMD_BASE;
  678. if (unlikely(*size > size_remaining))
  679. goto out_err;
  680. if (unlikely(cmd_id >= SVGA_3D_CMD_MAX - SVGA_3D_CMD_BASE))
  681. goto out_err;
  682. ret = vmw_cmd_funcs[cmd_id](dev_priv, sw_context, header);
  683. if (unlikely(ret != 0))
  684. goto out_err;
  685. return 0;
  686. out_err:
  687. DRM_ERROR("Illegal / Invalid SVGA3D command: %d\n",
  688. cmd_id + SVGA_3D_CMD_BASE);
  689. return -EINVAL;
  690. }
  691. static int vmw_cmd_check_all(struct vmw_private *dev_priv,
  692. struct vmw_sw_context *sw_context,
  693. void *buf,
  694. uint32_t size)
  695. {
  696. int32_t cur_size = size;
  697. int ret;
  698. while (cur_size > 0) {
  699. size = cur_size;
  700. ret = vmw_cmd_check(dev_priv, sw_context, buf, &size);
  701. if (unlikely(ret != 0))
  702. return ret;
  703. buf = (void *)((unsigned long) buf + size);
  704. cur_size -= size;
  705. }
  706. if (unlikely(cur_size != 0)) {
  707. DRM_ERROR("Command verifier out of sync.\n");
  708. return -EINVAL;
  709. }
  710. return 0;
  711. }
  712. static void vmw_free_relocations(struct vmw_sw_context *sw_context)
  713. {
  714. sw_context->cur_reloc = 0;
  715. }
  716. static void vmw_apply_relocations(struct vmw_sw_context *sw_context)
  717. {
  718. uint32_t i;
  719. struct vmw_relocation *reloc;
  720. struct ttm_validate_buffer *validate;
  721. struct ttm_buffer_object *bo;
  722. for (i = 0; i < sw_context->cur_reloc; ++i) {
  723. reloc = &sw_context->relocs[i];
  724. validate = &sw_context->val_bufs[reloc->index];
  725. bo = validate->bo;
  726. if (bo->mem.mem_type == TTM_PL_VRAM) {
  727. reloc->location->offset += bo->offset;
  728. reloc->location->gmrId = SVGA_GMR_FRAMEBUFFER;
  729. } else
  730. reloc->location->gmrId = bo->mem.start;
  731. }
  732. vmw_free_relocations(sw_context);
  733. }
  734. static void vmw_clear_validations(struct vmw_sw_context *sw_context)
  735. {
  736. struct ttm_validate_buffer *entry, *next;
  737. struct vmw_resource *res, *res_next;
  738. /*
  739. * Drop references to DMA buffers held during command submission.
  740. */
  741. list_for_each_entry_safe(entry, next, &sw_context->validate_nodes,
  742. head) {
  743. list_del(&entry->head);
  744. vmw_dmabuf_validate_clear(entry->bo);
  745. ttm_bo_unref(&entry->bo);
  746. sw_context->cur_val_buf--;
  747. }
  748. BUG_ON(sw_context->cur_val_buf != 0);
  749. /*
  750. * Drop references to resources held during command submission.
  751. */
  752. vmw_resource_unreserve(&sw_context->resource_list);
  753. list_for_each_entry_safe(res, res_next, &sw_context->resource_list,
  754. validate_head) {
  755. list_del_init(&res->validate_head);
  756. vmw_resource_unreference(&res);
  757. }
  758. }
  759. static int vmw_validate_single_buffer(struct vmw_private *dev_priv,
  760. struct ttm_buffer_object *bo)
  761. {
  762. int ret;
  763. /*
  764. * Don't validate pinned buffers.
  765. */
  766. if (bo == dev_priv->pinned_bo ||
  767. (bo == dev_priv->dummy_query_bo &&
  768. dev_priv->dummy_query_bo_pinned))
  769. return 0;
  770. /**
  771. * Put BO in VRAM if there is space, otherwise as a GMR.
  772. * If there is no space in VRAM and GMR ids are all used up,
  773. * start evicting GMRs to make room. If the DMA buffer can't be
  774. * used as a GMR, this will return -ENOMEM.
  775. */
  776. ret = ttm_bo_validate(bo, &vmw_vram_gmr_placement, true, false, false);
  777. if (likely(ret == 0 || ret == -ERESTARTSYS))
  778. return ret;
  779. /**
  780. * If that failed, try VRAM again, this time evicting
  781. * previous contents.
  782. */
  783. DRM_INFO("Falling through to VRAM.\n");
  784. ret = ttm_bo_validate(bo, &vmw_vram_placement, true, false, false);
  785. return ret;
  786. }
  787. static int vmw_validate_buffers(struct vmw_private *dev_priv,
  788. struct vmw_sw_context *sw_context)
  789. {
  790. struct ttm_validate_buffer *entry;
  791. int ret;
  792. list_for_each_entry(entry, &sw_context->validate_nodes, head) {
  793. ret = vmw_validate_single_buffer(dev_priv, entry->bo);
  794. if (unlikely(ret != 0))
  795. return ret;
  796. }
  797. return 0;
  798. }
  799. static int vmw_resize_cmd_bounce(struct vmw_sw_context *sw_context,
  800. uint32_t size)
  801. {
  802. if (likely(sw_context->cmd_bounce_size >= size))
  803. return 0;
  804. if (sw_context->cmd_bounce_size == 0)
  805. sw_context->cmd_bounce_size = VMWGFX_CMD_BOUNCE_INIT_SIZE;
  806. while (sw_context->cmd_bounce_size < size) {
  807. sw_context->cmd_bounce_size =
  808. PAGE_ALIGN(sw_context->cmd_bounce_size +
  809. (sw_context->cmd_bounce_size >> 1));
  810. }
  811. if (sw_context->cmd_bounce != NULL)
  812. vfree(sw_context->cmd_bounce);
  813. sw_context->cmd_bounce = vmalloc(sw_context->cmd_bounce_size);
  814. if (sw_context->cmd_bounce == NULL) {
  815. DRM_ERROR("Failed to allocate command bounce buffer.\n");
  816. sw_context->cmd_bounce_size = 0;
  817. return -ENOMEM;
  818. }
  819. return 0;
  820. }
  821. /**
  822. * vmw_execbuf_fence_commands - create and submit a command stream fence
  823. *
  824. * Creates a fence object and submits a command stream marker.
  825. * If this fails for some reason, We sync the fifo and return NULL.
  826. * It is then safe to fence buffers with a NULL pointer.
  827. *
  828. * If @p_handle is not NULL @file_priv must also not be NULL. Creates
  829. * a userspace handle if @p_handle is not NULL, otherwise not.
  830. */
  831. int vmw_execbuf_fence_commands(struct drm_file *file_priv,
  832. struct vmw_private *dev_priv,
  833. struct vmw_fence_obj **p_fence,
  834. uint32_t *p_handle)
  835. {
  836. uint32_t sequence;
  837. int ret;
  838. bool synced = false;
  839. /* p_handle implies file_priv. */
  840. BUG_ON(p_handle != NULL && file_priv == NULL);
  841. ret = vmw_fifo_send_fence(dev_priv, &sequence);
  842. if (unlikely(ret != 0)) {
  843. DRM_ERROR("Fence submission error. Syncing.\n");
  844. synced = true;
  845. }
  846. if (p_handle != NULL)
  847. ret = vmw_user_fence_create(file_priv, dev_priv->fman,
  848. sequence,
  849. DRM_VMW_FENCE_FLAG_EXEC,
  850. p_fence, p_handle);
  851. else
  852. ret = vmw_fence_create(dev_priv->fman, sequence,
  853. DRM_VMW_FENCE_FLAG_EXEC,
  854. p_fence);
  855. if (unlikely(ret != 0 && !synced)) {
  856. (void) vmw_fallback_wait(dev_priv, false, false,
  857. sequence, false,
  858. VMW_FENCE_WAIT_TIMEOUT);
  859. *p_fence = NULL;
  860. }
  861. return 0;
  862. }
  863. /**
  864. * vmw_execbuf_copy_fence_user - copy fence object information to
  865. * user-space.
  866. *
  867. * @dev_priv: Pointer to a vmw_private struct.
  868. * @vmw_fp: Pointer to the struct vmw_fpriv representing the calling file.
  869. * @ret: Return value from fence object creation.
  870. * @user_fence_rep: User space address of a struct drm_vmw_fence_rep to
  871. * which the information should be copied.
  872. * @fence: Pointer to the fenc object.
  873. * @fence_handle: User-space fence handle.
  874. *
  875. * This function copies fence information to user-space. If copying fails,
  876. * The user-space struct drm_vmw_fence_rep::error member is hopefully
  877. * left untouched, and if it's preloaded with an -EFAULT by user-space,
  878. * the error will hopefully be detected.
  879. * Also if copying fails, user-space will be unable to signal the fence
  880. * object so we wait for it immediately, and then unreference the
  881. * user-space reference.
  882. */
  883. void
  884. vmw_execbuf_copy_fence_user(struct vmw_private *dev_priv,
  885. struct vmw_fpriv *vmw_fp,
  886. int ret,
  887. struct drm_vmw_fence_rep __user *user_fence_rep,
  888. struct vmw_fence_obj *fence,
  889. uint32_t fence_handle)
  890. {
  891. struct drm_vmw_fence_rep fence_rep;
  892. if (user_fence_rep == NULL)
  893. return;
  894. memset(&fence_rep, 0, sizeof(fence_rep));
  895. fence_rep.error = ret;
  896. if (ret == 0) {
  897. BUG_ON(fence == NULL);
  898. fence_rep.handle = fence_handle;
  899. fence_rep.seqno = fence->seqno;
  900. vmw_update_seqno(dev_priv, &dev_priv->fifo);
  901. fence_rep.passed_seqno = dev_priv->last_read_seqno;
  902. }
  903. /*
  904. * copy_to_user errors will be detected by user space not
  905. * seeing fence_rep::error filled in. Typically
  906. * user-space would have pre-set that member to -EFAULT.
  907. */
  908. ret = copy_to_user(user_fence_rep, &fence_rep,
  909. sizeof(fence_rep));
  910. /*
  911. * User-space lost the fence object. We need to sync
  912. * and unreference the handle.
  913. */
  914. if (unlikely(ret != 0) && (fence_rep.error == 0)) {
  915. ttm_ref_object_base_unref(vmw_fp->tfile,
  916. fence_handle, TTM_REF_USAGE);
  917. DRM_ERROR("Fence copy error. Syncing.\n");
  918. (void) vmw_fence_obj_wait(fence, fence->signal_mask,
  919. false, false,
  920. VMW_FENCE_WAIT_TIMEOUT);
  921. }
  922. }
  923. int vmw_execbuf_process(struct drm_file *file_priv,
  924. struct vmw_private *dev_priv,
  925. void __user *user_commands,
  926. void *kernel_commands,
  927. uint32_t command_size,
  928. uint64_t throttle_us,
  929. struct drm_vmw_fence_rep __user *user_fence_rep,
  930. struct vmw_fence_obj **out_fence)
  931. {
  932. struct vmw_sw_context *sw_context = &dev_priv->ctx;
  933. struct vmw_fence_obj *fence = NULL;
  934. uint32_t handle;
  935. void *cmd;
  936. int ret;
  937. ret = mutex_lock_interruptible(&dev_priv->cmdbuf_mutex);
  938. if (unlikely(ret != 0))
  939. return -ERESTARTSYS;
  940. if (kernel_commands == NULL) {
  941. sw_context->kernel = false;
  942. ret = vmw_resize_cmd_bounce(sw_context, command_size);
  943. if (unlikely(ret != 0))
  944. goto out_unlock;
  945. ret = copy_from_user(sw_context->cmd_bounce,
  946. user_commands, command_size);
  947. if (unlikely(ret != 0)) {
  948. ret = -EFAULT;
  949. DRM_ERROR("Failed copying commands.\n");
  950. goto out_unlock;
  951. }
  952. kernel_commands = sw_context->cmd_bounce;
  953. } else
  954. sw_context->kernel = true;
  955. sw_context->tfile = vmw_fpriv(file_priv)->tfile;
  956. sw_context->cid_valid = false;
  957. sw_context->sid_valid = false;
  958. sw_context->cur_reloc = 0;
  959. sw_context->cur_val_buf = 0;
  960. sw_context->fence_flags = 0;
  961. INIT_LIST_HEAD(&sw_context->query_list);
  962. INIT_LIST_HEAD(&sw_context->resource_list);
  963. sw_context->cur_query_bo = dev_priv->pinned_bo;
  964. sw_context->cur_query_cid = dev_priv->query_cid;
  965. sw_context->query_cid_valid = (dev_priv->pinned_bo != NULL);
  966. INIT_LIST_HEAD(&sw_context->validate_nodes);
  967. ret = vmw_cmd_check_all(dev_priv, sw_context, kernel_commands,
  968. command_size);
  969. if (unlikely(ret != 0))
  970. goto out_err;
  971. ret = ttm_eu_reserve_buffers(&sw_context->validate_nodes);
  972. if (unlikely(ret != 0))
  973. goto out_err;
  974. ret = vmw_validate_buffers(dev_priv, sw_context);
  975. if (unlikely(ret != 0))
  976. goto out_err;
  977. vmw_apply_relocations(sw_context);
  978. if (throttle_us) {
  979. ret = vmw_wait_lag(dev_priv, &dev_priv->fifo.marker_queue,
  980. throttle_us);
  981. if (unlikely(ret != 0))
  982. goto out_throttle;
  983. }
  984. cmd = vmw_fifo_reserve(dev_priv, command_size);
  985. if (unlikely(cmd == NULL)) {
  986. DRM_ERROR("Failed reserving fifo space for commands.\n");
  987. ret = -ENOMEM;
  988. goto out_throttle;
  989. }
  990. memcpy(cmd, kernel_commands, command_size);
  991. vmw_fifo_commit(dev_priv, command_size);
  992. vmw_query_bo_switch_commit(dev_priv, sw_context);
  993. ret = vmw_execbuf_fence_commands(file_priv, dev_priv,
  994. &fence,
  995. (user_fence_rep) ? &handle : NULL);
  996. /*
  997. * This error is harmless, because if fence submission fails,
  998. * vmw_fifo_send_fence will sync. The error will be propagated to
  999. * user-space in @fence_rep
  1000. */
  1001. if (ret != 0)
  1002. DRM_ERROR("Fence submission error. Syncing.\n");
  1003. ttm_eu_fence_buffer_objects(&sw_context->validate_nodes,
  1004. (void *) fence);
  1005. vmw_clear_validations(sw_context);
  1006. vmw_execbuf_copy_fence_user(dev_priv, vmw_fpriv(file_priv), ret,
  1007. user_fence_rep, fence, handle);
  1008. /* Don't unreference when handing fence out */
  1009. if (unlikely(out_fence != NULL)) {
  1010. *out_fence = fence;
  1011. fence = NULL;
  1012. } else if (likely(fence != NULL)) {
  1013. vmw_fence_obj_unreference(&fence);
  1014. }
  1015. mutex_unlock(&dev_priv->cmdbuf_mutex);
  1016. return 0;
  1017. out_err:
  1018. vmw_free_relocations(sw_context);
  1019. out_throttle:
  1020. vmw_query_switch_backoff(sw_context);
  1021. ttm_eu_backoff_reservation(&sw_context->validate_nodes);
  1022. vmw_clear_validations(sw_context);
  1023. out_unlock:
  1024. mutex_unlock(&dev_priv->cmdbuf_mutex);
  1025. return ret;
  1026. }
  1027. /**
  1028. * vmw_execbuf_unpin_panic - Idle the fifo and unpin the query buffer.
  1029. *
  1030. * @dev_priv: The device private structure.
  1031. *
  1032. * This function is called to idle the fifo and unpin the query buffer
  1033. * if the normal way to do this hits an error, which should typically be
  1034. * extremely rare.
  1035. */
  1036. static void vmw_execbuf_unpin_panic(struct vmw_private *dev_priv)
  1037. {
  1038. DRM_ERROR("Can't unpin query buffer. Trying to recover.\n");
  1039. (void) vmw_fallback_wait(dev_priv, false, true, 0, false, 10*HZ);
  1040. vmw_bo_pin(dev_priv->pinned_bo, false);
  1041. vmw_bo_pin(dev_priv->dummy_query_bo, false);
  1042. dev_priv->dummy_query_bo_pinned = false;
  1043. }
  1044. /**
  1045. * vmw_execbuf_release_pinned_bo - Flush queries and unpin the pinned
  1046. * query bo.
  1047. *
  1048. * @dev_priv: The device private structure.
  1049. * @only_on_cid_match: Only flush and unpin if the current active query cid
  1050. * matches @cid.
  1051. * @cid: Optional context id to match.
  1052. *
  1053. * This function should be used to unpin the pinned query bo, or
  1054. * as a query barrier when we need to make sure that all queries have
  1055. * finished before the next fifo command. (For example on hardware
  1056. * context destructions where the hardware may otherwise leak unfinished
  1057. * queries).
  1058. *
  1059. * This function does not return any failure codes, but make attempts
  1060. * to do safe unpinning in case of errors.
  1061. *
  1062. * The function will synchronize on the previous query barrier, and will
  1063. * thus not finish until that barrier has executed.
  1064. */
  1065. void vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv,
  1066. bool only_on_cid_match, uint32_t cid)
  1067. {
  1068. int ret = 0;
  1069. struct list_head validate_list;
  1070. struct ttm_validate_buffer pinned_val, query_val;
  1071. struct vmw_fence_obj *fence;
  1072. mutex_lock(&dev_priv->cmdbuf_mutex);
  1073. if (dev_priv->pinned_bo == NULL)
  1074. goto out_unlock;
  1075. if (only_on_cid_match && cid != dev_priv->query_cid)
  1076. goto out_unlock;
  1077. INIT_LIST_HEAD(&validate_list);
  1078. pinned_val.bo = ttm_bo_reference(dev_priv->pinned_bo);
  1079. list_add_tail(&pinned_val.head, &validate_list);
  1080. query_val.bo = ttm_bo_reference(dev_priv->dummy_query_bo);
  1081. list_add_tail(&query_val.head, &validate_list);
  1082. do {
  1083. ret = ttm_eu_reserve_buffers(&validate_list);
  1084. } while (ret == -ERESTARTSYS);
  1085. if (unlikely(ret != 0)) {
  1086. vmw_execbuf_unpin_panic(dev_priv);
  1087. goto out_no_reserve;
  1088. }
  1089. ret = vmw_fifo_emit_dummy_query(dev_priv, dev_priv->query_cid);
  1090. if (unlikely(ret != 0)) {
  1091. vmw_execbuf_unpin_panic(dev_priv);
  1092. goto out_no_emit;
  1093. }
  1094. vmw_bo_pin(dev_priv->pinned_bo, false);
  1095. vmw_bo_pin(dev_priv->dummy_query_bo, false);
  1096. dev_priv->dummy_query_bo_pinned = false;
  1097. (void) vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL);
  1098. ttm_eu_fence_buffer_objects(&validate_list, (void *) fence);
  1099. ttm_bo_unref(&query_val.bo);
  1100. ttm_bo_unref(&pinned_val.bo);
  1101. ttm_bo_unref(&dev_priv->pinned_bo);
  1102. out_unlock:
  1103. mutex_unlock(&dev_priv->cmdbuf_mutex);
  1104. return;
  1105. out_no_emit:
  1106. ttm_eu_backoff_reservation(&validate_list);
  1107. out_no_reserve:
  1108. ttm_bo_unref(&query_val.bo);
  1109. ttm_bo_unref(&pinned_val.bo);
  1110. ttm_bo_unref(&dev_priv->pinned_bo);
  1111. mutex_unlock(&dev_priv->cmdbuf_mutex);
  1112. }
  1113. int vmw_execbuf_ioctl(struct drm_device *dev, void *data,
  1114. struct drm_file *file_priv)
  1115. {
  1116. struct vmw_private *dev_priv = vmw_priv(dev);
  1117. struct drm_vmw_execbuf_arg *arg = (struct drm_vmw_execbuf_arg *)data;
  1118. struct vmw_master *vmaster = vmw_master(file_priv->master);
  1119. int ret;
  1120. /*
  1121. * This will allow us to extend the ioctl argument while
  1122. * maintaining backwards compatibility:
  1123. * We take different code paths depending on the value of
  1124. * arg->version.
  1125. */
  1126. if (unlikely(arg->version != DRM_VMW_EXECBUF_VERSION)) {
  1127. DRM_ERROR("Incorrect execbuf version.\n");
  1128. DRM_ERROR("You're running outdated experimental "
  1129. "vmwgfx user-space drivers.");
  1130. return -EINVAL;
  1131. }
  1132. ret = ttm_read_lock(&vmaster->lock, true);
  1133. if (unlikely(ret != 0))
  1134. return ret;
  1135. ret = vmw_execbuf_process(file_priv, dev_priv,
  1136. (void __user *)(unsigned long)arg->commands,
  1137. NULL, arg->command_size, arg->throttle_us,
  1138. (void __user *)(unsigned long)arg->fence_rep,
  1139. NULL);
  1140. if (unlikely(ret != 0))
  1141. goto out_unlock;
  1142. vmw_kms_cursor_post_execbuf(dev_priv);
  1143. out_unlock:
  1144. ttm_read_unlock(&vmaster->lock);
  1145. return ret;
  1146. }